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BI 4

GII THIU
CC PORT XUT NHP IO
PORTA v thanh ghi TRISA
PORTB v thanh ghi TRISB
PORTC v thanh ghi TRISC
PORTD v thanh ghi TRISD
PORTE v thanh ghi TRISE

TP LNH C CHO CC PORT
LNH SET_TRIS_X() - LNH NH CU HNH VO/RA CHO PORT
LNH OUTPUT_X(VALUE) - XUT D LIIU 8 BIT RA PORT
LNH OUTPUT_HIGH(PIN) - LNH LM 1 CHN CA PORT LN MC CAO
LNH OUTPUT_LOW(PIN) - LNH LM 1 CHN CA PORT XUNG MC 0
LNH OUTPUT_TOGGLE(PIN) - LNH O TRNG THI CA 1 CHN
LNH OUTPUT_BIT(PIN,VALUE) - LNH XUT D LIU RA 1 CHN
LNH value = GET_TRIS_x() - LNH C THANH GHI NH CU HNH
LNH value = INPUT(pin) - LNH C D LIU T 1 CHN CA PORT
LNH INPUT_STATE() - LNH C TRNG THI NG VO
Value = INPUT_x()
LNH INPUT_STATE() - LNH C TRNG THI NG VO
LNH OUTPUT_DRIVE(PIN) - LNH C TRNG THI NG VO
LNH OUTPUT_FLOAT(PIN) - LNH TH NI CHN TN HIU
LNH PORT_B_PULLUP( ) - LNH TREO PORT B QUA IN TR LN NGUN

CC CHNG TRNH V D CHO CC PORT



Ca. -: :x ea ey :xa: :e Wq% 7-a a.e a.e :x 7,xye C. 7x
8x Ca. 4. qa x . e--: a te q ax, :- :a : e--: :xa 79q
I. GII THIU
Vi iu khin c cc port xut nhp d liu giao tip vi cc i tng iu khin. Tn hiu iu
khin t CPU gi ra port iu khin, ng thi c cc port nhn d liu v x l. Trong mt h thng
lun c cc tn hiu vo ra v nh h thng iu khin robo nh hnh sau:

Hnh 4-1: S kt ni port vi i tng iu khin.
Mi vi iu khin khc nhau c cu hnh cc port cng khc nhau, phn ny s kho st cc port ca
vi iu khin PIC bao gm port A, B, C, D , E v cc lnh ngn ng C lin quan n cc port.
Mi port ca vi iu khin PIC gm c thanh ghi port v thanh ghi nh hng cho Port v d nh
hnh 4-2 l PORTA v TRISA. Bit ca thanh ghi nh hng TRIS bng 0 th port c chc nng xut d
liu, nu bng 1 th c chc nng nhp d liu.
Ch : '0' tng ng vi 'OUT', '1' tng ng vi 'IN'.

Hnh 4-2: S kt ni port: xut nhp tn hiu iu khin.
Phn tip s kho st chi tit tng port.
II. CC PORT XUT NHP (IO)
1. PORTA v thanh ghi TRISA:
Ca. -: :x ea ey :xa: :e Wq% 7-a a.e a.e :x 7,xye C. 7x
Ca. 4. qa x . e--: a te q ax, :- :a : e--: :xa 79q 8?
PORTA l port hai chiu 6 bit, thanh ghi nh hng l TRISA.

Chn RA4 c a hp vi ng vo xung clock ca module Timer0 c tn l RA4/T0CKI c cu
hnh Schmitt trigger v cc mng h. Tt c cc chn cn li ca PORTA chun TTL khi n l ng vo
v khi xut d liu th theo chun CMOS.

Hnh 4-3: S mch chn RA3:RA0. Hnh 4-4: S mch chn RA4/T0CKI.
Nhng chn khc ca PortA c a hp vi cc ng vo tng t cho cc b chuyn i A/D v cc
b so snh. Thanh ghi ADCON1 s thit lp cc bit cho portA lm vic tng t hay s.
Thanh ghi TRISA iu khin hng cho PortA cho d portA s dng cho ng vo tng t. Khi s
dng portA l ng vo tng t th bit tng ng trong thanh ghi TRISA phi bng 1.
Cc chc nng ca PortA.
TN BIT# KIU M CHC NNG
RA0/AN0 Bit 0 TTL I/O
RA1/AN1 Bit 1 TTL I/O
RA2/AN2/V
REF-
/CV
REF
Bit 2 TTL I/O hoc V
REF-
hoc VC
REF
RA3/AN3/V
REF+
Bit 3 TTL I/O hoc V
REF+
RA4/T0CKI/C1OUT Bit 4 TTL I/O hoc ng vo xung clock cho
Timer0 hoc ng ra b so snh 1
Ca. -: :x ea ey :xa: :e Wq% 7-a a.e a.e :x 7,xye C. 7x
30 Ca. 4. qa x . e--: a te q ax, :- :a : e--: :xa 79q
RA5/AN4/ /C2OUT
Bit 5 TTL I/O hoc ng vo tng t



Hnh 4-5: S mch chn RA5.
Tm tt cc thanh ghi lin kt vi PortA.

2. PORTB v thanh ghi TRISB:
PortB l port hai chiu 8 bit. Thanh ghi nh hng l TRISB.

Ba chn ca PortB l RB3/PGM, RB6/PGC v RB7/PGD c a hp vi mch in g ri bn trong
v mnh lp trnh in p thp np chng trnh vo b nh ni. S kt ni mch np v mch g ri:
SS
Ca. -: :x ea ey :xa: :e Wq% 7-a a.e a.e :x 7,xye C. 7x
Ca. 4. qa x . e--: a te q ax, :- :a : e--: :xa 79q 3I

Hnh 4-6: Cc chn PortB giao tip vi mch np, g ri.
Mi chn ca PortB u c in tr ko ln. Bit (OPTION_REG<7>) nu bng 0 th s treo
tt c cc port qua in tr ln ngun. Khi PortB c thit lp l cc ng ra th s t ng tt chc nng
in tr ko ln, tng t khi CPU b reset.

Hnh 4-6: S kt ni port vi i tng iu khin.
Khi port dng kt ni vi nt nhn th cn phi dng in tr ko ln ngun to mc logic 1, khi
nhn nt th ngn mch ng vo xung mc 0, xem hnh 4-6. Trong ng dng ny phi cn in tr ko ln.
Vi ng dng port iu khin i tng l led th khng cn dng in tr ko ln.
Bn chn t RB4 n RB7 pht sinh ngt khi c s thay i mc logic. Ch c nhng chn c thit
lp cu hnh l ng vo th mi c chc nng ngt. Cc chn ng vo (RB7:RB4) c so snh vi gi tr
c c cht trong ln c trc ca PortB. Cc ng ra khng trng nhau ca cc chn RB4:RB7 c
OR li vi nhau to ngt PortB vi bit c bo ngt RBIF (INTCON<0>).
Ngt portB c th kch hot vi iu khin tr li trng thi hot ng nu ang ch ng (SLEEP).
Trong chng trnh phc v ngt th ngt c th xa bng cc cch sau:
o Bt k lnh c hay ghi PortB. iu ny s kt thc iu kin khng tng thch.
o Xa bit c RBIF.
iu kin khng tng thch s tip tc lm c bo ngt RBIF bng 1. Khi c PortB s chm dt
iu kin khng tng thch v cho php xa bit c bo ngt RBIF.
RBPU
Ca. -: :x ea ey :xa: :e Wq% 7-a a.e a.e :x 7,xye C. 7x
38 Ca. 4. qa x . e--: a te q ax, :- :a : e--: :xa 79q

Hnh 4-12: S mch cc chn RB3:RB0. Hnh 4-13: S mch cc chn RB7:RB4.
Ngt khng tng thch ca PortB c in tr ko ln d dng cho php giao tip vi phm hoc bn
phm ma trn.

Hnh 4-14: S kt ni port vi i tng iu khin.

Tn Bit# Kiu m Chc nng
RB0/INT Bit 0 TTL/ST I/O hoc ng vo ngt. C lp trnh in tr ko ln.
RB1 Bit 1 TTL I/O C lp trnh in tr ko ln.
RB2 Bit 2 TTL I/O C lp trnh in tr ko ln.
RB3/PGM Bit 3 TTL I/O hoc lp trnh ch LVP.
C lp trnh in tr ko ln.
RB4 Bit 4 TTL I/O (ngt khi c thay i). C lp trnh in tr ko ln.
RB5 Bit 5 TTL I/O (ngt khi c thay i). C lp trnh in tr ko ln.
RB6/PGC Bit 5 TTL/ST I/O (ngt khi c thay i) hoc chn mch g ri.
C lp trnh in tr ko ln. Xung lp trnh ni tip.
RB7/PGD Bit 5 TTL/ST I/O (ngt khi c thay i) hoc chn mch g ri.
Ca. -: :x ea ey :xa: :e Wq% 7-a a.e a.e :x 7,xye C. 7x
Ca. 4. qa x . e--: a te q ax, :- :a : e--: :xa 79q 33
C lp trnh in tr ko ln. D liu lp trnh ni tip.
Cc thanh ghi lin quan n portB:


3. PORTC v thanh ghi TRISC:
PortC l port hai chiu 8 bit. Thanh ghi nh hng l TRISC. Khi bit TRISC =1 th PORTC l port
nhp, khi bit TRISC= 0 th PORTC l port xut.
PortC a hp vi cc chc nng ngoi vi, cc chn PortC c mch m Schmitt Trigger ng vo.
Khi khi I
2
C c cho php th cc chn PORTC<4:3> c th c nh cu hnh cc mc I
2
C hoc
mc SMBUS bng cch s dng bit CKE (SSPSTAT<6>).
Khi cho php cc chc nng ngoi vi nn ch n cc bit TRISC cho mi chn ca PORTC. Ngi
s dng tham chiu ti phn thit b ngoi vi tng ng thit lp cho ng bit TRISC.

Hnh 4-15: S cc chn RC7:RC5 v RC2:RC0. Hnh 4-16: S mch cc chn RC4:RC3.



TN BIT# KIU
M
CHC NNG
RC0/T1OSO/T1CKI Bit 0 ST I/O hoc ng ra b dao ng
Ca. -: :x ea ey :xa: :e Wq% 7-a a.e a.e :x 7,xye C. 7x
34 Ca. 4. qa x . e--: a te q ax, :- :a : e--: :xa 79q
Timer1/ng vo xung ca Timer1.
RC1/T1OSI/CCP2 Bit 1 ST I/O hoc ng vo b dao ng
Timer1/ng vo Capture, ng ra
compare2/ng ra PWM.
RC2/CCP1 Bit 2 ST I/O hoc ng vo Capture1/ng ra
Compare1/ng ra PWM.
RC3/SCK/SCL Bit 3 ST RC3 cng c th l xung clock ni tip
ng b cho ch SPI v I
2
C.
RC4/SDI/SDA Bit 4 ST RC4 cng c th l d liu SPI hoc d
liu xut/nhp (ch I
2
C).
RC5/SDO Bit 5 ST I/O hoc ng ra d liu port ni tip
ng b.
RC6/TX/CK Bit 6 ST I/O hoc truyn bt ng b USART
hoc xung ng b.
RC7/RX/DT Bit 7 ST I/O hoc nhn bt ng b USART
hoc d liu ng b.

4. PORTD v thanh ghi TRISD:
PortD l port 8 bit vi ng vo c mch Schmitt Trigger. Thanh ghi TRISD s cu hnh l ng vo
hoc ng ra.
PortD c th nh cu hnh nh port ca vi x l 8 bit bng cch thit lp bit iu khin PSPMODE
(TRISE<4>). Trong cu hnh ny th cc b m ng vo dng TTL.
Ch : PortD v TRISD khng c xy dng cho chip PIC 28 chn.


Hnh 4-17: S mch cc chn PORTD.
Cc thanh ghi kt ni vi PortD.

Ca. -: :x ea ey :xa: :e Wq% 7-a a.e a.e :x 7,xye C. 7x
Ca. 4. qa x . e--: a te q ax, :- :a : e--: :xa 79q 35
Cc chc nng ca PortD.

TN
BIT# KIU M CHC NNG
RD0/PSP0 Bit 0 ST/TTL Port I/O hoc bit 0 ca port song song
RD1/PSP1 Bit 1 ST/TTL Port I/O hoc bit 1 ca port song song
RD2/PSP2 Bit 2 ST/TTL Port I/O hoc bit 2 ca port song song
RD3/PSP3 Bit 3 ST/TTL Port I/O hoc bit 3 ca port song song
RD4/PSP4 Bit 4 ST/TTL Port I/O hoc bit 4 ca port song song
RD5/PSP5 Bit 5 ST/TTL Port I/O hoc bit 5 ca port song song
RD6/PSP6 Bit 6 ST/TTL Port I/O hoc bit 6 ca port song song
RD7/PSP7 Bit 7 ST/TTL Port I/O hoc bit 7 ca port song song

5. PORTE v thanh ghi TRISE:
PORTE c 3 chn: RE0/ /AN5, RE1/ /AN6 v RE2/ /AN7 c cu hnh c lp thit lp
ng vo hoc ng ra. Nhng chn ny c mch in Schmitt Trigger ng vo.
PORTE l port nhp khi bit PSPMODE (TRISE<4>) bng 1, cc bit TRISE<0:2> phi bng 1 v cu
hnh cc bit trong thanh ghi ADCON1 portE l xut/nhp s. Trong ch ny, b m ng vo dng
TTL.
PORTE cng a hp vi cc ng vo tng t. Khi nh cu hnh l ng vo tng t th khi c cc
chn ny s c gi tr l 0.
Cc thanh ghi kt ni vi PORTE.


Hnh 4-18: S mch cc chn PORTE.
Cc chc nng ca PORTE.
RD WR CS
Ca. -: :x ea ey :xa: :e Wq% 7-a a.e a.e :x 7,xye C. 7x
36 Ca. 4. qa x . e--: a te q ax, :- :a : e--: :xa 79q
TN BIT# KIU M CHC NNG
RE0/ /AN5
Bit 0 ST/TTL I/O hoc ng ra iu khin c port song
song hoc ng vo tng t.
RE1/ /AN6
Bit 1 ST/TTL I/O hoc ng ra iu khin ghi port song
song hoc ng vo tng t.
RE2/ /AN7
Bit 2 ST/TTL I/O hoc ng ra chn la port song song
hoc ng tng t.
1 CS : VK t khng c chn.
0 CS : VK t c chn.

Trng thi port song song/cc bit iu khin:
Bit 7 IBF: bit bo trng thi b m ng vo y (Input Buffer Full Status bit):
1= mt word nhn v ang ch CPU c.
0= khng c word no c nhn.
Bit 6 OBF: bit bo trng thi b m ng ra y (Output Buffer Full Status bit):
1= b m ng ra vn cn gi word ghi trc .
0= b m ng ra c c.
Bit 5 IBOV: bit pht hin trn b m ng vo (Input Buffer Overflow Detect bit):
1= qu trnh ghi xy khi word ng vo trc cha c c.
0= khng xy ra trn.
Bit 4 PSPMODE: Bit chn la ch port song song
1= PORTD c nh ch l port song song.
0= PORTD c nh ch l port xut nhp.
Bit 3 Cha dng: c l 0
Cc bit PORTE l cc bit d liu trc tip:
Bit 2 Bit 2: bit iu khin hng cho chn RE2/ /AN7
1= ng vo.
0= ng ra.
Bit 1 Bit 1: bit iu khin hng cho chn RE1/ /AN6
1= ng vo.
0= ng ra.
Bit 0 Bit 0: bit iu khin hng cho chn RE0/ /AN5
1= ng vo.
0= ng ra.
III. TP LNH C CHO CC PORT
Cc lnh ca ngn ng lp trnh C lin quan n cc port bao gm:
Lnh OUTPUT_FLOAT()
Lnh OUTPUT_LOW()
Lnh OUTPUT_HIGH()
Lnh OUTPUT_TOGGLE()
Lnh OUTPUT_BIT()
Lnh OUTPUT_X()
RD
WR
CS
CS
WR
RD
Ca. -: :x ea ey :xa: :e Wq% 7-a a.e a.e :x 7,xye C. 7x
Ca. 4. qa x . e--: a te q ax, :- :a : e--: :xa 79q 37

Lnh SET_TRIS_X()
Lnh GET_TRIS_X()
Lnh INPUT_X()
Lnh INPUT()

Lnh PORT_A_PULLUPS()
Lnh PORT_B_PULLUPS()
Lnh INPUT_STATE()
Lnh OUTPUT_DRIVE()
1. LNH SET_TRIS_X() - LNH NH CU HNH VO/RA CHO PORT
C php: set_tris_x(value); thit lp cu hnh INPUT/OUTPUT cho portx
Thng s: value l 1 s nguyn 8 bit tng ng vi cc bit ca port I/O.
Chc nng: cc lnh c chc nng nh hng cho cc port I/O (TRI-State). Mi bit tng ng 1 chn.
Mc 1 th chn tng ng l ng vo, mc 0 th chn l ng ra
C hiu lc: cho tt c cc vi iu khin PIC.
V d: SET_TRIS_B (0x0F); // 0F=00001111: B7- B4 l ng ra, B3-B0 l ng vo.

2. LNH OUTPUT_X(VALUE) - XUT D LIIU 8 BIT RA PORTX
C php: output_x (value)
Thng s: value l hng s 8 bit kiu int
Chc nng: Xut d liu 1 byte ra 1 port.
C hiu lc: Lnh ny p dng cho tt c cc port.
V d: OUTPUT_B(0xF0); xut d liu F0 ra portB

3. LNH OUTPUT_HIGH(PIN) - LNH LM 1 CHN CA PORT LN MC CAO
C php: output_high(pin); tng ng lnh BSF PORTX,B
Thng s: pin l chn xut d liu - hy xem file nh ngha ca thit b "device.h" bit tn chnh xc.
Chc nng: lm 1 chn ca port ln mc cao.
C hiu lc: lnh ny p dng cho tt c cc thit b.
V d OUTPUT_HIGH(PIN_A0); // lm cho chn RA0 ca port A ln 1

4. LNH OUTPUT_LOW(PIN) - LNH LM 1 CHN CA PORT XUNG MC 0
C php: output_low(pin); tng ng lnh BCF PORTX,B
Thng s: pin l chn xut d liu - hy xem file nh ngha ca thit b "device.h" bit tn chnh xc.
Chc nng: lm 1 chn ca port xung mc thp.
C hiu lc: lnh ny p dng cho tt c cc thit b.
V d output_low(pin_a0); // lm cho chn RA0 ca PortA xung mc 0

5. LNH OUTPUT_TOGGLE(PIN) - LNH O TRNG THI CA 1 CHN
C php: output_toggle(pin);
Thng s: pin l chn xut d liu - hy xem file nh ngha ca thit b "device.h" bit tn chnh xc.
Ca. -: :x ea ey :xa: :e Wq% 7-a a.e a.e :x 7,xye C. 7x
3x Ca. 4. qa x . e--: a te q ax, :- :a : e--: :xa 79q
Chc nng: lm o trng thi 1 chn ca port.
C hiu lc: lnh ny p dng cho tt c cc thit b.
V d OUTPUT_TOGGLE(PIN_B0); // o trng thi chn RB0 ca port B

6. LNH OUTPUT_BIT(PIN,VALUE) - LNH XUT D LIU RA 1 CHN
C php: output_bit(pin,value);
Thng s: pin l chn xut d liu - hy xem file nh ngha ca thit b "device.h" bit tn chnh xc.
Chc nng: xut d liu 0 hoc 1 ra 1 chn ca port.
C hiu lc: lnh ny p dng cho tt c cc thit b.
V d: output_bit(pin_b0,0); // xut d liu 0 ra RB0

7. LNH value = GET_TRIS_X() - LNH C THANH GHI NH CU HNH
C php: value = get_tris_x();
Thng s: khng c thng s
Kt qu tr v: l byte d liu nh cu hnh t thanh ghi TRIS
Chc nng: kt qu tr v l gi tr ca thanh ghi TRIS ca cc port A, B, C or D.
C hiu lc: lnh ny p dng cho tt c cc thit b.

8. LNH value = INPUT(pin) - LNH C D LIU T 1 CHN CA PORT
C php: value = input(pin);
Thng s: pin l chn c - hy xem file nh ngha ca thit b "device.h" bit tn chnh xc
Kt qu tr v: 0 (or FALSE) nu chn mc thp, 1 (or TRUE) nu chn mc cao.
Chc nng: c d liu 1 bit t 1 chn ca port, chn ny phi cu hnh l chn vo.
C hiu lc: lnh ny p dng cho tt c cc thit b.
V d while (! Input (PIN_B1)); //i cho n khi chn Rb1 ln mc cao
If (input(PIN_A0))
Printf(A0 is now high \r\n);
Int16 i = PIN_B1
Whiel (!i); //i chn RB1 ln mc cao

9. LNH INPUT_STATE() - LNH C TRNG THI NG VO
C php: value = input_state(pin);
Thng s: pin l chn c - hy xem file nh ngha ca thit b "device.h" bit tn chnh xc
Tr v: kt qu c bng 1 nu chn c mc cao, kt qu c bng 0 nu chn c mc thp.
Chc nng: lnh c mc logic ca 1 chn nhng khng lm thay i hng ca chn.
C hiu lc: lnh ny p dng cho tt c cc thit b.
V d level = input_state(pin_A3);

10. Value = INPUT_X() - LNH C D LIU T PORTX
Ca. -: :x ea ey :xa: :e Wq% 7-a a.e a.e :x 7,xye C. 7x
Ca. 4. qa x . e--: a te q ax, :- :a : e--: :xa 79q 3?
C php: value = input_x();
Thng s: khng c.
Kt qu tr v: l d liu 8 bit ca portx.
Chc nng: lnh c mc logic ca 1 chn nhng khng lm thay i hng ca chn.
C hiu lc: lnh ny p dng cho tt c cc thit b.

11. LNH INPUT_STATE() - LNH C TRNG THI NG VO
C php: value = input_state(pin);
Thng s: pin l chn c - hy xem file nh ngha ca thit b "device.h" bit tn chnh xc
Tr v: kt qu c bng 1 nu chn c mc cao, kt qu c bng 0 nu chn c mc thp.
Chc nng: lnh c mc logic ca 1 chn nhng khng lm thay i hng ca chn.
C hiu lc: lnh ny p dng cho tt c cc thit b.
V d level = input_state(pin_A3);
12. LNH OUTPUT_DRIVE(PIN) - LNH C TRNG THI NG VO
C php: output_drive(pin);
Thng s: pin l chn c nh ngha trong file "device.h".
Tr v: khng c.
Chc nng: thit lp chn (pin) l ch xut.
C hiu lc: lnh ny p dng cho tt c cc thit b.
V d output (pin_A0);

13. LNH OUTPUT_FLOAT(PIN) - LNH TH NI CHN TN HIU
C php: output_float(pin);
Thng s: pin l chn c nh ngha trong file "device.h".
Tr v: khng c.
Chc nng: thit lp chn (pin) l ch nhp v th ni chn tn hiu ny thit b khc bn ngoi
ton quyn iu khin chn ny a d liu vo vi iu khin.
C hiu lc: lnh ny p dng cho tt c cc thit b.
V d if ((data & 0x80) == 0)
Output_low (pin_A0);
else output_float (pin_A0);

14. LNH PORT_B_PULLUP( ) - LNH TREO PORT B QUA IN TR LN NGUN
C php: port_b_pullup(value);
Thng s: value c 2 gi tr l true v false.
Tr v: khng c.
Chc nng: thit lp port B treo ln ngun qua in tr ko ln bn trong. Nu value l true th treo ln
ngun, nu l false th khng treo.
C hiu lc: lnh ny p dng cho tt c cc thit b.
Ca. -: :x ea ey :xa: :e Wq% 7-a a.e a.e :x 7,xye C. 7x
40 Ca. 4. qa x . e--: a te q ax, :- :a : e--: :xa 79q
V d port_b_pullup(false);


IV. CC CHNG TRNH V D CHO CC PORT

BI 4-1 IU KHIN: 4 LED SNG V 4 LED TT S DNG PORTB
#INCLUDE <16F877A.H>
#FUSES NOWDT,PUT,HS,NOPROTECT,NOLVP

VOID MAIN()
{ SET_TRIS_B(0x00); //PORTB LA OUTPUT
WHILE(1)
{
OUTPUT_B(0x0F); //4 LED TAT 4 LED SANG
}
}

BI 4-2 IU KHIN 8 LED CA PORTB CHP TT 8 LED

LNH: DELAY_MS(VALUE) - DELAY MS
LNH: DELAY_US(VALUE) - DELAY S

#INCLUDE <16F877A.H>
#FUSES NOWDT,PUT,HS,NOPROTECT,NOLVP
#USE DELAY(CLOCK=20000000) //CRYSTAL = 20MHZ
VOID MAIN()
{ SET_TRIS_B(0x00); //PORTB LA OUTPUT
WHILE(1)
{ OUTPUT_B(0xFF); //8 LED SANG
DELAY_MS(1000); // GOI HAM DELAY

OUTPUT_B(0x00); // 8 LED TAT
DELAY_MS(1000);
}
}

BI 4-3 PORTB CHP TT 8 LED 5 LN

#INCLUDE <16F877A.H>
#FUSES NOWDT,PUT,HS,NOPROTECT,NOLVP
#USE DELAY(CLOCK=20000000)
INT I;
VOID MAIN()
{ SET_TRIS_B(0x00); //PORTB LA OUTPUT
I=0;
WHILE(I<5)
{ OUTPUT_B(0xFF); //8 LED SANG
DELAY_MS(500); // GOI HAM DELAY

OUTPUT_B(0x00); // 8 LED TAT
Ca. -: :x ea ey :xa: :e Wq% 7-a a.e a.e :x 7,xye C. 7x
Ca. 4. qa x . e--: a te q ax, :- :a : e--: :xa 79q 4I
DELAY_MS(500);
I++; //TANG I LEN 1
}
}

BI 4-4 PORTB C 1 LED CHP TT NI VI RB0 CC BIT CN LI KHNG NH HNG
#INCLUDE <16F877A.H>
#FUSES NOWDT,PUT,HS,NOPROTECT,NOLVP
#USE DELAY(CLOCK=20000000)

VOID MAIN()
{ SET_TRIS_B(0x00); //PORTB LA OUTPUT
WHILE(1)
{ OUTPUT_HIGH(PIN_B0); // LED SANG
DELAY_MS(100); // GOI HAM DELAY

OUTPUT_LOW(PIN_B0); // LED TAT
DELAY_MS(100);
}
}

BI 4-5 N GIAO THNG XANH SNG 15S, VNG 5 GIY, 21GIY,
CHA HIN TH THI GIAN

#INCLUDE <16F877A.H>
#FUSES NOWDT,PUT,HS,NOPROTECT,NOLVP
#USE DELAY(CLOCK=20000000)
#DIFINE X1D2 0X84 ; //1000 0100
#DIFINE V1D2 0X44 ; //0100 0100
#DIFINE D1X2 0X21 ; //0010 0001
#DIFINE D1V2 0X22 ; //0010 0010

VOID MAIN()
{ SET_TRIS_B(0x00); //PORTB LA OUTPUT
WHILE(1)
{ OUTPUT_B(X1D2); //10000100
DELAY_MS(15000); // GOI HAM DELAY

OUTPUT_B(V1D2);
DELAY_MS(5000);

OUTPUT_B(D1X2);
DELAY_MS(15000);

OUTPUT_B(D1V2);
DELAY_MS(5000);
}
}

BI 4-6 PORTB 1 LED CHP TT NI VI RB0 DNG LNH OUTPUT_TOGGLE()
#INCLUDE <16F877A.H>
#FUSES NOWDT,PUT,HS,NOPROTECT,NOLVP
#USE DELAY(CLOCK=20000000)
Ca. -: :x ea ey :xa: :e Wq% 7-a a.e a.e :x 7,xye C. 7x
48 Ca. 4. qa x . e--: a te q ax, :- :a : e--: :xa 79q

VOID MAIN()
{ SET_TRIS_B(0x00);
WHILE(1)
{ OUTPUT_TOGGLE(PIN_B0); // AO TT CUA LED
DELAY_MS(100); // GOI HAM DELAY
}
}

BI 4-7 PORTB 1 LED CHP TT NI VI RB0 DNG LNH OUTPUT_BIT(PIN,VALUE)
#INCLUDE <16F877A.H>
#FUSES NOWDT,PUT,HS,NOPROTECT,NOLVP
#USE DELAY(CLOCK=20000000)

VOID MAIN()
{ SET_TRIS_B(0x00); //PORTB LA OUTPUT
WHILE(1)
{ OUTPUT_BIT(PIN_B4,0); // LED TAT
DELAY_MS(100); // GOI HAM DELAY

OUTPUT_BIT(PIN_B4,1); // LED SANG
DELAY_MS(100);
}


V. CC CHNG TRNH V D IU KHIN LED 7 ON

CACH KHAI BAO KIEU HANG SO MANG K T
CONST UNSIGNED CHAR
MA7DOAN[10]={0xC0,0xF9,0xA4,0xB0,0x99,0x92,0x82,0xF8,0x80, 0x90};

CACH KHAI BAO BIEN KIEU SO NGUYEN KIEU INTEGER:
INT DONVI; - KHAI BAO BIEN DONVI 8 BIT;
INT16 DONVI; - KHAI BAO BIEN DONVI 16 BIT;
XEM TRONG PHAN TR GIUP CUA CHNG TRNH
Type-Specifier
int1 Defines a 1 bit number
int8 Defines an 8 bit number
int16 Defines a 16 bit number
int32 Defines a 32 bit number
char Defines a 8 bit character
float Defines a 32 bit floating point number
short By default the same as int1
Int By default the same as int8
long By default the same as int16
void Indicates no specific type

BI 4-8 : IU KHIN LED 7 ON M THI GIAN T 0 N 9 DNG PORTB

Ca. -: :x ea ey :xa: :e Wq% 7-a a.e a.e :x 7,xye C. 7x
Ca. 4. qa x . e--: a te q ax, :- :a : e--: :xa 79q 43
S MCH IN GIAO TIP PIC VI 1 LED 7 ON

Hnh 4-19: S mch iu khin led 7 on.

#INCLUDE <16F877A.H>
#FUSES NOWDT,PUT,HS,NOPROTECT,NOLVP
#USE DELAY(CLOCK=20000000)

CONST UNSIGNED CHAR
MA7DOAN[10]={0xC0,0xF9,0xA4,0xB0,0x99,0x92,0x82,0xF8,0x80,0x90};

INT I; // BIEN DEM
UNSIGNED CHAR MI; // BIEN CHUA MA 7 DOAN

VOID MAIN()
{ SET_TRIS_B(0x00); //PORTB OUT
WHILE(1)
{
FOR (I=0; I<10; I++)
{ MI= MA7DOAN [I]; //LAY MA 7 D
OUTPUT_B(MI);
DELAY_MS(500);
}
}
}

BI 4-10 : IU KHIN LED 7 ON M THI GIAN T 9 XUNG 0 DNG PORTB

#INCLUDE <16F877A.H>
#FUSES NOWDT,PUT,HS,NOPROTECT,NOLVP
#USE DELAY(CLOCK=20000000)
CONST UNSIGNED CHAR
Ca. -: :x ea ey :xa: :e Wq% 7-a a.e a.e :x 7,xye C. 7x
44 Ca. 4. qa x . e--: a te q ax, :- :a : e--: :xa 79q
MA7DOAN[10]={0xC0,0xF9,0xA4,0xB0,0x99,0x92,0x82,0xF8,0x80, 0x90};
SIGNED INT I; // BIEN DEM KIEU CO DAU
UNSIGNED CHAR MI; // BIEN CHUA MA 7 DOAN
VOID MAIN()
{ SET_TRIS_B(0x00); //PORTC OUT
WHILE(1)
{
FOR (I=9; I>-1; I--)
{ MI= MA7DOAN [I]; //LAY MA 7 D
OUTPUT_B(MI);
DELAY_MS(500);
}
}
}

LENH WHILE(CONDITION)
{
STATEMENTS;

}
LENH FOR(I=MIN-VALUE;I<MAX-VALUE;I++)
{
STATEMENTS;

}

BI 4-11 : IU KHIN LED 7 ON M THI GIAN T 00 N 99 HIN TH TRN 2 LED
DNG PORTB V PORTD.

LNH CHIA NGUYN LY KT QU /
X = Y /10; (V D Y = 95 TH KT QU X = 9)
LNH CHIA NGUYN LY S D %
Z = Y % 10; (V D Y = 95 TH KT QU Z = 5)
S MCH IN GIAO TIP PIC VI 2 LED 7 ON
Ca. -: :x ea ey :xa: :e Wq% 7-a a.e a.e :x 7,xye C. 7x
Ca. 4. qa x . e--: a te q ax, :- :a : e--: :xa 79q 45

Hnh 4-20: S mch iu khin led 7 on.
CHNG TRNH
#INCLUDE <16F877A.H>
#FUSES NOWDT,PUT,HS,NOPROTECT,NOLVP
#USE DELAY(CLOCK=20000000)
CONST UNSIGNED CHAR
MA7DOAN[10]={0xC0,0xF9,0xA4,0xB0,0x99,0x92,0x82,0xF8,0x80, 0x90};

INT DEM, DONVI, CHUC; // BIEN DEM
UNSIGNED CHAR MDONVI, MCHUC; // BIEN CHUA MA 7 DOAN

VOID MAIN()
{ SET_TRIS_B(0x00); //PORTB OUT
SET_TRIS_C(0x00); // PORTC OUT

WHILE(1)
{
FOR (DEM=0;DEM<100;DEM++)
{ CHUC =DEM /10; //LAY HANG CHUC
DONVI= DEM %10; //LAY DONVI

MDONVI= MA7DOAN[DONVI]; //LAY MA 7 D
MCHUC = MA7DOAN[CHUC]; //LAY MA 7 D

OUTPUT_B(MDONVI);
OUTPUT_C(MCHUC);
DELAY_MS(300);
}
}
}

BI 4-12 : IU KHIN LED 7 ON M THI GIAN T 00 N 99 HIN TH TRN 2 LED
DNG PORTB V PORTD - DNG 2 VNG LP FOR.
Ca. -: :x ea ey :xa: :e Wq% 7-a a.e a.e :x 7,xye C. 7x
46 Ca. 4. qa x . e--: a te q ax, :- :a : e--: :xa 79q

#INCLUDE <16F877A.H>
#FUSES NOWDT,PUT,HS,NOPROTECT,NOLVP
#USE DELAY(CLOCK=20000000)
CONST UNSIGNED CHAR
MA7DOAN[10]={0xC0,0xF9,0xA4,0xB0,0x99,0x92,0x82,0xF8,0x80, 0x90};

INT DONVI, CHUC;
VOID MAIN()
{ SET_TRIS_B(0x00); //PORTB OUT
SET_TRIS_C(0x00); // PORTC OUT
WHILE(1)
{
FOR (CHUC=0; CHUC<10; CHUC++)
{
FOR (DONVI=0; DONVI<10; ++DONVI)
{
OUTPUT_B(MA7DOAN[DONVI]);
OUTPUT_C(MA7DOAN[CHUC]);
DELAY_MS(300);
}
}
}
}
CCH NY C HN CH L KHNG TH M S BT K V D M T 00 N 15.
http://www.mikroe.com/eng/chapters/view/2/chapter-1-pic16f887-microcontroller-device-overview/

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