Bi 421.

entity DAHOP_4KE is Port ( E : in STD_LOGIC; S : in STD_LOGIC_VECTOR (1 downto 0); I : in STD_LOGIC_VECTOR (3 downto 0); Q : out STD_LOGIC); end DAHOP_4KE; architecture Behavioral of DAHOP_4KE is begin PROCESS (S,I,E) BEGIN IF E='1' THEN CASE S IS WHEN "00" WHEN "01" WHEN "10" WHEN "11" WHEN OTHERS => END CASE; ELSE Q<='0'; END IF; END PROCESS; end Behavioral; bi 422. entity DAHOP_4KED is Port ( E : in STD_LOGIC; S : in STD_LOGIC_VECTOR (1 downto 0); I : in STD_LOGIC_VECTOR (3 downto 0); Q : out STD_LOGIC; QD : out STD_LOGIC); end DAHOP_4KED; architecture Behavioral of DAHOP_4KED is SIGNAL QT: STD_LOGIC; begin PROCESS (S,I,E) BEGIN IF E='1' THEN CASE S IS WHEN "00" WHEN "01" WHEN "10" WHEN "11" WHEN OTHERS => END CASE; ELSE QT <='0'; END IF; Q <= QT; QD <= NOT QT; END PROCESS; end Behavioral; bi 430. entity GIAIDAHOP_4K is Port ( I : in STD_LOGIC; S : in STD_LOGIC_VECTOR (1 downto 0); Q : out STD_LOGIC_VECTOR (3 downto 0)); end GIAIDAHOP_4K; architecture Behavioral of GIAIDAHOP_4K is begin PROCESS (I,S) BEGIN CASE S IS WHEN "00" => Q <="000"&I; WHEN "01" => Q <= "00" &I & '0'; WHEN "10" => Q <= '0'&I&"00"; WHEN "11" => Q <= I & "000"; WHEN OTHERS => NULL;

=> => => => NULL;

Q Q Q Q

<= <= <= <=

I(0); I(1); I(2); I(3);

=> => => => NULL;

QT QT QT<= QT

<= <= I(2); <=

I(0); I(1); I(3);

END CASE ; END PROCESS; end Behavioral; bi 431. entity GIAIDAHOP_4KE is Port ( E : in STD_LOGIC; S : in STD_LOGIC_VECTOR (1 downto 0); I : in STD_LOGIC; Q : out STD_LOGIC_VECTOR (3 downto 0)); end GIAIDAHOP_4KE; architecture Behavioral of GIAIDAHOP_4KE is begin PROCESS (I,S,E) BEGIN IF E = '1' THEN CASE S IS WHEN "00" => Q <="000"&I; WHEN "01" => Q <= "00" &I & '0'; WHEN "10" => Q <= '0'&I&"00"; WHEN "11" => Q <= I & "000"; WHEN OTHERS => NULL; END CASE ; ELSE Q <= "0000"; END IF ; END PROCESS; end Behavioral; bi 432. entity GIAIDAHOP_8K is Port ( I : in STD_LOGIC; S : in STD_LOGIC_VECTOR (2 downto 0); Q : out STD_LOGIC_VECTOR (7 downto 0)); end GIAIDAHOP_8K; architecture Behavioral of GIAIDAHOP_8K is begin PROCESS (I,S) BEGIN CASE S IS WHEN "000" => Q <="0000000"&I; WHEN "001" => Q <= "000000" &I & '0'; WHEN "010" => Q <= "00000"&I&"00"; WHEN "011" => Q <= "0000"&I & "000"; WHEN "100" => Q <= "000"&I & "0000"; WHEN "101" => Q <= "00"&I & "00000"; WHEN "110" => Q <= "0"&I & "000000"; WHEN "111" => Q <= I & "0000000"; WHEN OTHERS => NULL; END CASE ; END PROCESS; end Behavioral; bi 433. entity GAIDAHOP_8KE is Port ( E : in STD_LOGIC; S : in STD_LOGIC_VECTOR (2 downto 0); I : in STD_LOGIC; Q : out STD_LOGIC_VECTOR (7 downto 0)); end GAIDAHOP_8KE; architecture Behavioral of GAIDAHOP_8KE is begin PROCESS (I,S,E) BEGIN IF E = '1' THEN CASE S IS WHEN "000" => Q <="0000000"&I; WHEN "001" => Q <= "000000" &I & '0'; WHEN "010" => Q <= "00000"&I&"00"; WHEN "011" => Q <= "0000"&I & "000"; WHEN "100" => Q <= "000"&I & "0000"; WHEN "101" => Q <= "00"&I & "00000"; WHEN "110" => Q <= "0"&I & "000000"; WHEN "111" => Q <= I & "0000000";

WHEN OTHERS => NULL; END CASE ; ELSE Q <= "00000000"; END IF ; END PROCESS; end Behavioral; bi 507 entity CHIAXUNG_1HZ is Port ( CK50MHZ : in STD_LOGIC; CK1HZ : out STD_LOGIC; CK10HZ : out STD_LOGIC); end CHIAXUNG_1HZ; architecture Behavioral of CHIAXUNG_1HZ is SIGNAL CHIA1HZ: INTEGER RANGE 0 TO 25000000:=0; SIGNAL CHIA10HZ: INTEGER RANGE 0 TO 2500000:=0; SIGNAL CK1HZT: STD_LOGIC:='0'; SIGNAL CK10HZT: STD_LOGIC:='0'; begin PROCESS (CHIA1HZ,CK50MHZ,CK1HZT) BEGIN IF FALLING_EDGE(CK50MHZ) THEN IF CHIA1HZ=25000000 THEN CHIA1HZ <=0; CK1HZT <= NOT CK1HZT; ELSE CHIA1HZ <= CHIA1HZ + 1; END IF; END IF; CK1HZ <=CK1HZT; END PROCESS; PROCESS (CHIA10HZ,CK50MHZ,CK1HZT) BEGIN IF FALLING_EDGE(CK50MHZ) THEN IF CHIA10HZ=2500000 THEN CHIA10HZ <=0; CK10HZT <= NOT CK10HZT; ELSE CHIA10HZ <= CHIA10HZ + 1; END IF; END IF; CK10HZ <=CK10HZT; END PROCESS; end Behavioral; bi 508 entity CHIAXUNG_1HZ is Port ( CK50MHZ : in STD_LOGIC; CK1HZ : out STD_LOGIC; CK10HZ : out STD_LOGIC); end CHIAXUNG_1HZ; architecture Behavioral of CHIAXUNG_1HZ is SIGNAL CHIAHEX: STD_LOGIC_VECTOR(23 DOWNTO 0):=X"000000"; SIGNAL CK1HZT: STD_LOGIC:='0'; SIGNAL CK10HZT: STD_LOGIC:='0'; SIGNAL DEM: STD_LOGIC_VECTOR(3 DOWNTO 0):=B"0000"; begin PROCESS (CHIAHEX,CK50MHZ,CK10HZT) BEGIN IF FALLING_EDGE(CK50MHZ) THEN IF CHIAHEX = X"2625A0" THEN CHIAHEX <= X"000000"; CK10HZT <= NOT CK10HZT; ELSE CHIAHEX <= CHIAHEX + 1; END IF; END IF; CK10HZ <=CK10HZT; IF FALLING_EDGE(CK10HZT) THEN IF DEM = B"1010" THEN DEM <= B"0000"; CK1HZT <= NOT CK1HZT; ELSE DEM <=DEM +1; END IF ; END IF ; CK1HZ <= CK1HZT;

END PROCESS ; end Behavioral; bi 509 entity CHIAXUNG_1HZ is Port ( CK50MHZ : in STD_LOGIC; CK1HZ : out STD_LOGIC; CK1KHZ : out STD_LOGIC); end CHIAXUNG_1HZ; architecture Behavioral of CHIAXUNG_1HZ is SIGNAL CHIAHEX: STD_LOGIC_VECTOR(24 DOWNTO 0):='0'&X"000000"; SIGNAL CK1HZT: STD_LOGIC:='0'; begin PROCESS (CHIAHEX,CK50MHZ,CK1HZT) BEGIN IF FALLING_EDGE(CK50MHZ) THEN IF CHIAHEX ='1'&X"7D7840" THEN CHIAHEX <= '0'&X"000000"; CK1HZT <= NOT CK1HZT; ELSE CHIAHEX <= CHIAHEX + 1; END IF; END IF; CK1HZ <=CK1HZT; CK1KHZ <= CHIAHEX(14); --LAY XUNG 1525HZ END PROCESS; end Behavioral; 511. entity DEMNHIPHAN_4BIT_LP is Port ( CK50MHZ : in STD_LOGIC; RST : in STD_LOGIC; P : in STD_LOGIC; Q : out STD_LOGIC_VECTOR (3 downto 0)); end DEMNHIPHAN_4BIT_LP; architecture Behavioral of DEMNHIPHAN_4BIT_LP is SIGNAL CK1HZ:STD_LOGIC; begin CHIAXUNG_1HZ: ENTITY WORK.CHIAXUNG_1HZ PORT MAP( CK50MHZ => CK50MHZ,CK1HZ => CK1HZ); DEM_NP4BIT: ENTITY WORK.DEM_NP4BIT PORT MAP (CK1HZ => CK1HZ,RST => RST,Q => Q, P=> P); end Behavioral; chng trnh con chia xung 1hz entity CHIAXUNG_1HZ is Port ( CK50MHZ : in STD_LOGIC; CK1HZ : out STD_LOGIC); end CHIAXUNG_1HZ; architecture Behavioral of CHIAXUNG_1HZ is SIGNAL CHIAHEX: STD_LOGIC_VECTOR(27 DOWNTO 0):=X"0000000"; SIGNAL CK1HZT: STD_LOGIC:='0'; begin PROCESS (CHIAHEX,CK50MHZ,CK1HZT) BEGIN IF FALLING_EDGE(CK50MHZ) THEN IF CHIAHEX = X"17D7840" THEN CHIAHEX <= X"0000000"; CK1HZT <= NOT CK1HZT; ELSE CHIAHEX <= CHIAHEX + 1; END IF; END IF; CK1HZ <=CK1HZT; END PROCESS; end Behavioral; entity DEM_NP4BIT is Port ( CK1HZ : in STD_LOGIC; RST : in STD_LOGIC; P: IN STD_LOGIC; Q : out STD_LOGIC_VECTOR (3 downto 0)); end DEM_NP4BIT; architecture Behavioral of DEM_NP4BIT is SIGNAL QT:STD_LOGIC_VECTOR(3 DOWNTO 0);

begin PROCESS(CK1HZ,RST,QT) BEGIN IF RST='1' THEN QT <= "0000"; ELSIF RISING_EDGE(CK1HZ) AND P='1' THEN QT <= QT+1; END IF; Q <= QT; END PROCESS; end Behavioral; 513. entity DEMNHIPHAN_4BIT_LXSP is Port ( CK50MHZ : in STD_LOGIC; S : in STD_LOGIC; P : in STD_LOGIC; Q : out STD_LOGIC_VECTOR (3 downto 0); RST : in STD_LOGIC); end DEMNHIPHAN_4BIT_LXSP; architecture Behavioral of DEMNHIPHAN_4BIT_LXSP is SIGNAL CK1HZ:STD_LOGIC; begin CHIAXUNG_1HZ: ENTITY WORK.CHIAXUNG_1HZ PORT MAP( CK50MHZ => CK50MHZ, CK1HZ => CK1HZ); DEM_NP4BIT_LXSP: ENTITY WORK.DEM_NP4BIT_LXSP PORT MAP (CK1HZ => CK1HZ, RST => RST, Q => Q, S => S, P => P); end Behavioral; chng trnh con chia xung nh trn entity DEM_NP4BIT_LXSP is Port ( CK1HZ : in STD_LOGIC; S : in STD_LOGIC; P : in STD_LOGIC; RST : in STD_LOGIC; Q : out STD_LOGIC_VECTOR (3 downto 0)); end DEM_NP4BIT_LXSP; architecture Behavioral of DEM_NP4BIT_LXSP is SIGNAL QT:STD_LOGIC_VECTOR(3 DOWNTO 0); begin PROCESS(CK1HZ,RST,S,P) BEGIN IF RST='1' THEN IF S = '0' THEN QT <= "0000"; ELSE QT <= "1111"; END IF; ELSIF RISING_EDGE(CK1HZ) AND P = '1' THEN IF S = '0' THEN QT <= QT+1; ELSE QT <= QT-1; END IF; END IF; Q <= QT; END PROCESS; end Behavioral; 521. entity JOHNSON_8TSP is Port ( CK50MHZ : in STD_LOGIC; RST : in STD_LOGIC; Q : out STD_LOGIC_VECTOR (7 downto 0)); end JOHNSON_8TSP; architecture Behavioral of JOHNSON_8TSP is SIGNAL CK1HZ:STD_LOGIC; begin CHIAXUNG_1HZ: ENTITY WORK.CHIAXUNG_1HZ PORT MAP( CK50MHZ => CK50MHZ, CK1HZ => CK1HZ); J_8TSP: ENTITY WORK.J_8TSP PORT MAP (CK1HZ => CK1HZ, RST => RST, Q => Q ); end Behavioral;

chia xung nh trn entity J_8TSP is Port ( CK1HZ : in STD_LOGIC; RST : in STD_LOGIC; Q : out STD_LOGIC_VECTOR (7 downto 0)); end J_8TSP; architecture Behavioral of J_8TSP is SIGNAL QT:STD_LOGIC_VECTOR(7 DOWNTO 0); begin PROCESS (CK1HZ,RST) BEGIN IF RST = '1' THEN QT <= "00000000"; ELSIF FALLING_EDGE(CK1HZ) THEN QT <= NOT QT(0) & QT(7 DOWNTO 1); END IF; Q <= QT; END PROCESS; end Behavioral; 524. entity JOHNSON_2CT is Port ( CK50MHZ : in STD_LOGIC; RST : in STD_LOGIC; Q : out STD_LOGIC_VECTOR (7 downto 0)); end JOHNSON_2CT; architecture Behavioral of JOHNSON_2CT is SIGNAL CK1HZ:STD_LOGIC; begin CHIAXUNG_1HZ: ENTITY WORK.CHIAXUNG_1HZ PORT MAP( CK50MHZ => CK50MHZ, nCK1HZ => CK1HZ); J_8BIT_2CT: ENTITY WORK.J_8B_2CT PORT MAP (CK1HZ => CK1HZ, RST => RST, Q => Q ); end Behavioral; entity J_8B_2CT is Port ( CK1HZ : in STD_LOGIC; RST : in STD_LOGIC; Q : out STD_LOGIC_VECTOR (7 downto 0)); end J_8B_2CT; architecture Behavioral of J_8B_2CT is SIGNAL QT:STD_LOGIC_VECTOR(7 DOWNTO 0); begin PROCESS (CK1HZ,RST) VARIABLE DEM:INTEGER RANGE 0 TO 16 := 0; BEGIN IF RST ='1' THEN QT <="00000000"; ELSIF FALLING_EDGE(CK1HZ) THEN IF DEM < 8 THEN QT(3 DOWNTO 0 )<= QT(2 DOWNTO 0) & NOT QT(3) ; QT(7 DOWNTO 4) <= NOT QT(4) & QT(7 DOWNTO 5); ELSE QT(7 DOWNTO 4 )<= QT(6 DOWNTO 4) & NOT QT(7) ; QT(3 DOWNTO 0) <= NOT QT(0) & QT(3 DOWNTO 1); END IF; IF DEM = 15 THEN DEM:= 0; ELSE DEM :=DEM +1; END IF; END IF; Q <= QT; END PROCESS; end Behavioral; 525. entity JOHNSON_4CT is Port ( CK50MHZ : in STD_LOGIC; RST : in STD_LOGIC; Q : out STD_LOGIC_VECTOR (7 downto 0)); end JOHNSON_4CT; architecture Behavioral of JOHNSON_4CT is SIGNAL CK1HZ:STD_LOGIC; begin CHIAXUNG_1HZ: ENTITY WORK.CHIAXUNG_1HZ

PORT MAP( CK50MHZ => CK50MHZ, CK1HZ => CK1HZ); J_8BIT_4CT: ENTITY WORK.J_8BIT_4CT PORT MAP (CK1HZ => CK1HZ, RST => RST, Q => Q ); end Behavioral; entity J_8BIT_4CT is Port ( CK1HZ : in STD_LOGIC; RST : in STD_LOGIC; Q : out STD_LOGIC_VECTOR (7 downto 0)); end J_8BIT_4CT; architecture Behavioral of J_8BIT_4CT is SIGNAL QT:STD_LOGIC_VECTOR(7 DOWNTO 0); begin PROCESS (CK1HZ,RST) VARIABLE DEM:INTEGER RANGE 0 TO 48 := 0; BEGIN IF RST ='1' THEN QT <="00000000"; ELSIF FALLING_EDGE(CK1HZ) THEN IF DEM <16 THEN QT <= QT(6 DOWNTO 0) & NOT QT(7); ELSIF DEM < 32 THEN QT <= NOT QT(0) & QT( 7 DOWNTO 1); ELSIF DEM < 40 THEN QT(3 DOWNTO 0 )<= QT(2 DOWNTO 0) & NOT QT(3) ; QT(7 DOWNTO 4) <= NOT QT(4) & QT(7 DOWNTO 5); ELSE QT(7 DOWNTO 4 )<= QT(6 DOWNTO 4) & NOT QT(7) ; QT(3 DOWNTO 0) <= NOT QT(0) & QT(3 DOWNTO 1); END IF; IF DEM = 47 THEN DEM:=0; ELSE DEM := DEM +1; END IF ; END IF; Q <= QT; END PROCESS; end Behavioral; 541 entity DEMLEN_NP4BIT_HT_LED7DOAN is Port ( CK50MHZ : in STD_LOGIC; RST : in STD_LOGIC; ANODE : out STD_LOGIC_VECTOR (3 downto 0); SSEG : out STD_LOGIC_VECTOR (7 downto 0)); end DEMLEN_NP4BIT_HT_LED7DOAN; architecture Behavioral of DEMLEN_NP4BIT_HT_LED7DOAN is SIGNAL CK1HZ: STD_LOGIC; SIGNAL HEX: STD_LOGIC_VECTOR(3 DOWNTO 0); begin CHIAXUNG_1HZ: ENTITY WORK.CHIAXUNG_1HZ PORT MAP (CK50MHZ => CK50MHZ, CK1HZ => CK1HZ); DEM_NP4BIT: ENTITY WORK.DEM_NP4BIT PORT MAP (CK1HZ => CK1HZ, RST => RST, HEX => HEX); GIAIMA_7DOAN: ENTITY WORK.GIAIMA_7DOAN PORT MAP (HEX => HEX, SSEG => SSEG); ANODE <= "1110"; -- CAP NGUON CHO LED THU NHAT SANG end Behavioral; entity DEM_NP4BIT is Port ( CK1HZ : in STD_LOGIC; RST : in STD_LOGIC; HEX : out STD_LOGIC_VECTOR (3 downto 0)); end DEM_NP4BIT; architecture Behavioral of DEM_NP4BIT is SIGNAL HEXT : STD_LOGIC_VECTOR( 3 DOWNTO 0); begin PROCESS( CK1HZ,RST) BEGIN IF RST='1' THEN HEXT <= "1111"; ELSIF FALLING_EDGE(CK1HZ) THEN HEXT <= HEXT -1; END IF ; HEX <= HEXT; END PROCESS; end Behavioral; entity GIAIMA_7DOAN is Port ( HEX : in STD_LOGIC_VECTOR (3 downto 0);

SSEG : out STD_LOGIC_VECTOR (7 downto 0)); end GIAIMA_7DOAN; architecture Behavioral of GIAIMA_7DOAN is begin PROCESS(HEX) BEGIN CASE HEX IS WHEN "0000" => SSEG WHEN "0001" => SSEG WHEN "0010" => SSEG WHEN "0011" => SSEG WHEN "0100" => SSEG WHEN "0101" => SSEG WHEN "0110" => SSEG WHEN "0111" => SSEG WHEN "1000" => SSEG WHEN "1001" => SSEG WHEN "1010" => SSEG WHEN "1011" => SSEG WHEN "1100" => SSEG WHEN "1101" => SSEG WHEN "1110" => SSEG WHEN OTHERS => SSEG END CASE; END PROCESS; end Behavioral; 542. entity DEMLEN_NP4BIT_HT_LED7DOAN is Port ( CK50MHZ : in STD_LOGIC; RST : in STD_LOGIC; ANODE : out STD_LOGIC_VECTOR (3 downto 0); SSEG : out STD_LOGIC_VECTOR (7 downto 0)); end DEMLEN_NP4BIT_HT_LED7DOAN;

<= X"C0"; <= X"F9"; <= X"A4"; <= X"B0"; <= X"99"; <= X"92"; <= X"82"; <= X"F8"; <= X"80"; <= X"90"; <= X"88"; <= X"83"; <= X"C6"; <= X"A1"; <= X"86"; <= X"8E";

architecture Behavioral of DEMLEN_NP4BIT_HT_LED7DOAN is SIGNAL CK1HZ: STD_LOGIC; SIGNAL HEX: STD_LOGIC_VECTOR(3 DOWNTO 0); begin CHIAXUNG_1HZ: ENTITY WORK.CHIAXUNG_1HZ PORT MAP (CK50MHZ => CK50MHZ, CK1HZ => CK1HZ); DEM_NP4BIT: ENTITY WORK.DEM_NP4BIT PORT MAP (CK1HZ => CK1HZ, RST => RST,HEX => HEX); GIAIMA_7DOAN: ENTITY WORK.GIAIMA_7DOAN PORT MAP (HEX => HEX, SSEG => SSEG); ANODE <= "1110"; -- CAP NGUON CHO LED THU NHAT SANG end Behavioral; entity DEM_NP4BIT is Port ( CK1HZ : in STD_LOGIC; RST : in STD_LOGIC; HEX : out STD_LOGIC_VECTOR (3 downto 0)); end DEM_NP4BIT; architecture Behavioral of DEM_NP4BIT is SIGNAL HEXT : STD_LOGIC_VECTOR( 3 DOWNTO 0); begin PROCESS( CK1HZ,RST) BEGIN IF RST='1' THEN HEXT <= "0000"; ELSIF FALLING_EDGE(CK1HZ) THEN IF HEXT ="1010" THEN HEXT <= "0000"; ELSE HEXT <= HEXT +1; END IF ; END IF ; HEX <= HEXT; END PROCESS; end Behavioral; entity GIAIMA_7DOAN is Port ( HEX : in STD_LOGIC_VECTOR (3 downto 0); SSEG : out STD_LOGIC_VECTOR (7 downto 0));

end GIAIMA_7DOAN; architecture Behavioral of GIAIMA_7DOAN is begin PROCESS(HEX) BEGIN CASE HEX IS WHEN "0000" => SSEG <= X"C0"; WHEN "0001" => SSEG <= X"F9"; WHEN "0010" => SSEG <= X"A4"; WHEN "0011" => SSEG <= X"B0"; WHEN "0100" => SSEG <= X"99"; WHEN "0101" => SSEG <= X"92"; WHEN "0110" => SSEG <= X"82"; WHEN "0111" => SSEG <= X"F8"; WHEN "1000" => SSEG <= X"80"; WHEN "1001" => SSEG <= X"90"; WHEN "1010" => SSEG <= X"88"; WHEN "1011" => SSEG <= X"83"; WHEN "1100" => SSEG <= X"C6"; WHEN "1101" => SSEG <= X"A1"; WHEN "1110" => SSEG <= X"86"; WHEN OTHERS => SSEG <= X"8E"; END CASE; END PROCESS; end Behavioral; 544. entity DEM_00LEN99_HT_7DOAN is Port ( CK50MHZ : in STD_LOGIC; RST : in STD_LOGIC; ANODE : out STD_LOGIC_VECTOR (3 downto 0); SSEG : out STD_LOGIC_VECTOR (7 downto 0)); end DEM_00LEN99_HT_7DOAN; architecture Behavioral of DEM_00LEN99_HT_7DOAN is SIGNAL CK1HZ,CKQ:STD_LOGIC; SIGNAL BCD,BCD0,BCD1:STD_LOGIC_VECTOR( 3 DOWNTO 0); begin CHIAXUNG_1HZ: ENTITY WORK.CHIAXUNG_1HZ PORT MAP (CK50MHZ => CK50MHZ, CK1HZ => CK1HZ, CKQ => CKQ); DEM_00_99: ENTITY WORK.DEM_99_00 PORT MAP (CK1HZ => CK1HZ, RST => RST, BCD0 => BCD0, BCD1 => BCD1); DAHOP_2K: ENTITY WORK.DAHOP_2K PORT MAP (CKQ => CKQ, BCD => BCD, BCD0 => BCD0, BCD1 => BCD1, ANODE => ANODE); GIAIMA_7DOAN: ENTITY WORK.GIAIMA_7DOAN PORT MAP (BCD => BCD, SSEG => SSEG); end Behavioral; entity DEM_00_99 is Port ( CK1HZ : in STD_LOGIC; RST : in STD_LOGIC; BCD0 : out STD_LOGIC_VECTOR (3 downto 0); BCD1 : out STD_LOGIC_VECTOR (3 downto 0)); end DEM_99_00; architecture Behavioral of DEM_00_99 is SIGNAL BCD0T:STD_LOGIC_VECTOR( 3 DOWNTO 0):="0000"; SIGNAL BCD1T:STD_LOGIC_VECTOR( 3 DOWNTO 0):="0000"; begin PROCESS(CK1HZ,RST,BCD0T,BCD1T) BEGIN

IF RST='1' THEN BCD0T <= "1001"; BCD1T <= "1001"; ELSIF RISING_EDGE(CK1HZ) THEN IF BCD0T ="0000" THEN BCD0T <= "1001"; IF BCD1T ="0000" THEN BCD1T <="1001"; ELSE BCD1T <= BCD1T -1; END IF; ELSE BCD0T <= BCD0T-1; END IF ; END IF ; BCD0 <= BCD0T; BCD1 <= BCD1T; END PROCESS; end Behavioral; entity DAHOP_2K is Port ( CKQ : in STD_LOGIC; BCD0 : in STD_LOGIC_VECTOR (3 downto 0); BCD1 : in STD_LOGIC_VECTOR (3 downto 0); BCD : out STD_LOGIC_VECTOR (3 downto 0); ANODE : out STD_LOGIC_VECTOR (3 downto 0)); end DAHOP_2K; architecture Behavioral of DAHOP_2K is begin PROCESS(BCD0,BCD1,CKQ) BEGIN CASE CKQ IS WHEN '0' => BCD <= BCD0; ANODE <="1110"; WHEN OTHERS => BCD <=BCD1; ANODE <="1101"; END CASE ; END PROCESS; end Behavioral; entity GIAIMA_7DOAN is Port ( BCD : in STD_LOGIC_VECTOR (3 downto 0); SSEG : out STD_LOGIC_VECTOR (7 downto 0)); end GIAIMA_7DOAN; architecture Behavioral of GIAIMA_7DOAN is begin PROCESS(BCD) BEGIN CASE BCD IS WHEN "0000" => SSEG <= X"C0"; WHEN "0001" => SSEG <= X"F9"; WHEN "0010" => SSEG <= X"A4"; WHEN "0011" => SSEG <= X"B0"; WHEN "0100" => SSEG <= X"99"; WHEN "0101" => SSEG <= X"92"; WHEN "0110" => SSEG <= X"82"; WHEN "0111" => SSEG <= X"F8"; WHEN "1000" => SSEG <= X"80"; WHEN "1001" => SSEG <= X"90"; WHEN OTHERS => SSEG <= X"FF"; END CASE; END PROCESS; end Behavioral; 545. entity DEM_00LEN59_HT_7DOAN is Port ( CK50MHZ : in STD_LOGIC; RST : in STD_LOGIC; ANODE : out STD_LOGIC_VECTOR (3 downto 0); SSEG : out STD_LOGIC_VECTOR (7 downto 0)); end DEM_00LEN59_HT_7DOAN; architecture Behavioral of DEM_00LEN59_HT_7DOAN is SIGNAL CK1HZ,CKQ:STD_LOGIC; SIGNAL BCD,BCD0,BCD1:STD_LOGIC_VECTOR( 3 DOWNTO 0); begin CHIAXUNG_1HZ: ENTITY WORK.CHIAXUNG_1HZ

PORT MAP (CK50MHZ => CK50MHZ, CK1HZ => CK1HZ, CKQ => CKQ); DEM_00_59: ENTITY WORK.DEM_00_59 PORT MAP (CK1HZ => CK1HZ, RST => RST, BCD0=> BCD0, BCD1 DAHOP_2K: ENTITY WORK.DAHOP_2K PORT MAP (CKQ => CKQ, BCD => BCD, BCD0 => ANODE => ANODE); GIAIMA_7DOAN: ENTITY WORK.GIAIMA_7DOAN PORT MAP (BCD => BCD, SSEG => SSEG); end Behavioral; entity DEM_00_59 is Port ( CK1HZ : in STD_LOGIC; BCD0 : out STD_LOGIC_VECTOR (3 downto 0); BCD1 : out STD_LOGIC_VECTOR (3 downto 0); RST : in STD_LOGIC); end DEM_00_59; architecture Behavioral of DEM_00_59 is SIGNAL BCD0T:STD_LOGIC_VECTOR( 3 DOWNTO 0):="0000"; SIGNAL BCD1T:STD_LOGIC_VECTOR( 3 DOWNTO 0):="0000"; begin PROCESS(CK1HZ,RST,BCD0T,BCD1T) BEGIN IF RST='1' THEN BCD0T <= "0000"; BCD1T <= "0000"; ELSIF RISING_EDGE(CK1HZ) THEN IF BCD0T ="1001" THEN BCD0T <= "0000"; IF BCD1T ="0101" THEN BCD1T <="0000"; ELSE BCD1T <= BCD1T +1; END IF; ELSE BCD0T <= BCD0T+1; END IF ; END IF ; BCD0 <= BCD0T; BCD1 <= BCD1T; END PROCESS; end Behavioral; entity DAHOP_2K is Port ( CKQ : in STD_LOGIC; BCD0 : in STD_LOGIC_VECTOR (3 downto 0); BCD1 : in STD_LOGIC_VECTOR (3 downto 0); BCD : out STD_LOGIC_VECTOR (3 downto 0); ANODE : out STD_LOGIC_VECTOR (3 downto 0)); end DAHOP_2K; architecture Behavioral of DAHOP_2K is begin PROCESS(BCD0,BCD1,CKQ) BEGIN CASE CKQ IS WHEN '0' => BCD <= BCD0; ANODE <="1110"; WHEN OTHERS => BCD <=BCD1; ANODE <="1101"; END CASE ; END PROCESS; end Behavioral; entity GIAIMA_7DOAN is Port ( BCD : in STD_LOGIC_VECTOR (3 downto 0); SSEG : out STD_LOGIC_VECTOR (7 downto 0)); end GIAIMA_7DOAN; architecture Behavioral of GIAIMA_7DOAN is begin PROCESS(BCD) BEGIN CASE BCD IS WHEN "0000" => SSEG WHEN "0001" => SSEG WHEN "0010" => SSEG WHEN "0011" => SSEG WHEN "0100" => SSEG WHEN "0101" => SSEG

=>

BCD1); => BCD1,

BCD0, BCD1

<= X"C0"; <= X"F9"; <= X"A4"; <= X"B0"; <= X"99"; <= X"92";

WHEN "0110" WHEN "0111" WHEN "1000" WHEN "1001" WHEN OTHERS END CASE; END PROCESS;

=> => => => =>

SSEG <= X"82"; SSEG <= X"F8"; SSEG <= X"80"; SSEG <= X"90"; SSEG <= X"FF";

end Behavioral; 547 entity DEM_LEN_9999_HT_7DOAN is Port ( CK50MHZ : in STD_LOGIC; RST : in STD_LOGIC; ANODE : out STD_LOGIC_VECTOR (3 downto 0); SSEG : out STD_LOGIC_VECTOR (7 downto 0)); end DEM_LEN_9999_HT_7DOAN; architecture Behavioral of DEM_LEN_9999_HT_7DOAN is SIGNAL CK1HZ: STD_LOGIC; SIGNAL CKQ: STD_LOGIC_VECTOR(1 DOWNTO 0); SIGNAL BCD,BCD0,BCD1 : STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL BCD2,BCD3: STD_LOGIC_VECTOR(3 DOWNTO 0); begin CHIAXUNG_1HZ: ENTITY WORK.CHIAXUNG_1HZ PORT MAP (CK50MHZ => CK50MHZ, CK1HZ => CK1HZ, CKQ => CKQ); DEM_9999C2: ENTITY WORK.DEM_9999C2 PORT MAP (CK1HZ => CK1HZ, RST => RST, BCD0 => BCD0,BCD2 => BCD2,BCD3 =>BCD3, BCD1 => BCD1); DAHOP_4K: ENTITY WORK.DAHOP_4K PORT MAP (CKQ => CKQ, BCD => BCD, BCD0 => BCD0, BCD1 => BCD1, BCD2 => BCD2, BCD3 => BCD3, ANODE => ANODE); GIAIMA_7DOAN: ENTITY WORK.GIAIMA_7DOAN PORT MAP (BCD => BCD, SSEG => SSEG); end Behavioral; entity CHIAXUNG_1HZ is Port ( CK50MHZ : in STD_LOGIC; CK1HZ : out STD_LOGIC; CKQ : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)); end CHIAXUNG_1HZ; architecture Behavioral of CHIAXUNG_1HZ is SIGNAL CHIAHEX: STD_LOGIC_VECTOR(27 DOWNTO 0):=X"0000000"; SIGNAL CK1HZT: STD_LOGIC:='0'; begin PROCESS (CHIAHEX,CK50MHZ,CK1HZT) BEGIN IF FALLING_EDGE(CK50MHZ) THEN IF CHIAHEX = X"17D7840" THEN CHIAHEX <= X"0000000"; CK1HZT <= NOT CK1HZT; ELSE CHIAHEX <= CHIAHEX + 1; END IF; END IF; CK1HZ <=CK1HZT; CKQ <= CHIAHEX( 14 DOWNTO 13); END PROCESS; end Behavioral; entity DEM_9999C2 is Port ( CK1HZ : in STD_LOGIC; RST : in STD_LOGIC; BCD0,BCD1,BCD2,BCD3 : OUT STD_LOGIC_VECTOR (3 downto 0)); end DEM_9999C2; architecture Behavioral of DEM_9999C2 is SIGNAL BCD0T,BCD1T,BCD2T,BCD3T :STD_LOGIC_VECTOR(3 DOWNTO 0); begin PROCESS (CK1HZ,RST,BCD0T,BCD1T,BCD2T,BCD3T)

BEGIN IF RST ='1' THEN BCD0T <="0000"; BCD1T <="0000"; BCD2T <="0000";BCD3T <="0000"; ELSIF FALLING_EDGE(CK1HZ) THEN IF BCD0T ="1001" THEN BCD0T <="0000";--KIEM TRA DON VI IF BCD1T = "1001" THEN BCD1T <="0000";-- KIEM TRA CHUC IF BCD2T = "1001" THEN BCD2T <="0000";--KIEM TRA TRAM IF BCD3T = "1001" THEN BCD3T <="0000";--KIEM TRA NGHIN ELSE BCD3T <= BCD3T+1; END IF ; ELSE BCD2T <= BCD2T+1; END IF ; ELSE BCD1T <= BCD1T+1; END IF ; ELSE BCD0T <= BCD0T+1; END IF ; END IF ; BCD0 <= BCD0T; BCD1 <= BCD1T; BCD2 <= BCD2T; BCD3 <= BCD3T; END PROCESS; end Behavioral; entity DAHOP_4K is Port ( CKQ : in STD_LOGIC_VECTOR(1 DOWNTO 0); ANODE : OUT STD_LOGIC_VECTOR (3 downto 0); BCD0 : in STD_LOGIC_VECTOR (3 downto 0); BCD1 : in STD_LOGIC_VECTOR (3 downto 0); BCD2 : in STD_LOGIC_VECTOR (3 downto 0); BCD3 : in STD_LOGIC_VECTOR (3 downto 0); BCD : out STD_LOGIC_VECTOR (3 downto 0)); end DAHOP_4K; architecture Behavioral of DAHOP_4K is begin PROCESS (CKQ,BCD0,BCD1,BCD2,BCD3) BEGIN CASE CKQ IS WHEN "00" => BCD <= BCD0; ANODE <= "1110"; WHEN "01" => BCD <= BCD1; ANODE <= "1101"; WHEN "10" => BCD <= BCD2; ANODE <= "1011"; WHEN OTHERS => BCD <= BCD2; ANODE <= "0111"; END CASE ; END PROCESS; end Behavioral; 548. entity DEM_LEN_1234_HT_7DOAN is Port ( CK50MHZ : in STD_LOGIC; RST : in STD_LOGIC; ANODE : out STD_LOGIC_VECTOR (3 downto 0); SSEG : out STD_LOGIC_VECTOR (7 downto 0)); end DEM_LEN_1234_HT_7DOAN; architecture Behavioral of DEM_LEN_9999_HT_7DOAN is SIGNAL CK1HZ: STD_LOGIC; SIGNAL CKQ: STD_LOGIC_VECTOR(1 DOWNTO 0); SIGNAL BCD,BCD0,BCD1 : STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL BCD2,BCD3: STD_LOGIC_VECTOR(3 DOWNTO 0); begin CHIAXUNG_1HZ: ENTITY WORK.CHIAXUNG_1HZ PORT MAP (CK50MHZ => CK50MHZ, CK1HZ => CK1HZ, CKQ => CKQ); DEM_9999C2: ENTITY WORK.DEM_1234C2 PORT MAP (CK1HZ => CK1HZ, RST => RST, BCD0 => BCD0,BCD2 => BCD2,BCD3 =>BCD3, BCD1 => BCD1); DAHOP_4K: ENTITY WORK.DAHOP_4K PORT MAP (CKQ => CKQ, BCD => BCD, BCD0 => BCD0, BCD1 => BCD1, BCD2 => BCD2, BCD3 => BCD3, ANODE => ANODE); GIAIMA_7DOAN: ENTITY WORK.GIAIMA_7DOAN PORT MAP (BCD => BCD, SSEG => SSEG)

end Behavioral; entity CHIAXUNG_1HZ is Port ( CK50MHZ : in STD_LOGIC; CK1HZ : out STD_LOGIC; CKQ : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)); end CHIAXUNG_1HZ; architecture Behavioral of CHIAXUNG_1HZ is SIGNAL CHIAHEX: STD_LOGIC_VECTOR(27 DOWNTO 0):=X"0000000"; SIGNAL CK1HZT: STD_LOGIC:='0'; begin PROCESS (CHIAHEX,CK50MHZ,CK1HZT) BEGIN IF FALLING_EDGE(CK50MHZ) THEN IF CHIAHEX = X"02625A0" THEN CHIAHEX <= X"0000000"; CK1HZT <= NOT CK1HZT; ELSE CHIAHEX <= CHIAHEX + 1; END IF; END IF; CK1HZ <=CK1HZT; CKQ <= CHIAHEX( 14 DOWNTO 13); END PROCESS; entity DEM_1234C2 is Port ( CK1HZ : in STD_LOGIC; RST : in STD_LOGIC; BCD0,BCD1,BCD2,BCD3 : OUT STD_LOGIC_VECTOR (3 downto 0)); end DEM_9999C2; architecture Behavioral of DEM_1234C2 is SIGNAL BCD0T,BCD1T,BCD2T,BCD3T :STD_LOGIC_VECTOR(3 DOWNTO 0); begin PROCESS (CK1HZ,RST,BCD0T,BCD1T,BCD2T,BCD3T) BEGIN IF RST ='1' THEN BCD0T <="0000"; BCD1T <="0000"; BCD2T <="0000";BCD3T <="0000"; ELSIF FALLING_EDGE(CK1HZ) THEN IF BCD0T ="1001" THEN BCD0T <="0000"; IF BCD1T = "1001" THEN BCD1T <="0000"; IF BCD2T = "1001" THEN BCD2T <="0000"; BCD3T <= BCD3T+1;--khong can kiem tra toi nghin ELSE BCD2T <= BCD2T+1; END IF ; ELSE BCD1T <= BCD1T+1; END IF ; ELSE BCD0T <= BCD0T+1; END IF ; END IF ; IF (BCD3T ="0001" AND BCD2T ="0010" AND BCD1T ="0011" AND BCD0T ="0101" )THEN BCD0T<="0000";BCD1T<="0000";BCD2T<="0000";BCD3T<="0000";END IF; BCD0 <= BCD0T; BCD1 <= BCD1T; BCD2 <= BCD2T; BCD3 <= BCD3T; END PROCESS; end Behavioral; entity DAHOP_4K is Port ( CKQ : in STD_LOGIC_VECTOR(1 DOWNTO 0); ANODE : OUT STD_LOGIC_VECTOR (3 downto 0); BCD0 : in STD_LOGIC_VECTOR (3 downto 0); BCD1 : in STD_LOGIC_VECTOR (3 downto 0); BCD2 : in STD_LOGIC_VECTOR (3 downto 0); BCD3 : in STD_LOGIC_VECTOR (3 downto 0); BCD : out STD_LOGIC_VECTOR (3 downto 0)); end DAHOP_4K; architecture Behavioral of DAHOP_4K is begin PROCESS (CKQ,BCD0,BCD1,BCD2,BCD3) BEGIN CASE CKQ IS WHEN "00" => BCD <= BCD0; ANODE <= "1110"; WHEN "01" => BCD <= BCD1; ANODE <= "1101"; WHEN "10" => BCD <= BCD2; ANODE <= "1011"; WHEN OTHERS => BCD <= BCD3; ANODE <= "0111"; END CASE ; END PROCESS; end Behavioral; 548C2

entity DEM_LEN_9999_HT_7DOAN is Port ( CK50MHZ : in STD_LOGIC; RST : in STD_LOGIC; ANODE : out STD_LOGIC_VECTOR (3 downto 0); SSEG : out STD_LOGIC_VECTOR (7 downto 0)); end DEM_LEN_9999_HT_7DOAN; architecture Behavioral of DEM_LEN_9999_HT_7DOAN is SIGNAL CK1HZ: STD_LOGIC; SIGNAL CKQ: STD_LOGIC_VECTOR(1 DOWNTO 0); SIGNAL BCD,BCD0,BCD1 : STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL BCD2,BCD3: STD_LOGIC_VECTOR(3 DOWNTO 0); begin CHIAXUNG_1HZ: ENTITY WORK.CHIAXUNG_1HZ PORT MAP (CK50MHZ => CK50MHZ, CK1HZ => CK1HZ, CKQ => CKQ); DEM_9999: ENTITY WORK.DEM_9999 PORT MAP (CK1HZ => CK1HZ, RST => RST, BCD0 => BCD0,BCD2 => BCD2,BCD3 =>BCD3, BCD1 => DAHOP_4K: ENTITY WORK.DAHOP_4K PORT MAP (CKQ => CKQ, BCD => BCD, BCD0 => BCD0, BCD1 => BCD1, BCD2 => BCD2, BCD3 => BCD3, ANODE => ANODE); GIAIMA_7DOAN: ENTITY WORK.GIAIMA_7DOAN PORT MAP (BCD => BCD,

BCD1);

SSEG => SSEG); end Behavioral; entity CHIAXUNG_1HZ is Port ( CK50MHZ : in STD_LOGIC; CK1HZ : out STD_LOGIC; CKQ : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)); end CHIAXUNG_1HZ; architecture Behavioral of CHIAXUNG_1HZ is SIGNAL CHIAHEX: STD_LOGIC_VECTOR(27 DOWNTO 0):=X"0000000"; SIGNAL CK1HZT: STD_LOGIC:='0'; begin PROCESS (CHIAHEX,CK50MHZ,CK1HZT) BEGIN IF FALLING_EDGE(CK50MHZ) THEN IF CHIAHEX = X"02625A0" THEN CHIAHEX <= X"0000000"; CK1HZT <= NOT CK1HZT; ELSE CHIAHEX <= CHIAHEX + 1; END IF; END IF; CK1HZ <=CK1HZT; CKQ <= CHIAHEX( 14 DOWNTO 13); END PROCESS; end Behavioral; entity DEM_9999 is Port ( CK1HZ : in STD_LOGIC; RST : in STD_LOGIC; BCD0 : out STD_LOGIC_VECTOR (3 downto 0); BCD1 : out STD_LOGIC_VECTOR (3 downto 0); BCD2 : out STD_LOGIC_VECTOR (3 downto 0); BCD3 : out STD_LOGIC_VECTOR (3 downto 0)); end DEM_9999; architecture Behavioral of DEM_9999 is SIGNAL CKC,CKT,CKN:STD_LOGIC; SIGNAL BCD3K : STD_LOGIC_VECTOR (3 downto 0); SIGNAL BCD2K : STD_LOGIC_VECTOR (3 downto 0); SIGNAL BCD1K : STD_LOGIC_VECTOR (3 downto 0); SIGNAL BCD0K : STD_LOGIC_VECTOR (3 downto 0); begin

DEM_DVI: ENTITY WORK .DEM_DVI PORT MAP (RST => RST , CK1HZ => CK1HZ, BCD3K=>BCD3K , BCD2K => BCD2K,BCD1K => BCD1K, BCD0K => BCD0K,BCD0 => BCD0,CKC => CKC); DEM_CHUC: ENTITY WORK.DEM_CHUC PORT MAP(RST => RST , CKC => CKC,BCD3K=>BCD3K,BCD2K=>BCD2K,BCD1K=>BCD1K,BCD0K=>BCD0K, BCD1 => BCD1, CKT =>CKT); DEM_TRAM: ENTITY WORK.DEM_TRAM PORT MAP (RST =>RST ,CKT => CKT,BCD3K=>BCD3K,BCD2K=>BCD2K,BCD1K=>BCD1K,BCD0K=>BCD0K, BCD2 => BCD2 ,CKN =>CKN); DEM_NGAN: ENTITY WORK.DEM_NGAN PORT MAP (RST =>RST ,CKN=>CKN,BCD3K=>BCD3K,BCD2K=>BCD2K,BCD1K=>BCD1K,BCD0K=>BCD0K, BCD3 =>BCD3); end Behavioral; entity DEM_DVI is Port ( CK1HZ : in STD_LOGIC; RST : in STD_LOGIC; BCD3K : IN STD_LOGIC_VECTOR (3 downto 0); BCD2K : IN STD_LOGIC_VECTOR (3 downto 0); BCD1K : IN STD_LOGIC_VECTOR (3 downto 0); BCD0 : out STD_LOGIC_VECTOR (3 downto 0); BCD0K : out STD_LOGIC_VECTOR (3 downto 0); CKC : out STD_LOGIC); end DEM_DVI; architecture Behavioral of DEM_DVI is SIGNAL BCDT : STD_LOGIC_VECTOR( 3 DOWNTO 0); begin PROCESS( CK1HZ,RST,BCDT) BEGIN IF RST='1' THEN BCDT <= "0000"; ELSIF FALLING_EDGE(CK1HZ) THEN IF BCDT ="1001" THEN BCDT <="0000"; ELSE BCDT <= BCDT +1; END IF ; END IF ; IF BCDT="0101" AND BCD1K="0011" AND BCD2K="0010" AND BCD3K ="0001" THEN BCDT <= "0000"; END IF; BCD0 <= BCDT;BCD0K <= BCDT; END PROCESS; CKC <='1' WHEN BCDT="1001" ELSE '0'; end Behavioral; entity DEM_CHUC is Port ( CKC : in STD_LOGIC; RST : in STD_LOGIC; BCD3K : IN STD_LOGIC_VECTOR (3 downto 0); BCD2K : IN STD_LOGIC_VECTOR (3 downto 0); BCD0K : IN STD_LOGIC_VECTOR (3 downto 0); BCD1 : out STD_LOGIC_VECTOR (3 downto 0); BCD1K : out STD_LOGIC_VECTOR (3 downto 0); CKT : out STD_LOGIC); end DEM_CHUC; architecture Behavioral of DEM_CHUC is SIGNAL BCDT : STD_LOGIC_VECTOR( 3 DOWNTO 0); begin PROCESS( CKC,RST,BCDT) BEGIN IF RST='1' THEN BCDT <= "0000"; ELSIF FALLING_EDGE(CKC) THEN IF BCDT ="1001" THEN BCDT <="0000"; ELSE BCDT <= BCDT +1; END IF ; END IF ; IF BCD0K="0101" AND BCDT="0011" AND BCD2K="0010" AND BCD3K ="0001" THEN BCDT <= "0000";

END IF; BCD1 <= BCDT;BCD1K <=BCDT; END PROCESS; CKT <='1' WHEN BCDT="1001" ELSE '0'; end Behavioral; entity DEM_TRAM is Port ( CKT : in STD_LOGIC; RST : in STD_LOGIC; BCD3K : IN STD_LOGIC_VECTOR (3 downto 0); BCD1K : IN STD_LOGIC_VECTOR (3 downto 0); BCD0K : IN STD_LOGIC_VECTOR (3 downto 0); BCD2 : out STD_LOGIC_VECTOR (3 downto 0); BCD2K : out STD_LOGIC_VECTOR (3 downto 0); CKN : out STD_LOGIC); end DEM_TRAM ; architecture Behavioral of DEM_TRAM is SIGNAL BCDT : STD_LOGIC_VECTOR( 3 DOWNTO 0); begin PROCESS( CKT,RST,BCDT) BEGIN IF RST='1' THEN BCDT <= "0000"; ELSIF FALLING_EDGE(CKT) THEN IF BCDT ="1001" THEN BCDT <="0000"; ELSE BCDT <= BCDT +1; END IF ; END IF ; IF BCD0K="0101" AND BCD1K="0011" AND BCDT="0010" AND BCD3K ="0001" THEN BCDT <= "0000"; END IF; BCD2 <= BCDT;BCD2K <= BCDT; END PROCESS; CKN <='1' WHEN BCDT="1001" ELSE '0'; end Behavioral; ntity DEM_NGAN is Port ( CKN : in STD_LOGIC; RST : in STD_LOGIC; BCD2K : IN STD_LOGIC_VECTOR (3 downto 0); BCD1K : IN STD_LOGIC_VECTOR (3 downto 0); BCD0K : IN STD_LOGIC_VECTOR (3 downto 0); BCD3K : out STD_LOGIC_VECTOR (3 downto 0); BCD3 : out STD_LOGIC_VECTOR (3 downto 0)); end DEM_NGAN; architecture Behavioral of DEM_NGAN is SIGNAL BCDT : STD_LOGIC_VECTOR( 3 DOWNTO 0); begin PROCESS( CKN,RST,BCDT) BEGIN IF RST='1' THEN BCDT <= "0000"; ELSIF FALLING_EDGE(CKN) THEN IF BCDT ="1001" THEN BCDT <="0000"; ELSE BCDT <= BCDT +1; END IF ; END IF ; IF BCD0K="0101" AND BCD1K="0011" AND BCD2K="0010" AND BCDT ="0001" THEN BCDT <= "0000"; END IF ; BCD3 <= BCDT; BCD3K<=BCDT; END PROCESS; end Behavioral; entity DAHOP_4K is Port ( CKQ : in STD_LOGIC_VECTOR(1 DOWNTO 0); ANODE : OUT STD_LOGIC_VECTOR (3 downto 0); BCD0 : in STD_LOGIC_VECTOR (3 downto 0); BCD1 : in STD_LOGIC_VECTOR (3 downto 0); BCD2 : in STD_LOGIC_VECTOR (3 downto 0); BCD3 : in STD_LOGIC_VECTOR (3 downto 0);

BCD : out STD_LOGIC_VECTOR (3 downto 0)); end DAHOP_4K; architecture Behavioral of DAHOP_4K is begin PROCESS (CKQ,BCD0,BCD1,BCD2,BCD3) BEGIN CASE CKQ IS WHEN "00" => BCD <= BCD0;ANODE <= "1110"; WHEN "01" => BCD <= BCD1;ANODE <= "1101"; WHEN "10" => BCD <= BCD2; ANODE <= "1011"; WHEN OTHERS => BCD <= BCD3;ANODE <= "0111"; END CASE ; END PROCESS; end Behavioral; 549 entity DEM_LEN_9999_HT_7DOAN is Port ( CK50MHZ : in STD_LOGIC; RST : in STD_LOGIC; ANODE : out STD_LOGIC_VECTOR (3 downto 0); SSEG : out STD_LOGIC_VECTOR (7 downto 0)); end DEM_LEN_9999_HT_7DOAN; architecture Behavioral of DEM_LEN_9999_HT_7DOAN is SIGNAL CK1HZ: STD_LOGIC; SIGNAL CKQ: STD_LOGIC_VECTOR(1 DOWNTO 0); SIGNAL BCD,BCD0,BCD1 : STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL BCD2,BCD3: STD_LOGIC_VECTOR(3 DOWNTO 0); begin CHIAXUNG_1HZ: ENTITY WORK.CHIAXUNG_1HZ PORT MAP (CK50MHZ => CK50MHZ, CK1HZ => CK1HZ, CKQ => CKQ); DEM_9999C2: ENTITY WORK.DEM_9999C2 PORT MAP (CK1HZ => CK1HZ, RST => RST, BCD0 => BCD0,BCD2 => BCD2,BCD3 =>BCD3, BCD1 => BCD1); DAHOP_4K: ENTITY WORK.DAHOP_4K PORT MAP (CKQ => CKQ, BCD => BCD, BCD0 => BCD0, BCD1 => BCD1, BCD2 => BCD2, BCD3 => BCD3, ANODE => ANODE); GIAIMA_7DOAN: ENTITY WORK.GIAIMA_7DOAN PORT MAP (BCD => BCD, SSEG => SSEG); end Behavioral; entity DEM_9999C2 is Port ( CK1HZ : in STD_LOGIC; RST : in STD_LOGIC; BCD0,BCD1,BCD2,BCD3 : OUT STD_LOGIC_VECTOR (3 downto 0)); end DEM_9999C2; architecture Behavioral of DEM_9999C2 is SIGNAL BCD0T,BCD1T,BCD2T,BCD3T :STD_LOGIC_VECTOR(3 DOWNTO 0); begin PROCESS (CK1HZ,RST,BCD0T,BCD1T,BCD2T,BCD3T) BEGIN IF RST ='1' THEN BCD0T <="0100"; BCD1T <="0011"; BCD2T <="0010";BCD3T <="0001"; ELSIF FALLING_EDGE(CK1HZ) THEN IF BCD0T ="0000" THEN BCD0T <="1001"; IF BCD1T = "0000" THEN BCD1T <="1001"; IF BCD2T = "0000" THEN BCD2T <="1001"; IF BCD3T = "0000" THEN BCD3T <="1001"; ELSE BCD3T <= BCD3T-1;END IF;

ELSE BCD2T <= BCD2T-1; END IF ; ELSE BCD1T <= BCD1T-1; END IF ; ELSE BCD0T <= BCD0T-1; END IF ; END IF ; IF (BCD3T ="0000" AND BCD2T ="0000" AND BCD1T ="0000" AND BCD0T ="0000" )THEN BCD0T<="0100";BCD1T<="0011";BCD2T<="0010";BCD3T<="0001";END IF; BCD0 <= BCD0T; BCD1 <= BCD1T; BCD2 <= BCD2T; BCD3 <= BCD3T; END PROCESS; end Behavioral; 550 entity DEM_LEN_9999_HT_7DOAN is Port ( CK50MHZ : in STD_LOGIC; RST : in STD_LOGIC; ANODE : out STD_LOGIC_VECTOR (3 downto 0); SSEG : out STD_LOGIC_VECTOR (7 downto 0)); end DEM_LEN_9999_HT_7DOAN; architecture Behavioral of DEM_LEN_9999_HT_7DOAN is SIGNAL CK1HZ: STD_LOGIC; SIGNAL CKQ: STD_LOGIC_VECTOR(1 DOWNTO 0); SIGNAL BCD,BCD0,BCD1 : STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL BCD2,BCD3: STD_LOGIC_VECTOR(3 DOWNTO 0); begin CHIAXUNG_1HZ: ENTITY WORK.CHIAXUNG_1HZ PORT MAP (CK50MHZ => CK50MHZ, CK1HZ => CK1HZ, CKQ => CKQ); DEM_9999C2: ENTITY WORK.DEM_9999C2 PORT MAP (CK1HZ => CK1HZ, RST => RST, BCD0 => BCD0,BCD2 => BCD2,BCD3 =>BCD3, BCD1 => BCD1); DAHOP_4K: ENTITY WORK.DAHOP_4K PORT MAP (CKQ => CKQ,BCD => BCD, BCD0 => BCD0, BCD1 => BCD1, BCD2 => BCD2, BCD3 => BCD3, ANODE => ANODE); GIAIMA_7DOAN: ENTITY WORK.GIAIMA_7DOAN PORT MAP (BCD => BCD, SSEG => SSEG); end Behavioral; entity DEM_9999C2 is Port ( CK1HZ : in STD_LOGIC; RST : in STD_LOGIC; BCD0,BCD1,BCD2,BCD3 : OUT STD_LOGIC_VECTOR (3 downto 0)); end DEM_9999C2; architecture Behavioral of DEM_9999C2 is SIGNAL BCD0T,BCD1T,BCD2T,BCD3T :STD_LOGIC_VECTOR(3 DOWNTO 0); begin PROCESS (CK1HZ,RST,BCD0T,BCD1T,BCD2T,BCD3T) BEGIN IF RST ='1' THEN BCD0T <="0000"; BCD1T <="0000"; BCD2T <="0000";BCD3T <="0000"; ELSIF FALLING_EDGE(CK1HZ) THEN IF BCD0T ="1001" THEN BCD0T <="0000";--HANG DON VI CUA GIAY IF BCD1T = "0101" THEN BCD1T <="0000";--HANG CHUC CUA GIAY IF BCD2T = "1001" THEN BCD2T <="0000";--HANG DV CUA PHUT IF BCD3T = "0101" THEN BCD3T <="0000";--HANG CHUC CUA PHUT ELSE BCD3T <= BCD3T+1;END IF; ELSE BCD2T <= BCD2T+1; END IF ; ELSE BCD1T <= BCD1T+1; END IF ; ELSE BCD0T <= BCD0T+1; END IF ; END IF ; IF (BCD3T ="0101" AND BCD2T ="1001" AND BCD1T ="0101" AND BCD0T ="1001" )THEN BCD0T<="0100";BCD1T<="0011";BCD2T<="0010";BCD3T<="0001";END IF; BCD0 <= BCD0T; BCD1 <= BCD1T; BCD2 <= BCD2T; BCD3 <= BCD3T; END PROCESS; end Behavioral;

551 entity DEMLEN_4S0_HT_7DOAN is Port ( CK50MHZ : in STD_LOGIC; RST : in STD_LOGIC; ANODE : out STD_LOGIC_VECTOR (3 downto 0); SSEG : out STD_LOGIC_VECTOR (7 downto 0)); end DEMLEN_4S0_HT_7DOAN ; architecture Behavioral of DEMLEN_4S0_HT_7DOAN is SIGNAL CK1HZ: STD_LOGIC; SIGNAL CKQ: STD_LOGIC_VECTOR(1 DOWNTO 0); SIGNAL BCD,BCD0,BCD1 : STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL BCD2,BCD3: STD_LOGIC_VECTOR(3 DOWNTO 0); begin CHIAXUNG_1HZ: ENTITY WORK.CHIAXUNG_1HZ PORT MAP (CK50MHZ => CK50MHZ, CK1HZ => CK1HZ, CKQ => CKQ); DEM_9999C2: ENTITY WORK.DEM_9999C2 PORT MAP (CK1HZ => CK1HZ, RST => RST, BCD0 => BCD0,BCD2 => BCD2,BCD3 =>BCD3, BCD1 => BCD1); DAHOP_4K: ENTITY WORK.DAHOP_4K PORT MAP (CKQ => CKQ, BCD => BCD, BCD0 => BCD0, BCD1 => BCD1, BCD2 => BCD2, BCD3 => BCD3, ANODE => ANODE); GIAIMA_7DOAN: ENTITY WORK.GIAIMA_7DOAN PORT MAP (BCD => BCD, SSEG => SSEG); end Behavioral; entity DEM_9999C2 is Port ( CK1HZ : in STD_LOGIC; RST : in STD_LOGIC; BCD0,BCD1,BCD2,BCD3 : OUT STD_LOGIC_VECTOR (3 downto 0)); end DEM_9999C2; architecture Behavioral of DEM_9999C2 is SIGNAL BCD0T,BCD1T,BCD2T,BCD3T :STD_LOGIC_VECTOR(3 DOWNTO 0); begin PROCESS (CK1HZ,RST,BCD0T,BCD1T,BCD2T,BCD3T) BEGIN IF RST ='1' THEN BCD0T <="0000"; BCD1T <="0000"; BCD2T <="0000";BCD3T <="0000"; ELSIF FALLING_EDGE(CK1HZ) THEN IF BCD0T ="1001" THEN IF BCD1T = "1001" THEN IF BCD2T = "1001" THEN IF BCD3T = "1001" THEN BCD3T <="0000";BCD2T <="0000"; BCD1T <="0000";BCD0T <="0000"; ELSE BCD3T <= BCD3T+1; END IF ; ELSE BCD2T <= BCD2T+1; END IF ; ELSE BCD1T <= BCD1T+1; END IF ; ELSE BCD0T <= BCD0T+1; END IF ; END IF ; BCD0 <= BCD0T; BCD1 <= BCD1T; BCD2 <= BCD2T; BCD3 <= BCD3T; END PROCESS; end Behavioral; 552 entity DEMXUONG_4S0_HT_7DOAN is Port ( CK50MHZ : in STD_LOGIC; RST : in STD_LOGIC; ANODE : out STD_LOGIC_VECTOR (3 downto 0); SSEG : out STD_LOGIC_VECTOR (7 downto 0));

end DEMXUONG_4S0_HT_7DOAN ; architecture Behavioral of DEMXUONG_4S0_HT_7DOAN is SIGNAL CK1HZ: STD_LOGIC; SIGNAL CKQ: STD_LOGIC_VECTOR(1 DOWNTO 0); SIGNAL BCD,BCD0,BCD1 : STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL BCD2,BCD3: STD_LOGIC_VECTOR(3 DOWNTO 0); begin CHIAXUNG_1HZ: ENTITY WORK.CHIAXUNG_1HZ PORT MAP (CK50MHZ => CK50MHZ, CK1HZ => CK1HZ, CKQ => CKQ); DEM_9999C2: ENTITY WORK.DEM_9999C2 PORT MAP (CK1HZ => CK1HZ, RST => RST, BCD0 => BCD0,BCD2 => BCD2,BCD3 =>BCD3, BCD1 => BCD1); DAHOP_4K: ENTITY WORK.DAHOP_4K PORT MAP (CKQ => CKQ, BCD => BCD, BCD0 => BCD0, BCD1 => BCD1, BCD2 => BCD2, BCD3 => BCD3, ANODE => ANODE); GIAIMA_7DOAN: ENTITY WORK.GIAIMA_7DOAN PORT MAP (BCD => BCD, SSEG => SSEG); end Behavioral; entity DEM_9999C2 is Port ( CK1HZ : in STD_LOGIC; RST : in STD_LOGIC; BCD0,BCD1,BCD2,BCD3 : OUT STD_LOGIC_VECTOR (3 downto 0)); end DEM_9999C2; architecture Behavioral of DEM_9999C2 is SIGNAL BCD0T,BCD1T,BCD2T,BCD3T :STD_LOGIC_VECTOR(3 DOWNTO 0); begin PROCESS (CK1HZ,RST,BCD0T,BCD1T,BCD2T,BCD3T) BEGIN IF RST ='1' THEN BCD0T <="1001"; BCD1T <="1001"; BCD2T <="1001";BCD3T <="1001"; ELSIF FALLING_EDGE(CK1HZ) THEN IF BCD0T ="0000" THEN IF BCD1T = "0000" THEN IF BCD2T = "0000" THEN IF BCD3T = "0000" THEN BCD3T <="1001";BCD2T <="1001"; BCD1T <="1001";BCD0T <="1001"; ELSE BCD3T <= BCD3T-1; END IF ; ELSE BCD2T <= BCD2T-1; END IF ; ELSE BCD1T <= BCD1T-1; END IF ; ELSE BCD0T <= BCD0T-1; END IF ; END IF ; BCD0 <= BCD0T; BCD1 <= BCD1T; BCD2 <= BCD2T; BCD3 <= BCD3T; END PROCESS; end Behavioral; 553 entity DEMLENXUONG_4S0_HT_7DOAN is Port ( CK50MHZ : in STD_LOGIC; RST : in STD_LOGIC; ANODE : out STD_LOGIC_VECTOR (3 downto 0); SSEG : out STD_LOGIC_VECTOR (7 downto 0)); end DEMLENXUONG_4S0_HT_7DOAN ; architecture Behavioral of DEMLENXUONG_4S0_HT_7DOAN is SIGNAL CK1HZ: STD_LOGIC; SIGNAL CKQ: STD_LOGIC_VECTOR(1 DOWNTO 0); SIGNAL BCD,BCD0,BCD1 : STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL BCD2,BCD3: STD_LOGIC_VECTOR(3 DOWNTO 0); begin CHIAXUNG_1HZ: ENTITY WORK.CHIAXUNG_1HZ PORT MAP (CK50MHZ => CK50MHZ, CK1HZ => CK1HZ,

DEM_9999C2: BCD0 BCD1 DAHOP_4K:

CKQ => CKQ); ENTITY WORK.DEM_9999C2 PORT MAP (CK1HZ => CK1HZ, RST => RST, => BCD0,BCD2 => BCD2,BCD3 =>BCD3, => BCD1); ENTITY WORK.DAHOP_4K PORT MAP (CKQ => CKQ, BCD => BCD, BCD0 => BCD0, BCD1 => BCD1, BCD2 => BCD2, BCD3 => BCD3, ANODE => ANODE);

GIAIMA_7DOAN:

ENTITY WORK.GIAIMA_7DOAN PORT MAP (BCD => BCD, SSEG => SSEG);

end Behavioral; entity CHIAXUNG_1HZ is Port ( CK50MHZ : in STD_LOGIC; CKQ : out STD_LOGIC_VECTOR (1 downto 0); CK1HZ : out STD_LOGIC); end CHIAXUNG_1HZ; architecture Behavioral of CHIAXUNG_1HZ is SIGNAL CHIAHEX:STD_LOGIC_VECTOR(24 DOWNTO 0):='0'&X"000000"; SIGNAL CK1HZT: STD_LOGIC:='0'; begin PROCESS(CHIAHEX,CK1HZT,CK50MHZ) BEGIN IF RISING_EDGE(CK50MHZ) THEN IF CHIAHEX = '1'& X"7D7480" THEN CHIAHEX <='0'& X"000000"; CK1HZT <= NOT CK1HZT; ELSE CHIAHEX <= CHIAHEX +1; END IF; END IF; CK1HZ <= CK1HZT; CKQ <= CHIAHEX(14 DOWNTO 13); END PROCESS; end Behavioral; entity DEM_9999C2 is Port ( CK1HZ : in STD_LOGIC; RST : in STD_LOGIC; BCD0,BCD1,BCD2,BCD3 : OUT STD_LOGIC_VECTOR (3 downto 0)); end DEM_9999C2; architecture Behavioral of DEM_9999C2 is SIGNAL BCD0T,BCD1T,BCD2T,BCD3T :STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL S :STD_LOGIC; begin PROCESS (CK1HZ,RST,BCD0T,BCD1T,BCD2T,BCD3T) BEGIN IF RST ='1' THEN BCD0T <="0000"; BCD1T <="0000"; BCD2T <="0000";BCD3T <="0000";S <='0'; ELSIF FALLING_EDGE(CK1HZ) THEN IF S='0' THEN IF BCD0T ="1001" THEN IF BCD1T = "1001" THEN IF BCD2T = "1001" THEN IF BCD3T = "1001" THEN S<='1'; ELSE BCD3T <= BCD3T+1; END IF ; ELSE BCD2T <= BCD2T+1; END IF ; ELSE BCD1T <= BCD1T+1; END IF ; ELSE BCD0T <= BCD0T+1; END IF ; ELSE IF BCD0T ="0000" THEN IF BCD1T = "0000" THEN IF BCD2T = "0000" THEN IF BCD3T = "0000" THEN S<='0';

ELSE BCD3T <= BCD3T-1; END IF ; ELSE BCD2T <= BCD2T-1; END IF ; ELSE BCD1T <= BCD1T-1; END IF ; ELSE BCD0T <= BCD0T-1; END IF ; END IF ; END IF ; BCD0 <= BCD0T; BCD1 <= BCD1T; BCD2 <= BCD2T; BCD3 <= BCD3T; END PROCESS; end Behavioral; 560 n giao thng entity DENGIAOTHONG is Port ( CK50MHZ : in STD_LOGIC; RST : in STD_LOGIC; DENLEDDON : out STD_LOGIC_VECTOR (7 downto 0); SSEG : out STD_LOGIC_VECTOR (7 downto 0); ANODE : out STD_LOGIC_VECTOR (3 downto 0)); end DENGIAOTHONG; architecture Behavioral of DENGIAOTHONG is SIGNAL CK1HZ: STD_LOGIC; SIGNAL CKQ: STD_LOGIC_VECTOR(1 DOWNTO 0); SIGNAL THOIGIAN1,THOIGIAN2: STD_LOGIC_VECTOR (5 DOWNTO 0); SIGNAL CHUC1,DONVI1,CHUC2,DONVI2,BCD : STD_LOGIC_VECTOR (3 DOWNTO 0); begin CHIAXUNG_1HZ : ENTITY WORK.CHIAXUNG_1HZ PORT MAP (CK50MHZ => CK50MHZ,CK1HZ =>CK1HZ,CKQ => CKQ); DEMGIAY : ENTITY WORK.DEMGIAY PORT MAP (RST =>RST, CK1HZ =>CK1HZ ,DENLEDDON=>DENLEDDON , THOIGIAN1=>THOIGIAN1, THOIGIAN2=> THOIGIAN2); HEXTOBCD : ENTITY WORK.HEXTOBCD PORT MAP (THOIGIAN1=>THOIGIAN1,THOIGIAN2=>THOIGIAN2, CHUC1=>CHUC1,DONVI1=>DONVI1,CHUC2=>CHUC2,DONVI2=>DONVI2); DAHOP4_QUET : ENTITY WORK.DAHOP4_QUET PORT MAP (CHUC1=>CHUC1,DONVI1=>DONVI1,CHUC2=>CHUC2,DONVI2=>DONVI2,BCD=>BCD,ANODE => ANODE,CKQ=> CKQ); GIAIMA_7DOAN: ENTITY WORK.GIAIMABCD PORT MAP (BCD=>BCD,SSEG=>SSEG); end Behavioral; entity DEMGIAY is Port ( RST,CK1HZ : in STD_LOGIC; DENLEDDON : out STD_LOGIC_VECTOR (7 downto 0); THOIGIAN1 : out STD_LOGIC_VECTOR (5 downto 0); THOIGIAN2 : out STD_LOGIC_VECTOR (5 downto 0)); end DEMGIAY; architecture Behavioral of DEMGIAY is SIGNAL DEMGIAY:INTEGER RANGE 0 TO 50:=0; SIGNAL THOIGIAN2T,THOIGIAN1T: STD_LOGIC_VECTOR(5 DOWNTO 0); begin PROCESS(RST,THOIGIAN2T,THOIGIAN1T,CK1HZ) BEGIN IF RST='1' THEN DEMGIAY <= 0 ; ELSIF FALLING_EDGE(CK1HZ) THEN DEMGIAY <= DEMGIAY+1; IF DEMGIAY=40 THEN DEMGIAY <= 0 ; ELSIF DEMGIAY =0 THEN THOIGIAN1T<="001111";--15 THOIGIAN2T<="010100";--20 DENLEDDON<=B"1000_0100";--X1D2 ELSIF DEMGIAY = 15 THEN THOIGIAN1T <="000101";--05 THOIGIAN2T <="000101";--05 DENLEDDON<=B"0100_0100";--V1D2 ELSIF DEMGIAY = 20 THEN THOIGIAN1T <="010100";--20 THOIGIAN2T <="001111";--15 DENLEDDON<=B"0010_0010";--VD1V2 ELSE THOIGIAN2T<=THOIGIAN2T-1; THOIGIAN1T<=THOIGIAN1T-1; END IF; END IF; THOIGIAN2<=THOIGIAN2T; THOIGIAN1<=THOIGIAN1T; END PROCESS; end Behavioral;

entity HEXTOBCD is Port ( THOIGIAN1,THOIGIAN2 : in STD_LOGIC_VECTOR (5 downto 0); CHUC1,DONVI1 : out STD_LOGIC_VECTOR (3 downto 0); CHUC2,DONVI2 : out STD_LOGIC_VECTOR (3 downto 0)); end HEXTOBCD; architecture Behavioral of HEXTOBCD is begin PROCESS (THOIGIAN1,THOIGIAN2) VARIABLE BCD1,BCD2:STD_LOGIC_VECTOR(13 DOWNTO 0); BEGIN BCD1:=(OTHERS=>'0'); BCD1(5 DOWNTO 0):=THOIGIAN1; BCD2:=(OTHERS=>'0'); BCD2(5 DOWNTO 0):=THOIGIAN2; FOR I IN 0 TO 4 LOOP BCD1:=BCD1(12 DOWNTO 0)&BCD1(13); IF BCD1(9 DOWNTO 6)>= "0101" THEN BCD1(9 DOWNTO 6):=BCD1(9 DOWNTO 6)+"0011"; END IF; IF BCD1(13 DOWNTO 10)>= "0101" THEN BCD1(13 DOWNTO 10):=BCD1(13 DOWNTO 10)+"0011"; END IF; END LOOP; BCD1:=BCD1(12 DOWNTO 0)&BCD1(13); FOR I IN 0 TO 4 LOOP BCD2:=BCD2(12 DOWNTO 0)&BCD2(13); IF BCD2(9 DOWNTO 6)>= "0101" THEN BCD2(9 DOWNTO 6):=BCD2(9 DOWNTO 6)+"0011"; END IF; IF BCD2(13 DOWNTO 10)>= "0101" THEN BCD2(13 DOWNTO 10):=BCD2(13 DOWNTO 10)+"0011"; END IF; END LOOP; BCD2:=BCD2(12 DOWNTO 0)& BCD2(13); CHUC1 <= BCD1(13 DOWNTO 10); DONVI1 <= BCD1(9 DOWNTO 6); CHUC2 <= BCD2(13 DOWNTO 10); DONVI2 <= BCD2(9 DOWNTO 6); END PROCESS; end Behavioral; entity DAHOP4_QUET is Port ( BCD0,BCD1 : in STD_LOGIC_VECTOR (3 downto 0); BCD2,BCD3 : in STD_LOGIC_VECTOR (3 downto 0); BCD : out STD_LOGIC_VECTOR (3 downto 0); CKQ : in STD_LOGIC_VECTOR (1 downto 0); ANODE : out STD_LOGIC_VECTOR (3 downto 0)); end DAHOP4_QUET; architecture Behavioral of DAHOP4_QUET is begin PROCESS(CKQ,BCD0,BCD1,BCD2,BCD3) BEGIN CASE CKQ IS WHEN"00" =>BCD<= BCD0; ANODE <="1110"; WHEN"01" =>BCD<= BCD1;ANODE <="1101"; WHEN"10" =>BCD<= BCD2; ANODE <="1011"; WHEN OTHERS =>BCD<= BCD3;ANODE <="0111"; END CASE ; END PROCESS ; 561 entity DEM_BCD_MHTT is Port ( CK50MHZ : in STD_LOGIC; RST : in STD_LOGIC; COUNT : out STD_LOGIC_VECTOR (3 downto 0)); end DEM_BCD_MHTT; architecture Behavioral of DEM_BCD_MHTT is SIGNAL CK1HZ:STD_LOGIC; begin CHIAXUNG_1HZ: ENTITY WORK.CHIAXUNG_1HZ PORT MAP (CK50MHZ => CK50MHZ, CK1HZ => CK1HZ); STATE_COUNT: ENTITY WORK.STATE_COUNT PORT MAP (CK1HZ =>CK1HZ,COUNT=>COUNT,RST=>RST); end Behavioral; entity STATE_COUNT is Port ( RST : in STD_LOGIC; CK1HZ : in STD_LOGIC;

COUNT : out STD_LOGIC_VECTOR (3 downto 0)); end STATE_COUNT; architecture Behavioral of STATE_COUNT is TYPE STATE_FSM IS ( STATE0,STATE1,STATE2,STATE3,STATE4,STATE5,STATE6,STATE7,STATE8,STATE9); SIGNAL PR_STATE,NX_STATE:STATE_FSM; begin PROCESS(CK1HZ,RST) BEGIN IF RST='1' THEN PR_STATE <= STATE0; ELSIF RISING_EDGE(CK1HZ) THEN PR_STATE <= NX_STATE; END IF ; END PROCESS; PROCESS(PR_STATE) BEGIN CASE PR_STATE IS WHEN STATE0 => COUNT <= "0000"; NX_STATE <= STATE1; WHEN STATE1 => COUNT <= "0001"; NX_STATE <= STATE2; WHEN STATE2 => COUNT <= "0010"; NX_STATE <= STATE3; WHEN STATE3 => COUNT <= "0011"; NX_STATE <= STATE4; WHEN STATE4 => COUNT <= "0100"; NX_STATE <= STATE5; WHEN STATE5 => COUNT <= "0101"; NX_STATE <= STATE6; WHEN STATE6 => COUNT <= "0110"; NX_STATE <= STATE7; WHEN STATE7 => COUNT <= "0111"; NX_STATE <= STATE8; WHEN STATE8 => COUNT <= "1000"; NX_STATE <= STATE9; WHEN STATE9 => COUNT <= "1001"; NX_STATE <= STATE0; WHEN OTHERS => NULL; END CASE ; END PROCESS; end Behavioral; 570 BAI_570_GIOPHUTGIAY_DAUCHAM ntity DEM_LEN_9999_HT_7DOAN is Port ( CK50MHZ : in STD_LOGIC; RST,SW : in STD_LOGIC; ANODE : out STD_LOGIC_VECTOR (3 downto 0); SSEG : out STD_LOGIC_VECTOR (7 downto 0)); end DEM_LEN_9999_HT_7DOAN; architecture Behavioral of DEM_LEN_9999_HT_7DOAN is SIGNAL CK1HZ: STD_LOGIC; SIGNAL CKQ: STD_LOGIC_VECTOR(1 DOWNTO 0); SIGNAL BCD,BCD0,BCD1 : STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL BCD2,BCD3: STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL ANODET :STD_LOGIC_VECTOR(3 DOWNTO 0); begin CHIAXUNG_1HZ: ENTITY WORK.CHIAXUNG_1HZ PORT MAP (CK50MHZ => CK50MHZ, CK1HZ => CK1HZ, CKQ => CKQ); DEM_9999C2: ENTITY WORK.DEM_9999C2 PORT MAP (CK1HZ => CK1HZ, RST => RST, BCD0 => BCD0,BCD2 => BCD2,BCD3 =>BCD3, BCD1 => BCD1); DAHOP_4K: ENTITY WORK.DAHOP_4K PORT MAP (CKQ => CKQ, BCD => BCD, BCD0 => BCD0, BCD1 => BCD1, BCD2 => BCD2, BCD3 => BCD3, ANODE => ANODE, ANODET =>ANODET); GIAIMA_7DOAN: ENTITY WORK.GIAIMA_7DOAN PORT MAP (BCD => BCD,SW=>SW, SSEG => SSEG, CK1HZ => CK1HZ,CK50MHZ=>CK50MHZ,

ANODET =>ANODET); end Behavioral; entity DEM_9999C2 is Port ( CK1HZ : in STD_LOGIC; RST : in STD_LOGIC; BCD0,BCD1,BCD2,BCD3 : OUT STD_LOGIC_VECTOR (3 downto 0)); end DEM_9999C2; architecture Behavioral of DEM_9999C2 is SIGNAL BCD0T,BCD1T,BCD2T,BCD3T :STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL TAM :STD_LOGIC_VECTOR(7 DOWNTO 0); begin PROCESS (CK1HZ,RST,BCD0T,BCD1T,BCD2T,BCD3T) BEGIN IF RST ='1' THEN BCD0T <="0000"; BCD1T <="0000"; BCD2T <="0000";BCD3T <="0000"; ELSIF FALLING_EDGE(CK1HZ) THEN IF TAM =X"3B" THEN TAM <=X"00"; IF BCD0T ="1001" THEN BCD0T <="0000";--HANG DON VI CUA PHUT IF BCD1T = "0101" THEN BCD1T <="0000";--HANG CHUC CUA PHUT IF BCD2T = "1001" THEN BCD2T <="0000";--HANG DV CUA GIO IF BCD3T = "0101" THEN BCD3T <="0000";--HANG CHUC CUA GIO ELSE BCD3T <= BCD3T+1;END IF; ELSE BCD2T <= BCD2T+1; END IF ; ELSE BCD1T <= BCD1T+1; END IF ; ELSE BCD0T <= BCD0T+1; END IF ; ELSE TAM <= TAM +1;END IF; END IF ; IF (BCD3T ="0101" AND BCD2T ="1001" AND BCD1T ="0101" AND BCD0T ="1001" )THEN BCD0T<="0100";BCD1T<="0011";BCD2T<="0010";BCD3T<="0001";END IF; BCD0 <= BCD0T; BCD1 <= BCD1T; BCD2 <= BCD2T; BCD3 <= BCD3T; END PROCESS; end Behavioral; 565 n giao thng entity DEN_GT is Port ( CK1HZ,STBY,TEST : in STD_LOGIC; R1,R2,Y1,Y2,G1,G2 : out STD_LOGIC); end DEN_GT; architecture Behavioral of DEN_GT is CONSTANT TIMEMAX : INTEGER :=15; CONSTANT TIMERG : INTEGER :=10; CONSTANT TIMERY : INTEGER :=5; CONSTANT TIMEGR : INTEGER :=10; CONSTANT TIMEYR : INTEGER :=5; CONSTANT TIMETEST : INTEGER :=1; TYPE STATES IS (RG,RY,GR,YR,YY); SIGNAL PR_STATE,NX_STATE:STATES; SIGNAL FIX_TIME: INTEGER RANGE 0 TO TIMEMAX; begin PROCESS(CK1HZ,STBY) VARIABLE VAR_TIME :INTEGER :=0; BEGIN IF STBY ='1' THEN PR_STATE <= YY; ELSIF CK1HZ'EVENT AND CK1HZ ='1' THEN VAR_TIME:= VAR_TIME +1; IF VAR_TIME = FIX_TIME THEN PR_STATE <= NX_STATE ; VAR_TIME:=0; END IF; END IF; END PROCESS; PROCESS (TEST,PR_STATE) BEGIN CASE PR_STATE IS WHEN RG => R1 <='1'; Y1<='0';G1<='0';R2<='0';Y2<='0';G2<='1'; IF TEST ='0' THEN FIX_TIME <= TIMERG; ELSE FIX_TIME <= 1; END IF; NX_STATE <= RY; WHEN RY => R1 <='1'; Y1<='0';G1<='0';R2<='0';Y2<='1';G2<='0'; IF TEST ='0' THEN FIX_TIME <= TIMERY; ELSE FIX_TIME <= 1;

WHEN GR

WHEN YR

WHEN

YY

END IF; NX_STATE <= GR; => R1 <='0'; Y1<='0';G1<='1';R2<='1';Y2<='0';G2<='0'; IF TEST ='0' THEN FIX_TIME <= TIMEGR; ELSE END IF; NX_STATE <= YR; => R1 <='0'; Y1<='1';G1<='0';R2<='1';Y2<='0';G2<='0'; IF TEST ='0' THEN FIX_TIME <= TIMEYR; ELSE END IF; NX_STATE <= RG; => R1 <='0'; Y1<='1';G1<='0';R2<='0';Y2<='1';G2<='0'; IF TEST ='0' THEN FIX_TIME <= TIMEYR; ELSE END IF; NX_STATE <= RG; END CASE; END PROCESS;

FIX_TIME <= 1;

FIX_TIME <= 1;

FIX_TIME <= 1;

end Behavioral;