VHDL 12533375633445 Phpapp01

Thit k nh my tnh
Nguyn Thnh Kin

B mn K thut My tnh Khoa Cng ngh thng tin, H BKHN
Ti liu tham kho
Text Book:
Circuit Design with VHDL, Volnei A.Pedroni, MIT press. VHDL Programming by Examples, Douglas L.Perry, McGraw Hill. 1076 IEEE Standard Vhdl Language Reference Manual 2002, IEEE Computer Society. Microprocessor Design Principles and Practices with VHDL, Enoch O. Hwang. HDL Chip Design- A Practical Guide for Designing, Synthesizing and Simulating ASICs and FPGAs using VHDL or Verilog, Douglas J.Smith.
Reference Books:
Copyright by N.T.K - 8/2008
Phn mm hc tp

Active-HDL 7.1.sp2 Quartus (for Altera FPGAs) ISE (for Xilinx FPGAs) www.opencores.org
Ging vin
Nguyn Thnh Kin Ging vin B mn K thut My tnh Khoa CNTT, HBKHN. Mobile: +84983588135 Email: kiennt-fit@mail.hut.edu.vn
Yu cu mn hc
Tham gia >75% s gi hc.

Ngh 5 bui => Hc li. Ngh 3 bui => Khng thi ln 1. Bi kim tra gia k: 20% Bi tp ln: 20% Bi kim tra cui k: 60%
Cch tnh im:

Ni dung mn hc
I. Thit k mch vi ngn ng VHDL.

II. Thit k CPU.

1. Gii thiu VHDL. 2. Cu trc code. 3. Cc kiu d liu. 4. Cc php ton v thuc tnh. 5. Code song song/Code tun t. 6. Tn hiu v bin. 7. My hu hn trng thi. 8. Phng php thit k a cp (Packages,Components,Subprogram) 9. Attibutes & Configurations. 10. Tng hp m VHDL.
1. Nguyn tc thit k CPU. 2. Cc thnh phn ca CPU. 3. Ti u ha, m phng, tng hp v trin khai CPU.
Ni dung mn hc
1. Gii thiu VHDL. 2. Cu trc code. 3. Cc kiu d liu. 4. Cc php ton v thuc tnh. 5. Code song song/Code tun t. 6. Tn hiu v bin. 7. My hu hn trng thi. 8. Phng php thit k a cp (Packages, Components, Subprogram). 9. Attibutes & Configurations.
II. Thit k CPU.

1. Gii thiu ngn ng VHDL.

Phng php thit k bng HDL Phng php thit k truyn thng
VHDL l g?
Mt ngn ng m t phn cng:

VHDL - VHSIC Hardware Description Language. VHSIC - Very High Speed Integrated Circuits.
L chun do B QP M pht trin t thp nin 70. Da trn ngn ng lp trnh ADA, nhm to ra ti liu m t hot ng ca cc mch in t.

1987 c IEEE chun ha trong IEEE 1076-1987. 1993 hon thin li thnh IEEE 1076-1993. 2002 gii quyt vn protected types=>IEEE 1076-2002
VHDL l chun c lp m t h thng:
Cc nh pht trin h thng da trn VHDL m t, thit k h thng. Cc phn mm m phng c th thc hin m phng hot ng ca h thng m t. Cc phn mm tng hp c th thc hin tng hp sinh ra mch thc thc hin h thng. Mch sau khi tng hp c th c np xung chip thc hin chc nng m t.
Chc nng: m t hot ng ca cc h thng hoc mch in t nhm thc hin cc h thng hoc mch ny trn linh kin thc.
u im ca VHDL:
Cho php hot ng ca h thng c m t (modeled) v kim th (simulated) trc khi cc cng c tng hp dch thit k sang phn cng thc t (gates and wires). Cho php m t h thng song song. Khi cc m hnh VHDL c dch sang gates and wires th n c th c np ln phn cng CPLD v FPGA thc thi.
Hai ng dng chnh ca VHDL l:
PLD (Programmable Logic Device):

CPLD (Complex PLD) FPGA (Field Programmable Gate Array).
ASIC (Application-Specific IC)
Quy trnh thit k mch da trn VHDL
Cc cng c thit k VHDL
B cng c ca nh sn xut chip:
Quartus/Maxplus => tng hp VHDL code ln chip CPLD/FPGA ca Altera. ISE => tng hp VHDL code ln chip CPLD/FPGA ca Xilinx. ActiveHDL Leonardo Spectrum (Mentor Graphics). Synplify (Synplicity). ModelSim (Mentor Graphics).
Mt s cng c ca cc hng th ba:

Mt v d VHDL n gin
Mt v d VHDL n gin
Ni dung mn hc
II. Thit k CPU.

Code structure
library IEEE; use IEEE.std_logic_1164.all; ENTITY full_adder IS PORT (a,b,cin: in bit; s,cout:out bit); END full_adder; Architecture dataflow of full_adder is begin s <= a xor b xor cin; cout <= (a and b) or (a and cin) or (b and cin); end dataflow;
Cu trc code

Th vin LIBRARY ENTITY ARCHITECTURE
Th vin LIBRARY
A LIBRARY l mt tp cc on m thng c s dng. t cc on m thng s dng vo th vin cho php chng c th c ti s dng hoc chia s gia cc thit k khc nhau.
Th vin LIBRARY
Khai bo th vin:
Th vin LIBRARY
Cc th vin thng s dng:

ieee.std_logic_1164 (from the ieee library), standard (from the std library), and work (work library).
LIBRARY ieee; -- A semi-colon (;) indicates USE ieee.std_logic_1164.all; -- the end of a statement or LIBRARY std; USE std.standard.all; LIBRARY work; USE work.all;
-- declaration, while a double -- dash (--) indicates acomment.
Th vin LIBRARY
std_logic_1164
Gi ca th vin IEEE h tr multi-level logic. Gi th vin ti nguyn (kiu d liu, text IO) cho mi trng thit k VHDL. Gi th vin cha cc thit k ca ngi dng mi to ra.
std
work
Th vin LIBRARY
Th vin IEEE:
std_logic_1164
std_logic (8 mc logic),std_ulogic (9 mc logic) Thc hin cc php ton s hc v so snh. Thc hin cc php ton vi kiu DL std_logic_vector, d liu coi l c du
std_logic_arith
std_logic_signed
std_logic_unsigned
Thc hin cc php ton vi kiu DL std_logic_vector, d liu coi l khng du.
Cu trc code

ENTITY
ENTITY l danh sch c t ca cc cng vo ra (input/output pins) ca mch.

BLACK_BOX rst d[7:0] clk co q[7:0]
PORT l giao din ca mch vi cc mch bn ngoi khc, PORT thng l cc chn pin.
ENTITY
signal_mode: chiu truyn d liu
IN, OUT, INOUT (2chiu), BUFFER (khi tn hiu ra c dng cho cc tn hiu khc bn trong). bit, std_logic, integer t tn theo quy tc t tn chun, trnh cc t kha.
signal_type:
Port_name:
ENTITY
Ch signal_mode cho bit chiu d liu c truyn nhn:
Entity
IN OUT trong)
D liu ch i vo ENTITY D liu ch i ra khi ENTITY (v khng c s dng bn D liu l hai chiu (i vo v ra) D liu i ra khi ENTITY v cng c a quay trbyli vo trong Copyright N.T.K - 8/2008
INOUT BUFFER
V d v ENTITY
ENTITY mux IS PORT (a, b: IN std_logic_vector(7 downto 0); sel: IN STD_LOGIC_VECTOR(0 to 1); c: OUT STD_LOGIC_VECTOR(7 downto 0)); END mux;
Cu trc code

ARCHITECTURE
Phn ARCHITECTURE m t mch hot ng nh th no.
Mt ARCHITECTURE lun gn vi mt ENTITY v m t hot ng ca ENTITY . Mt ARCHITECTURE ch gn vi mt ENTITY nhng Mt ENTIY c th c nhiu by N.T.K - 8/2008 ARCHITECTURE khc nhau Copyright
ARCHITECTURE
ARCHITECTURE c hai phn:
Phn khai bo (optional)
Khai bo tn hiu v bin. M t cch kt ni, hot ng ca mch.

Phn m code:
ARCHITECTURE
V d v mch NAND:
M t kt ni mch: Mch thc hin thao tc NAND trn 2 u vo (a,b) v gn (<=) kt qu cho u ra x.
VD1: Full_adder
B cng hai s 1bit y

library IEEE; use IEEE.std_logic_1164.all;
ENTITY full_adder IS PORT (a,b,cin: in std_logic; s,cout:out std_logic); END full_adder;
A(7:0) C(7:0) B(7:0) Adder
Architecture dataflow of full_adder is begin s <= a xor b xor cin; cout <= (a and b) or (a and cin) or (b and cin); end dataflow;
library IEEE; use IEEE.std_logic_1164.all;

ENTITY adder IS PORT (A,B: IN std_logic_vector(7 downto 0); C: OUT std_logic_vector(7 downto 0)); END adder;
A(7:0) B(7:0) Adder
C(7:0) begin
Architecture dataflow of adder is C <= A+B; end dataflow;
VD2: D Flip-flop, asyn reset

LIBRARY ieee; USE ieee.std_logic_1164.all; --------------------------------------ENTITY dff IS PORT ( d, clk, rst: IN STD_LOGIC; q: OUT STD_LOGIC); END dff; --------------------------------------ARCHITECTURE behavior OF dff IS BEGIN PROCESS (rst, clk) BEGIN D flip-flop tch cc theo sn dng ca xung IF (rst='1') THEN ng h clk vi tn hiu reset khng ng b. q <= '0'; Hot ng: ELSIF (clk'EVENT AND clk='1') + rst = 1 => q<=0 khng ph thuc clk. THEN + rst = 0, sn dng clk => q<=d. q <= d; END IF; END PROCESS; DEMO END behavior; Copyright by N.T.K - 8/2008
VD2: RS Flip-flop, asyn reset
Bi tp ti lp:
Vit VHDL code m t flip-flop RS ng b theo sn m vi tn hiu reset khng ng b.
VD2: RS Flip-flop, asyn reset

LIBRARY ieee; USE ieee.std_logic_1164.all; --------------------------------------ENTITY RSff IS PORT ( r,s,clk,rst: IN STD_LOGIC; q: OUT STD_LOGIC); END RSff; --------------------------------------ARCHITECTURE behavior OF RSff IS BEGIN PROCESS (rst, clk) BEGIN IF (rst='1') THEN q <= '0'; ELSIF (clk'EVENT AND clk=0') THEN if (r='0' and s='1')then q<= '1'; elsif (r='1' and s='0') then q<='0'; elsif (r='1' and s='1') then q<= '-'; end if; END IF; END PROCESS; END behavior;
VD3: asyn-reset DFF & NAND

ENTITY example IS PORT ( a, b, clk: IN BIT; q: OUT BIT); END example; --------------------------------------ARCHITECTURE example OF example IS SIGNAL temp : BIT; BEGIN temp <= a NAND b; PROCESS (clk) BEGIN IF (clk'EVENT AND clk='1') THEN q<=temp; END IF; END PROCESS; END example; --------------------------------------Copyright by N.T.K - 8/2008
S kt hp gia mch t hp v mch dy

DEMO
VD4: B dn knh Multilpexor
a,b: hai knh vo 8bit sel: cc bit chn knh c: knh ra 8bit
VD4: B dn knh Multilpexor

LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY mux IS PORT ( a,b : IN STD_LOGIC_VECTOR (7 DOWNTO 0); sel : IN STD_LOGIC_VECTOR(1 DOWNTO 0); c : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)); END ENTITY mux; --------------------------------------ARCHITECTURE example OF mux IS BEGIN PROCESS (a, b, sel) BEGIN IF (sel = "00") THEN c <= "00000000"; ELSIF (sel=01) THEN c <= a; ELSIF (sel = "10") THEN c <= b; ELSE c <= ZZZZZZZZ; END IF; END PROCESS; END example; Copyright by N.T.K - 8/2008
Demostration
S dng phn mm ActiveHDL thit k v m phng b cng y :

To workspace lm vic. To mt mch thit k design. Vit VHDL source code. Thm file vo design. Dch workspace. a tn hiu vo dng waveform m phng.
Ni dung mn hc
II. Thit k CPU.

3. Cc kiu d liu.
3.1. Cc kiu i tng.

3.1.1. Signal 3.1.2. Variable 3.1.3. Constant
3.2. Cc kiu d liu.
3.1. Cc kiu i tng
Mt i tng VHDL bao gm 1 trong cc loi sau:
Signal: biu din cho dy kt ni gia cc cng ca cc thnh phn trong h thng. Variable: c s dng lu tr d liu ni b tm thi, ch visible bn trong process. Constant: hng s
3.1.1. Signal
Cc i tng signal c s dng kt ni - truyn thng gia cc entity nhm to nn h thng.
Signal
3.1.1. Signal
Phn loi:
External Signal: l cc tn hiu kt ni h thng vi bn ngoi, to nn giao din ghp ni ca h thng vi cc h thng khc. Internal Signal: l cc tn hiu ch nhng bn trong h thng, khng nhn thy t bn ngoi, to ra s truyn thng gia cc thnh phn bn trong h thng.
3.1.1. Signal
External Signal & Internal Signal:

Internal Signal
External Signal
Khai bo trong Entity
Khai bo trong Architecture
ENTITY myboard IS ARCHITECTURE structure OF myboard IS PORT ( [SIGNAL] a,b,c: inout bit; SIGNAL x,y: bit; data,extbus,result: inout bit_vector(0 to 7)); SIGNAL intbus: bit_vector(0 to 7); END myboard; BEGIN Copyright by N.T.K - 8/2008
3.1.1. Signal
V tr khai bo signal:

Phn khai bo ca ENTITY Phn khai bo ca ARCHITECTURE Phn khai bo ca PACKAGE
Khai bo signal:
SIGNAL name: mode type [:=initial_value]
Khng cn trong ENTITY
Ch cn trong ENTITY
3.1.1. Signal
V d khai bo signal trong package:

LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; PACKAGE sigdecl IS TYPE bus_type IS ARRAY(0 to 7) OF std_logic; SIGNAL vcc : std_logic := 1; SIGNAL ground : std_logic := 0; FUNCTION magic_function( a : IN bus_type) RETURN bus_type; END sigdecl; => USE WORK.sigdecl.ALL;
3.1.1. Signal
Phm vi tc ng ca khai bo signal:
Mt signal c khai bo trong PACKAGE th s dng c (visible) trong tt c cc thit k s dng gi package ny. Mt signal c khai bo trong ENTITY th s dng c (visible) trong tt c cc ARCHITECTURE gn vi ENTITY ny. Mt signal c khai bo trong phn khai bo ca ARCHITECTURE th ch s dng c trong architecture ny. Mt signal c khai bo trong 1 khi (block) bn trong ARCHITECTURE th ch s dng c bn trong khi .
3.1.1. Signal
V d v phm vi tc ng ca signal
A B D E F
3.1.1. Signal
Mt c im quan trng ca signal khi c s dng bn trong mt phn ca m tun t (vd PROCESS, FUNCTION, PROCEDURE) l:
Gi tr khng c cp nht ngay lp tc sau cu lnh, m phi n kt thc on m tun t .
V nh tm hiu, hm sau hi
3.1.2. Bin (variable)
Bin variable ch biu din cc d liu ni b, ch c th s dng bn trong PROCESS, FUNCTION, hoc PROCEDURE. Gi tr ca bin variable khng th truyn ra ngoi trc tip. Gi tr ca bin c cp nht trc tip sau tng dng m lnh.
3.1.2. Bin (variable)
Khai bo bin:
VARIABLE name: type [range] [:= init_value];
VARIABLE control: BIT := '0'; VARIABLE count: INTEGER RANGE 0 TO 100; VARIABLE y: STD_LOGIC_VECTOR (7 DOWNTO 0) := "10001000";
V d v s dng variable trong VHDL
LIBRARY ieee; USE ieee.std_logic_1164.all; --------------------------------------ENTITY count_ones IS PORT ( din: IN STD_LOGIC_VECTOR (7 DOWNTO 0); ones: OUT INTEGER RANGE 0 TO 8); END count_ones; --------------------------------------ARCHITECTURE ok OF count_ones IS BEGIN PROCESS (din) VARIABLE temp: INTEGER RANGE 0 TO 8; BEGIN temp := 0; FOR i IN 0 TO 7 LOOP IF (din(i)='1') THEN temp := temp + 1; END IF; END LOOP; ones <= temp; END PROCESS; END ok; Copyright by N.T.K - 8/2008
LIBRARY ieee; LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_1164.all; --------------------------------------------------------------------------------ENTITY mux IS ENTITY mux IS PORT ( a, b, c, d, s0, s1: IN STD_LOGIC; PORT ( a, b, c, d, s0, s1: IN STD_LOGIC; y: OUT STD_LOGIC); 7y: OUT STD_LOGIC); END mux; END mux; --------------------------------------------------------------------------------ARCHITECTURE not_ok OF mux IS ARCHITECTURE ok OF mux IS SIGNAL sel : INTEGER RANGE 0 TO 3; BEGIN BEGIN PROCESS (a, b, c, d, s0, s1) PROCESS (a, b, c, d, s0, s1) VARIABLE sel : INTEGER RANGE 0 TO BEGIN BEGIN sel <= 0; sel := 0; IF (s0='1') THEN sel <= sel + 1;END IF; IF (s0='1') THEN sel := sel + 1; END IF; IF (s1='1') THEN sel <= sel + 2;END IF; IF (s1='1') THEN sel := sel + 2; END IF; CASE sel IS CASE sel IS WHEN 0 => y<=a; WHEN 0 => y<=a; WHEN 1 => y<=b; WHEN 1 => y<=b; WHEN 2 => y<=c; WHEN 2 => y<=c; WHEN 3 => y<=d; WHEN 3 => y<=d; END CASE; END CASE; END PROCESS; END PROCESS; END not_ok; Copyright END ok; by N.T.K - 8/2008
So snh gia Signal & Variable
3.1.3. Hng s (Constant)
Hng s Constant l cc tn c gn cho cc gi tr c th ca 1 kiu DL. S dng hng s cho php ngi thit k xy dng m hnh d hiu (better-documented) v d thay i. Khai bo hng s:

CONSTANT name : type := value; Hng s c th khai bo trong package, entity hoc architecture. Phm vi tc ng ging nh tn hiu signal.
3.1.3. Hng s (Constant)
V d v khai bo hng s:
CONSTANT set_bit : BIT := '1'; CONSTANT pi: REAL := 3.1414; CONSTANT datamemory : memory := ( ('0','0','0','0'), ('0','0','0','1'), ('0','0','1','1'));
3.2. Cc kiu d liu VHDL
3.2.1. Kiu d liu v hng
Kiu d liu v hng (Scalar Types):

Integer types Real types Enumerated types Physical types
Kiu s nguyn Integer

Kiu dl s nguyn 32 bit, synthesizable. H tr cc php tan: +, -, *, / Di gi tr biu din c:
-2,147,483,647 => +2,147,483,647
ARCHITECTURE test OF test IS BEGIN PROCESS(X) VARIABLE a : INTEGER; VARIABLE b : int_type; BEGIN a := 1; --Ok 1 a := -1; --Ok 2 a := 1.0; --error 3 END PROCESS; END test;
Kiu s thc Real

Kiu dl s thc, un-synthesizable. Di gi tr biu din c:

-1.0E+38 => +1.0E+38.
ARCHITECTURE test OF test IS SIGNAL a : REAL; BEGIN a <= 1.0; --Ok 1 a <= 1; --error 2 a <= -1.0E10; --Ok 3 a <= 1.5E-20; --Ok 4 a <= 5.3 ns; --error 5 END test;
Kiu d liu lit k ENUMERATED
Kiu d liu lit k rt hu ch cho vic m hnh ha tru tng, biu din chnh xc cc gi tr cn cho tnh ton.
TYPE bit IS ('0', '1'); TYPE bit_vector IS ARRAY (NATURAL RANGE <>) OF BIT;
TYPE fourval IS ( X, 0, 1, Z ); TYPE state IS (idle, forward, backward, stop); TYPE color IS ( red, yellow, blue, green, orange );
Cc kiu d liu lit k nh ngha trc
Kiu d liu lit k ENUMERATED
Vic m ha cc d liu lit k c thc hin tun t v t ng. V d:

TYPE color IS (red, green, blue, white); C 4 d liu lit k, dng 2 bit biu din, gn 00=>red, 01=>green, 10=>blue, 11=>white.
ENTITY traffic_light IS PORT(sensor : IN std_logic; clock : IN std_logic; red_light : OUT std_logic; IF (sensor = 1) THEN green_light : OUT std_logic; next_state <= green; yellow_light : OUT std_logic); ELSE END traffic_light; next_state <= red; ------------------------------------------------------------ END IF; ARCHITECTURE simple OF traffic_light IS WHEN yellow => TYPE t_state is (red, green, yellow); red_light <= 0; Signal present_state, next_state : t_state; green_light <= 0; BEGIN yellow_light <= 1; PROCESS(present_state, sensor) next_state <= red; BEGIN END CASE; CASE present_state IS END PROCESS; WHEN green => PROCESS next_state <= yellow; BEGIN red_light <= 0; WAIT UNTIL clockEVENT and clock=1; green_light <= 1; present_state <= next_state; yellow_light <= 0; END PROCESS; WHEN red => END simple; red_light <= 1; green_light <= 0; yellow_light <= 0; Copyright by N.T.K - 8/2008
Kiu d liu PHYSICAL
Kiu d liu Physical c dng biu din cc i lng vt l nh khong cch, thi gian, dng in Kiu d liu Physical khng ch ch ra i tng m cn ch ra c cc n v m i tng c th c.
TYPE current IS RANGE 0 to 1000000000 UNITS na; --nano amps ua = 1000 na; --micro amps ma = 1000 ua; --milli amps a = 1000 ma; --amps END UNITS;by N.T.K - 8/2008 Copyright
Primary unit Secondary units
Kiu d liu PHYSICAL
VHDL chun nh ngha sn mt kiu d liu physical l time:

TYPE TIME IS RANGE -2147483647 to 2147483647 UNITS fs; --femtosecond ps = 1000 fs; --picosecond ns = 1000 ps; --nanosecond us = 1000 ns; --microsecond ms = 1000 us; --millisecond sec = 1000 ms; --second min = 60 sec; --minute hr = 60 min; --hour END UNITS;
PACKAGE example IS TYPE current IS RANGE 0 TO 1000000000 UNITS na; --nano amps ua = 1000 na; --micro amps ma = 1000 ua; --milli amps a = 1000 ma; --amps END UNITS; TYPE load_factor IS (small, med, big ); END example; ---------------------------------------------------------------USE WORK.example.ALL; ENTITY delay_calc IS PORT ( out_current : OUT current; load : IN load_factor; delay : OUT time); END delay_calc; ARCHITECTURE delay_calc OF delay_calc IS BEGIN delay <= 10 ns WHEN (load = small) ELSE delay <= 20 ns WHEN (load = med) ELSE delay <= 30 ns WHEN (load = big) ELSE delay <= 10 ns; out_current <= 100 ua WHEN (load = small)ELSE out_current <= 1 ma WHEN (load = med) ELSE out_current <= 10 ma WHEN (load = big) ELSE out_current <= 100 ua; Copyright by N.T.K - 8/2008 END delay_calc;
3.2.2. Kiu d liu tng hp
Kiu d liu tng hp(CompositeTypes)

Kiu mng (Array Types) Kiu bn ghi (Record Types)
Kiu mng (Array Types)
Kiu d liu mng nhm cc phn t cng kiu vi nhau nh l 1 i tng n. Cc phn t trong mng c truy nhp bng ch s. Ba loi mng hay dng:
1D 1Dx1D 2D
Thc t, cc kiu d liu nh ngha sn trong VHDL ch bao gm kiu v hng v vector (mng mt chiu ca cc bit). Cc kiu DL nh ngha sn c th tng hp bao gm:
Scalars: BIT, STD_LOGIC, STD_ULOGIC, and BOOLEAN. Vectors: BIT_VECTOR, STD_LOGIC_VECTOR, STD_ULOGIC_VECTOR, INTEGER, SIGNED, and UNSIGNED.
Khai bo mng:
TYPE name IS ARRAY (spec) OF data_type;
Khai bo s dng kiu mng:
SIGNAL/VARIABLE/CONSTANT signal_name: type_name [:= initial_value];

TYPE data_bus IS ARRAY(0 TO 31) OF BIT;
VARIABLE X: data_bus; VARIABLE Y: BIT; Y := X(0); --line 1 Y := X(15); --line 2
V d v mng 1Dx1D
TYPE row IS ARRAY (7 DOWNTO 0) OF STD_LOGIC; -- 1D array TYPE matrix IS ARRAY (0 TO 3) OF row; -- 1Dx1D array SIGNAL x: matrix; -- 1Dx1D signal -------------------------------------------------------------------------------------------TYPE matrix IS ARRAY (0 TO 3) OF STD_LOGIC_VECTOR(7 DOWNTO 0);
V d v mng 2D
TYPE matrix2D IS ARRAY (0 TO 3, 7 DOWNTO 0) OF STD_LOGIC; -- 2D array
Khi to d liu mng:

... :="0001"; -- for 1D array ... :=('0','0','0','1') -- for 1D array ... :=(('0','1','1','1'), ('1','1','1','0')); -- for 1Dx1D or -- 2D array
V d v mng 1D
PACKAGE array_example IS TYPE data_bus IS ARRAY(0 TO 31) OF BIT; TYPE small_bus IS ARRAY(0 TO 7) OF BIT; END array_example; ------------------------------------------------------------------USE WORK.array_example.ALL; ENTITY extract IS PORT ( data : IN data_bus; start : IN INTEGER; data_out : OUT small_bus); END extract; ARCHITECTURE test OF extract IS BEGIN PROCESS(data, start) BEGIN FOR i IN 0 TO 7 LOOP data_out(i) <= data(i + start); END LOOP; END PROCESS; END test; Copyright by N.T.K - 8/2008
V d v mng 1Dx1D
ARCHITECTURE basic OF rom IS CONSTANT z_state : data_out := (Z, Z, Z, Z CONSTANT x_state : data_out := (X, X, X, LIBRARY IEEE; CONSTANT rom_data : mem_data := USE IEEE.std_logic_1164.ALL; ( ( 0, 0, 0, 0), PACKAGE memory IS ( ( 0, 0, 0, 1), CONSTANT width : INTEGER := 3; ( ( 0, 0, 1, 0), CONSTANT memsize : INTEGER := 7; ( ( 0, 0, 1, 1), TYPE data_out IS ARRAY(0 TO width) ( ( 0, 1, 0, 0), OF std_logic; TYPE mem_data IS ARRAY(0 TO memsize) ( ( 0, 1, 0, 1), ( ( 0, 1, 1, 0), OF data_out; ( ( 0, 1, 1, 1) ); END memory; BEGIN LIBRARY IEEE; ASSERT addr <= memsize USE IEEE.std_logic_1164.ALL; REPORT addr out of range USE WORK.memory.ALL; SEVERITY ERROR; ENTITY rom IS data <= rom_data(addr) AFTER 10 ns WHEN c PORT( addr : IN INTEGER; data <= z_state AFTER 20 ns WHEN cs = 0 E PORT( data : OUT data_out; data <= x_state AFTER 10 ns; PORT( cs : IN std_logic); END basic; END rom;
Kiu mng khng rng buc
Kiu mng khng rng buc v kch thc (Unconstrained arrays):
Kch thc mng khng c ch ra khi khai bo. Kch thc mng s c ch ra khi khai bo signal/variable/constant s dng kiu mng ny.
TYPE BIT_VECTOR IS ARRAY(NATURAL RANGE <>) OF BIT;
Kiu d liu con subtype
Khai bo kiu d liu con c s dng nh ngha cc tp con ca mt kiu d liu. Tp con c th cha tan b khong gi tr ca kiu c s nhng cng c th ch cha mt phn.
TYPE INTEGER IS -2,147,483,647 TO +2,147,483,647; SUBTYPE NATURAL IS INTEGER RANGE 0 TO +2,147,483,647;
V d v khai bo subtype
PACKAGE mypack IS SUBTYPE eightbit IS BIT_VECTOR(0 TO 7); SUBTYPE fourbit IS BIT_VECTOR(0 TO 3); FUNCTION shift_right(val : BIT_VECTOR) RETURN BIT_VECTOR; END mypack; ------------------------------------------------------------------------------PACKAGE BODY mypack IS FUNCTION shift_right(val : BIT_VECTOR) RETURN BIT_VECTOR IS VARIABLE result : BIT_VECTOR(0 TO (valLENGTH -1)); BEGIN result := val; IF (valLENGTH > 1) THEN FOR i IN 0 TO (valLENGTH -2) LOOP result(i) := result(i 1); END LOOP; result(valLENGTH -1) := 0; ELSE result(0) := 0; END IF; RETURN result; END shift_right; END mypack;
Kiu bn ghi record
Kiu d liu bn ghi nhm cc i tng c kiu khc nhau nh mt i tng duy nht. Mi thnh phn ca bn ghi c th c truy cp bng tn trng ca n. Cc thnh phn ca bn ghi c th cng kiu hoc khc kiu d liu. Kiu d liu c th bao gm c mng v bn ghi.
Kiu bn ghi record
V d v kiu bn ghi:
TYPE optype IS ( add, sub, mpy, div, jmp ); TYPE instruction IS RECORD opcode : optype; src : INTEGER; dst : INTEGER; END RECORD;
Kiu bn ghi record

PROCESS(X) VARIABLE inst : instruction; VARIABLE source, dest : INTEGER; VARIABLE operator : optype; BEGIN source := inst.src; --Ok line 1 dest := inst.src; --Ok line 2 source := inst.opcode; --error line 3 operator := inst.opcode; --Ok line 4 inst.src := dest; --Ok line 5 inst.dst := dest; --Ok line 6 inst := (add, dest, 2); --Ok line 7 inst := (source); --error line 8 END PROCESS;
TYPE optype IS ( add, sub, mpy, div, jmp ); TYPE instruction IS RECORD opcode : optype; src : INTEGER; dst : INTEGER; END RECORD;
Kiu bn ghi record

TYPE word IS ARRAY(0 TO 3) OF std_logic; TYPE t_word_array IS ARRAY(0 TO 15) OF word; TYPE addr_type IS RECORD source : INTEGER; key : INTEGER; END RECORD; TYPE data_packet IS RECORD addr : addr_type; data : t_word_array; checksum : INTEGER; parity : BOOLEAN; END RECORD;
PROCESS(X) VARIABLE packet : data_packet; BEGIN packet.addr.key := 5; --Ok packet.addr := (10, 20); --Ok packet.data(0) := (0, 0, 0, 0); packet.data(10)(4) := 1; --error packet.data(10)(0) := 1; --Ok END PROCESS;
Kiu d liu File
Cc file bao gm cc dy tun t ca mt kiu d liu (c th l INTEGER, record) Cui mi file c nh du kt thc bng k t End of file.
Kiu d liu File
Cc thao tc thc hin vi file:

READ (file, data)Procedure WRITE (file, data)Procedure ENDFILE (file)Function, returns boolean
Kiu d liu File
Khai bo kiu file:
TYPE int_file IS FILE OF INTEGER;
Khai bo i tng file:
FILE myfile : int_file IS IN /test/data_file
V d v truy cp file
LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; ENTITY rom IS PORT(addr : IN INTEGER; cs : IN std_logic; data : OUT INTEGER); END rom; ARCHITECTURE rom OF rom IS BEGIN PROCESS(addr, cs) VARIABLE rom_init : BOOLEAN := FALSE; --line 1 TYPE rom_data_file_t IS FILE OF INTEGER; --line 2 FILE rom_data_file : rom_data_file_t IS IN /dlp/test1.dat; --line 3 TYPE dtype IS ARRAY(0 TO 63) OF INTEGER; VARIABLE rom_data : dtype; --line 4 VARIABLE i : INTEGER := 0; --line 5 BEGIN IF (rom_init = false) THEN --line 6 WHILE NOT ENDFILE(rom_data_file) --line 7 AND (i < 64) LOOP READ(rom_data_file, rom_data(i)); --line 8 i := i + 1; --line 9 END LOOP; rom_init := true; --line 10 END IF; IF (cs = 1) THEN --line 11 data <= rom_data(addr); --line 12 ELSE data <= -1; --line 13 END IF; END PROCESS; Copyright by N.T.K - 8/2008 END rom;
Cc kiu DL c th tng hp
ti mn hc Thit k nh MT
Nhm: 6 ngi/nhm
ti mn hc Thit k nh MT
ti c 2 phn:
Phn 1: Nghin cu v d v vit CPU trong ti liu VHDL Programming by Example 4th Ed Douglas L.Perry. Phn 2: Thc hin 1 trong cc ti sau:
ti phn 2 (C)
1.
2.
3. 4. 5. 6. 7.
8051 PIC 16F84 VHDL & Verilog AVR ATTiny64. AVR AT90S1200. AVR ATMega. miniMIPS. SuperH-2 (Aquarius).
8.
9.
10.
MIPS I (YACC-Yet Another CPU) Verilog. Yellow Star (MIPS R3000) Verilog. OpenRISC 1000 (32/64bit RISC).
ti phn 2 (others)
1. 2.
3. 4. 5. 6. 7. 8.
PCI Bridge. Ethernet MAC 10/100 Mbps

VGA/LCD Controller. PS2 Interfaces (y/c hardware). UART Controller. FPU (Floating Point Unit). M ha AES. M ha DES.
Ch : Nn lm cng mn n FPGA.
ti phn 3 (ko lm)

Nghin cu,tm hiu ngn ng Verilog.

Nghin cu,tm hiu ngn ng VHDL-AMS.
Yu cu:
Bo co:
Tm hiu v xy dng li s khi ca vk. Phn tch k tng khi. Thc hin test kim nghim hot ng. Tm hiu hot ng trong 1 chu k ng h. Ni r cng vic tng ngi.
Ti liu tham kho
Cch thit k 1 vk bng VHDL:

MicroProcessor Design. VHDL Programming by Examples (4th). www.opencores.org www.asics.ws
Websites:

Lch bo v: 17/11

30% im Khng bo v -> ko thi L1 Nu lm tt => +10 im vo bi thi a im: b mn KTMT C1-322. Thi gian: 8h 17h Y/c: Mang slide + M ngun + Ti liu TK
Khi bo co s phi demo chng trnh (chy m phng). Nu ai demo phc tp, t em my tnh.

VHDL 12533375633445 Phpapp01

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VHDL 12533375633445 Phpapp01

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Thit k nh my tnh

Nguyn Thnh Kin

Ti liu tham kho

Copyright by N.T.K - 8/2008

Copyright by N.T.K - 8/2008

Copyright by N.T.K - 8/2008

Tham gia >75% s gi hc.

Cch tnh im:

Copyright by N.T.K - 8/2008

I. Thit k mch vi ngn ng VHDL.

II. Thit k CPU.

I. Thit k mch vi ngn ng VHDL.

II. Thit k CPU.

1. Gii thiu ngn ng VHDL.

Copyright by N.T.K - 8/2008

1. Gii thiu ngn ng VHDL.

Mt ngn ng m t phn cng:

Copyright by N.T.K - 8/2008

1. Gii thiu ngn ng VHDL.

VHDL l chun c lp m t h thng:

1. Gii thiu ngn ng VHDL.

Copyright by N.T.K - 8/2008

1. Gii thiu ngn ng VHDL.

Hai ng dng chnh ca VHDL l:

PLD (Programmable Logic Device):

CPLD (Complex PLD) FPGA (Field Programmable Gate Array).

ASIC (Application-Specific IC)

Copyright by N.T.K - 8/2008

Quy trnh thit k mch da trn VHDL

Copyright by N.T.K - 8/2008

Cc cng c thit k VHDL

B cng c ca nh sn xut chip:

Mt s cng c ca cc hng th ba:

Copyright by N.T.K - 8/2008

Copyright by N.T.K - 8/2008

I. Thit k mch vi ngn ng VHDL.

II. Thit k CPU.

Th vin LIBRARY ENTITY ARCHITECTURE

Copyright by N.T.K - 8/2008

Copyright by N.T.K - 8/2008

Cc th vin thng s dng:

-- declaration, while a double -- dash (--) indicates acomment.

Copyright by N.T.K - 8/2008

Copyright by N.T.K - 8/2008

Th vin LIBRARY ENTITY ARCHITECTURE

Copyright by N.T.K - 8/2008

ENTITY l danh sch c t ca cc cng vo ra (input/output pins) ca mch.

signal_mode: chiu truyn d liu

Th vin LIBRARY ENTITY ARCHITECTURE

Copyright by N.T.K - 8/2008

Phn ARCHITECTURE m t mch hot ng nh th no.

ARCHITECTURE c hai phn:

Phn khai bo (optional)

Khai bo tn hiu v bin. M t cch kt ni, hot ng ca mch.

Copyright by N.T.K - 8/2008

B cng hai s 1bit y

A(7:0) C(7:0) B(7:0) Adder

library IEEE; use IEEE.std_logic_1164.all;

A(7:0) B(7:0) Adder

Architecture dataflow of adder is C <= A+B; end dataflow;

Copyright by N.T.K - 8/2008

VD2: D Flip-flop, asyn reset

VD2: RS Flip-flop, asyn reset