Digital Pulse Counter - Two Digits

This project of Digital Pulse Counter. There are two 7 segment displays and IC 4026 used here to count up to 99. The 5th pin of 4026 gives out a pulse when it moves from 9 to 0. The pulse from the one's place fed to the ten's place 4026 to move to the next digit as one's place digit moves to 0 from 9. Note the connection from pin 5 of second IC to pin 1 of first IC Once you have done the single digit project and gets it working doing this project is a piece of cake. Below is the circuit used to build the counter.

Description:
This project is about implementation of a two digit totalizing counter. This counter has got practical applications in many fields like audio oscilloscope, MultiMeter, digital watches etc. It is also used in banks but the count is randomly generated. The basic idea in which the project is based is the conversion of BCD counter to a seven segment decoder circuit. The entire idea behind the totalizing counter is that it counts from 0 to 99 and then resets to 0 and starts counting again in this repeated manner. Thus the basic logic lies behind the design of the counter which generates the count of the digit in the units place in the usual manner that is for every clock pulse it gives an increment in the count and thus counts from 0 to 9 but the count in the tens place should be incremented by 1 only at The eleventh pulse. Thus we require two mod 10 counter for the purpose such that the units place counter counts from 0 to 9 in usual manner and the tenth place counter changes to count after every 10th clock pulse

WORKING:
Once the reset switch is ON the circuit is ready. Now we start giving the clock pulse. With each clock pulse the LSB counter is incremented by 1. When the LSB counter reaches 9 the next clock pulse makes the LSB 0 and the MSB counter is incremented by 1. For this Q4 of LSB is given to the clock of MSB. This continues until 98 are reached. The next clock pulse makes count 99. For this Q1 and Q4 of LSB and MSB are to the input of the counter is still on 99 and the circuit is reset to 00.

Uses:
This project is about implementation of a two digit totalizing counter. This counter has got practical applications in many fields like audio oscilloscope, Multimeter, digital watches etc. It is also used in banks but the count is randomly generated. The basic idea in which the project is based is the conversion of BCD counter to a seven segment decoder circuit.

CONCLUSION:

The TWO DIGIT TOTALISING COUNTER counted from 00 to 99 with increment of 1 per clock pulse. As soon as 99 were reached the beeper started beeping. At this state there was no effect of clock pulse on the counter. When the reset switch was pressed, the counter was reset to 00 and the beeper stopped beeping.

CD4026BE Decade BINARY Counter with 7 Segment Display Drivers

Manufacturer:
Texas Instruments

Family:
CMOS Decade Counter/Divider with Decoded 7-Segment Display Outputs and Display Enable.

Description:
CD4026B consist of a 5-stage decade counter and an output decoder which converts the decade code to a 7-segment decoded output for driving one stage in a numerical display. These devices are particularly advantageous in display applications where power dissipation low and /or low package count are important. Inputs common to both types are CLOCK, RESET, & CLOCK INHIBIT; common outputs are CARRY OUT and the seven decoded outputs (a, b, c, d, e, f, and g). Additional inputs and outputs for the CD4026B include DISPLAY ENABLE input and DISPLAY ENABLE and UNGATED "C-SEGMENT" outputs. Signals peculiar to the CD4033B are RIPPLE-BLANKING INPUT AND LAMP TEST INPUT and a RIPPLE-BLANKING OUTPUT.

PIN DIAGRAM:

Pin Name number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CLK CI DE DEO CO F G VDD D A E B C UCS RST Clock in

Purpose

Clock inhibit - when low, clock pulses increment the seven-segment Display enable - the chip outputs to the seven-segment when this is high (i.e. when it's low, the seven-segment is off) - useful to conserve battery life, for instance Display enable out - for chaining 4026s Carry out output - Is high when changing from 9 to 0. It provides an output at 1/10 of the clock frequency, to drive the clock input of another 4026 to provide multi-digit counting. Output for the seven-segment's F input Output for the seven-segment's G input The connection to the 0 V rail Output for the seven-segment's D input Output for the seven-segment's A input Output for the seven-segment's E input Output for the seven-segment's B input Output for the seven-segment's C input Ungraded C-segment - an output for the seven-segment's C input which is not affected by the DE input. This output is high unless the count is 2, when it goes low. Reset - resets all outputs to low when taken high

16

VSS

The connection to the +9 V rail

Counter:
A counter , by function , is a sequential circuit consisting a set of flip flop connected in a suitable manner to count the sequence of the input pulse presented to it in digital form. Counters can be broadly classified under 3 heads as follows: 1. Asynchronous and Synchronous Counter: In asynchronous counter the output of one flip flop is connected as clock to the next flip flop . But in synchronous counter , for each flip flop has separate clock . 2. Single and Multi-mode Counter: In single mode counter operate only either up or down count . But in multi-mode counter both up and down counter can be operate 3. Modulus Counter: Modulus counter mean it operate the predetermined state. For example in mod 10 counter , it count only 10 state.

MOD-10 COOUNTER
In the previous tutorial we saw that an Asynchronous counter can have 2n-1 possible counting states e.g. MOD-16 for a 4-bit counter, (0-15) making it ideal for use in Frequency Division. But it is also possible to use the basic asynchronous counter to construct special counters with counting states less than their maximum output number by forcing the counter to reset itself to zero at a pre-determined value producing a type of asynchronous counter that has truncated sequences. Then an n-bit counter that counts up to its maximum modulus (2n) is called a full sequence counter and a n-bit counter whose modulus is less than the maximum possible is called a truncated counter. But why would we want to create an asynchronous truncated counter that is not a MOD-4, MOD-8, or some other modulus that is equal to the power of two. The answer is that we can by using combinational logic to take advantage of the asynchronous inputs on the flip-flop. If we take the modulo-16 asynchronous counter and modified it with additional logic gates it can be made to give a decade (divide-by-10) counter output for use in standard decimal counting and arithmetic circuits. Such counters are generally referred to as Decade Counters. A decade counter requires resetting to zero when the output count reaches the decimal value of 10, i.e. when DCBA = 1010 and to do this we need to feed this condition back to the

reset input. A counter with a count sequence from binary "0000" (BCD = "0") through to "1001" (BCD = "9") is generally referred to as a BCD binary-codeddecimal counter because its ten state sequence is that of a BCD code but binary decade counters are more common.

Asynchronous Decade Counter

This type of asynchronous counter counts upwards on each leading edge of the input clock signal starting from "0000" until it reaches an output "1010" (decimal 10). Both outputs QB and QD are now equal to logic "1" and the output from the NAND gate changes state from logic "1" to a logic "0" level and whose output is also connected to the CLEAR (CLR) inputs of all the J-K Flip-flops. This causes all of the Q outputs to be reset back to binary "0000" on the count of 10. Once QB and QD are both equal to logic "0" the output of the NAND gate returns back to a logic level "1" and the counter restarts again from "0000". We now have a decade or Modulo-10 counter.

Decade Counter Truth Table

Output bit Pattern Decimal Clock QD 1 2 3 4 5 6 7 8 9 10 11 QC QB QA Value 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 1 0 1 1 1 0 0 1 0 0 Counter resets its 0 0 1 1 0 2 1 3 0 4 1 5 0 6 1 7 0 8 1 9 Outputs back to Zero

Decade Counter Timing Diagram

summry:
Asynchronous Counters can be made from Toggle or D-type flip-flops. They are called asynchronous counters because the clock input of the flipflops are not all driven by the same clock signal. Each output in the chain depends on a change in state from the previous flipflops output. Asynchronous counters are sometimes called ripple counters because the data appears to "ripple" from the output of one flip-flop to the input of the next. They can be implemented using "divide-by-n" circuits. Truncated counters can produce any modulus number count.

Disadvantages of Asynchronous Counters:

An extra "re-synchronizing" output flip-flop may be required. To count a truncated sequence not equal to 2n, extra feedback logic is required. Counting a large number of bits, propagation delay by successive stages may become undesirably large. This delay gives them the nickname of "Propagation Counters".

Counting errors at high clocking frequencies. Synchronous Counters are faster using the same clock signal for all flip-flops.