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Agenda
1.Explanation of Layout and Function of Circuit Board 2.Operation Explanation per Board
2-1 Drive Description on SMPS 2-2 Operation Explanation of Driving Circuit 2-3 Logic-Main Board 2-4 Scaler Board
SM PS
Y- MAIN X- MAIN
Lo g ic - Main
E- buffer
F- buffer
G- buffer
COF x 7
.X-MAIN BOARD : It makes the drive wave form by switching FETs to Timing Controlle coming from logic-board and supplies X electrode of panel with the drive wave form via connector.
.Y-MAIN BOARD : It makes the drive wave form by switching FETs to Timing Controller coming from the logic-board and provides Y electrode of panel with the drive wave form via Scan Driver IC on Y buffer board in order.
.LOGIC MAIN BOARD : It process image signal and performs buffering of the logic-main board (to create XY drive signal and output) and the address driver output signal. Then it supplies the output signal to the address driver IC(COF Module).
.Y-BUFFER (Upper,Lower) : It is the board to impress the scan waveform on the Y board and consist of 2 boards (upper board and lower board). 8 Y-buffers are fixed at the scan driver (STV7617 of STC corp. : 64 or 65 Output).
.AC Noise Filter : It has functions to remove noise(low frequency) coming from AC LINE and prevent surge. It gives serious effects on the safety regulations (EMC, EMI) according to AC filter.
.COF(Chip on Flexible) : It impress the Va pulse to the address electrode in the address section and forms the address discharge by electric potential difference with scanning pulse to be dismissed by the Y electrode. It is made in the form of COF and one COF consists of 4 Data Drive IC (STV7610A :96 Output), otherwise single scan is made of 7 COF.
Address Electrode
Back panel
Y4 8 0 X
Re fe r e n c e
- A1 ,A2 , , , : Add r e s s Ele c tr od e - Y1 ,Y2 , , , : S c an & S us ta in Ele c tr od e - X : Com m o n & S us ta in Ele c tr od e
ADDRESS OPERATION
SUSTAIN OPERATION
Reset
Address
Sustain
Function Sustain Erase Wall Charge Set Issue Operation margin Contrast Short Time
Function Select On Cell Issue High Speed Low Voltage Low Failure
Function Discharge On Cell Issue High Efficiency Low Voltage ERC Performance
SF2
SF3
SF4
SF5
SF6
SF7
1T 2T 4T 8T 16T
32T
64T
128T
sustain
D X Y1 Y2 Yn
SF2
SF3
SF4
SF5
SF6
SF7
1T 2T 4T 8T 16T
32T
64T
128T
sustain
Lo g ic B'd
X- Ma in B'd
PDP Panel
852 X 4 80 Pixe ls 853 X 3 X 480 Ce lls X- Puls e Ge ne ra to r
Inp ut Da ta Pro c e s s o r
Da ta Co ntro lle r
Clo c k : 27MHz
Clo c k : 60MHz
20MHz 40MHz
Po we r S up p ly
LVDS
Dig ita l B'd Ana lo g B'd Aud io Pro c e s s o r Vid e o S /W Co mb Filte r Tune r
AC Po we r S o urc e 220V
CN805 (10 P)
CN805 (10 P)
Y- Ma in
CN804 (9P)
CN804 (9P)
CN801 (10 P)
X- Ma in
CN803 (10 P)
Log ic
CN402
CN101 CN403
CN101
CN806)
EF1
GF1 AC Inle t
CN111 CN601
CN802
CN801
Digital
Ana log
PIN CONFIGURATION
[ S c a le r : Ana log
CN101(Co ntro l) NO 1 2 3 4 5 6 7 8 9 10 11 12 PIN Name GND S CL1 S DA1 GND S AFT GND MUTE GND MAFT GND ANAL_CVBS GND CN102(Vid e o /S ync ) NO 1 2 3 4 5 6 7 8 9 10 11 12 PIN Name ANAL_YCOMB GND ANAL_CCOMB GND ANAL_Y2 GND ANAL_PB2 GND ANAL_PR2 GND ANAL_H ANAL_V
Dgita l ]
CN103(Vid e o /S ync ) NO 1 2 3 4 5 6 7 8 9 10 11 12 PIN Name ANAL_YCOMB GND ANAL_CCOMB GND ANAL_Y2 GND ANAL_PB2 GND ANAL_PR2 GND ANAL_H ANAL_V NO 1 2 3 4 5 6 7 8 9 10 11 12 13 14
[ S c a le r Dgita l
PIN Name GND GND Tx Out0- / Rx In0Tx Out0+ / Rx In0+ GND GND Tx Out1- / Rx In1Tx Out1+ / Rx In1+ GND GND Tx Out2- / Rx In2Tx Out2+ / Rx In2+ GND GND
Log ic (CN601) ]
NO 17 18 19 20 21 22 23 24 25 26 27 28 29 31 PIN Name GND GND Tx Out0- / Rx In0Tx Out0- / Rx In0GND GND GND GND RES ET_MN GND IIC S CL2 GND IIC S DA2 GND GND 16 Tx CLK Out+ / Rx CLK In+
PIN CONFIGURATION
[ S MPS
CN801(An a lo g Tu) NO 1 2 3 4 5 6 7 8 9 10 Po we r GND A33V GND GND AMP12V AMP12V GND D12V GND D6V
[ S MPS
CN804(X- Ma in) Po we r D5V VG GND GND VE GND GND VS VS NO 1 2 3 4 5 6 7 8 9 10
X,Y- Ma in / Buffe r ]
CN805(Y- Ma in) Po we r D5V VG GND Vs c a n GND Vs e t GND GND VS VS CN806/ 812(Buffe r) NO 1 2 3 4 5 Po we r Va Va N. C. GND GND
COLD
Vs (+ 8 5V)
DC/DC Converter
DC/DC Con ve r te r
Vs et (+ 9 5V) Ve (+ 11 0 V)
NOIS E FILTER
Retur n PWM c o ntrol S tag e Va_S witc hing S tag e Aux ilia ry S tag e
Vcc
DC/DC Con ve r te r
Vs c an (+ 78 V)
Va(+ 7 9 V) Retur n
S tand_By
A1 2 V(+ 1 2V) D5 V (+ 5V)) Retur n MAG- AMP D3 .3 V (+ 3 .3 V) Vg (+ 15 V) 1 2 V Amp(+ 12 v) A6 V(+ 6V) PWM c o ntrol D6 V(+ 6V) V_analo g S witc hing S tag e Reg .
PS - ON/Relay S ignal
COLD
HOT
S tag e
COLD
2. Input controller SMPS works in whole section of AC 90~264V. It is possible to start in the AC 90 and can restart with new input voltage, even in interruption of electric power. STD_5V comes out when AC is impressed
3. Output Controller Given SMPS have 15 output voltages. The following shows the specification of output voltage and output current in case of their successive drive.
12VAMP + 1 2V VT S T D_5V + 3 3V + 5V
3-1. Overvoltage protection It has circuit to maintain normal voltage, additionally with circuit for sensing overvoltage, so it means any overvoltage does not give impacts on other output controller. SMPS prevents overvoltage in the latch mode. VS(85V) works protection function more than 100V, over 94V for VA(75V), over 8.2V for D6V, over 4.7V for D3.3V
4. Detail Description AC-DC Converter It converts AC into DC by using the power factor improvementcircuit. This converter was designated to control the high frequency noise, with the function to improve the power factor. This part becomes input controller of another constant-voltage.
[ P F C Drive F ET (S P W4 7 N6 0) Dra in P u ls e ]
[ P F C Drive F ET (S P W4 7 N6 0) Ga te P u ls e ]
Configuration of VS output Major part of PDF SMPS outputs 85V 5A. It takes asymmetrical half bridge converter and connects 2 converters with 85V output in parallel, which increases efficiency than one 85V converter, on the other hand, decreases its size.
[ VS ET Puls e ]
[ VE Puls e ]
[ Vs c an Puls e ]
[ Va Ma in P uls e ]
NG S TB_5V
OK
PFC
OK NG
OK
PFC
NG PFC
NG
VS
OK
Vs c an VE,Vs e t OK
2) Working Principle of Driver Circuit To develop image on the PDP, the voltage should be impressed into the X, Y and ADDRESS electrodes (which are component of each pictorial element) under the proper conditions. The driver wave form which is currently applied to is ADS (Address & Display Separate: Driving method to work by dividing address and constant-current section ) Based on this method, the discharge to be done in the pictorial element of PDP can be divided into 3 types as follows.
Address Discharge: to form the wall voltage within pictorial element by providing lighting pictorial element with information(impressing data voltage) : It is the discharge produced by difference between the positive electric potential of address electrode (normally, Va impressed voltage of 70~75V +Positive Wall charge) and negative electric potential of Y electrode (GND level impression+ Negative Wall charge).
If the wall voltage formerly exists in the pictorial element(i.e., the pictorial element is on), the discharge makes forms again because the voltage higher than one of the discharging starting time is impressed by combination of the wall voltage and of the next impressed constant-current. While if the wall voltage does not exist in the pictorial element (i.e., the pictorial element is off), the discharge does not form because the voltage could not reach to the level of the discharging starting time, only with constant-current.
Vs
: 85V
Vscan : 70V ~ 80V - Scan bias Vdd : 3.3V Vcc : 15V Logic Signal : Supplied from logic board : Gate signal of each FET - Logic signal buffer IC - FET Gate drive IC
Addre s s P uls e
A 2. . . . . 1, X Y 2. . . . 1,
A es s (=D a) El ect r ode ddr at Com on & Sus t ai n El ect r ode m Scan & Sus t ai n El ect r ode
V s V et s V can s
V e V a
110V 79V
Y Falling Ramp Pulse Most of Negative Wall charges accumulated on the Y electrode by the X bias of about 200V are used to remove Positive Wall charges in the Y Falling Ramp zone, and most of Positive charges accumulated on the (0V) Rising Ramp zone toward the address electrode are maintained, having distribution of wall charges beneficial for the subsequent address discharge.
1st Sustain Pulse The Sustain Pulse always begins from the Y electrode, it is because Positive Wall charges are formed on the Y electrode if address discharge occurs. The wall charges formed by the address discharge are less than those for the sustain discharge, and thus the strength of the initial discharge is weak. Sustain discharge usually become stable after 5~6 times of discharge depending on structure of electrode and environment. Therefore, the initial long sustain pulse is intended to form the initial discharge stable and form the wall charges much as possible as.
OUT L
OUT H
O TL U O TH U
O TL U
O TH U
O T3 U O T4 U O T6 U O T5 U
TPOU T
CN 803 28. 636M z X H 2002 O SC CY 2305 U 2003 EPC2 U 2011 EPC2 U 2007 EPC2 U 2006 64M SD M RA U 2014
X 2000 60M z H 64M CY 2305 U 2002 SD M RA U 2013 R ESET SPS10- M EM A C SI M OY EM R CO TR N OLLER U 2000 Ci r cui t X CO TRO N L X CO TR N OL CN 101
EP20K 400EBC652- 1 Y CO TR N OL Y CO TRO N L CN 201 28BV 256K U 2001 IIC V CC(3. 3V ) GD N I I C(SCL, SDA ) CN 2002 CN 401
A 101~106 DRV A 201~206 DRV A 301~306 DRV CLK BLK POL, STB , ,
40M z H X 2001
CN 402
A 501~506 DRV A 601~606 DRV A 701~706 DRV CLK BLK POL, STB , ,
CN 403
e-buff er
f-buff er
g-buff er
REMARKS
Ex te rnal : 2,4 On Inte rnal : 3 On
4 2" S D
OFF 1 2 3 4
N o. LV connect or DS
I t em LED for operat i on check I 2C connect or 256K Y connect or X connect or CN 401(E- addres s buf fer connect or) CN 402(F- addres s buf fer connect or) CN 403(G addres s buf fer] connect or) Power connect or Power fus e O ON S/ W PTI
Expl anat i on Connect or for recei vi ng R B, H V D TA , D G , , A EN CLK encoded i n t he LV from i m DS age board. LED t o s how t hat Sync, cl ock i s nor m l y i nput i nt o t he l ogi c board al Connect or connect i ng t he K Scan Board t hat checks and adj us t s 256K dat a ey Eeprom t o s ave t abl e, A t abl e, dri vi ng w PC avef orm t i m ng and ot her opt i on, et c i Connect or t o out put cont r ol s i gnal of t he Y dri vi ng board Connect or t o out put cont r ol s i gnal of t he X dri vi ng board Connect or t o out put addres s dat a, cont r ol s i gnal t o t he E-buf fer board Cnnec t or t o out put addres s dat a, cont r ol s i gnal t o t he F-buf fer board Connect or t o out put addres s dat a, cont r ol s i gnal t o t he G -buf fer board Connect or t o recei ve power 95V t o t he l ogi c board ] Fus e at t ac hed t o power [5V t o t he l ogi c board ] I nner / O er cut -off S/ W ut
Logi c Board
Funct i on
- Pr oces s es I m age s i gnal (WL, er r or di s per s i on, A / PC) - O put s i m ut age s i gnal as addr es s dr i ver cont r ol s i gnal , dat a s i gnal buf fer boar d - O put s t he X dr i vi ng boar d cont r ol s i gnal ut Y
R ar ks em
Logi c M n ai
- D i ver s dat a s i gnal and cont r ol s i gnal t o t he el r i ght / r i ght CO F - D i ver s dat a s i gnal and cont r ol s i gnal t o t he el m ddl e/ l ow CO i er F - D i ver s dat a s i gnal and cont r ol s i gnal t o t he el Ri ght / Low CO er F
V PC3230
CVBS
20. 25M K 4S641632E K 4S643232E A 500 SI K 4S643232E SD 6000 A BA 7657 V PC3230 20. 25M 14. 3181M K 4S643232E M 160 27V
Y/ C
Y/ Pb/ Pr/ H/ V
74H C4052
DVI L/ R R/ G/ B/ H V / D- SU L/ R B
S- VH Y/ C S
DVI , D- SU L/ R B S- VH L/ R S
RS- 232
DVI
DVI SOU D N
D- SU B
D- SU B Sound
S- VI DEO
18. 432M
Y/ C CN1 01
U 64083 PD
20M
L/ R CN1 02
S- CV BS
TEA 6425
Y/ Pb/ Pr
BA 7657 TA 1101
M CV - BS
TU ER 2 N TU ER 1 N
VODEO
COM EN PON T1
COM EN PON T2
SOU D OU T N TPU
RF IN T PU
PC
DI V
(SCALER PIP)
TV V deo/ S-V deo/ Com / i i ponent 1, 2(SD ) Com ponent 1, 2(H ) D 32 32 32 0 0 0 0 0 0 0 PC DI V
12. Option
I TEM PI X SH FT I SH FT TEST I PI X N M U BER SH FT LI N I E SH FT TI M I E COU TRY N TEM PRO P TECT SN D O I EM SN TH G I ROU H V D M TE I EO U I RC A FN LA G A E NUG CU M STO ER TU ER N TV V deo/ S- V de o/ Com / i i ponent 1, 2(SD) Com ponent 1, 2(H D) 0 0 2 1 4 0 0 0 0 10 0 0 0 0
0 : OFF 1: ON 1 : TH OU H R G 0 : N TH OU H OT R G U t : 100m ec ni s 0 : for cus t om er 0 : Engl i s h 0 : CE 0: 1 TU ER N 1 : for m l i t ar y i 2 : Spani s h
PC
DI V
0 : OFF 0 : m nut e i
Rem k ar
1 : ON 1 : s econd
N ber of s hi ft ed Li nes hori zont al l y um N ber of s hi ft ed Li nes vert i cal l y um Ti m fi xed at SH FT TEST e I 0 : dom t i c es 1: U SA 2 : Japan
1 : Fr ench 1: VB M 1: 2 TU ER N
* Dimensions in mm
Che ck V t age s ol on t he SM PS (V , V Ve, V et . . ) s a, s OK Che ck t he dam aged com pone nt s on X Y-M n & , ai A ddres s Board
N O
N Dam O aged Com pone nt s Che ck t he Fus es on X Y-M n Boards , ai (F4003, F5003) OK Change Y M n - ai N O Change X M n - ai N O N O Change t he dam aged Board
I can s ee s om V deo e i ex) TV V de o or et c I nput s our ce , i Che ck whe t her al ways N V deo o i about al l A i nput s V
Di gi t al
Alexander (V2)
Mozart (V3)
Nelson (V3)
Brightness Contrast ratio Tuner Audio out Sound Speaker Video input S-Video input Component Input Side Input DVI Power Consumption Etc.
700cd/m2 1200:1 2Tuner 10W x 2 Dolby Virtual Not Included 1Rear 1Rear 2Rear 1Rear 330W -
1000cd/m2 3000:1 2Tuner 15W x 2 SRS Tru Surround XT Included 2Rear 1Rear 2Rear CVBS, S-Video 1Rear 330W Touch Pad, Melody
1000cd/m2 3000:1 1Tuner 15W x 2 SRS Tru Surround XT Not Included 1Rear 1Rear 1Rear 1Rear 330W -