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B CNG THNG TRNG I HC KINH T - K THUT CNG NGHIP KHOA IN - IN T YYYYY YYYYY

THC TP NNG CAO HDL


Ti: Tng quan v HDL, VHDL, Verilog v thit k b gii m dng verilog
Ging vin hng dn Sinh vin thc hin : : Ch c Hong Phm Tin i V Xun o L Tun t inh Cng t Phng Tin t Trn Hu Long Lp Nhm : in T 2AHN : 6

H Ni 01- 2012

MC LC

LI NI U.....................................................................................................3 TNG QUAN V HDL, VHDL, VERILOG V THIT K B GII M DNG VERILOG...........................................................................................................4 PHN I: PHN II: TNG QUAN V HDL VERILOG........................................................4 TNG QUAN V VHDL........................................................31 Thit k t trn xung (top-down)...........................................................22 2.1. Gii thiu v ngn ng m t phn cng VHDL. .................................31 2.2. Cu trc mt m hnh h thng m t bng VHDL...............................33 2.2.1. Thc th (entity) ca m hnh. ....................................................33 2.2.2. Kin trc ca m hnh. .................................................................35 PHN III: THIT K B GII M DNG VERILOG...........37 3.1. V d 1: Thit k mch gii m 3 sang 8........................................37 3.2. V d 2 : Thit k mch gii m 4 sang 16.......................................44 KT LUN....................................................................................................... 49

LI NI U

Hin nay cc mch tch hp ngy cng thc hin c nhiu chc nng hn, do chng ngy cng tr nn phc tp hn. Cc phng php thit k mch truyn thng nh dng ti thiu ho hm Boolean hay dng s cc phn t khng cn p ng c cc yu cu t ra khi thit k. Hn na cc mch thit k ra yu cu phi c th nghim k lng trc khi a vo ch to hng lot.

Mt khc cn phi xy dng mt b ti liu hng dn vn hnh h thng hon chnh d hiu v thng nht. Chng ta lm vic vi mt s chng trnh phn mm h tr cho vic thc hin m t mch hay hiu c cch thit k mch. V d: Proteus, HDL,VHDL, VerilogTrong phn ny chng ta s dng hai ngn ng phn cng chun cng nghip l VHDL v Verilog. C hai ngn ng ny u c s dng rng ri v c IEE chp nhn.

Di y l bi vit : Tng quan v HDL, VHDL, Verilog v thit k b gii m dng Verilog. Bi vit ny s gip chng ta hiu mt cch tng quan nht v HDL, VHDL, Verilog v bit cch thit k mt b gii m s dng Verilog, thng qua phn mm Quatus II.

TNG QUAN V HDL, VHDL, VERILOG V THIT K B GII M DNG VERILOG

PHN I:

TNG QUAN V HDL VERILOG.

1.1. 1.1.1.

Gii thiu v HDL v verilog:


Lch s pht trin HDL: 4

a) ISP (circa 1977) d n nghin cu CMU (Carnegie Mellon University) M phng nhng khng tng hp
b)

Abel (circa 1983) c trin bi Data-I/O

Mc tiu dng cho cc thit b lun l kh lp trnh Khng tt cho my trng thi c) Verilog ( circa 1985) pht trin bi Gateway ( now Cadence) c t c a ra t 1985 Ban u c pht trin cho m phng, tng t C v Pascal Hiu qu v d vit Berkeley pht trin cng c tng hp vo thp nin 80 c IEEE chun ha Verilog standardized (Verilog-1995 standard) Verilog-2001 standard d) VHDL (circa 1987) - DoD sponsored standard Da trn VHSIC pht trin bi DARPA Tng t nh Ada (Nhn mnh vo ti s dng v bo tr)

Ng ngha phng m r rng

Rt tng qut nhng di dng c IEEE chun ha VHDL standardized (87 and 93) Cu trc nghim ngt
1.1.2.

Gii thiu v HDLs:

a) HDLs (Hardware Description Languages)

Khng l mt ngn ng lp trnh Ta C

Thm nhng chc nng m hnh ha, m phng chc nng.

Verilog vs. VHDL b) Cc bc thit k bng HDL M t mch t kha Bin dch kim tra c php (syntax) M phng kim tra chc nng ca mch 1.1.3. Verilog HDL: a) Verilog l mt ngn ng ln C nhiu tnh nng cho tng hp v m phng phn cng C th biu din nhng c trng mc thp Transistor

C th hot ng nh ngn ng lp trnh

Cu trc lp Cu trc iu khin.


b) c)

Cc cng c m phng chp nhn ton b khi nim ca Verilog Cc cng c tng hp cng ch chp nhn mt phn cc khi nim ca Verilog

d) Ch tp trung nghin cu mt phn S dng mt mc thch hp Tp trung trn nhng cu trc tng hp c 6

Tp trung trnh nhng cu trc gy khi tng hp

1.2. Ngn ng c t phn cng (HDL):


L ngn ng thuc lp ngn ng my tnh ( computer language). Dng miu t cu trc v hot ng ca mt vi mch. Dng m phng, kim tra hot ng ca vi mch. Biu din hnh vi theo thi gian v cu trc khng gian ca mch. Bao gm nhng k hiu biu din thi trang v s ng thi ( time and concurrence). u im: D qun l nhng mch ln v phc tp.

Uyn chuyn v c lp vi cng ngh. Cho php ti s dng nhng thit k c sn. Mch c th dc tng hp t ng t c t.

VerilogTM & VHDL. c s dng rng ri trong cng nghip. Theo chun IEEE (Institute of Electrical and Electronics Engineerings). c h tr bi cc cng c tng hp ASIC (appilcationspecific integrated circuits) v FPGA (fieldprogrammable gate arrays).

1.3. Phng php lun thit k HDL:


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Kim tra: thit k ng yu cu cha? thc Chc nng: Hnh vi I/O Mc thanh ghi (Kin trc) Mc l lun (Cng) Mc transistor (in t) Timing: Waveform Behavior

nh x c t thnh cc hin

Di y l lu thit k ASICs bng HDL: 8

1.3.1. Design spelification ( thit k nim): c t chi tit: Chc nng. Thi gian. Nng lng tiu hao. 9

Biu din: th trng thi ( state transation graph). My trng thi (algorithmic state machine). Ngn ng cp cao: system C , superLog
1.3.2.

Thit k phn hoch ( design partition):

Mch ln c phn chia thnh cc mch nh hn. Mi mch nh ny c c t bng HDL. Mi mch nh c th c tng hp trong thi gian chp nhn c. Phng php thit k t trn xung ( top down design/ hierarchical design).

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1.3.3. Design Entry: c t thit k theo mt dng chun Ngy nay dng HDL. M hnh hnh vi (behavioral modeling). c s dng nhiu trong cng nghip. Ch ra mch s thc hin chc nng g. Khng cn ch ra xy dng phn cng nh th no. Cc bc thit k dng m hnh hnh vi: To hnh vi nguyn mu cho thit k. Kim tra chc nng: S dng nhng cng c tng hp ti u v nh x thit k vo mt cng ngh.
1.3.4. M

phng v kim tra chc nng ( Simulation and function

verification). Quay v bc 3 nu pht hin li. Ba bc tin hnh kim tra. Lp k hoch kim tra: chc nng no cn kim tra v kim ra th no? Thit k mu kim tra ( testbench). Thc hin kim tra. 11

1.3.5. Thit k tch hp v kim tra ( design integration and verification) Cc mch nh c tch hp li v kim tra Chc nng: Cn c cc testbench ring kim tra chc nng ng nhp xut hot ng ca bus y l bc quyt nh v phi c thc hin hon ho m bo tnh ng n ca qu trnh tng hp.

1.3.6. Presynthesis Sign off: Bo m tt c cc chc nng c th hin trong testbench. Bo m nhng khc bit gia cc chc nng biu din bng m hnh hnh vi v thit k c gii quyt hon ton. Sign off c thc hin sau khi tt c cc li chc nng gii quyt xong.

1.3.7. Tng hp mc cng v nh x cng ngh (Gate level synthesis and technology mapping) S dng cng c tng hp to ra biu din lun l ti u v thc hin theo mt cng ngh hin c.

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Cng c ti u loi b nhng d tha v gim din tch mch logic cn dng thc hin. Kt qu s c nh x vo mt FPGA: Netlist. C s d liu.

1.3.8. Thit k sau tng hp ( Post synthesis design validation): B so snh c thc hin bng phn mm hoc bng ha. Tm hiu v gii quyt s khc bit mt cch cn thn.

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Verilog behavioral description: Phn m t hnh vi ca verilog. Logic Synthesis: logic tng hp. Gate level description: Phn m t mc cng. Stimulus generation: my kch thch. Testbench for post synthesis design validation: Mu kim tra cho thit k sau tng hp. Response Comparation: p ng li s so snh. Check signal: Kim tra tn hiu.

1.3.9.

Kim tra thi gian sau tng hp ( Post synthesis timing verification):

Thi gian trn mch phi ph hp vi thit k trn nhng ng then cht (critical path). Bc ny c lp li sau bc loi b in dung khng mong mun ( parasitic extraction) Thc hin tng hp li nu thi gian khng ph hp vi thit k. Thay i kch thc transitor. Thay i kin trc mch. Thay i cng ngh. 14

1.3.10.

Kim tra sn phm v m phng li ( test generation and

fault simulation). Sau khi ch to mch tch hp phi c kim tra tnh ng n ( li sn xut khng phi li thit k). C th dng li nhng mu kim tra m hnh hnh vi kim tra sn phm sau khi ch to. M phng li l quyt nh mt tp hp cc mu dng kim tra c cc li ny hay khng -> s dng phn mm to thm cc mu th.

1.3.11.

Sp t v ni dy ( placement ang routing).

Sp xp cc linh kin (cell) ln mt vng gii hn v kt ni cc ng tn hiu gia chng. Chn tn hiu clock vo mch sao cho khng xy ra lch xung clock ( clock skew).

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1.3.12.

Kim tra vt l v in ( Physical and electrical design rule

checks). Layout vt l ca thit k phi c kim tra cc rng buc. dy vt liu ( material width) Chng lp ( overlap) Tch bit ( separation) + Kim tra in: Fan out Cc tn hiu khng trn ln vi nhau (compromise). Nhiu. Tiu hao nng lng.
1.3.13.

Loi b k sinh ( Parasitic extraction)

in dung k sinh ( Parasitic capacitance) 16

Khng c trong thit k nh hng xu n hot ng ca mch Lm gim bng thng S dng phn mm to ra cc kim tra chnh xc v cc c tnh in v thi gian ( electrical characteristics and timing performance). 1.3.14. Design sign off: Cc rng buc c tha mn. c t bao gm hnh dng hnh hc cho qu trnh sn xut. Cc ti nguyn c m rng chip sn xut ra tha mn thit k v hiu sut v chc nng.

1.4. a)

M hnh cu trc v m hnh hnh vi trong HDLs:


Cu trc (Structural) ch tra cu trc phn cng tht s ca mch

Mc tru tng thp Cc cng c bn ( v d and, or, not) Cu trc phn cp thng qua cc module Tng t lp trnh hp ng
b)

Hnh vi (Behavioral) ch ra hot ng ca mch

trn cc bits Mc tru tng cao hn Biu din bng cc biu thc (v d out = (a & b) | c) 17

Khng phi tt c cc c t hnh u tng hp c Khng s dng: + - * / % > >= < <= >> <<

1.5. Nhng nguy him trong thit k Verilog:


Chng trnh tun t, b tng hp c th s phi thm phn nhiu chi tit cng Cn mt b priority encoder Nu song song nhng chng trnh song, c th c trng thi khng xc nh Nhiu khi always, khi no thc thi trc? To ra nhiu trng thi khng d dnh trc if (x == 1) out = 0; if (y == 1) out = 1; // else out retains previous state? R-S latch! Khng tnh trc c s phn t phn cng x = x + 1 c th cn RT NHIU phn t phn cng

1.6. M hnh cu trc cho mch lun l t hp:


1.6.1. M hnh mch t hp

Mt m hnh Verilog ca mt mch tm tt cc m t chc nng bng gc nhn cu trc hay hnh vi trn nhng mi quan h ng vo-ng ra Mt m hnh cu trc l mt cu trc kt ni (netlist) cha Cc cng

Cc khi chc nng 18

Mt m hnh hnh vi l M hnh chuyn i mc thanh ghi ( Register Transfer Level RTL)

Cc biu thc Boolean n gin

Mt gii thut

1.6.2. M hnh cu trc mch t hp

Thit k cu trc tng t nh to ra mt s (schematic)

Schematic Hnh biu din cng logic, Ng vo ra, Cc ng kt ni gia cc cng. M hnh cu trc HDL Danh sch cc cng cbn v kt ni gia chng

Cc pht biu ch ra ng vo-ra

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1.6.3. Verilog primitives Primitives l cc i tng c bn c th c s dng trong thit k 26 i tng chc nng c nh ngha trc

1.6.4. M hnh cu trc trong Verilog 20

Module

V d:

1.6.5. Module ports 21

a) Giao tip vi mi trng bn ngoi b) Kiu ca port quyt nh chiu truyn liu Mt chiu (Unidirectional) input output Hai chiu (Bidirectional) inout c) Kiu ca module port phi c khai bo tng minh v khng cn theo th t xut hin trong port list 1.6.6. Quy tt trong Verilog Phn bit ch hoa thng (Case sensitive) Identifier: a-z, A-Z, 0-9, _ v $ Tn bin khng c bt u bng $ hay k s v c th ti a l 1024 k t Mt pht biu c kt thc bng ; Ch thch // mt dng ch thch /**/ ch thch nhiu dng Cc identifiers c phm vi nht nh C th vit cc pht biu trn mt dng hay nhiu dng Thit k t trn xung (top-down) a) H thng phc tp c phn chia thnh nhng n v chc nng nh hn D thit k D kim tra 22

b) Cc module lng nhau trong Verilog h tr thit k t trn xung c) Module tham kho n module khc c gi l module cha, module c module khc tham kho n gi l module con d) su ca cc module lng nhau khng gii hn e) Mi module con phi c tn duy nht trong phm vi module cha (tr cc primitives) 1.6.7. Binary full adder

1.6.8. Thit k phn cp v t chc m ngun Top-level module l module cp cao nhht

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Module mc thp nht Cha cc primitives Cc module khng phn chia nh hn Tt c cc module c t trong mt hay nhiu tp tin khc nhau Cng c m phng tch hp cc module t cc tp tin 1.6.9. Mch cng 16-bit ripple carry

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1.6.10.

Cy phn cp mch cng 16-bit ripple carry.

1.6.11.

Hin thc mch cng 16-bit ripple carry.

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1.6.12.

Vectors trong Verilog.

Mt vector c biu din bng ngoc vung cha dy lin tip cc bit sum[3:0] vector sum kch thc 4 bit Bit tri nht l MSB Bit phi nht l LSB C th truy xut tng bit hay tng dy bit trong vector sum[1] bit th 2 t phi sang ca sum sum[2:1] bit th 2 v 3 t phi sang ca sum sum[4] gi tr x (khng xc nh) C th gn, so snh 2 vector vi nhau
1.7.

M phng lun l, kim chng thit k v phng php lun kim tra.
Cc gi tr lun l trong Verilog.

1.7.1.

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1.7.2.

Phng php lun kim tra.

a) Kim tra mch thc hin ng chc nng Kim tra ngu nhin phc tp v khng chnh xc Cn lp k hoch kim tra t m Kim tra mch ln b) Kim tra tt c cc trng hp Mch cng 16 bit cn kim tra 223 trng hp Kim tra phn cp half_adder full_adder Add_rca_4 cn kim tra 29 trng hp Chn mt s trng hp kim tra kt ni ca cc 27

Add_rca_4 trong Add_rca_16

Kim tra theo chiu ngc so vi cy phn cp thit k

1.8.

Thi gian tr truyn lan.


Thi gian tr truyn lan.

1.8.1.

Ng vo thay i ng ra khng thay i ngay lp tc Cc phn t c bn ca verilog c thi gian tr l 0 Cc vi mch thc t c sn xut da trn cc th vin chun c nh ngha trc Ngi thit k ch quan tm n tnh ng n ca mch S dng cc cng c tng hp hin thc cc thit k tha mn cc rng buc thi gian timescale <time_unit base>/<precision base> Ch th bin dch Ch ra n v thi gian v chnh xc thi gian tr Phi c khai bo trc khi cc module

V d: Timecase

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1.8.2.

Cc loi tr lan truyn.

Tr qun tnh (inertial delay)

Tr truyn (transport delay) Gy ra do cc dy ni 0.033ns/1cm 29

C th b qua wire #2 long_wire


1.9.

M hnh bng s tht cho mch lun l t hp v tun t vi verilog.

1.9.1.

Bng s tht trong verilog.

Table Ng ra phi c kiu v hng (scalar) Dng k hiu ? thay cho 0, 1, x Th t cc ct trong <input_list> tng ng vi th t trong khai bo input ca module Mch t hp <input_list>:<output> Mch tun t <input_list>:<state>:<output/next_state> Ng ra phi c khai bo kiu thanh ghi Dng k hiu - biu din ng ra khng thay i

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PHN II:

TNG QUAN V VHDL

2.1. Gii thiu v ngn ng m t phn cng VHDL.

VHDL l ngn ng m t phn cng cho cc mch tch hp tc cao, l mt loi ngn ng m t phn cng c pht trin cho chng trnh VHSIC ( Very High Speed Itergrated Circuit) ca b quc phng M. Mc tiu ca vic pht trin VHDL l c c mt ngn ng m phng phn cng tiu chun v thng nht cho php th nghim cc h thng s nhanh hn cng nh cho php d dng a cc h thng vo ng dng trong thc t.

VHDL c pht trin nh mt ngn ng c lp khng gn vi bt k mt phng php thit k, mt b m t hay cng ngh phn cng no. Ngi thit k c th t do la chn cng ngh, phng php thit k trong khi ch s dng mt ngn ng duy nht. V khi em so snh vi cc ngn ng m phng phn cng khc k ra trn ta thy VHDL c mt s u im hn hn cc ngn ng khc:

Th nht l tnh cng cng: VHDL c pht trin di s bo tr ca chnh ph M v hin nay l mt tiu chun ca IEEE. VHDL c s h tr ca nhiu nh sn xut thit b cng nh nhiu nh cung cp cng c thit k m phng h thng.

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Th hai l kh nng h tr nhiu cng ngh v phng php thit k. VHDL cho php thit k bng nhiu phng php v d phng php thit k t trn xung, hay t di ln da vo cc th vin sn c. VHDL cng h tr cho nhiu loi cng c xy dng mch nh s dng cng ngh ng b hay khng ng b, s dng ma trn lp trnh c hay s dng mng ngu nhin.

Th ba l tnh c lp vi cng ngh: VHDL hon ton c lp vi cng ngh ch to phn cng. Mt m t h thng dng VHDL thit k mc cng c th c chuyn thnh cc bn tng hp mch khc nhau tu thuc cng ngh ch to phn cng mi ra i n c th c p dng ngay cho cc h thng thit k.

Th t l kh nng m t m rng: VHDL cho php m t hot ng ca phn cng t mc h thng s cho n mc cng. VHDL c kh nng m t hot ng ca h thng trn nhiu mc nhng ch s dng mt c php cht ch thng nht cho mi mc. Nh th ta c th m phng mt bn thit k bao gm c cc h con c m t chi tit.

Th nm l kh nng trao i kt qu: V VHDL l mt tiu chun c chp nhn, nn mt m hnh VHDL c th chy trn mi b m t p ng c tiu chun VHDL. Cc kt qu m t h thng c th c trao i gia cc nh thit k s dng cng c thit k khc nhau nhng cng tun theo tiu chun VHDL. Cng nh mt nhm 32

thit k c th trao i m t mc cao ca cc h thng con trong mt h thng ln (trong cc h con c thit k c lp).

Th su l kh nng h tr thit k mc ln v kh nng s dng li cc thit k: VHDL c pht trin nh mt ngn ng lp trnh bc cao, v vy n c th c s dng thit k mt h thng ln vi s tham gia ca mt nhm nhiu ngi. Bn trong ngn ng VHDL c nhiu tnh nng h tr vic qun l, th nghim v chia s thit k. V n cng cho php dng li cc phn c sn.

2.2. Cu trc mt m hnh h thng m t bng VHDL. Thng thng mt m hnh VHDL bao gm ba phn: thc th, kin trc v cc cu hnh. i khi ta x dng cc gi( packages) v m hnh kim tra hot ng ca h thng( testbench). 2.2.1. Thc th (entity) ca m hnh. Phn khai bo thc th ch r TN ca thc th v lit k cc li vo v ra v c dng chung nh sau Entity tn_thc_th is Generic (khai bo generic); Port (khai bo cc tn hiu vo ra); End tn_thc_th; Mt thc th lun bt u vi t kha entity, theo sau l tn ca thc th v t kha is. Ri n cc khai bo cng vi t kha port. Mt thc th lun kt thc vi t kha end v tn ca thc th. 33

Tn thc th l tn ca thc th do ngi dng t. Cc tn hiu vo ra: tn ca cc tn hiu do ngi dung t, ngn cch vi nhau bi du phy, ch ra cc tn hiu ni vi bn ngoi. Cc ch ca tn hiu khai bo trong port: ch ra chiu ca tn hiu, c cc mode sau:

in: ch ra rng tn hiu l mt tn hiu vo. out: ch ra rng tn hiu l mt tn hiu ra khi thc th v ch cc thc th khc dng n tn hiu ny mi c th c gi tr ca n.

buffer: tn hiu l tn hiu ra v gi tr ca n c th c c c bn trong thc th.

inout: tn hiu c th l tn hiu vo hoc tn hiu ra.

V d 1: ENTITY Adder IS -- declares the generic identifier n having a default value 4 GENERIC (n: INTEGER := 4); PORT ( -- the vector size is 3 downto 0 since n is 4 A, B: IN STD_LOGIC_VECTOR(n-1 DOWNTO 0); Cout: OUT STD_LOGIC; SUM: OUT STD_LOGIC_VECTOR(n-1 DOWNTO 0)); 34

S: OUT STD_LOGIC); END Siren; 2.2.2. Kin trc ca m hnh. Cu trc ca n nh sau: ARCHITECTURE tn_architecture OF tn_entity IS [cc phn khai bo:signal, component] BEGIN [code] END tn_architecture; Trong kin trc m hnh chng ta c th khai bo tt c mi th lin quan ti chng trnh, trong c cc process, cc chng trnh con vi li gi hm component, v khai bo cc signal v cc cu lnh port map kt ni cc thnh phn con c trong kin trc. Ni chung cng nh ngn ng C th y kin trc(architecture) l thn ca chng trnh ca ta.

V d 2 : -- using a FOR-GENERATE statement to generate four instances of the full adder -- component for a 4-bit adder LIBRARY IEEE; 35

USE IEEE.STD_LOGIC_1164.ALL; ENTITY Adder4 IS PORT ( Cin: IN STD_LOGIC; A, B: IN STD_LOGIC_VECTOR(3 DOWNTO 0); Cout: OUT STD_LOGIC; SUM: OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); END Adder4; ARCHITECTURE Structural OF Adder4 IS COMPONENT FA PORT ( ci, xi, yi: IN STD_LOGIC; co, si: OUT STD_LOGIC); END COMPONENT; SIGNAL Carryv: STD_LOGIC_VECTOR(4 DOWNTO 0); BEGIN Carryv(0) <= Cin; Adder: FOR k IN 3 DOWNTO 0 GENERATE FullAdder: FA PORT MAP (Carryv(k), A(k), B(k), Carryv(k+1), SUM(k)); END GENERATE Adder; Cout <= Carryv(4); 36

END Structural;

PHN III: THIT K B GII M DNG VERILOG


Mch gii m l mch c chc nng ngc li vi mch m ho tc l nu c 1 m s p vo ng vo th tng ng s c 1 ng ra c tc ng, m ng vo thng t hn m ng ra. Tt nhin ng vo cho php phi c bt ln cho chc nng gii m. Mch gii m c ng dng chnh trong ghp knh d liu, hin th led 7 on, gii m a ch b nh, thit k b cng.

3.1. V d 1: Thit k mch gii m 3 sang 8. Mch gii m 3 ng sang 8 ng bao gm 3 ng vo to nn 8 t hp trng thi, ng vi mi t hp trng thi c p vo s c 1 ng ra c tc ng.

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T bng s tht ta c th v c s mch logic ca mch gii m trn

Cu trc mch gii m 3 sang 8 Rt gn hm logic s dng mch gii m :

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Nhiu hm logic c ng ra l t hp ca nhiu ng vo c th c xy dng t mch gii m kt hp vi mt s cng logic ng ra(mch gii m chnh l 1 mch t hp nhiu cng logic c MSI). Mch gii m c bit hiu qu hn so vi vic s dng cc cng logic ri trong trng hp c nhiu t hp ng ra. V d sau thc hin mch cng 3 s X, Y, Z cho tng l S v s nh l C thc hin bng mch gii m : Gi s mch cng thc hin chc nng logic nh bng sau : T bng cho php ta xc nh c cc t hp logic ng vo S ri C mc cao.

S(x, y, z) = C(x, y, z) =

(1,2,4,7) (3,5,6,7)

x 0 0 0 0 1

y 0 0 1 1 0

z 0 1 0 1 0

s 0 1 1 0 1

c 0 0 0 1 0 39

Nh vy s cn 1 cng OR ni chung cc t hp logic th 1, 2, 4, 7 a ra ng S.Tng t ng ra C cng cn 1 cng OR vi ng vo l t hp logic th 2, 5, 6, 7.

Vy mch gii m thc hin bng logic trn s c mc nh sau :

Phn code mch gii m 3 sang 8:

module decoder_38 (data , code ,enable); 40

output [7:0] data; input [2:0] code; input enable ; reg [7:0] data;

always @(enable & data) begin data=0; if (enable) begin

case(code) 0: data = 8'b00000001; 1: data = 8'b00000010; 2: data = 8'b00000100; 3: data = 8'b00001000; 4: data = 8'b00010000; 5: data = 8'b00100000; 6: data = 8'b01000000; 7: data = 8'b10000000; endcase 41

end end endmodule

Phn mch thu c:

42

data~112

enable code[0..2]

data~111

data~110

data~109

data~108

data[0..7]

data~107

data~106

data~105

43

Phn mch m phng:

3.2. V d 2 : Thit k mch gii m 4 sang 16.

Phn code mch gii m 4 sang 16:

module decoder ( binary_in , // 4 bit binary input decoder_out , // 16-bit out 44

enable );

// Enable for the decoder

input [3:0] binary_in ; input enable ; output [15:0] decoder_out ;

reg [15:0] decoder_out ;

always @ (enable or binary_in) begin decoder_out = 0; if (enable) begin case (binary_in) 4'h0 : decoder_out = 16'h0001; 4'h1 : decoder_out = 16'h0002; 4'h2 : decoder_out = 16'h0004; 4'h3 : decoder_out = 16'h0008; 4'h4 : decoder_out = 16'h0010; 4'h5 : decoder_out = 16'h0020; 45

4'h6 : decoder_out = 16'h0040; 4'h7 : decoder_out = 16'h0080; 4'h8 : decoder_out = 16'h0100; 4'h9 : decoder_out = 16'h0200; 4'hA : decoder_out = 16'h0400; 4'hB : decoder_out = 16'h0800; 4'hC : decoder_out = 16'h1000; 4'hD : decoder_out = 16'h2000; 4'hE : decoder_out = 16'h4000; 4'hF : decoder_out = 16'h8000; endcase end end

endmodule

Phn mch thu c: 46

D co e 0 4 e dr~7 d co e_ u 1 1 e d r o t~ 9

b a _ [0 ] in ry in ..3

d co e_ u 1 0 e d r o t~ 9 D co e 0 4 e dr~6

d co e_ u 1 9 e d r o t~ 8

D co e 0 4 e dr~5

d co e_ u 1 8 e d r o t~ 8

D co e 0 4 e dr~4 d co e_ u 1 7 e d r o t~ 8

d co e_ u 1 6 e d r o t~ 8 D co e 0 4 e dr~3

d co e_ u 1 5 e d r o t~ 8

D co e 0 4 e dr~2

d co e_ u 1 4 e d r o t~ 8

D co e 0 4 e dr~1 d co e_ u 1 3 e d r o t~ 8

d c d r_ u ..1 ] e o e o t[0 5

d co e_ u 1 2 e d r o t~ 8 D co e 0 4 e dr~0

d co e_ u 1 1 e d r o t~ 8

D co e 0 3 e dr~9

d co e_ u 1 0 e d r o t~ 8

D co e 0 3 e dr~8

d co e_ u 1 9 e d r o t~ 7

D co e 0 3 e dr~7

d co e_ u 1 8 e d r o t~ 7

d co e_ u 1 7 e d r o t~ 7

D co e 0 3 e dr~6

d co e_ u 1 6 e d r o t~ 7

D co e 0 3 e dr~5

D co e 0 3 e dr~4

D co e 0 3 e dr~3

D co e 0 3 e dr~2

e a le nb

Phn mch m phng:

47

48

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49

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