Bai Giang VHDL

MC LC
CHNG 1 :
GII THIU TP LNH TRONG NGN NG VHDL ................... 1
1.1
Nhng phn t ngn ng c bn :.................................................................... 1
1.1.1
Li ch thch : ............................................................................................. 1
1.1.2
Nhng iu cn bit v ngn ng VHDL :................................................... 1
1.1.3
i tng d liu : ...................................................................................... 1
1.1.4
Loi d liu : ............................................................................................... 2
1.2
Ton t d liu :................................................................................................ 4
1.3
Entity (thc th): ............................................................................................... 6
1.4
Architecture (cu trc) : ................................................................................... 6
1.4.1
C php cho dataflow model : .................................................................... 6
1.4.2
C php cho behavioral model : .................................................................. 7
1.4.3
C php ca structural model : .................................................................... 7
1.5
Generic : ............................................................................................................ 8
1.5.1
C php trong khai bo ENTITY :............................................................... 8
1.5.2
C php trong khai bo component : ........................................................... 9
1.5.3
C php trong thuyt minh component : ...................................................... 9
1.6
Package (gi) : ................................................................................................. 10
1.6.1
C php khai bo PACKAGE: .................................................................. 10
1.6.2
C php khai bo thn chnh Package: ....................................................... 11
1.7
Nhng cu lnh ng thi theo cu trc Dataflow : ...................................... 12
1.7.1
Gn cc tn hiu ng thi : ....................................................................... 12
1.7.2
Gn tn hiu c iu kin : ......................................................................... 12
1.7.3
Gn tn hiu c chn la : ...................................................................... 13
1.7.4
V d cho kiu dataflow : .......................................................................... 13
1.8
Nhng cu lnh tun t theo cu trc Behavioral : ....................................... 14
1.8.1
Process : .................................................................................................... 14
1.8.2
Nhng php gn tn hiu tun t : .............................................................. 14
1.8.3
Php gn bin : .......................................................................................... 15
1.8.4
Wait : ........................................................................................................ 15
1.8.5
If then else :............................................................................................... 15
1.8.6
Case: ......................................................................................................... 16
1.8.7
Null : ......................................................................................................... 16
1.8.8
For : .......................................................................................................... 16
1.8.9
While : ...................................................................................................... 17
1.8.10 Loop : ....................................................................................................... 17
1.8.11 Exit : ......................................................................................................... 17
1.8.12 Next : ........................................................................................................ 17
1.8.13 Function (hm) : ........................................................................................ 17
1.8.14 Procedure (th tc) : .................................................................................. 19
1.8.15 V d v kiu Behavioral : ......................................................................... 20
1.9
Cc cu lnh kiu Structural : ........................................................................ 21
1.9.1
Khai bo Component : ............................................................................... 21
1.9.2
Port map :.................................................................................................. 21
1.9.3
Open : ....................................................................................................... 22
1.9.4
Generate : .................................................................................................. 22
1.9.5
V d v cch vit on m theo kiu Structure: ........................................ 23
1.10 Cc th tc chuyn i : ................................................................................. 25
1.10.1 Conv_integer ( ) : ...................................................................................... 25
1.10.2 Conv_Std_Logic_Vector (,): ..................................................................... 25
CHNG 2 :
DNG NGN NG VHDL M T CC MCH S C BN ...... 27
2.1
Ngn ng VHDL m t cc cng logic c bn: .............................................. 27
2.1.1
on m VHDL m t cng NAND 2 ng vo: ......................................... 27
2.1.2
Ngn ng VHDL m t cng NOR 3 ng vo: .......................................... 28
2.1.3
Dng ngn ng VHDL m t mt h thng bo ng cho xe hi: .............. 29
2.2
B gii m LED 7 on:.................................................................................. 31
2.2.1
Xy dng cu trc b gii m LED 7 on: ............................................... 31
2.2.2
Ngn ng VHDL m t mch gii m LED 7 on: .................................. 34
2.2.3
Cu trc structural biu din gii m s thp phn ra Led 7 on: .............. 35
2.2.4
Cu trc dataflow biu din gii m s thp phn ra Led 7 on: ............... 37
2.2.5
Cu trc behavioral biu din gii m s thp phn ra Led 7 on: ............ 38
2.3
B cng: ........................................................................................................... 38
2.3.1
B cng ton phn (FA): ........................................................................... 38
2.3.2
B cng ton phn hai s nh phn c nhiu hn 1 bit: .............................. 40
2.3.3
B cng hai s nh phn nhiu bit cho kt qu hin th nhanh: ................... 41
2.4
B tr: ............................................................................................................. 42
2.4.1
B tr mt bit: ........................................................................................... 42
2.4.2
S tch hp c hai b cng v b tr trong cng mt mch s: ................... 43
2.5
Thnh phn thc hin cc php ton logic s hc (ALU): ............................ 45
2.6
B gii m:....................................................................................................... 49
2.7
B m ha:....................................................................................................... 52
2.8
2.8 B ghp knh: .......................................................................................... 53
2.9
B m ba trng thi: ..................................................................................... 57
2.10
B so snh:....................................................................................................... 58
2.11
B dch v b xoay (shifter / Rotator): ........................................................... 60
2.12
B nhn: .......................................................................................................... 62
2.13 My trng thi hu hn FSM: ....................................................................... 64

2.13.1 M hnh my trng thi hu hn FSM (Finite-State-Machine): .................. 65
2.13.2 Phng trnh kch thch (Excitation Equation): .......................................... 67
2.13.3 Phng trnh trng thi tip theo (Next-state Equation): ............................ 67
2.13.4 Bng trng thi tip theo (Next-state Table): ............................................. 68
ii
2.13.5
2.13.6
V d phn tch 1 Moore FSM: .................................................................. 70

V d phn tch Mealy FSM: ..................................................................... 76
2.14 Cc linh kin tun t: ..................................................................................... 80

2.14.1 Cc thanh ghi (Registers): ......................................................................... 80
2.14.2 Thanh ghi tp tin (Register Files): ............................................................. 82
2.14.3 B nh truy xut ngu nhin (Random Access Memory): .......................... 85
2.15 B m (Counters): ......................................................................................... 88
2.15.1 B m ln nh phn (Binary Up Counter):................................................ 89
2.15.2 M VHDL cho b m ln 4 bit: ............................................................... 90
2.15.3 B m ln xung nh phn (Binary Up-Down Counter): .......................... 91
2.15.4 M VHDL cho 1 b m ln xung 4 bit nh sau: ..................................... 92
2.15.5 B m ln xung c song song : ............................................................ 93
2.15.6 B m ln xung BCD (BCD Up-Down Counter): .................................. 95
2.16 Thanh ghi dch (Shift registers):..................................................................... 95
2.16.1 Thanh ghi dch ni tip ra song song: ........................................................ 96
2.16.2 Thanh ghi dch ni tip ra song song v song song ra ni tip: ................... 97
CHNG 3 :
TM HIU KIT FPGA SPARTAN 3 ................................................ 100
3.1
Tng quan kit FPGA Spartan 3 : ................................................................ 100
3.2
SRAM bt ng b : ..................................................................................... 101
3.3
Led 7 on:.................................................................................................... 105
3.4
Cc cng tc trt (SW), cc nt n (PB) v cc Led : ............................... 107
3.5
Cng VGA : ................................................................................................... 107
3.6
Cng PS/2 Mouse v Keyboard : .................................................................. 108
3.6.1
Bn phm :............................................................................................... 109
3.6.2
Mouse : ................................................................................................... 109
3.6.3
Ngun cp p: ......................................................................................... 110
3.7
Cng ni tip RS-232 : .................................................................................. 110
3.8
Cc ngun xung clock : ................................................................................. 111
3.9
Cch thit lp cc mode hot ng cho FPGA : .......................................... 111
3.10 Thit lp cch lu tr cho Platform : ........................................................... 112

3.10.1 Default Option : ...................................................................................... 113
3.10.2 Flash Read option : .................................................................................. 113
3.10.3 Disable Option : ...................................................................................... 114
3.11 S kt ni cc board m rng vo kit Spartan 3 : ....................................... 114
3.11.1 Port m rng A1: .................................................................................... 115
3.11.2 Port m rng A2 :.................................................................................... 116
3.11.3 Port m rng B1 : .................................................................................... 117
CHNG 4 :
CC CNG GIAO TIP DNG TRN BOARD SPARTAN 3 ..... 119
iii
4.1
Giao tip RS232 (cng COM) : ..................................................................... 119
4.2
Giao tip bn phm PS/2 : ............................................................................. 122
4.2.1
S chn kt ni: .................................................................................. 122
4.2.2
Cc tn hiu ca PS/2 : ............................................................................ 122
4.2.3
Nguyn tc truyn d liu : ..................................................................... 122
4.2.4
M qut bn phm (Scancode) : ............................................................... 124
4.3
Giao tip VGA : ............................................................................................ 125
4.3.1
S chn kt ni : ................................................................................. 125
4.3.2
Cc tn hiu ca VGA : ........................................................................... 125
4.3.3
Nguyn tc to hnh :............................................................................... 125
4.3.4
Nguyn tc qut tn hiu in to nh : ............................................... 125
4.3.5
Mt vi chun Video in hnh cho TV v PC : ....................................... 126
4.3.6
Gin thi gian cho cc tn hiu ca chun VGA : ................................ 127
CHNG 5 :
CC NG DNG THC HIN ................................................ 128
5.1
ng h v m sn phm :.......................................................................... 129
5.2
Giao tip PS/2 :.............................................................................................. 129
iv
MC LC HNH
Hnh 2. 1 : on m VHDL cho cng NAND 2 ng vo................................................... 28
Hnh 2. 2 : Cng NOR 3 ng vo (a) on m VHDL; (b) s mch; (c) thi gian m
phng. .............................................................................................................................. 29
Hnh 2. 3 : Gin xung ca h thng bo ng trong xe hi: (a) Dng xung trn l
thuyt; (b) Dng xung trn thc t. ................................................................................... 30
Hnh 2. 4 : Mch bo ng trong xe hi (a) on m VHDL c vit di dng dataflow;
(b) m phng gin xung. .............................................................................................. 31
Hnh 2. 5 : Bng chn tr ca b gii m 7 on. ............................................................. 32
Hnh 2. 6 : Mch gii m LED 7 on. ............................................................................. 34
Hnh 2. 7 : S biu din thi gian hin th mt s trn Led 7 on ca mt s thp phn
tng ng. ........................................................................................................................ 38
Hnh 2. 8 : B cng ton phn (a) bng chn tr; (b) s mch; (c) k hiu logic. ......... 39
Hnh 2. 9 : B cng hai s nh phn 8 bit. ......................................................................... 40
Hnh 2. 10 : (a) Mch vn hnh tn hiu Carry-Lookahead t c1 n c 4 ; (b) mt mu bit
ca b cng Carry-Lookahead. ........................................................................................ 42
Hnh 2. 11 : B tr 1 bit (a) bng chn tr; (b) s mch; (c) k hiu logic. ................... 43
Hnh 2. 12 : Mch cng v tr chui 8 bit nh phn (a) bng vhn tr; (b) s mch; (c)
k hiu logic. .................................................................................................................... 44
Hnh 2. 13 : Mch ALU 4 bit. ........................................................................................... 46
Hnh 2. 14 : Hot ng ca khi ALU (a) Bng cc trng thi; (b) Bng chn tr ca LE;
(c) Bng chn tr ca AE; (d) Bng chn tr ca CE. ........................................................ 47
Hnh 2. 15 : Ba karnaugh, biu thc, s mch cho: (a) LE; (b) AE; (c) CE. ................ 48
Hnh 2. 16: on m VHDL cho mt khi ALU. ............................................................... 49
Hnh 2. 17 : Dng sng m phng cho 8 thut ton c bn ca khi ALU vi hai gi tr ng
vo l 5 v 3. .................................................................................................................... 49
Hnh 2. 18 : Mt b gii m 3 sang 8 (a) Bng chn tr; (b) s mch; (c) k hiu logic.
......................................................................................................................................... 50
Hnh 2. 19 : Mt b gii m 3 sang 8 c xy dng t 7 b gii m 1 sang 2. ................ 51
Hnh 2. 20 : Mt b m ha 8 sang 3 (a) Bng chn tr; (b) s mch; (c) k hiu logic.
......................................................................................................................................... 52
Hnh 2. 21 : Bng chn tr cho mt b m ha 8 sang 3 c s u tin. .............................. 53
Hnh 2. 22 : B ghp knh t 2 sang 1 (a) Bng chn tr; (b) s mch; (c) k hiu logic.
......................................................................................................................................... 54
Hnh 2. 23 : B ghp knh 8 sang 1 (a) Bng chn tr; (b) s mch; (c) k hiu logic. 54
Hnh 2. 24 : B ghp knh 8 sang 1 c s dng (a) B gii m 3 sang 8; (b) 7 b ghp knh
2 sang 1. ........................................................................................................................... 55
Hnh 2. 25 : Dng b ghp knh 8 thnh 1 biu din hm
F ( x, y, z ) x' yz' xy' z xyz' xyz. ................................................................................... 57
Hnh 2. 26 : B m ba trng thi (a) bng chn tr; (b) k hiu logic; (c) bng chn tr cho
vic phn chia iu khin cho mch m ba trng thi; (d) s mch. ........................... 58
Hnh 2. 27 : B so snh 4 bit n gin cho (a) X=3; (b) X Y ; (c) X<5. ........................ 59
Hnh 2. 28 : B so snh lp (a) So snh tng cp bit x i v y i ; (b) 4-bit X=Y. .................. 60
Hnh 2. 29 : S hot ng ca b dch v b xoay. ........................................................... 60
Hnh 2. 30 : B dch / b xoay 4 bit: (a) Bng trng thi hot ng;(b) s mch; (c) k
hiu logic. ........................................................................................................................ 61
Hnh 2. 31 : Php nhn (a) nhn bng tay; (b) phng php thc hin; (c) s mch.... 63
Hnh 2. 32 : S mch ca Moore FSM v Mealy FSM. ................................................ 65
Hnh 2. 33 : (a) S khi Moore FSM; (b) S khi Mealy FSM................................. 67
Hnh 2. 34 : Bng trng thi tip theo vi 4 trng thi v tn hiu ng vo C. ................... 68
Hnh 2. 35 : Bng ng ra (a) Moore FSM; (b)Mealy FSM. ............................................... 69
Hnh 2. 36 : S cc trng thi trong mt mch tun t................................................. 70
Hnh 2. 37 : Moore FSM n gin .................................................................................... 71
Hnh 2. 38 : S trng thi y ca mch Moore FSM. ........................................... 73
Hnh 2. 39 : Gin thi gian ca Moore FSM m phng bng xilinx. ............................ 76
Hnh 2. 40 : Mealy FSM n gin. ................................................................................... 76
Hnh 2. 41 : Bng chn tr ng ra. ................................................................................... 77
Hnh 2. 42 : Trng thi y ca Mealy FSM. ............................................................... 77
Hnh 2. 43 : Tnh ton thi gian mu cho Mealy FSM ...................................................... 78
Hnh 2. 44 : Gin thi gian ca Mealy FSM c m phng bng xilinx. .................... 80
Hnh 2. 45 : Thanh ghi 4 bit vi mc xa khng ng b. ................................................. 81
Hnh 2. 46 : K hiu logic ca thanh ghi........................................................................... 81
Hnh 2. 47 : Gin m phng cho thanh ghi 4 bit. ......................................................... 82
Hnh 2. 48 : Mch thanh ghi c thm chn iu khin. ..................................................... 83
Hnh 2. 49 : Mch hon chnh ca thanh ghi 4x4.............................................................. 83
Hnh 2. 50 : Tn hiu m phng cho ghi 4x4 vi 1 Port ghi, 2 Port c. ............................ 85
Hnh 2. 51 : K hiu logic ca chip RAM. ......................................................................... 86
Hnh 2. 52 : Mch nh bit trong RAM. ............................................................................. 86
Hnh 2. 53 : S cc nh dng li trong chip RAM 4x4. .......................................... 87
Hnh 2. 54 : B m ln nh phn (a) Bng chn tr; (b) S mch; (c) K hiu logic. ... 89
Hnh 2. 55 : B m ln 4 bit S mch; bng chn tr; k hiu logic. .......................... 90
Hnh 2. 56 : Tn hiu m phng cho b m ln 4 bit. ....................................................... 91
Hnh 2. 57 : B cng ,tr bn phn (a) Bng chn tr; (b) S mch; (c) K hiu logic. 92
Hnh 2. 58 : B m ln xung 4 bit: (a) S mch; (b) Bng chn tr; (c) K hiu logic.
......................................................................................................................................... 92
Hnh 2. 59 : Tn hiu m phng cho b m ln xung 4 bit. ............................................. 93
Hnh 2. 60 : (a) S mch m ln xung 4 bit c sa i ; (b) Bng chn tr ; (c) k hiu
logic ca m ln xung 4 bit c sa i. ......................................................................... 94
Hnh 2. 61 : B m BCD (a) b m ln; (b) b m xung. ........................................... 95
Hnh 2. 62 : B chuyn i 4 bit ni tip ra song song. ..................................................... 96
Hnh 2. 63 : Tn hiu m phng ca mt b chuyn i 4 bit ni tip ra song song. .......... 97
Hnh 2. 64 : (a) S mch thanh ghi dch ni tip ra song song v song song ra ni tip;
(b) Bng chn tr ; (c) k hiu logic ca thanh ghi dch ni tip ra song song v song song
ra ni tip. ........................................................................................................................ 98
Hnh 2. 65 : Tn hiu m phng thanh ghi dch ni tip ra song song v song song ra ni
tip. .................................................................................................................................. 98
Hnh 3. 1 : S khi kit Xilinx FPGA Spartan-3 Starter. ............................................. 100
Hnh 3. 2: Mch in pha trc kit FPGA Xilinx Spartan-3 Starter. ................................. 101
Hnh 3. 3 : Mch in pha sau kit FPGA Xilinx Spartan-3 Starter..................................... 101
vi
Hnh 3. 4 : S kt ni gia chn gia FPGA v 2 SRAM 256Kx16. ............................ 102

Hnh 3. 5 : Bng kt ni chn gia FPGA vi 18 ng a ch ca SRAM .................... 103
Hnh 3. 6 : Bng kt ni chn gia FPGA vi chn OE v WE ca................................. 103
Hnh 3. 7 : Bng kt ni chn gia IC10 vi cc chn ca FPGA. .................................. 104
Hnh 3. 8 : Bng kt ni chn gia IC11 vi cc chn ca FPGA. .................................. 105
Hnh 3. 9 : S b tr cc thanh ca LED 7 on. ........................................................ 105
Hnh 3. 10 : Bng kt ni chn gia LED 7 on vi chn ca FPGA. ........................... 106
Hnh 3. 11 : Bng kt ni tn hiu iu khin hin th 4 LED vi chn ca FPGA. .......... 106
Hnh 3. 12 : Bng hin th LED 7 on tng ng vi 16 k t t 0 n F. ..................... 106
Hnh 3. 13 : Tn hiu m t hin th cc LED 7 on bng phng php qut led. .......... 107
Hnh 3. 14 : Bng kt ni chn gia cc cng tc trt vi cc chn ca FPGA. ........... 107
Hnh 3. 15 : Bng kt ni chn gia cc nt nhn vi cc chn ca FPGA. .................... 107
Hnh 3. 16 : Bng kt ni chn gia 8 n LED vi cc chn ca FPGA. ...................... 107
Hnh 3. 17 : S chn ca cng VGA........................................................................... 108
Hnh 3. 18 : Bng kt ni chn gia cc tn hiu ca cng vi cc chn ca FPGA. ....... 108
Hnh 3. 19 : Bng m ha hin th 3 bit cho 8 mu c bn. ............................................. 108
Hnh 3. 20 : S chn ca cng PS/2. .......................................................................... 108
Hnh 3. 21 : M qut bn phm. ...................................................................................... 109
Hnh 3. 22 : Cc m iu khin c bit ca bn phm. .................................................. 109
Hnh 3. 23 : Cu trc lung bit qun l cng PS/2. ......................................................... 110
Hnh 3. 24 : Cch kt ni jumper trn board chn ngun p ty ngi thit k. ......... 110
Hnh 3. 25 : S chn ca cng RS-232. ...................................................................... 110
Hnh 3. 26 : S kt ni chn gia cng RS-232 vi cc chn ca FPGA. ................... 111
Hnh 3. 27 : Kt ni chn gia ngun dao ng xung clock vi chn ca FPGA. ........... 111
Hnh 3. 28 : Bng thit lp cc trng thi hot ng cho FPGA thng qua chn J8. ....... 112
Hnh 3. 29 : V tr nt n reset chng trnh np cho kit v LED hin th. .................. 112
Hnh 3. 30 : S kt ni jumper la chn cc mode lu tr ca FPGA. ................... 113
Hnh 3. 31 : S kt ni chn gia FPGA vi Platform Flash ch Default. .......... 113
Hnh 3. 32 : S kt ni chn gia FPGA vi Platform Flash ch Flash Read. .... 114
Hnh 3. 33 : V tr kt ni thm cc board mch m rng trn board Spartan 3. ............. 114
Hnh 3. 34 : Mt s c tnh ca cc port m rng A1, A2, B1. ...................................... 115
Hnh 3. 35 : Cu trc chung ca mt port m rng. ........................................................ 115
Hnh 3. 36 : Bng chn kt ni gia port m rng A1 vi con FPGA spartan 3. ........ 116
Hnh 3. 37 : Bng chn kt ni gia port m rng A2 vi con FPGA spartan 3. ........ 117
Hnh 3. 38 : Bng chn kt ni gia port m rng B1 vi con FPGA spartan 3. ........ 118
Hnh 4. 1 : Mt p dng ca RS-232............................................................................... 119
Hnh 4. 2 : Cc chn chc nng ca DB25 v DB9 loi u c. ................................... 120
Hnh 4. 3 : Cc chn chc nng ca DB25 v DB9 loi u ci. .................................... 121
Hnh 4. 4 : Nghi thc truyn v nhn d liu gia DTE v DCE. .................................... 122
Hnh 4. 5 : Chn kt ni ca chun PS/2 loi 5 chn v 6 chn. ..................................... 122
Hnh 4. 6 : Th t truyn data t Keyboard n Host. .................................................... 124
Hnh 4. 7 : Th t truyn data t Host n Keyboard. .................................................... 124
Hnh 4. 8 : M Scancode ca Keyboard. ......................................................................... 124
Hnh 4. 9 : Chn kt ni ca chun VGA. ....................................................................... 125
Hnh 4. 10 : Tn hiu qut xen k . .................................................................................. 126
vii
Hnh 4. 11 : Tn hiu qut lin tc .................................................................................. 126

Hnh 4. 12 : Thi gian thc hin ca tn hiu Vertical Sync v Horizontal Sync. ............. 127
Hnh 4. 13 : Gin thi gian ca tn hiu Vertical Sync v Horizontal Sync................. 127
viii
Chng 1 : Gii thiu tp lnh trong ngn ng VHDL
CHNG 1 : GII THIU TP LNH TRONG NGN NG

VHDL
VDHL l ngn ng m t phn cng cho cc kiu mch s trong phm v cc kt ni n
gin ca cc cng n nhng h thng phc tp. VHDL l vit tt ca VHSIC Hardware
Description Language v VHSIC l vit tt ca Very High Speed Integrated Circuits. Trong
chng ny ch tm tt ngn gn nguyn l c bn ca VHDL v c php ca n. Nhiu
chc nng cao cp ca ngn ng VHDL b b qua. Cho nn chng ta cn phi tham kho
cc ti liu khc c nhng ci nhn chi tit hn.
1.1
Nhng phn t ngn ng c bn :
1.1.1 Li ch thch :
Li ch thch c ch ra sau hai du gch ni lin tip (--) v c kt thc cui dng.
V d : -- y l li ch dn.
1.1.2 Nhng iu cn bit v ngn ng VHDL :
C php nhn bit VHDL :
Mt dy ca mt hoc nhiu k t vit hoa, k t thng, ch s, ng gch di .
K t thng v k t hoa c x l nh nhau.
K t u tin thng l mt ch ci.
K t cui cng khng th l ng gch di.
Khng th c 2 ng gch di cng mt lc.
1.1.3 i tng d liu :
C 3 loi i tng d liu : bin, hng, tn hiu.
i tng d liu tn hiu i din cho tn hiu logic trn ng dy trong mch , mt tn
hiu khng c b nh do nu ngun tn hiu b mt th tn hiu khng c gi tr.
i tng d liu bin nh ni dung ca n v dng tnh ton trong m hnh hnh vi.
i tng d liu hng cn c1 gi tr ban u khi khai bo v gi tr ny khng i.
V d :
Signal x: bit;
Variable y: integer;
Constant one: STD_Logic_Vector {3 Downto 0} := 0001 ;
Thit k cc ng dng trn Kit FPGA Spartan III
1.1.4 Loi d liu :

1.1.4.1
Bit v Bit_vector :
Loi Bit v Bit_vector c xc nh trc trong VHDL. i tng ca nhng loi ny l

gi tr 0 v 1 . Loi Bit_vctor l mt vector n gin ca loi Bit. Mt vector vi tt c
cc bit c cng gi tr c th c biu din bng t kha others.
V d :
Signal x: bit;
Signal y: Bit_vector ( 7 downto 0);
x <= 1;
y <= 00000010;
y <= (others => 0); -- same as 00000000
1.1.4.2
STD_Logic v STD_Logic_Vector :
Loi STD_Logic v STD_Logic_Vector cung cp nhiu gi tr hn loi Bit trong kiu

mch thc chnh xc hn. i tng ca lai ny c th c nhng gi tr sau:
0 -- mc 0
1 -- mc 1
Z -- tng tr cao
- -- khng quan tm
L -- mc 0 yu
H -- mc 1 yu
U -- khng t gi tr ban u
X -- khng xc nh
W-- khng xc nh yu
Loi STD_Logic v STD_Logic_Vector khng c xc nh trc v th phi khai bo 2

th vin s dng loi ny:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
Nu i tng loi STD_Logic_Vector c dng nh s nh phn trong cc thao tc s
hc, khi ta s dng lnh use vi hai c php sau:
USE IEEE.STD_LOGIC_SIGNED.ALL; cho s c du.
USE IEEE.STD_LOGIC_UNSIGNED.ALL; cho s khng du.

Mt vector m tt c cc bit c gi tr ging nhau c th c biu din ngn gn bng cch
s dng t kha others vi c php sau:
V d:
LIBRARY IEEE;
SIGNAL x: STD_LOGIC;
SIGNAL y: STD_LOGIC_VECTOR(7 DOWNTO 0);
x <= 'Z';
y <= "0000001Z";
y <= (OTHERS => '0'); -- same as "00000000"
1.1.4.3
Integer :
Loi Integer c xc nh trc nh ngha cc i tng s nh phn dng vi tnh

ton s hc. Mc nh 1 tn hiu khai bo Integer dng ti a 32 bit ch mt k hiu s.
Integers cng c th dng t bit hn vi khai bo t kha RANGE.
V d :
SIGNAL x: INTEGER;
SIGNAL y: INTEGER RANGE 64 to 64;
1.1.4.4
Boolean :
Loi Boolean c xc nh trc nh nghi cc i tng ch c 2 gi tr TRUE hoc

FALSE
V d: SIGNAL x: BOOLEAN;
1.1.4.5
Bng lit k Type :
Mt bng lit k cho php ngi dng ch r nhng gi tr m i tng d liu c th c.

C php: TYPE identifier IS ( tr 1, tr 2, ).
V d: TYPE state_type IS ( S1,S2,S3);
Signal state: state_type;
State <= S1;
1.1.4.6
Array :
Loi ARRAY nhm cc i tng d liu ring l ca cng mt loi thnh mt mng mt
chiu hay nhiu chiu.
C php :
TYPE identifier IS ARRAY (range) OF type;
V d : TYPE byte IS ARRAY(7 DOWNTO 0) OF BIT;

TYPE memory_type IS ARRAY(1 TO 128) OF byte;
SIGNAL memory: memory_type;
memory(3) <= "00101101";
1.1.4.7
Subtype :
SUBTYPE l tp hp con ca mt loi m loi c s rng buc v phm vi.

C php :
SUBTYPE identifier IS type RANGE range;
V d : SUBTYPE integer4 IS INTEGER RANGE 8 TO 7;

SUBTYPE cell IS STD_LOGIC_VECTOR(3 DOWNTO 0);
TYPE memArray IS ARRAY(0 TO 15) OF cell;
Mt vi chun Subtype
NATURAL dy s nguyn bt u t s 0.
POSITIVE dy s nguyn bt u t s 1.
1.2
Ton t d liu :
VHDL c xy dng t cc ton t c gii thiu bng di y:

Ton t Logic
Ton t
V d
AND
And
a AND b
OR
Or
a OR b
NOT
Not
NOT a
NAND
Nand
a NAND b
NOR
Nor
a NOR b
XOR
Xor
a XOR b
XNOR
Xnor
a XNOR b
Ton t s hc (Arithmetic Operators)
Php cng (addition)
a+b
Php tr (subtraction)
a-b
Php nhn (multiplication (integer or floating point))
a*b
Php chia ( division (integer or floating point))
a/b
MOD
Ly phn d, du theo b ( modulus (integer))
a MOD b
REM
Ly phn d, du theo a (remainder (integer))
a REM b
**
Ly tha (exponentiation)
A ** 2
&
Php ni (concatenation)
a & b
ABS
Tr tuyt i (absolute)
a ABS b
Ton t quan h (Relational Operators)

=
Bng
/=
Khng bng
<
Nh hn
<=
Nh hn hoc bng
>
Ln hn
>=
Ln hn hoc bng
Ton t dch (Shift Operators)

sll
Dch tri logic (shift left logical)
srl
Dch phi logic (shift right logical)
sla
Dch tri s hc (shift left arithmetic)
sra
Dch phi s hc (shift right arithmetic)
rol
Xoay tri (rotate left)
ror
Xoay phi (rotate right)
1.3
Entity (thc th):
Mt khai bo ENTITY biu th mt giao din ngi dng hoc bn ngoi ca moun ging
vi khai bo ca mt chc nng. N ch r tn ca thc th v giao din ca n. Giao din
gm c nhng tn hiu vo v ra thc th s dng t kha i din l IN v OUT .
C php :
ENTITY entity-name IS
PORT (list-of-port-names-and-types);
END entity-name;
V d : LIBRARY IEEE;
ENTITY Siren IS PORT(
M: IN STD_LOGIC;
D: IN STD_LOGIC;
V: IN STD_LOGIC;
S: OUT STD_LOGIC);
END Siren;
1.4
Architecture (cu trc) :
Thn ARCHITECTURE nh ngha s thc thi hin thi ca cc chc nng ca mt

ENTITY. iu ny ging vi s xc nh hoc s thc thi ca mt chc nng. C php cho
ARCHITECTURE khc nhau ty thuc vo m hnh (dataflow, behavioral, or structural)
m bn s dng.
1.4.1 C php cho dataflow model :
ARCHITECTURE architecture-name OF entity-name IS
signal-declarations; -- khai bo tn hiu
BEGIN
concurrent-statements;
END architecture-name;
Nhng pht biu concurrent c thc hin mt cch ng thi.
V d
ARCHITECTURE Siren_Dataflow OF Siren IS

SIGNAL term_1: STD_LOGIC;
BEGIN
term_1 <= D OR V;
S <= term_1 AND M;
END Siren_Dataflow;
1.4.2 C php cho behavioral model :

signal-declarations;
function-definitions;
procedure-definitions;
BEGIN
PROCESS-blocks;
Nhng cu lnh bn trong process-block c thc hin tun t, lin tc. Tuy nhin chnh
process-block l concurrent-statements.
V d : ARCHITECTURE Siren_Behavioral OF Siren IS
SIGNAL term_1: STD_LOGIC;
BEGIN
PROCESS (D, V, M)
BEGIN
term_1 <= D OR V;
S <= term_1 AND M;
END PROCESS;
END Siren_Behavioral;
1.4.3
C php ca structural model :

component-declarations;
BEGIN
instance-name: PORT MAP-statements;
Cho mi thnh phn khai bo s dng cn c mt kin trc hay mt thc th ph hp cho
cc thnh phn . Cu lnh PORT MAP l cu lnh ng thi.
V d : ARCHITECTURE Siren_Structural OF Siren IS
COMPONENT myOR PORT (
in1, in2: IN STD_LOGIC;
out1: OUT STD_LOGIC);
END COMPONENT;
SIGNAL term1: STD_LOGIC;
BEGIN
U0: myOR PORT MAP (D, V, term1);
S <= term1 AND M;
END Siren_Structural;
1.5
Generic :
GENERIC cho php thng tin i qua ENTITY, v d kch thc ca Vector trong danh
sch PORT s khng c bit cho n khi thi gian chnh xc. GENERIC ca mt
ENTITY c th hin khi dng t kha GENERIC trc danh sch PORT khai bo trong
ENTITY. Mt b nhn dng c khai bo nh GENERIC l mt hng v ch c th c
c. B nhn dng sau c th c dng trong khai bo ENTITY v nhng kin trc
ph hp ca n mi ni hng s c i hi.
1.5.1 C php trong khai bo ENTITY :
GENERIC (identifier: type); -- with no default value
or
GENERIC (identifier: type := constant); -- with a default value given by the constant
V d ENTITY Adder IS
-- declares the generic identifier n having a default value 4
GENERIC (n: INTEGER := 4);
PORT (
-- the vector size is 3 downto 0 since n is 4
A, B: IN STD_LOGIC_VECTOR(n-1 DOWNTO 0);
Cout: OUT STD_LOGIC;
SUM: OUT STD_LOGIC_VECTOR(n-1 DOWNTO 0));
S: OUT STD_LOGIC);
END Siren;
Gi tr cho mt GENERIC hng cng c th c cp trong mt cu lnh khai bo
Component hoc mt cu lnh thuyt minh Component.
1.5.2 C php trong khai bo component :
COMPONENT component-name
GENERIC (identifier: type := constant);
-- with an optional value given by the constant
END COMPONENT;
1.5.3 C php trong thuyt minh component :
label: component-name GENERIC MAP (constant) PORT MAP (association-list);
V d: ARCHITECTURE ...
COMPONENT mux2 IS
-- declares the generic identifier n having a default value 4
GENERIC (n: INTEGER := 4);
PORT (S: IN STD_LOGIC; -- select line

D1, D0: IN STD_LOGIC_VECTOR(n-1 DOWNTO 0);-- data bus input
Y: OUT STD_LOGIC_VECTOR(n-1 DOWNTO 0)); -- data bus output
END COMPONENT;
...
BEGIN
U0: mux2 GENERIC MAP (8) PORT MAP (mux_select, A, B, mux_out);
...
1.6
Package (gi) :
Mt package cung cp c ch nhm li vi nhau v chia s khai bo m c dng cho

mt vi ENTITY. Chnh mt gi bao hm c mt s khai bo, ty chn, mt thn chnh.
Khai bo gi v thn chnh c lu tr cng nhau trong mt file ring bit t phn cn li
ca nhng n v thit k. Tn file a cho file ny cn ging tn package. hon thnh
thit k kt hp chnh xc nn dng MAX+PLUS II. Trc tin bn cn kt hp Package
nh mt n v ring bit. Sau bn c th kt hp n v m dng Package .
Khai bo Package v Body:
Khai bo PACKAGE cha cc khai bo c th chia s gia cc n v ENTITY. N cung
cp giao din m cc linh kin c th thy trong n v ENTITY khc. Ty chn
PACKAGE BODY cha ng s thc thi ca cc chc nng v cc th tc c khai bo
trong PACKAGE.
1.6.1 C php khai bo PACKAGE:
PACKAGE package-name IS
type-declarations;
subtype-declarations;
variable-declarations;
constant-declarations;
component-declarations;
function-declarations;
procedure-declarations;
END package-name;
10
1.6.2 C php khai bo thn chnh Package:

PACKAGE BODY package-name IS
function-definitions; -- for functions declared in the package declaration
procedure-definitions; -- for procedures declared in the package declaration
END package-name;
V d LIBRARY IEEE;
PACKAGE my_package IS
SUBTYPE bit4 IS STD_LOGIC_VECTOR(3 DOWNTO 0);
FUNCTION Shiftright (input: IN bit4) RETURN bit4; -- declare a function
SIGNAL mysignal: bit4; -- a global signal
END my_package;
PACKAGE BODY my_package IS

-- implementation of the Shiftright function
FUNCTION Shiftright (input: IN bit4) RETURN bit4 IS
BEGIN
RETURN '0' & input(3 DOWNTO 1);
END shiftright;
END my_package;
s dng PACKAGE, bn ch n gin dng mt LIBRARY v cu lnh USE cho
Package .Trc khi kt hp Moun dng Package, trc tin bn cn kt hp chnh
Package nh mt ENTITY cp cao.
C php :
LIBRARY WORK;
USE WORK.package-name.ALL;
V d : LIBRARY WORK;
USE WORK.my_package.ALL;
ENTITY test_package IS PORT (
x: IN bit4; z: OUT bit4);
END test_package;
11
ARCHITECTURE Behavioral OF test_package IS

BEGIN
mysignal <= x;
z <= Shiftright(mysignal);
END Behavioral;
1.7
Nhng cu lnh ng thi theo cu trc Dataflow :
Pht biu Concurrent s dng cho m hnh Dataflow c thi hnh mt cch ng thi. Do
th t cc pht biu ny khng c nh hng kt qu ng ra.
1.7.1 Gn cc tn hiu ng thi :
Gn mt ga tr hoc kt qu ca c lng mt biu thc cho tn hiu. Pht biu ny c
thc thi khi no tn hiu trong biu thc thay i gi tr. Tuy nhin vic gn thc s gi
tr cho tn hiu din ra sau thi gian tr no v khng tc thi nh nhng php gn bin.
Biu thc c th l cc biu thc logic hoc s hc.
C php :
signal <= expression;
V d : y <= '1';
z <= y AND (NOT x);
Mt vector m tt c bit c cng gi tr c th dng t kha OTHERS nh di y:
SIGNAL x: STD_LOGIC_VECTOR(7 DOWNTO 0);
x <= (OTHERS => '0'); -- 8-bit vector of 0, same as "00000000"
1.7.2 Gn tn hiu c iu kin :
Chn mt hoc vi gi tr khc nhau gn cho tn hiu da trn iu kin khc nhau. Cu
lnh s thc thi khi 1 s gi tr hay iu kin thay i trong tn hiu
C php :
signal <= value1 WHEN condition ELSE

value2 WHEN condition ELSE
value3;
V d : z <= in0 WHEN sel = "00" ELSE

in1 WHEN sel = "01" ELSE
in2 WHEN sel = "10" ELSE
in3;
12
Gn tn hiu c chn la :
1.7.3
Chn mt hoc vi gi tr khc nhau gn cho tn hiu da trn gi tr ca biu thc c

chn. Tt c cc trng hp c th c ca biu thc cn c a .T kha OTHERS c
th dng ch r nhng trng hp cn li. Cu lnh s thc thi khi tn hiu trong biu
thc hoc mt gi tr thay i.
C php :
WITH expression SELECT

signal <= value1 WHEN choice1,
value2 WHEN choice2 | choice3,
value4 WHEN OTHERS;
Trong c php trn nu biu thc bng trng hp 1 th value1 c gn cho signal. V
th nu biu thc bng trng hp 2 hoc trng hp 3 th value2 c gn cho tn hiu.
Nu biu thc khng c trong cc trng hp trn th value4 trong ty chn WHEN
OTHERS c gn cho tn hiu.
V d : WITH sel SELECT
z <=
in0 WHEN "00",

in1 WHEN "01",
in2 WHEN "10",
in3 WHEN OTHERS;
1.7.4 V d cho kiu dataflow :

-- outputsa1ifthe 4-bit input is a prime number, 0 otherwise
LIBRARY IEEE;
ENTITY Prime IS PORT (
number: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
yes: OUT STD_LOGIC);
END Prime;
ARCHITECTURE Prime_Dataflow OF Prime IS
BEGIN
WITH number SELECT
13
yes <= '1' WHEN "0001" | "0010",

'1' WHEN "0011" | "0101" | "0111" | "1011" | "1101",
'0' WHEN OTHERS;
END Prime_Dataflow;
1.8
Nhng cu lnh tun t theo cu trc Behavioral :
M hnh behavioral cho php nhng pht biu thc thi lin tc ging nh mt chng
trnh my tnh thng thng. Pht biu Sequential statements gm nhiu chun xy dng
nh: gn bin, if then else, cc vng lp.
1.8.1 Process :
Khi PROCESS cha nhng pht biu c thc thi tun t. Tuy nhin chinh pht biu
PROCESS l mt concurrent statements (pht biu ng thi). Khi nhiu PROCESS trong
1 kin trc s thc thi mt cch ng thi . Cc khi x l ny kt hp vi nhau thnh
concurrent statements khc.
C php :
process-name: PROCESS (sensitivity-list)

variable-declarations;
BEGIN
sequential-statements;
END PROCESS process-name;
Danh sch tn hiu nhy c tch bit bi du phy (,) m n x l. Nhng t khc, mi
khi tn hiu trong danh sch thay di gi tr , vic x l c thc thi tt c pht biu tun
t theo danh sch. Sau khi pht biu cui cng c thc thi , vic x l s hon li cho
n thi gian tip theo khi mt tn hiu trong danh sch thay i gi tr trc khi thc thi
ln na.
V d: PROCESS (D, V, M)
BEGIN
term_1 <= D OR V;
S <= term_1 AND M;
END PROCESS;
1.8.2 Nhng php gn tn hiu tun t :
14
Gn gi tr cho mt tn hiu. Pht biu ny ging nh bn sao ca concurrent ngoi tr n

c thc thi mt cch tun t ch khi no s thc thi tin n n.
C php:
signal <= expression;
V d :
y <= '1';
z <= y AND (NOT x);
1.8.3 Php gn bin :

Gn 1 gi tr hoc kt qu c lng ca 1 biu thc n 1 bin. Gi tr ny lun gn cho
bin ngay lp tc khi m pht biu ny thc thi. Bin ny ch biu th bn trong khng x l
(PROCESS).
C php:
signal := expression;
V d : y := '1';
yn := NOT y;
1.8.4 Wait :
Khi 1 Process c danh sch nhy, process lun tr hon sau khi thc thi pht biu trc .
Mt kh nng s dng danh sch nhy tr hon Process l dng pht biu WAIT. N
cn c pht biu trc tin trong PROCESS.
C php :
WAIT UNTIL condition;
V d :
-- suspend until a rising clock edge

WAIT UNTIL clockEVENT AND clock = '1';
1.8.5
If then else :
C php:
IF condition THEN
sequential-statements1;
ELSE
END IF;
IF condition1 THEN
ELSIF condition2 THEN
15
ELSE
END IF;
V d: IF count /= 10 THEN -- not equal
count := count + 1;
ELSE
count := 0;
END IF;
1.8.6 Case:
C php:
CASE expression IS
WHEN choices => sequential-statements;
WHEN choices => sequential-statements;
WHEN OTHERS => sequential-statements;

END CASE;
V d: CASE sel IS
WHEN "00" => z <= in0;
WHEN "01" => z <= in1;
WHEN "10" => z <= in2;
WHEN OTHERS => z <= in3;
END CASE;
1.8.7 Null :
Pht biu NULL khng lm g c.
C php:
NULL;
1.8.8 For :
C php :
FOR identifier IN start [TO | DOWNTO] stop LOOP

END LOOP;
16
Pht biu LOOP cn gii hn tnh cc b. Vic nhn bit c thc hin ngm v th khng
khai bo r bin l s cn thit.
V d : sum := 0;
FOR count IN 1 TO 10 LOOP
sum := sum + count;
END LOOP;
1.8.9 While :
C php:
WHILE condition LOOP

END LOOP;
1.8.10 Loop :
C php:
LOOP
EXIT WHEN condition;
END LOOP;
1.8.11 Exit :
Pht biu EXIT ch dng bn trong vng lp. N thc hin hnh ng nhy ra khi vng
lp cui v thng dng kt hp vi pht biu LOOP.
C php:
EXIT WHEN condition;
1.8.12 Next :
Pht biu NEXT ch c th c dng bn trong vng lp . N thc hin b qua phn cui
ca cc vng lp v bt vng lp tip theo. N thng dng kt hp vi pht biu FOR.
C php :
NEXT WHEN condition;
V d : sum := 0;
FOR count IN 1 TO 10 LOOP
NEXT WHEN count = 3;
sum := sum + count;
END LOOP;
1.8.13 Function (hm) :
C php khai bo FUNCTION
17
FUNCTION function-name (parameter-list) RETURN return-type;

C php nh ngha FUNCTION
FUNCTION function-name (parameter-list) RETURN return-type IS
BEGIN
END function-name;
C php gi FUNCTION
function-name (actuals);
Thng s trong danh sch thng s ch c th hoc l tn hiu hoc l bin ca ng IN.
V d:
LIBRARY IEEE;
ENTITY test_function IS PORT (
x: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
z: OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END test_function;
ARCHITECTURE Behavioral OF test_function IS
FUNCTION Shiftright (input: IN bit4) RETURN bit4 IS
BEGIN
RETURN '0' & input(3 DOWNTO 1);
END shiftright;
SIGNAL mysignal: bit4;
BEGIN
PROCESS
BEGIN
mysignal <= x;
z <= Shiftright(mysignal);
END PROCESS;
18
END Behavioral;
1.8.14 Procedure (th tc) :
C php khai bo PRODUCE
PROCEDURE procedure -name (parameter-list);
C php nh ngha PRODUCE
PROCEDURE procedure-name (parameter-list) IS
BEGIN
END procedure-name;
C php gi PRODUCE
procedure -name (actuals);
Thng s trong danh sch thng s l cc bin ca ng IN ,OUT hay INOUT.
V d:
LIBRARY IEEE;
ENTITY test_procedure IS PORT (
x: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
z: OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END test_procedure;
ARCHITECTURE Behavioral OF test_procedure IS
PROCEDURE Shiftright (input: IN bit4; output: OUT bit4) IS
BEGIN
output := '0' & input(3 DOWNTO 1);
END shiftright;
BEGIN
PROCESS
VARIABLE mysignal: bit4;
BEGIN
19
Shiftright(x, mysignal);
z <= mysignal;
END PROCESS;
END Behavioral;
1.8.15 V d v kiu Behavioral :
LIBRARY IEEE;
ENTITY bcd IS PORT (
I: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
Segs: OUT STD_LOGIC_VECTOR(1 TO 7));
END bcd;
ARCHITECTURE Behavioral OF bcd IS
BEGIN
PROCESS(I)
BEGIN
CASE I IS
WHEN "0000" => Segs <= "1111110";
WHEN "0001" => Segs <= "0110000";
WHEN "0010" => Segs <= "1101101";
WHEN "0011" => Segs <= "1111001";
WHEN "0100" => Segs <= "0110011";
WHEN "0101" => Segs <= "1011011";
WHEN "0110" => Segs <= "1011111";
WHEN "0111" => Segs <= "1110000";
WHEN "1000" => Segs <= "1111111";
WHEN "1001" => Segs <= "1110011";
WHEN OTHERS => Segs <= "0000000";
END CASE;
END PROCESS;
20
END Behavioral;
1.9
Cc cu lnh kiu Structural :
M hnh cu trc cho php kt ni bng tay mt vi linh kin vi nhau s dng tn hiu .
Tt c cc linh kin c s dng cn nh ngha trc vi phn ENTITY v
ARCHITECTURE ca chng trong cng 1 file hoc cc file ring. Trong mun cao nht,
mi linh kin s dng trong bng kt ni c khai bo trc tin dng pht biu
COMPONENT. Sau nhng khai bo COMPONENT c p dng vi linh kin tht
s trong mch bng cch dng pht biu PORT MAP. Sau nhng tn hiu c dng kt
ni cc linh kin vi nhau theo bng kt ni.
1.9.1 Khai bo Component :
Khai bo tn v giao din ca linh kin c dng trong m t mch .Vic khai bo cho
mi linh kin phi c dng ph hp vi ENTITY v ARCHITECTURE ca linh kin
. Khai bo tn v giao din phi ph hp, chnh xc tn v giao din c ch r trong
phn ENTITY ca linh kin .
C php
COMPONENT component-name IS
END COMPONENT;
or
COMPONENT component-name IS
GENERIC (identifier: type := constant);
END COMPONENT;
V d :
COMPONENT half_adder IS PORT (
xi, yi, cin: IN STD_LOGIC;
cout, si: OUT STD_LOGIC);
END COMPONENT;
1.9.2 Port map :
21
Pht biu PORT MAP thuyt minh khai bo 1 linh kin vi linh kin tht trong mch bng
cch ch r kt ni nh th no cc ng dng ca linh kin ny c hnh thnh.
C php :
label: component-name PORT MAP (association-list); hoc
label: component-name GENERIC MAP (constant) PORT MAP (association-list);

Danh sch kt hp c th ch r dng phng php hoc positional hoc named.
V d : kt hp theo v tr (positional association):
SIGNAL x0, x1, y0, y1, c0, c1, c2, s0, s1: STD_LOGIC;
U1: half_adder PORT MAP (x0, y0, c0, c1, s0);
U2: half_adder PORT MAP (x1, y1, c1, c2, s1);
V d : kt hp theo tn (named association):
SIGNAL x0, x1, y0, y1, c0, c1, c2, s0, s1: STD_LOGIC;
U1: half_adder PORT MAP (cout=>c1, si=>s0, cin=>c0, xi=>x0, yi=>y0);
U2: half_adder PORT MAP (cin=>c1, xi=>x1, yi=>y1, cout=>c2, si=>s1);
1.9.3 Open :
T kha OPEN dng trong danh sch kt hp ca PORT MAP ch rng port ra ring
bit khng c kt ni hoc s dng. N khng dng cho 1 port ng vo.
V d :
U1: half_adder PORT MAP (x0, y0, c0, OPEN, s0);
1.9.4 Generate :
Pht biu GENERATE lm vic nh on m m rng. N cung cp cch n gin sao
chp nhng linh kin ging nhau.
C php :
label: FOR identifier IN start [TO | DOWNTO] stop GENERATE
port-map-statements;
END GENERATE label;
V d:
-- using a FOR-GENERATE statement to generate four instances of the full adder
-- component for a 4-bit adder
LIBRARY IEEE;
22
ENTITY Adder4 IS PORT (

Cin: IN STD_LOGIC;
A, B: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
Cout: OUT STD_LOGIC;
SUM: OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END Adder4;
ARCHITECTURE Structural OF Adder4 IS
COMPONENT FA PORT (
ci, xi, yi: IN STD_LOGIC;
co, si: OUT STD_LOGIC);
END COMPONENT;
SIGNAL Carryv: STD_LOGIC_VECTOR(4 DOWNTO 0);
BEGIN
Carryv(0) <= Cin;
Adder: FOR k IN 3 DOWNTO 0 GENERATE
FullAdder: FA PORT MAP (Carryv(k), A(k), B(k), Carryv(k+1), SUM(k));
END GENERATE Adder;
Cout <= Carryv(4);
END Structural;
1.9.5 V d v cch vit on m theo kiu Structure:
V d ny da trn mch sau :
-- declare and define the 2-input OR gate

LIBRARY IEEE;
ENTITY myOR IS PORT (
23
END myOR;
ARCHITECTURE OR_Dataflow OF myOR IS
BEGIN
out1 <= in1 OR in2; -- performs the OR operation
END OR_Dataflow;
-- declare and define the 2-input AND gate
LIBRARY IEEE;
ENTITY myAND IS PORT (
END myOR;
ARCHITECTURE OR_Dataflow OF myAND IS
BEGIN
out1 <= in1 AND in2; -- performs the AND operation
END OR_Dataflow;
-- topmost module for the siren
LIBRARY IEEE;
ENTITY Siren IS PORT (
M: IN STD_LOGIC;
D: IN STD_LOGIC;
V: IN STD_LOGIC;
S: OUT STD_LOGIC);
END Siren;
ARCHITECTURE Siren_Structural OF Siren IS
-- declaration of the needed OR gate
COMPONENT myOR PORT (
24

END COMPONENT;
-- declaration of the needed AND gate
COMPONENT myAND PORT (
END COMPONENT;
-- signal for connecting the output of the OR gate
-- with the input to the AND gate
SIGNAL term1: STD_LOGIC;
BEGIN
U0: myOR PORT MAP (D, V, term1);
U1: myAND PORT MAP (term1, M, S);
END Siren_Structural;
1.10
Cc th tc chuyn i :
1.10.1 Conv_integer ( ) :
Chuyn loi std_logic_vector thnh Integer
Yu cu:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
C php :
CONV_INTEGER(std_logic_vector)
V d : LIBRARY IEEE;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
SIGNAL four_bit: STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL n: INTEGER;
n := CONV_INTEGER(four_bit);
1.10.2 Conv_Std_Logic_Vector (,):
Chuyn loi Integer thnh std_logic_vector
Yu cu :
LIBRARY IEEE;
25
USE IEEE.STD_LOGIC_ARITH.ALL;
C php :
CONV_STD_LOGIC_VECTOR (integer, number_of_bits)
V d :
LIBRARY IEEE;
USE IEEE.STD_LOGIC_ARITH.ALL;
SIGNAL four_bit: STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL n: INTEGER;
four_bit := CONV_STD_LOGIC_VECTOR(n, 4);
26
Chng 2 : Dng ngn ng VHDL m t cc mch s c bn
CHNG 2 : DNG NGN NG VHDL M T CC

MCH S C BN
2.1
Ngn ng VHDL m t cc cng logic c bn:
Mt mch s c m t bi mt phng trnh Boolean u c th d dng chuyn sang

ngn ng VHDL bng cch s dng kiu vit dng d liu (dataflow). cp dng d
liu, mt mch c th c thit lp t cc cng AND, OR hay NOT khi m t cc cng
ny bng ngn ng VHDL ta s dng cc cu lnh ng thi.
2.1.1 on m VHDL m t cng NAND 2 ng vo:
Di y l on m VHDL vit cho cng NAND 2 ng vo. y cng l mt on m
mu minh ha cho cch vit ngn ng VHDL. Dng u tin trong on m VHDL bt u
bng hai du - - l dng ch thch cho on m. Hai dng lnh LIBRARY v USE c
dng ch r th vin IEEE c s dng trong on m. Th vin ny cha tt c cc
phn t logic cn thit cho on m pha di. Hai dng lnh ny tng ng vi dng
lnh #include trong lp trnh C++.
Mi mt thnh phn trong ngn ng VHDL t phn t cng NAND n gin cho n b vi
x l phc tp th u bao gm hai b phn: phn thc th v phn thn cu trc. Phn thc
th tng t nh khai bo hm trong C++. N khai bo tt c cc tn hiu ng vo v ng ra
trong mch. Mi mt thc th phi c t tn, v d trong on m bn di l
NAND2gate. Thc th cha mt danh sch PORT, n s quy nh s lng ng vo v ra
ca cng NAND. V d trong an m x, y l nhng tn hiu ng vo dng STD_LOGIC
v f l tn hiu ng ra cng dng STD_LOGIC. Dng STD_LOGIC cng ging nh dng
loi BIT, ngoi tr n cha thm nhng gi tr khc ngoi hai gi tr 0 v 1.
Phn thn cu trc n cha an m m t hot ng ca NAND 2 ng vo. Mi mt thn
cu trc cng cn phi c t tn. V d trong an m phn thn cu trc c tn l
Dataflow. Trong phn thn cu trc c th c mt hay nhiu cu lnh ng thi. Khng
ging nh trong C++ ni m cc dng lnh c thc thi mt cch tun t, nhng dng
lnh trong thn cu trc c thc thi mt cch song song. Du <= c dng gn cho
mt tn hiu. V phi ca du <= l biu din php ton logic gia cc bin s ng vo x
v y, kt qu s c gn cho ng ra f nm bn tri ca du <=. on m m t cng
NAND bng ngn ng VHDL c vit nh sau.
27
Hnh 2. 1 : on m VHDL cho cng NAND 2 ng vo.

2.1.2 Ngn ng VHDL m t cng NOR 3 ng vo:
Di y l on m VHDL cho cng NOR 3 ng vo. C 3 tn hiu ng vo l x, y, z v
mt tn hiu ng ra c khai bo trong phn thc th. Trong v d ny c khai bo thm
hai tn hiu ni: xory v xoryorz, c hai tn hiu ny u thuc loi STD_LOGIC. T kha
SIGNAL trong phn thn cu trc c dng khai bo hai tn hiu ni ny. Cc tn hiu
ni ny c s dng nh nhng nt tn hiu trung gian trong mch. Tt c cc cu lnh
gn tn hiu c thc thi mt cch ng thi. iu va nu c minh ha r nt trong
hnh 2.2b.
Hnh 2.2c l qu trnh m phng theo thi gian cho hot ng ca mch hnh 2.2b. Trong
gin xung ny, chng ta thy ng ra f ch bng 1 khi v ch khi tt c cc ng vo ca n
u phi c gi tr 0. Do f ch bng 1 ti hai khong thi gian t 0-100ns v t 800900ns, cn trong nhng khong thi gian khc f u nhn gi tr 0.
28
Hnh 2. 2 : Cng NOR 3 ng vo (a) on m VHDL; (b) s mch; (c) thi gian m
phng.
2.1.3 Dng ngn ng VHDL m t mt h thng bo ng cho xe hi:
Trong mt h thng bo ng cho xe hi, chng ta thng kt ni h thng ny vi mt ci
ci bo ng, khi c mt tc ng t bn ngoi no vo h thng th chung s vang ln.
Theo tng ny, chng ta phi c: mt cng tc iu khin ng ngt chnh cho h thng
c t tn l M; mt cng tc i din cho vic ng m ca xe c t tn l D; mt
b pht hin dao ng c t tn l V. Chng ta s quy nh mc logic cho tng k hiu
ny nh sau: ca xe m khi D=1, trng hp khc th D=0; tng t nh th, khi xe b
rung ng th V=1, trng hp khc V=0; chng ta mun ci S reo ln th S=1. Nh vy c
ba trng hp lm cho chung bo hiu reo ln l D=1 hoc V=1 hoc c hai D=V=1, trong
ba trng hp trn cng tc iu khin chnh ca h thng s ng li lm chung bo ng
vang ln tc l M=1. Tuy nhin, vn t ra y l khi ngi ch xe m ca xe ra vo
bn trong li xe th h khng mun ci bo ng vang ln. Do lc ny cng tc iu
khin chnh M=0 tng ng vi ton b h thng bo ng s ngng hot ng bt k D v
V ang l 0 hay 1. Da trn nhng phn tch trn ta lp bng chn tr cho hm S gm 3 bin
M, D,V nh sau:
T bng chn tr ta c th vit c phng trnh Boolean cho ng ra S nh sau:
29
T phng trnh trn ta s thit lp c s mch cho c h thng bo ng ny nh

sau:
Ngoi ra ta c th rt gn biu thc S bng cch s dng cc tin v cc nh l c bn

trong i s Boolean:
T biu thc S rt gn ta s thit lp c mch bo ng n gin hn, s dng t cng

logic hn nhng yu cu chng trm vn m bo.
Gin xung ng ngt chung c m t r nt thng qua hnh 2.3
Hnh 2. 3 : Gin xung ca h thng bo ng trong xe hi: (a) Dng xung trn l
thuyt; (b) Dng xung trn thc t.
30
Ta nhn thy c xut hin thi gian tr khi ngt v m chung. iu ny hon ton ph hp
vi thc t khi thi cng mch.
Ta s vit chng trnh VHDL cho biu thc logic ca mch bo ng trong xe hi:
on m ny c vit cp Dataflow khng phi v ta nhn vo tn thn cu trc ca
n l Dataflow xc nh. M v m ha cp Dataflow s dng cc phng trnh
logic m t mch. Trong on m di y ta s dng cch ny m t s hot ng
ca cc cng AND, OR, NOT bng nhng cu lnh gn tn hiu ng thi.
Hnh 2. 4 : Mch bo ng trong xe hi (a) on m VHDL c vit di dng dataflow;

(b) m phng gin xung.
2.2
B gii m LED 7 on:
2.2.1 Xy dng cu trc b gii m LED 7 on:

By gi chng ta s tng hp mch cho mt b gii m 7 on li cho mt b hin th LED
7 on. B gii m 7 on chuyn i mt ng vo 4 bit thnh 7 ng ra cho vic iu khin
31
7 n trong b hin th LED 7 on. 4 bit ng vo ny m ha cho mt trng thi nh phn

tng ng ca mt s thp phn. Cho mt s thp phn ng vo, 7 ng tn hiu ng ra
c bt ln theo mt trt t nh trc ca b hin th LED tng trng cho mt s
thp phn. Di y l s ca b hin th LED 7 on vi cc tn ca tng on c
gn nh sau:
S hot ng ca b gii m 7 on c gii thiu trong bng chn tr hnh 2.5. 4 ng vo

c gii m l I 3 , I 2 , I 1 , I 0 , v 7 ng ra m mi ng ra th c dn nhn l seg a, seg
b,, seg g. Mi mt cch kt ni ng vo th tng trng cho mt s thp phn hin th
trong LED 7 on v chng c biu din trong ct Display. Mi mt on th sng ln
khi n trang thi 1 v tt i khi n nhn gi tr 0. V d trng hp 4 bit ng vo l 0000
th LED s ch hin th ln 6 on a, b, c, d, e v f tng ng vi cc on ny s nhn
gi tr 1 v ch duy nht mt on g khng hin th v n nhn gi tr 0.
Trong bng di y ta ch rng cc gi tr ng vo t 1010 n 1111 th khng c
biu th, v ta cng khng cn quan tm n nhng gi tr ca cc on LED hin th cho
cc gi tr .
Hnh 2. 5 : Bng chn tr ca b gii m 7 on.

T bng chn tr ta c th vit c biu thc logic cho on seg a mt cch d dng da
vo nhng gi tr 1 trong ct seg a.
32
Mun thu gn biu thc logic a thun tin trong vic m t mch sau ny ta phi s
dng phng php ba Karnaugh c gii thiu phn trn. Trng thi no ca seg a
khng c trong bng chn tr hnh 2.5 th ta c th mc nh bng 0 hoc bng 1 sao cho
thun li trong vic ti gin biu thc.
T ba Karnaugh kt hp vi cc php bin i n gin trong i s Boolean ta c th vit

gn li biu thc a nh sau:
Vic lp biu thc Boolean cho cc on b, c, d, e, f, g c thc hin tng t nh cho a.
Cui cng ta s c cc kt qu sau:
T 7 biu thc a, b, c, d, e, f, g ta s v c s mch gii m LED 7 on nh sau:
33
Hnh 2. 6 : Mch gii m LED 7 on.

2.2.2 Ngn ng VHDL m t mch gii m LED 7 on:
Vic dng ngn ng VHDL m t cho mt mch kt ni hay mch tun t c th c
thc hin bng mt trong ba cp sau: structural, dataflow v behavioral.
cp structural, l cp thp nht, trc tin bn phi t thit k mch. Phi v mch,
bn dng VHDL biu din cc thnh phn v cc cng logic cn thit cho mch. Bn
phi dng ngn ng VHDL m t s mch biu din mt cch chnh xc cc cng logic
ny c kt ni vi nhau nh th no.
cp dataflow, bn dng cc hm logic c xy dng sn trong VHDL gn cho
cc cu lnh trong vic kt ni tn hiu. Vic m t mt mch s, trc tin bn li phi t
thit k mch. Cc phng trnh Boolean dng m t mch th c th c d dng
chuyn i thnh cc cu gn lnh trong ngn ng VHDL bng cc t kha logic c sn.
Tt c cc cu lnh c vit trong hai cy trc Structural v dataflow u c thc thi
mt cch ng thi. iu ny th tri ngc vi nhng cu lnh trong ngn ng my tnh,
ni m cc cu lnh ny c thc thi mt cch tun t. M t mch cp Behavioral
34
th l ging nht vi ngn ng ca my tnh. Bn phi c tt c cc tiu chun ca mt

chng trnh ngn ng cp cao nh FOR LOOP, WHILE LOOP, IF THEN ELSE, CASE
v cc s gn bin. Nhng cu lnh ny c tp trung x l trong khi PROCESS v c
thc thi mt cch tun t.
2.2.3 Cu trc structural biu din gii m s thp phn ra Led 7 on:
35
36
2.2.4 Cu trc dataflow biu din gii m s thp phn ra Led 7 on:
Di y l on m VHDL cho b gii m BCD ra LED 7 on c vit cp
dataflow. Trong phn cu trc ny th vic gn 7 cu lnh ng thi cho 7 tn hiu c s
dng. Biu thc logic a c chuyn i thnh ngn ng VHDL nh sau:
37
2.2.5 Cu trc behavioral biu din gii m s thp phn ra Led 7 on:
Di y l on m VHDL cho b gii m BCD ra LED 7 on c vit cp
behavioral. Trong phn cu trc ny, mt khi Process c s dng. Tt c cc cu lnh
trong khi Process c thc thi mt cch tun t. Nu trong cng mt cu trc m c
nhiu khi Process th mi mt khi Process s c thc thi mt cch ng thi.
Cc t trong du ( ) ca khi Process ch cc bin ang xt trong khi process, nu
mt trong cc bin ny thay i gi tr th cc dng lnh trong khi Process mi c thc
thi t u cho n cui khi Process .
Hnh 2. 7 : S biu din thi gian hin th mt s trn Led 7 on ca mt s thp phn
tng ng.
2.3
B cng:
2.3.1 B cng ton phn (FA):

38
xy dng cu trc cho mt b cng thc hin php ton cng cho cc s c hai gi tr
nh phn, X x n 1 ...x0 v Y y n 1 ... y 0 . Trc tin ta cng tng cp bit li vi nhau x i v
y i , sau ta cng thm bit nh c i vo kt qu ny ta s c kt qu cui cng ca php
cng hai s nh phn. Trong bit nh c i l bit nhn gi tr 1 khi kt qu php cng trc
ca n l c nh (1+1=0 vit 0 nh 1 sang ct tip theo). Do si
ci
xi
yi
ci v
1 nu kt qu php cng si l c nh sang ct k tip. Mch thc hin php cng
theo tng cp bit nh vy ta gi l b cng ton phn (FA) v bng chn tr ca n c

biu din trong hnh 2.8(a). Biu thc logic ca si v ci 1 c chng minh nh sau:
T hai biu thc trn ta c th v s mch cho b cng ton phn c biu din trong
hnh 2.8(b). Hnh 2.8(c) biu din k hiu logic ca b cng ton phn.
Hnh 2. 8 : B cng ton phn (a) bng chn tr; (b) s mch; (c) k hiu logic.
on m VHDL cho b cng ton phn thc hin php cng mt cp bit c vit theo cu
trc Dataflow c dng nh sau:
39
2.3.2 B cng ton phn hai s nh phn c nhiu hn 1 bit:

Phn trn ta kho st b cng ton phn cho mt cp bit, trong phn ny ta s trnh by
phng php cng hai s nh phn 8 bit li vi nhau (Ripple Carry Adder). S mch
thc hin vic cng ny c biu din trong hnh 2.9, n bao gm cc b cng ton phn
mt cp bit c mc ni tip vi nhau. Vic cng c thc hin t cp bit u tin bn
phi hay cp bit c trng s nh nht trong chui bit nh phn, lc ny ta phi set c 0 =0.
Mch cng tip tc thc hin t phi qua tri, c1 =1 nu php cng cp bit x 0 v y 0 vi
nhau c nh v c1 =0 cho trng hp cng khng c nh. C thc hin cng tun t nh
vy cho n bit cout .
Hnh 2. 9 : B cng hai s nh phn 8 bit.

Di y l on m VHDL c vit theo cu trc Structural cho b cng hai s nh phn
4 bit. Khi chng ta cn lp li 4 ln b cng ton phn, chng ta c th dng 4 ln cu lnh
PORT MAP hoc l c th s dng cu lnh FOR-GENERATE vn hnh 4 thnh phn
ny mt cch t ng nh trong on m biu din di y. Cu lnh FOR k IN 3
DOWNTO 0 GENERATE quyt nh lp li cu lnh PORT MAP bao nhiu ln v gi tr
s dng cho php m s ln lp l k.
40
2.3.3 B cng hai s nh phn nhiu bit cho kt qu hin th nhanh:

B cng Ripple Carry Adder th thc hin vic cng chm bi v trng thi nh ng vo
ca mt cp bit th ph thuc vo trng thi nh ng ra ca cp bit lin trc n. V th
trc khi mu bit th i c th c hiu lc ti ng ra th n phi ch i mu bit th i-1 t
c gi tr n nh trc. Trong b cng hai s nh phn nhiu bit cho kt qu hin th
nhanh (Carry-Lookahead Adder) th mi mt mu bit loi tr s ph thuc vo trng thi
nh ng ra ca tn hiu trc , n s dng gi tr ca hai bit X v Y mt cch trc tip
suy ra cc tn hiu cn thit. Cho mi mt mu bit th i th tn hiu nh ng ra ci 1 s c
bt ln 1 nu mt trong hai iu kin sau y l ng:
Hay
Hay ni mt cch khc:

Nu chng ta t:
V
41
Th ta s c cch vit tng qut nh sau:

T cng thc tng qut ny ta c th suy ra cc cng thc c th sau:
T biu thc trn ta c th v c s mch cho b cng Carry-Lokkahead nh sau:
Hnh 2. 10 : (a) Mch vn hnh tn hiu Carry-Lookahead t c1 n c 4 ; (b) mt mu bit

ca b cng Carry-Lookahead.
2.4
B tr:
2.4.1 B tr mt bit:
Chng ta c th xy dng mch cho b tr thc hin vic tr mt bit tng t nh phng
php m chng ta dng khi xy dng b cng ton phn. Tuy nhin bit tng si trong
php cng uc thay th bng bit hiu d i trong php tr, v trng thi nh ng vo, trng
42
thi nh ng ra tn hiu trong b cng c thay th bng mn ng vo ( b i ) v mn ng

ra ( bi 1 ) tn hiu. Do d i
nhng trng hp khc bi
xi
1
yi
bi v bi
1 nu chng ta cn mn trong php tr,
0 . Bng chn tr cho b tr 1 bit c biu din trong hnh
2.11(a) thng qua hai biu thc logic ca d i v bi 1 :
Hnh 2. 11 : B tr 1 bit (a) bng chn tr; (b) s mch; (c) k hiu logic.
2.4.2 S tch hp c hai b cng v b tr trong cng mt mch s:
Chng ta c th xy dng mt thnh phn trong cha ng hai thnh phn tch bit l
b cng v b tr bng cch sa i li s ca mch cng Ripple Carry (hay c th l
mch Carry-Lookahead Adder). Vic sa i mch biu din cho b tr c thc hin
bng cch cng gi tr m ca hai ton hng. ph nh mt gi tr nh phn nh trong
phn trc gii thiu, chng ta s chuyn i tt c cc bit trong chui bit t 0 thnh 1
v ngc li mt cch d dng.
Ng vo S s c dng la chn chc nng ca mch l mch cng hay mch tr. Khi
S=1 th mch hot ng nh mt b tr. Ton hng B cn phi c o li. Chng ta nh
rng x 1 x' , do o B th ta ch vic em B S B' (khi S=1). Cui cng, vic
cng thm 1 vo c thc hin bng cch bt bit nh tn hiu c 0 ln 1. Mt khc, thc
hin chc nng ca b cng th S=0. Khi S=0 th ton hng B s khng cn phi o trang
43
thi iu ny c thc hin nh cng XOR. Trong trng hp ny, chng ta cng mun
c0 S 0 .
Mt mch thc hin c hai vic cng v tr c biu din trong hnh 2.12(b) v k hiu
logic ca n c th hin trong hnh 2.12(c).
Hnh 2. 12 : Mch cng v tr chui 8 bit nh phn (a) bng vhn tr; (b) s mch; (c)
k hiu logic.
M VHDL vit theo cu trc Behavioral cho mch cng v tr chui 8 bit nh phn:
44
2.5
Thnh phn thc hin cc php ton logic s hc (ALU):
Thnh phn ny gi tt l khi ALU l mt trong nhng thnh phn quan trng trong mt
b vi x l, chng m nhn trch nhim thc hin cc hot ng lin quan n s hc hay
cc s hot ng ca cc mch logic nh b cng, b tr, cng logic AND, OR. xy
dng mch cho khi ALU, chng ta c th dng cng mt tng nh khi xy dng cho
mt mch thc hin c hai chc nng ca b cng v b tr nh c trnh by phn
trn. Mt ln na, chng ta s s dng b cng Ripple Carry khi xty dng s khi v
sau ta chn thm cc mch kt ni logic vo pha trc hai ng vo thut ton ca b
cng. Theo cch ny, cc ng vo s cp s c sa i cho ph hp vi s hot ng m
n cn biu din trc khi n i qua b cng ton phn. Ton b s vn hnh mch ca
b ALU 4 bit c biu din trong hnh 2.13.
Chng ta quan st hnh 2.13 thy c hai mch kt ni pha trc b cng ton phn (FA)
l LE v AE. B LE (logic extender) l b dng diu khin tt c mi hot ng
logic, trong khi b AE (arithmetic extender) l b dng diu khin tt c mi hot ng
v s hc. B LE thc thi cc hot ng logic chnh xc t hai ng vo s cp l a i v b i
trc khi kt qu ca n vt ra ng x i ca b FA. Hay ni cch khc, b AE ch sa i
45
ng vo b i v cho ra kt qu ti ng ra y i ca b FA. B FA nhn gi tr x i v y i s thc

thi cc php ton s hc chnh xc.
Hnh 2. 13 : Mch ALU 4 bit.

Chng ta thy t s mch phi hp b cng v b tr cho n vic cng v tr, chng ta
ch cn sa li ng vo th hai ca b FA y i m thi, v th tt c cc hot ng c th
c thc hin vi php cng. Do , b AE ch ly gi tr ca ng vo b i v sa i n
ph hp vi s hot ng c thc thi ca mch. Ng ra y i ca n s c kt ni n
ng vo th hai ca b FA. Trong mch phi hp b cng v b tr, vic cng c thc
thi trong b FA. Khi cc php ton s hc ang c thc thi, b LE phi cho tn hiu qua
m khng lm thay i t ng vo s cp a i n x i trong b FA.
Khng ging nh b AE ni ch sa i cc thut ton, b LE thc thi cc hot ng logic
chnh xc. Do , nu chng ta mun thc hin php ton A OR B, th b LE s ly tng
cp bit th a i v b i (ca A v B) thc hin php Or chng li vi nhau. Do , b LE c
hai ng vo a i v b i v ng ra ca n l x i . Khi gi tr chun b hin th kt qu ca cc
hot ng logic, chng ta khng mun b FA sa i n, m a gi tr ny hin th ra ng
ra s cp f i . iu ny c th thc hin c bng cch chng ta bt c hai gi tr y i ca b
FA v c 0 xung 0. Khi vic cng bt k s no vi 0 cng khng lm thay i gi tr
ban u ca n.
B CE m nhn vic nh trng thi tn hiu s cp c 0 , gip cho vic thc thi mch c
thc hin mt cch chnh xc. Trong cc hot ng logic th trng thi bit nh tn hiu c 0
lun c t bng 0.
46
Hnh 2. 14 : Hot ng ca khi ALU (a) Bng cc trng thi; (b) Bng chn tr ca LE;
(c) Bng chn tr ca AE; (d) Bng chn tr ca CE.
Trong hnh 2.14 cc ng tn hiu S 2 , S1 v S 0 c dng la chn s hot ng ca
khi ALU. S 2
S2
1 , th khi ALU s c chn la hot ng theo cc php ton s hc.
0 , th khi ALU s c chn la hot ng theo cc php ton logic. Hai ng S 0
v S 1 cho php la chn mt trong bn b LE hay AE hot ng. Do mch ALU c th

c 8 s hot ng khc nhau l:
- Cho mt tn hiu no i qua m khng lm i gi tr ca n.
- Thc hin php ton logic AND hai s A v B.
- Thc hin php ton logic OR hai s A v B.
- Thc hin php ton logic NOT cho mt s no .
- Thc hin php cng hai s A v B.
- Thc hin php tr hai s A v B.
- Thc hin php cng 1 vo mt s A.
- Thc hin php tr A cho 1.
Trong 8 hot ng trn, mi hot ng s c cc gi tr X, Y v c 0 khc nhau.
Trong cc hnh 2.14(b), (c) v (d) ta thy x i ch ph thuc vo 5 bin s S 2 , S1 , S 0 , a i v
b i ; y i ch ph thuc vo 4 bin s S 2 , S1 , S 0 v b i ; v c 0 ch ph thuc vo 3 ng vo la
47
chn S 2 , S1 , S 0 . Ba Karnaugh v biu thc tng ng cho cc biu thc x i , y i v c 0 c

biu din trong hnh 2.15.
Hnh 2. 15 : Ba karnaugh, biu thc, s mch cho: (a) LE; (b) AE; (c) CE.
on m VHDL ca b ALU c vit theo cu trc behavioral c biu din trong hnh
2.16. Dng sng m phng cc thut ton ca khi ALU khi hai s ng vo l 5 v 3 c
biu din trong hnh 2.17.
48
Hnh 2. 16: on m VHDL cho mt khi ALU.
Hnh 2. 17 : Dng sng m phng cho 8 thut ton c bn ca khi ALU vi hai gi tr ng
vo l 5 v 3.
2.6
B gii m:
B gii m cn c gi l b phn knh, n c n ng ra, s ng ra ny ph thuc vo s m

bit la chn ng vo. Mi quan h gia n v m l n
2 m . Trong b gii m c thm mt

49
ng Enable cho php b gii m hot ng hay ngng hot ng. Khi E=0 th tt c
cc ng ra u mang gi tr 0. Khi E=1 th b gii m s hot ng, n s la chn ng ra
no a d liu n ty thuc vo cc ng vo la chn m. V d mt b gii m 3
sang 8. Nu ng vo a ch l 101 th th ng ra Y5 c la chn a d liu ra ( Y5 ln
mc cao), trong khi tt c cc ng ra cn li u khng c la chn (tch cc mc
thp).
Mt b gii m thng dng rt nhiu thnh phn v chng ta mun ti mi thi im ch
c mt thnh phn c cho php hot ng m thi. V d trong mt h thng nh ln s
dng nhiu con chip nh, ti mi thi im ch c mt con chip nh c tch cc cho php
hot ng m thi. Mt ng ra ca b gii m s c ni n mt ng vo tch cc trong
mi con chip. Mt a ch c to ra t b gii m s lm tch cc mt con chip nh tng
ng. Bng chn tr, s mch v k hiu logic ca b gii m 3 sang 8 c biu din
trong hnh 2.18.
Mt b gii m kch c ln c th s dng mt vi cc b gii m nh hn. V d trong
hnh 2.19 s dng 7 b gii m 1 sang 2 xy dng b gii m 3 sang 8.
Hnh 2. 18 : Mt b gii m 3 sang 8 (a) Bng chn tr; (b) s mch; (c) k hiu logic.
50
Hnh 2. 19 : Mt b gii m 3 sang 8 c xy dng t 7 b gii m 1 sang 2.

on m VHDL c vit theo cu trc Behavioral cho b gii m 3 sang 8.
51
2.7
B m ha:
Mt b m ha c xem nh l s o ngc ca mt b gii m. B m ha s m ha
2 n bit d liu ng vo thnh m n bit. S hot ng ca b m ha c hiu nh sau: ch

mt ng ng vo c bt ln 1, tt c cc ng vo cn li u bng 0 ng vi mt gi tr
ca Y0,Y1 ,Y2 . V d khi I 3 =1 th 3 gi tr Y2Y1Y0 011 .
Hnh 2. 20 : Mt b m ha 8 sang 3 (a) Bng chn tr; (b) s mch; (c) k hiu logic.
Khuyt im ca b m ha ny l ch: Nu hai hay nhiu ng vo I i cng c tch cc
ti mt thi im, th ng ra s m ha sai ngay lp tc. V d nu ng vo 1 v 4 ca b
m ha 8 sang 3 cng c tch cc mt lc. Khi Y 2 va nhn gi tr 1 ca I 4 va mang
gi tr 0 ca I 1 . gii quyt vn ny, ngi ta mi t ra mt quy lut u tin cho th
t thc hin ca cc ng vo I i .
52
Hnh 2. 21 : Bng chn tr cho mt b m ha 8 sang 3 c s u tin.

T hng th 3 n hng th 10 trong hnh 2.21 ta c th vit c cc biu thc sau:
Suy ra
T bng chn tr hnh 2.21 ta c th vit c biu thc Z nh sau:

Trong bng chn tr hnh 2.21 ta thy I 7 l c u tin cao nht v I 0 l c u tin
thp nht. V d nu ng vo I 3 c u tin cao nht th ta khong cb quan tm n
nhng ng vo c u tin thp hn l I 2 , I 1 , I 0 c trng thi l 0 hay 1, ng ra ca mch
s l I 3 tc l gi tr nh phn 011. Trong trng hp khng c ng vo no c chn th
ta cn thm mt ng ra Z phn bit s khc nhau gia trng hp khng c ng vo no
c chn v trng hp c mt hay nhiu ng vo c chn. Z=1 khi c mt hay nhiu
ng vo c chn, trng hp cn li Z=0. Khi Z=0 tt c cc ng ra Y u v ngha.
2.8
B ghp knh:
53
B ghp knh cn gi l b MUX cho php la chn mt tn hiu ng vo t n ng vo. Do

n l k hiu cho cc tn hiu ng vo, s l k hiu cho ng vo la chn. Mi quan h
gia n v s l 2 s n . Cu trc ca mt b ghp knh 2 sang 1 c gii thiu k trong
cc chng trc, trong phn ny ta s nhc li cch xy dng minh ha m thi.
Hnh 2. 22 : B ghp knh t 2 sang 1 (a) Bng chn tr; (b) s mch; (c) k hiu logic.
T vic gii thiu cch xy dng b ghp knh 2 sang 1 ta c th xy dng cc b ghp
knh c kch thc ln hn nh b ghp knh 8 sang 1 tng t nh cch lm trn. C
8 ng d liu ng vo cho nn s c 3 ng vo la chn. Ty thuc vo gi tr nh phn
ca 3 ng vo la chn m mt trong 8 ng vo d liu s c chn a gi tr t ng
vo y n ng ra. V d nu gi tr la chn l 101 th ng vo d 5 c chn v d liu
ca d 5 s c a n ng ra.
lp bng chn tr cho b ghp knh 8 sang 1 th ta ch c 3 bit la chn nn s c
2 3 =8 trng thi khc ca ng vo d liu.
Hnh 2. 23 : B ghp knh 8 sang 1 (a) Bng chn tr; (b) s mch; (c) k hiu logic.
54
Hnh 2. 24 : B ghp knh 8 sang 1 c s dng (a) B gii m 3 sang 8; (b) 7 b ghp knh
2 sang 1.
Trong hnh 2.23(b) ta phi hiu rng cng AND ng vai tr l mt cng tc v n c
iu khin bt bi 3 ng vo la chn d liu. Khi cng AND ny c bt ln 1 d liu
d tng ng qua cng s c a ti chn y ti ng ra, cng thi im ny tt c cc
cng AND cn li u nhn gi tr 0.
Trong mch hnh 2.23(b) ta cn s dng cc cng AND 4 ng vo trong c 3 ng vo
la chn d liu tch cc cng. Chng ta cng c th s dng cng AND 2 ng vo nh
trong hnh 2.24(a), mt ng vo d liu v mt ng vo la chn c iu khin t ng ra
ca b gii m 3 sang 8. Ti mi thi im ch c mt trong 8 ng ra b gii m trng
thi tch cc cc ng ra cn li u mc thp.
Trong nhng b ghp knh ln hn ta c th c xt dng t cc b ghp knh nh hn.
V d b ghp knh 8 thnh 1 c th c xt dng bng 7 b ghp knh 2 thnh 1 nh
trong hnh 2.24(b), 4 b ghp knh 2 thnh 1 trn cng cung cp 8 ng vo d liu, v
chng c iu khin bi mt ng la chn duy nht l s 0 . cp ny n s la
chn mt t mi nhm hai ng vo d liu. Nhm cc b ghp knh gia cng lm nhim
v tng t nh 4 b ghp knh trn v c iu khin bi ng s1 . Cui cng l b
ghp knh di cng s dng ng iu khin l s 2 la chn mt trong hai ng ra
ca b ghp knh tng gia.
Ngn ng VHDL cho b ghp knh 4 thnh1 trong mi knh c 8 bit c biu din
di y. Hai cch vit khc nhau ca cng mt b ghp knh cng c th hin: Cch 1:
vit cp behavioral, dng mt cu lnh Process; Cch 2: vit theo cp Dataflow,
dng cu lnh gn tn hiu la chn ng thi.
55
Dng b ghp knh biu din mt hm:

B ghp knh c th c dng biu din mt biu thc Boolean mt cch d dng.
Biu thc c n bin th ta s dng b ghp knh c 2 n ng vo v n ng tn hiu iu
khin la chn, n bin ng vo s c kt ni vi n ng vo la chn ca b ghp knh.
Ty theo gi tr ca bin n m mt ng d liu ng vo s c la chn v gi tr t ng
vo s c da n ng ra. V th chng ta cn phi kt ni 2 n ng d liu d vi
cc gi tr 0 hoc 1. Khi d th i bng 1 tc l ta s vit c mt tch s ca cc bin x, y, z
tng ng vi gi tr ti d th i . hiu r hn v iu ny ta s xt mt v d dng b
ghp knh biu din mt hm sau y:
56
Hnh 2. 25 : Dng b ghp knh 8 thnh 1 biu din hm

F ( x, y, z ) x' yz' xy' z xyz' xyz.
2.9
B m ba trng thi:
B m ba trng thi l b c ba trng thi: 0, 1 v trng thi th ba c biu th bng Z.

Gi tr ca Z c trng cho trng thi tr khng cao. B m ba trng thi c dng kt
ni mt vi dch v trn cng mt bus. Mt bus c mt hay nhiu ng dy truyn tn
hiu. Nu hai hay nhiu dch v c kt ni mt cch trc tip n mt bus m khng s
dng b m ba trng thi, th nhng tn hiu ny s b sai lc trong bus . Trong b m
ba trng thi c s dng chn E (enable) iu khin hot ng ca n. Khi E=0, b m
ba trng thi khng c tch cc v ng ra y trng thi tr khng cao. Khi E=1, b m
c cho php hot ng v ng vo d s a c d liu ca n n ng ra y.
Mt mch ch vi mt cng logic th khng th to ra trng thi tr khng cao c. Do
cung cp trng thi tr khng cao, mch m ba trng thi s dng hai con transistor
CMOS c bit kt ni vi cc cng logic nh trong hnh 2.26(d). Trong chng 5 ta s
gii thiu chi tit hn v h tranistor CMOS ny. Chng ny ta s ch gii thiu h CMOS
mt cch n gin m thi. Transistor pMOS trn dn khi mc 0, tc A=0. Khi n dn
th tn hiu mc cao t ngun Vcc s c a ra y. Transitor nMOS pha di dn khi
B=1, v tn hiu mc thp t t s c a n ng ra y. Khi c hai con transistor ny
u khng dn ng ra y trng thi tr khng cao.
Vic c thm hai con transistor h CMOS ny, chng ta cn phi c mt mch iu
khin chng hot ng lin kt vi nhau to thnh mt b m ba trng thi. Bng chn
tr ca mch iu khin c cho trong hnh 2.26(c).
Khi E=0, c hai con transistor CMOS u tt, y trng thi tr khng cao. Khi E=1 v d=0,
nu chng ta mun y=0 th nMOS dn v pMOS tt, lc ny ng ra y s b ko xung thp;
nu chng ta mun y=1 th nMOS tt v pMOS dn, lc ny ng ra y s b y ln mc cao
do y c ni ln ngun. Mch c hai ng vo E v d nn bng chn tr s c 4 cp gi tr
l 00, 01, 10, 11. Da vo cc gi tr ny cng thm cch gii thch v hot ng ca cc
con transistor CMOS ta c th hon thnh bng chn tr nh hnh 2.26(c).
57
Hnh 2. 26 : B m ba trng thi (a) bng chn tr; (b) k hiu logic; (c) bng chn tr cho
vic phn chia iu khin cho mch m ba trng thi; (d) s mch.
on m VHDL vit theo cu trc Behavioral cho b m ba trng thi.
2.10
B so snh:
Thng thng so snh hai gi tr vi nhau th ta dng cc thut ng bng, ln hn v

nh hn ni ln kt qu ca php so snh ny. Mt b so snh l mt mch thc hin
nhim v so snh hai s nh phn gm c nhiu bit. so snh mt gi tr l bng hay
khng bng mt gi tr hng s, th mt cng AND c bn cn phi c s dng. V d
so snh mt bin x gm 4 bit vi hng s cho trc l 3, mch in thc hin php so snh
ny s c biu din trong hnh 2.27(a). Ng ra ca cng AND l 1 khi ng vo ca n
bng vi gi tr 3.
Cc cng XOR v XNOR c th c s dng cho vic so snh s khng bng nhau hay s
bng nhau gia hai gi tr mt cch thch hp. Ng ra cng XOR l 1 khi c hai gi tr ng
vo l khc nhau. V th ta c th s dng cng XOR so snh tng cp bit mt ca chui
bit nh phn. Mt b so snh 4 bit khng ngang bng nhau c biu din trong hnh
58
2.27(b). trong hnh 2.27(b), 4 cng XOR c s dng, mi cng XOR s so snh mt cp
bit trong chui bit nh phn gm 4 bit. Ng ra ca cc cng XOR c ni n cng OR c
4 ng vo, v th nu mt trong cc cp bit tng ng ca hai s nh phn m khc nhau, th
kt qu ng ra F s bng 1. Tng t nh vy, mt b so snh bng nhau c th c xy
dng bng cch s dng cng XNOR. Ng ra cng XNOR bng 1 khi c hai ng vo ca
n c cng gi tr.
so snh ln hn v nh hn, chng ta c th xy dng mt bng chn tr v xy dng s
mch t phng php thng thng. V d so snh mt s X gm 4 bit nh hn 5, bng
chn tr, biu thc v s mch c biu din trong hnh 2.27(c).
Hnh 2. 27 : B so snh 4 bit n gin cho (a) X=3; (b) X
Y ; (c) X<5.
xy dng mt b so snh hai s c nhiu bit, ta thng s dng cu trc ca mt mch

lp, tc l s xy dng mt mch so snh tng cp bit tng ng ca hai s sau ta kt
ni cc mch so snh tng cp bit ny li vi nhau to thnh mch so snh nhiu bit.
Mt b so snh mt cp bit gm c hai ng vo bit cn so snh x i v y i v mt ng ra
p i biu din kt qu so snh gia hai cp bit. p i =1 nu hai bit so snh bng nhau, ngc
59
li p i =0 nu hai bit so snh khng bng nhau. Ban u bit p 0 c bt ln 1, vic so snh
c thc hin t b so snh tng cp u tin n b so snh tng cp bit cui cng. Kt qu
cui cng, nu p 4 p3 p 2 p1 p 0 1 th hai s c so snh l bng nhau, cc
trng hp cn li hai s em so snh l khng bng nhau.
Hnh 2. 28 : B so snh lp (a) So snh tng cp bit x i v y i ; (b) 4-bit X=Y.

2.11
B dch v b xoay (shifter / Rotator):
B dch v b xoay c s dng cho vic dch chuyn cc bit trong chui bit nh phn qua
phi hoc tri. S khc nhau gia b dch v b xoay c biu din trong hnh 2.29
Hnh 2. 29 : S hot ng ca b dch v b xoay.

Mt b ghp knh c dng dch chuyn mt bit qua bn tri hoc qua phi ca dng
bit ban u. Kch thc ca b ghp s quyt nh s lng cc loi hot ng c th c
thc thi. V d chng ta c th dng mt b ghp knh 4 thnh 1 thc thi 4 hot ng
60
c bit c din t trong hnh 2.30(a). Hai ng vo la chn s 0 v s1 c s dng la

chn mt trong bn hot ng trong hnh 2.30(a). C 4 bit ng vo, chng ta s cn s dng
4 b ghp knh 4 thnh 1 nh trong hnh 2.30(b). Nhng ng vo ca cc b ghp knh
c kt ni nh th no s ty thuc vo 4 trng thi hot ng trong bng 2.30(a).
Hnh 2. 30 : B dch / b xoay 4 bit: (a) Bng trng thi hot ng;(b) s mch; (c) k
hiu logic.
Trong v d trn, khi s1
s0
0 , chng ta mun a thng bit n ng ra m khng thc
hin vic dch. V d chng ta mun a gi tr ini n ng ra outi . Khi s1
s0
0,
d 0 ca b ghp knh c la chn, do ini c kt ni n d 0 ca b ghp knh mux i
c ng ra l outi . Khi s1
0 v s 0
1 , chng ta mun dch sang tri, ngha l chng ta
mun a gi tr ini ra ng outi 1 . Vi s1
0 v s 0
1 , d 1 ca b ghp knh c la
chn, do ini c kt ni n d 1 ca b ghp knh mux i
c ng ra l outi 1 . Trong s
la chn ny, chng ta cng mun dch bit 0, v th d 1 ca b ghp knh mux 0 c ni
trc tip n 0.
Ngn ng VHDL cho b dch / b xoay 8 bit c vit theo cu trc Behavioral c chc
nng c gii thiu trong hnh 2.30(a).
61
2.12
B nhn
Trong trng hc, chng ta bit cch nhn hai s thp phn vi nhau da trn phng
php dch v cng. Bt k s l s thp phn hay l s nh phn cng u thc hin php
nhn tng t nhau. Trong thc t vic nhn hai s nh phn l d dng hn bi v bn ch
nhn hai gi tr 0 v 1, kt qu php nhn cng l 0 hoc 1. Hnh 2.31(a) biu din cch
nhn hai s 4 bit bng tay, tha s th nht M m3 m2 m1 m0 nhn vi tha s th hai
Q
q3 q 2 q1 q0 cho kt qu l tch P
p 7 p 6 p5 p 4 p3 p 2 p1 p 0 .
Cch nhn hai s nh phn c thc hin hon ton ging vi cch nhn hai s thp phn.
l phng php nhn, dch v cng. Trong b nhn chng ta phi s dng mt thanh ghi
lu tr gi tr trung gian v gi tr cui cng.
Php nhn cho kt qu nhanh hn trong cc mch kt hp c th c xy dng da trn
cng phng php trn. Trong cc mch kt hp cng, cc cng AND c s dng
nhn cc bit cho ra cc kt qu trung gian v cc b cng c dng cng tt c cc
kt qu trung gian ny li vi nhau cho ra kt qu cui cng. Chng ta thy rng vic
AND hai bit th cho cng mt kt qu vi nhn hai bit.
62
Trong hnh 2.31(c) biu din s kt ni ca cc b cng ton phn cng cc kt qu

trung gian v cng kt qu cui cng. Bn b cng trong mi hng c kt ni theo kiu
b cng c nh trng thi d ca bit trc (Ripple Carry Adder). Bit nh cui cng ca b
cng c kt ni thng ra bit c trng s ln nht ca kt qu tch. Khi bt u thc hin
php nhn bit c 0 c set bng 0.
Hnh 2. 31 : Php nhn (a) nhn bng tay; (b) phng php thc hin; (c) s mch.
63
2.13
My trng thi hu hn FSM
S khc nhau chnh gia cc mch kt hp v cc mch tun t l cc mch kt hp ch

ph thuc vo cc ng vo hin ti, trong khi ngoi cc ng vo hin ti, cc mch tun t
cn ty thuc vo cc ng vo trc . Cc ng vo trc c nh trong b nh
trng thi, c to ra t mt hoc nhiu mch flip-flop. Ni dung ca cc mch flip-flop
b nh trng thi ti bt k thi im no tng ng vi trng thi hin ti ca mch. Mch
thay i t mt trng thi n trng thi tip theo khi ni dung ca b nh trng thi thay
i.
Mt mch tun t hot ng tng bc thng qua mt chui cc trng thi. V b nh trng
thi l hu hn, cho nn tng s cc trng thi c kh nng khc nhau cng hu hn. V l
do ny, mt mch tun t cng c xem nh mt my trng thi- hu hn (FSM). D ch
c mt s hu hn cc trng thi khc nhau, FSM c th i n bt k trng thi no khi
cn thit. T , chui cc trng thi m FSM i qua c th di v tn .
b sung b nh trng thi, mt my trng thi- hu hn cha hai phn kt hp: trng
thi logic tip theo v ng ra lgic. Ph thuc vo trng thi hin thi ca my v cc tn
hiu vo, trng thi lgic tip theo quyt nh trng thi tip theo l g bng vic thay i
ni dung ca b nh trng thi. a ra trng thi hin ti v cc ng vo, trng thi lgic
tip theo to ra mt gi tr mi tng ng trng thi tip theo ca my. Bng vic thay
i cc gi tr ng vo flip-flop, mch trng thi tip theo lm cho b nh trng thi thay
i n gi tr mi. Gi tr mi ca trng thi tip theo c ghi vo b nh trng thi ti
cnh tch cc ca xung clock tip theo.
Tc trong cc chui my trng thi- hu hn thng qua cc trng thi c quyt nh
bi xung clock. Ti mi cnh tch cc ca tn hiu xung clock , b nh thanh ghi trng thi
c cho php v gi tr trng thi tip theo c ct gi vo trong cc flip-flop. Yu t
gii hn tc xung clock l trong thi gian m n thc hin tt c cc thao tc d liu
gn ti mt trng thi ring bit. Tt c cc thao tc d liu c gn ti mt trng thi phi
kt thc trong mt chu k xung clock cc kt qu c th c ghi vo trong cc thanh
ghi ti cnh xung clock tch cc tip theo.
Phn kt hp th hai mt FSM l ng ra logic. Ng ra logic to cc tn hiu ng ra cn
thit cho FSM. Cc tn hiu ng ra ty thuc vo trng thi hin ti ca my v c th hoc
khng ph thuc vo cc tn hiu ng vo. D tn hiu ng ra c ph thuc vo ng vo
hay khng vn c 2 kiu ca FSMs. Moore FSM l FSM c ng ra ca my ch ph thuc
vo trng thi hin ti v khng ph thuc vo cc tn hiu vo, trong khi Mealy FSM l
FSM c ng ra ph thuc vo c trng thi hin ti v tn hiu vo.
64
2.13.1 M hnh my trng thi hu hn FSM (Finite-State-Machine):

Hnh 2.32a trnh by tng qut s cho Moore FSM m cc u ra ca n ch ph thuc
vo trng thi hin ti ca n. Hnh 2.32b cho thy tng qut s cho Mealy FSM m
nhng u ra ca n ph thuc vo c trng thi hin thi ca my ln cc u vo na.
Trong c hai hnh, chng ta nhn thy cc u vo m trng thi logic tip theo l nhng tn
hiu vo s cp v trng thi hin ti ca my. Trng thi logic tip theo to cc gi tr kch
thch thay i b nh trng thi. Mt im khc nhau trong hai hnh l i vi Moore
FSM, ng ra lgic ch c trng thi hin thi nh ng vo ca n, trong khi i vi
Mealy FSM, ng ra lgic c c trng thi hin thi v cc tn hiu vo nh cc ng vo ca
n.
Hnh 2. 32 : S mch ca Moore FSM v Mealy FSM.

65
Hnh 2.32a v 2.32b l mt mch mu tng ng ca mt Moore FSM v Mealy FSM. Hai
mch th ng nht ngoi tr ng ra ca chng. i vi Moore FSM, mch ng ra l mt
cng AND 2 ng vo m gi tr ng vo ca n ly t cc ng ra ca hai D flip-flop. Ch
trng thi FSM tng ng vi ni dung ca b nh trng thi, m ni dung l cc flipflop. Ni dung (hay trng thi) ca mt flip-flop tng ng vi gi tr ng ra Q ( hay Q').
T , mch ny ch ph thuc vo trng thi hin ti ca my. i vi Mealy FSM, mch
ng ra l mt cng AND 3 ng vo, m hai ng vo ca n ly t cc flip-flop, ng vo th
ba cng AND ny c ni ti ng vo C s cp. Vi kt ni ph ny, ng ra mch ny ty
thuc vo c hai trng thi hin ti v ng vo.
Vi c hai mch, b nh trng thi gm c hai D flip-flop. Vi hai flip-flop, tng ng vi
bn gi tr khc nhau. T , my trng thi- hu hn ny c th c bt k 1 trong 4 trng
thi khc nhau. Trng thi m FSM ny s i n tip theo ph thuc vo gi tr ti cc ng
vo D flip-flop.
Mi flip-flop trong b nh trng thi yu cu mt mch kt hp to mt gi tr trng thi
tip theo cho cc u vo ca n. V chng ta c 2 D flip-flop, mi ci c 1 ng vo D, bi
vy, trng thi logic tip theo ca mch gm c hai mch kt hp; mt cho u vo D 0 v
mt cho D1. Cc ng vo ti hai mch kt hp ny l Qs, n tng ng cho trng thi hin
ti cc flip-flop v ng vo s cp C. Ch l khng cn thit cho rng ng vo C l mt
ng vo ti tt c cc mch kt hp. Trong mch mu, ch duy nht mch kt hp di
ph thuc vo ng vo C.
Phn tch mch tun t (Analysis of Sequential Circuits):
Thng khi chng ta a ra mt mch tun t v cn bit s hot ng ca n. Phn tch
mch tun t l qu trnh trong ta a ra cho mt mch tun t v ta mun m t chnh
xc s hot ng ca mch ang c.Vic m t ca mt mch tun t c th l trong bng
trng thi tip theo / bng u ra, hay mt s trng thi. Cc bc phn tch ca cc
mch tun t nh sau:
1. Dn xut nhng phng trnh kch thch t mch trng thi logic tip theo.
2. Dn xut ra nhng phng trnh trng thi tip theo bng vic th nhng phng trnh
kch thch vo cc phng trnh c tnh ca flip-flop.
3. Dn xut bng trng thi tip theo- t cc phng trnh trng thi tip theo.
4. Dn xut nhng phng trnh ng ra (nu c) t mch lgic ng ra.
5. Dn xut bng ng ra (nu c) t nhng phng trnh ng ra.
6. V s trng thi t bng trng thi- k tip v bng ng ra.
66
(a)
(b)
Hnh 2. 33 : (a) S khi Moore FSM; (b) S khi Mealy FSM
2.13.2 Phng trnh kch thch (Excitation Equation):
Cc phng trnh kch thch l cc phng trnh ca mch logic trng thi tip theo trong
FSM. V trng thi logic tip theo l mt mch kt hp, bi vy, dn xut ra cc phng
trnh kch thch ch l phn tch mt mch kt hp nh c tho lun cc phn trn.
Mch trng thi tip theo c dn xut ra bi nhng phng trnh "kch thch" flip-flop
bng vic lm cho chng thay i trng thi. Nhng phng trnh ny cung cp nhng tn
hiu ti cc ng vo ca flip-flop, v c biu th nh mt chc nng ca trng thi hin
ti v cc ng vo n FSM. Trng thi hin thi c xc nh bi ni dung hin ti ca
flip-flop, ngha l, tn hiu ng ra ca flip-flop Q ( v Q'). C mt phng trnh cho mi
ng vo ca flip-flop.
Sau y l hai phng trnh kch thch mu cho 2 D flip-flop. Phng trnh u tin cung
cp mch trng thi tip theo cho ng vo ca D flip-flop 1, v phng trnh th 2 cung cp
mch cho ng vo ca D flip-flop 0.
D1 = Q1'Q0
(1)
D0 = Q1'Q0' + CQ1'
(2)
2.13.3 Phng trnh trng thi tip theo (Next-state Equation):
Cc phng trnh trng thi tip theo ch r trng thi tip theo ca cc flip-flop l ph
thuc vo ba th:
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1) Trng thi hin ti ca cc flip-flop.

2) Hnh vi chc nng ca cc flip-flop.
3) Cc ng vo n flip-flop.
Trng thi hin ti ca cc flip-flop ch l ng ra Q ca cc flip-flop.
Nh vy, dn xut ra cc phng trnh trng thi tip theo, chng ta th cc phng
trnh kch thch vo trong cc phng trnh c tnh tng ng ca flip-flop.
Chng hn, phng trnh c tnh cho D flip-flop l:
Qnext = D
Bi vy, thay hai phng trnh kch thch (1) v (2) t mc 2.13.2.1 vo trong phng trnh
c tnh cho D flip-flop s a cho chng ta hai phng trnh trng thi k tip nh sau:
Q1next = D1 = Q1'Q0
(3)
Q0next = D0 = Q1'Q0' + CQ1'
(4)
2.13.4 Bng trng thi tip theo (Next-state Table):
Bng trng thi tip theo n gin l bng chn tr c dn ra t cc phng trnh trng
thi tip theo. N lit k mi s kt hp gia cc gi tr ca trng thi hin ti (Q) v cc
gi tr u vo, cc gi tr trng thi tip theo (Q next) nn l g. Cc gi tr trng thi tip
theo ny c c bng vic th trng thi hin ti v cc gi tr u vo vo trong nhng
phng trnh trng thi tip theo thch hp. Hnh 2.34 cho thy bng trng thi tip theo
mu vi nhng trng thi hin ti Q1Q0 bng 00, 01, 10, v 11, v mt tn hiu ng vo C.
Nhng mc trong bng l cc gi tr trng thi tip theo Q1next , Q0next.
Hnh 2. 34 : Bng trng thi tip theo vi 4 trng thi v tn hiu ng vo C.

Cc gi tr trng thi tip tip theo ny c c t vic th cc gi tr hin ti Q 1Q0 v gi
tr ng vo C vo trong cc phng trnh trng thi tip theo (3) v (4) t mc 2.13.2.2
trn. V d, phn trn cng bn tri ni cho chng ta rng nu trng thi hin thi l 00 v
iu kin ng vo C= 0 l ng khi trng thi tip theo m FSM s i n l 01. V 01
cng l trng thi tip theo t trng thi hin ti 00 v iu kin C= 1 l ng, iu ny c
ngha chuyn tip t trng thi 00 ti 01 khng ph thuc vo ng vo iu kin C , v vy
y l mt s chuyn tip v iu kin. T trng thi 01, c hai chuyn tip c iu kin:
FSM s chuyn n trng thi 10 nu iu kin C=0 l ng, hoc nu C=1 n s chuyn
n trng thi 11. C hai trng thi 10 v 11 chuyn n trng thi 00 v iu kin.
68
Phng trnh ng ra (Output Equation):

Cc phng trnh u ra l cc phng trnh c dn xut ra t ng ra mch lgic kt hp
trong FSM. Ph thuc vo kiu FSM (Moore hay Mealy), cc phng trnh ng ra c th
ch ph thuc trn trng thi hin ti hoc c hai trng thi hin ti v cc ng vo.
Vi mch Moore hnh 2.32a, phng trnh ng ra l :
Y = Q1'Q0
(5)
Vi mch Mealy hnh 2.32b, phng trnh ng ra l
Y = CQ1'Q0
(6)
Mt kiu FSM s c nhiu tn hiu ng ra, v th s c mt phng trnh cho mi tn hiu
ng ra.
Bng ng ra (Output Table):
Ging nh bng trng thi k tip, bng ng ra l bng chn tr c dn ra t cc phng
trnh ng ra.Cc bng ng ra cho Moore v Mealy c cht khc bit. Vi Moore FSM, cc
danh sch bng ng ra cho mi s kt hp ca gi tr hin ti cc gi tr u ra nn l g.
Trong khi vi Mealy FSM, cc danh sch bng ng ra cho mi s kt hp ca trng thi
hin ti v cc gi tr ng vo gi tr cc ng ra l g. Cc gi tr ng ra ny c c bng
vic th trng thi hin ti v cc gi tr ng vo vo trong nhng phng trnh ng ra thch
hp hnh 2.35a v 2.35b cho thy rng bng ng ra mu cho Moore v Mealy c bt
ngun t phng trnh ng ra (5) v (6) tng ng mc 2.13.2.4 trn. Vi Moore FSM,
tn hiu u ra Y ch ph thuc vo gi tr trng thi hin ti Q1Q0. Trong khi , vi Mealy
FSM tn hiu u ra Y th ph thuc vo c trng thi hin ti ln ng vo C.
Hnh 2. 35 : Bng ng ra (a) Moore FSM; (b)Mealy FSM.

S trng thi (State Diagram):
Mt s trng thi l mt th vi cc nt v cc ng nh hng ni ti cc nt. S
trng thi bng th minh ha hot ng ca FSM. C mt nt cho mi trng thi
FSM v cc nt ny c gn nhn vi trng thi m chng i din. Vi mi chuyn trng
thi ca FSM c mt ng nh hng kt ni cho hai nt. ng nh hng bt ngun
t nt tng ng cho trng thi hin ti m FSM chuyn t , v i n nt tng ng cho
trng thi tip theo m FSM chuyn ti. Cc ng c th c hoc khng c cc nhn trn
69
chng. Cc ng c cc chuyn tip v iu kin t trng thi ny sang trng thi khc
s khng c nhn. Trong trng hp ny, ch c mt ng c th bt ngun t nt .
Chuyn tip c iu kin t mt trng thi s c hai ng theo 2 hng. Hai ng t
trng thi ny c gn nhn tng ng vi cc iu kin tn hiu ng vo - mt ng
vi nhn khi m iu kin l ng v ng khc vi nhn khi iu kin l sai.
Hnh 2.36a cho thy mt s trng thi nh vi bn trng thi, 00, 01, 10, v 11, v mt
tn hiu ng vo C. S trng thi ny c bt ngun t bng trng thi tip theo hnh
2.34 v bng u ra hnh 2.35a. C 3 chuyn tip v iu kin 00 ti 01, 10 ti 00, v 11
ti 00, v mt chuyn tip c iu kin t 01 n 10 hay 11. Vi chuyn tip c iu kin
t 01, nu iu kin C=0 l ng, khi chuyn tip t 01 n 10 c thc hin. Cn li,
nu iu kin C=0 l sai, ngha l C=1 l ng, khi chuyn tip t 01 n 11 c thc
hin.
Hnh 2. 36 : S cc trng thi trong mt mch tun t

Tn hiu ng ra Y hnh 2.36a c gn nhn bn trong mi nt biu th rng ng ra ch
ph thuc vo trng thi hin ti. V d, khi FSM trng thi 01, ng ra Y l 1, trong khi,
trng thi 11, Y l 0. T , s trng thi ny l cho Moore FSM.
Trong hnh 2.36b , ng ra Y c gn nhn trn ng i biu th rng ng ra l ph thuc
vo c hai trng thi hin ti v tn hiu vo C. V d , khi FSM trng thi 01, nu FSM
theo ng tri cho C = 0 n trng thi 10, khi n s xut ng ra l 0 cho Y. Tuy
nhin, nu FSM theo ng bn phi cho C = 1 n trng thi 11, khi n s xut ng
ra l 1 cho Y. Do y l s trng thi cho Mealy FSM.
2.13.5 V d phn tch 1 Moore FSM:
By gi chng ta s minh ha ton b qu trnh phn tch Moore FSM vi 1 v d.
V d 2.1:
70
Hnh 2.37 cho thy mt mch tun t n gin. Chng ta kt lun rng y l mt Moore
kiu FSM v ng ra lgic gm 1 cng AND 2 ng vo m cng ch ph thuc vo trng thi
hin ti Q1Q0. Chng ta s theo su bc trn phn tch chi tit ca mch ny.
Hnh 2. 37 : Moore FSM n gin

Bc 1 l ch ra phng trnh kch thch l cc phng trnh cho mch trng thi logic tip
theo. Nhng phng trnh ny th ty thuc vo trng thi hin thi ca cc flip-flop Q1 v
Q0, v ng vo C. Mt phng trnh cn cho mi ng vo d liu ca tt c cc flip-flop
trong b nh trng thi. Mch mu ca chng ta c hai flip-flop vi hai u vo D1, v D0,
v th chng ta c hai phng trnh kch
Hai phng trnh ny c c t vic phn tch hai mch kt hp m cung cp cc ng vo

D1 v D0 ti hai flip-flop. Cho v d c bit ny, c hai mch kt hp ny ch n gin l
mch to tng hai mc.
Bc 2 s dn xut ra phng trnh trng thi tip theo. Cc phng trnh ny ni chng ta
bit trng thi tip theo s l trng thi hin ti no ca b nh trng thi, hnh vi chc
nng ca flip-flop v cc ng vo n flip-flop. Mt phng trnh cho mi flip-flop. Hnh
vi chc nng ca flip-flop c m t bng phng trnh c tnh ca n, m ca D flipflop l Qnext= D. Cc u vo ti flip-flop ch l cc phng trnh kch thch c dn xut
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ra t bc 1. T y, chng ta thay phng trnh kch thch vo trong phng trnh c tnh
cho mi flip-flop thu c phng trnh trng thi tip theo cho flip-flop . Vi hai
flip-flop trong v d, chng ta c hai phng trnh trng thi-tip theo, mt cho Q1next v
mt cho Q0next.
Bc 3 s dn xut ra bng trng thi tip theo. Cc gi tr trng thi tip theo trong bng
c c bng vic thay mi kt hp ca trng thi hin ti v nhng gi tr u vo trong
cc phng trnh trng thi tip theo thu c trong bc 2. Trong v d ca chng ta, c
hai flip-flop, Q1 v Q0, v ng vo C. T bng s c tm phn trng thi tip theo. C
hai bt cho cc phn bit u tin cho Q1next, v bit th 2 cho Q0next . Bng trng thi tip
theo
V d tm Q1next cho trng thi hin ti Q1Q0 = 00 v C = 1 (mc mu xanh) , chng ta

thay gi tr Q1=0 ,Q0=0 v C=1 vo trong phng trnh
Q1next= C'Q1 + Q1Q0' +CQ1'Q0 =(1' 0)+(0 0' )+(1 0' 0) c gi tr 0.
Tng t , chng ta c Q0next bng cch thay cng gi tr Q0, Q1, v C vo trong phng
trnh Q0next =C'Q0+CQ0'=(1' 0)+(1 0' ) c gi tr 1.
Bc 4 s dn xut ra phng trnh ng ra t mch lgic ng ra. Mt phng trnh ng ra
cn cho mi tn hiu ng ra. V d chng ta, c ch c mt tn hiu u ra Y ch ph thuc
vo trng thi hin ti ca my. Phng trnh u ra cho Y l
Bc 5 dn xut bng ng ra. Ging nh bng trng thi tip theo, bng u ra c c
bng vic thay tt c cc kt hp c kh nng ca cc gi tr trng thi hin ti vo trong
phng trnh ng ra cho Moore FSM. Bng ng ra cho v d Moore FSM l
72
Bc 6 s v s trng thi, c dn xut t bng trng thi tip theo v bng ng ra.
Mi trng thi trong bng trng thi tip theo s c mt nt tng ng c nhn vi trng
thi lp m trong s trng thi. Mi phn trng thi tip theo trong bng trng thi tip
theo, s tng ng vi mt hng i. Hng i ny bt ngun t nt c gn nhn vi
trng thi hin ti v cc kt thc ti nt c gn nhn vi phn trng thi tip theo.
Hng c nhn vi nhng iu kin u vo tng ng.
V d, trong bng trng thi tip theo, khi trng thi hin ti Q 1Q0 l 00 trng thi tip theo
Q1next Q0next l 01 vi ng vo C=1. T , trong s trng thi, c mt hng i t nt 00
ti nt 01 vi nhn C=1. i vi Moore FSM, cc ng ra ch ph thuc vo trng thi hin
ti, nh vy cc gi tr ng ra t bng ng ra c nm bn trong mi nt ca s trng
thi. S trng thi y cho v d ca chng ta c ch hnh 2.38.
Hnh 2. 38 : S trng thi y ca mch Moore FSM.
S tnh ton thi gian mu cho s thc hin ca mch.
73
Hai D flip-flop c dng trong mch kch cnh dng flip-flop v th chng thay i
trng thi ca chng ti mi cnh ln xung clock. u tin, chng ta gi thit rng hai flipflop ny trng thi 0. Cnh ln u tin thi gian t 0. Bnh thng, flip-flop s thay i
trng thi vo thi gian ny, tuy nhin, mt khi C=0 gi tr cc flip-flop vn khng i.
Vo thi gian t 1, C thay i C=1, ti cnh ln xung clock tip theo vo thi gian t 2, cc
gi tr flip-flop Q1Q0 thay i ti 01. thi gian t 4 khi Q1Q0=11, u ra Y cng thay i
n 1 v Y=Q1*Q0. Vo thi gian t 5, ng vo C ri xung 0 nhng ng ra Y vn l 1. Q1Q0
vn l 11 cho d c cnh ln xung clock tip theo v C=0. Vo thi gian t 6, C thay i thnh
1 v v th ti cnh ln xung clock tip theo vo thi gian t 7, Q1Q0 tng dn ln na ti 00
v chu trnh lp li.
Khi C=1, chu trnh FSM thng qua bn trng thi lp li. Khi C=0, FSM dng li ti
trng thi hin ti cho n khi C c tch cc li. Nu chng ta gii thch 4 trng thi m
ha nh 1 s thp phn, th chng ta c th kt lun rng mch hnh 2.37 l mt b m
ln modulo-4 m chu trnh thng qua 4 gi tr 0, 1, 2, v 3. Ng vo C cho php hoc khng
cho php m.
M VHDL theo hnh vi ca Moore FSM trong v d 2.1 nh sau v gin thi gian
hnh 2.39.
LIBRARY IEEE;
ENTITY MooreFSM IS PORT (
clock: IN STD_LOGIC;
reset: IN STD_LOGIC;
C: IN STD_LOGIC;
Y: OUT STD_LOGIC);
END MooreFSM;
ARCHITECTURE Behavioral OF MooreFSM IS
TYPE state_type IS (s0, s1, s2, s3);
74
SIGNAL state: state_type;

BEGIN
next_state_logic: PROCESS (clock)
BEGIN
IF (reset = '1') THEN
state <= s0;
ELSIF (clock'EVENT AND clock = '1') THEN
CASE state is
WHEN s0 =>
IF C = '1' THEN
state <= s1;
ELSE
state <= s0;
END IF;
WHEN s1 =>
IF C = '1' THEN
state <= s2;
ELSE
state <= s1;
END IF;
WHEN s2=>
IF C = '1' THEN
state <= s3;
ELSE
state <= s2;
END IF;
WHEN s3=>
IF C = '1' THEN
state <= s0;
ELSE
state <= s3;
END IF;
END CASE;
END IF;
END PROCESS;
output_logic: PROCESS (state)
BEGIN
CASE state IS
WHEN s0 =>
75
y <= '0';
WHEN s1 =>
y <= '0';
WHEN s2 =>
y <= '0';
WHEN s3 =>
y <= '1';
END CASE;
END PROCESS;
END Behavioral;
Hnh 2. 39 : Gin thi gian ca Moore FSM m phng bng xilinx.

2.13.6 V d phn tch Mealy FSM:
V d 2.2: Minh ha qu trnh thc hin mt s phn tch trn mt Mealy FSM
Hnh 2.40 cho thy mt Mealy FSM n gin. Mch ny cng ging nh mch trong hnh
2.37 ngoi tr mch ng ra, m trong v d ny l mt cng AND 3-ng vo, n khng ch
ph thuc vo ng vo hin ti Q1Q0 m cn ph thuc vo ng vo C.
Hnh 2. 40 : Mealy FSM n gin.
76
Phn tch mch ny cng ging nh phn tch Moore FSM trong v d 2.1 trn to bng
trng thi tip theo trong bc 3. Ch khc l dn xut phng trnh ng ra v bng ng ra
trong bc 4 v 5. i vi Mealy FSM, phng trnh ng ra th ty thuc vo c trng thi
hin ti v trng thi ng vo. V mch ch c 1 tn hiu ng ra, chng ta c phng trnh
ng ra ph thuc vo C nh sau.
Hnh 2.41 ch bng kt qu ng ra c c bng cch thay tt c cc gi tr c th c ca
Q0, Q1, C vo phng trnh ng ra:
Hnh 2. 41 : Bng chn tr ng ra.

Vi s trng thi, chng ta khng th t gi tr ng ra vo bn trong mt nt k v gi
tr ng ra ty thuc vo trng thi hin ti v gi tr ng vo. Do , gi tr ng ra c t
ln hng i tng ng ti gi tr trng thi hin ti v gi tr ng vo nh hnh 2.42 . Tn
hiu ng ra Y l 0 cho tt c cc hng ngoi tr tn hiu bt ngun t trng thi 11 c ng
vo iu kin C=1. Trn mt hng Y l 1.
Hnh 2. 42 : Trng thi y ca Mealy FSM.

Mt s tnh ton thi gian mu c a vo hnh 2.43 cho Moore FSM t thi gian t 5.
Vo thi gian t 5, ng vo C xung 0, v v vy ng ra Y cng xung 0 v Y=C*Q1*Q0.
Vo thi gian t 6, C tng ln 1, v do Y cng ln 1 ngay lp tc. V ng ra mch l mt
mch kt hp, Y khng thay i ti cnh tch cc ca xung clock, nhng thay i ngay lp
tc khi cc ng vo thay i. thi gian t 7 khi Q1Q0 thay i ti 00, Y li thay i v 0.
77
Hnh 2. 43 : Tnh ton thi gian mu cho Mealy FSM

Ngoi tr s khc nhau trong mch ny l to tn hiu ng ra Y nh th no, Mealy FSM
chy ging nh FSM Moore t v d 2.1 theo cch n thay i t mt trng thi ti trng
thi tip theo. iu ny l tt nhin, v thc t l c 2 bng trng thi tip theo ng nht.
Nh vy, mch Mealy FSM cng l mt b m ln modulo 4.
M VHDL theo hnh vi ca Mealy FSM trong v d 2.2 nh sau v gin thi gian hnh
2.44.
LIBRARY IEEE;
ENTITY MealyFSM IS PORT (
clock: IN STD_LOGIC;
reset: IN STD_LOGIC;
C: IN STD_LOGIC;
Y: OUT STD_LOGIC);
END MealyFSM;
ARCHITECTURE Behavioral OF MealyFSM IS
TYPE state_type IS (s0, s1, s2, s3);
SIGNAL state: state_type;
BEGIN
next_state_logic: PROCESS (clock)
BEGIN
IF (reset = '1') THEN
state <= s0;
ELSIF (clock'EVENT AND clock = '1') THEN
CASE state is
WHEN s0 =>
IF C = '1' THEN
state <= s1;
ELSE
78
state <= s0;

END IF;
WHEN s1 =>
IF C = '1' THEN
state <= s2;
ELSE
state <= s1;
END IF;
WHEN s2=>
IF C = '1' THEN
state <= s3;
ELSE
state <= s2;
END IF;
WHEN s3=>
IF C = '1' THEN
state <= s0;
ELSE
state <= s3;
END IF;
END CASE;
END IF;
END PROCESS;
output_logic: PROCESS (state, C)
BEGIN
CASE state IS
WHEN s0 =>
y <= '0';
WHEN s1 =>
y <= '0';
WHEN s2 =>
y <= '0';
WHEN s3 =>
IF (C = '1') THEN
y <= '1';
ELSE
y <= '0';
END IF;
END CASE;
79
END PROCESS;
END Behavioral;
Hnh 2. 44 : Gin thi gian ca Mealy FSM c m phng bng xilinx.

2.14
Cc linh kin tun t:
Trong h thng my tnh chng ta thng mun nhiu bit thng tin. Hn na chng ta
mun nhm 1 vi bit li vi nhau v xem chng nh 1 thnh phn, v d nh s nguyn
c thnh lp t 8 bit. Trong chng ny chng ta s xem xt cc thanh ghi v mch nh
lu tr nhiu bit thng tin.Cc thanh ghi c nhiu chc nng hn bng cch thm vo
cc chc nng m v dch bit. Chng ta s xem xt 1 vi b m v thanh ghi dch .
2.14.1 Cc thanh ghi (Registers):
Khi chng ta mun lu tr 1 byte d liu chng ta phi kt hp 8 flip-flop li vi nhau v
chng lm vic nh 1 thnh phn. Mt thanh ghi ch l mt mch vi 2 hay nhiu D flipflop kt hp li vi nhau bng cch ny tt c chng cng lm vic chnh xc vi nhau v
ng b vi 1 xung clock. Ch c 1 khc bit l mi flip-flop trong nhm c dng lu
tr 1 bit khc nhau ca d liu.
Hnh 2.45 ch ra 1 thanh ghi 4 bit vi mc xa khng ng b. Bn flip-flop D tch cc
mc thp v dng mc xa khng ng b. Ch trong mch cc ng vo iu khin Clk ,
WE, v Clear c ni chung sao cho khi ng vo ring bit c tch cc, th tt c cc
flip-flop s chy chnh xc vi nhau. 4 Bit d liu ng vo c kt ni t d 0 n d3, trong
khi 4 bit q0 n q3 xem nh 4 bit ng ra ca thanh ghi. Khi chn cho php ghi WE(write
enable) tch cc mc thp c tch cc. V d WE=0, d liu tng ng trn chn d
c lu tr vo thanh ghi (4 flip-flop) khi c cnh xung ca xung clock tip theo. Khi
WE khng tch cc, ni dung trong thanh ghi vn khng i. Thanh ghi c th c xa
khng ng b bng cch tch cc chn Clear. Ni dung ca thanh ghi lun c trn cc
chn q, v vy khng cn chn iu khin c d liu t thanh ghi.
80
Hnh 2. 45 : Thanh ghi 4 bit vi mc xa khng ng b.

Hnh 2.46 ch ra k hiu logic ca thanh ghi. Chn vi s 4 trn tn hiu d v q cho bit n
c rng 4 bit v vy gi l thanh ghi 4 bit.
Hnh 2. 46 : K hiu logic ca thanh ghi.

on m VHDL cho thanh ghi 4 bit. Ch m ny cng ging cho D flip-flop n. im
khc bit chnh l d liu ng vo v ra l 4 bit.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY reg4 IS
PORT (
Clock, Clear, WE : IN STD_LOGIC;
d : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END reg4;
ARCHITECTURE Behavior OF reg4 IS
BEGIN
PROCESS(Clock, Clear)
BEGIN
IF Clear = '0' THEN
q <= (others => '0'); -- same as 0000
ELSIF Clock'EVENT AND Clock = '1' THEN
IF WE = '0' THEN
81
q<=d;
END IF;
END IF;
END PROCESS;
END Behavior;
Tn hiu m phng cho thanh ghi ch hnh 2.47. Ch trong gin sng khi WE tch
cc 200ns, ng ra q khng i tc khc khi ng vo c gi tr 5. S thay i xut hin
cnh ln tip theo ca xung clock ti 300ns. Mt khc khi Clear tch cc ti 600ns, q c
reset xung 0 ngay.
Hnh 2. 47 : Gin m phng cho thanh ghi 4 bit.

2.14.2 Thanh ghi tp tin (Register Files):
Khi ta mun lu tr vi s ng thi, ta c th dng vi thanh ghi ring trong mch. Tuy
nhin c khi bn mun x l nhng thanh ghi ny nh mt thnh phn, tng t nh xc
nh cc v tr ring l ca mt mng. Do thay v c 1 vi thanh ghi ta mun c 1 mng
thanh ghi. Mng cc thanh ghi ny c xem nh thanh ghi tp tin. Trong mt thanh ghi
tp tin, tt c cc tn hiu iu khin tng ng u c ni chung. Hn na, tt c d liu
u vo v ra tng ng cho tt c cc thanh ghi cng c ni chung. Ni cch khc, v
d tt c cc chn d3 ca tt c cc thanh ghi c ni chung. V th thanh ghi tp tin ch
c 1 cch set ng vo v ng ra cho tt c cc thanh ghi. ch r thanh ghi no trong
thanh ghi tp tin m bn mun c/ghi, t u/n u, th thanh ghi tp tin c cc ng
i ch cho mc ch ny.
Trong mt mch vi x l cn c mt ALU, thanh ghi tp tin th thng c dng cho
nhng ton hng ngun ca ALU. Khi ALU c hai ton hng ng vo, chng ta mun
thanh ghi tp tin c hai gi tr ng ra t hai v tr khc nhau ca thanh ghi tp tin. V th mt
thanh ghi tp tin thng c mt Port ghi v hai Port c. Tt c 3 Port s c cc chn a
ch v chn cho php ring. Port c c trng thi tr khng cao khi chn cho php c
khng c tch cc. Trong chu k hot ng, d liu trn Port c c gi tr lp tc sau
khi chn cho php c c tch cc, trong khi Port ghi xut hin mc tch cc cnh ln
tip theo ca xung clock.
82
Mch thanh ghi hnh 2.45 khng c chn iu khin cho vic c d liu ng ra. iu
khin khi ta mun d liu ng ra v t chn ng ra trng thi tr khng cao, chng ta
cn thm vo b m 3 trng thi mi ng ra. Tt c cc chn cho php ca b m 3
trng thi c kt ni chung khi chng ta mun iu khin tt c ng ra cng lc. Hn na
chng ta cn c 2 Port c. V d, 2 ng ra iu khin ca mi thanh ghi v th ta c th kt
ni 2 b m 3 trng thi n mi ng ra. Mch thanh ghi c sa i nh hnh 2.48.
Hnh 2. 48 : Mch thanh ghi c thm chn iu khin.

AE v BE l cc chn cho php c tn hiu tng ng ca Port A v Port B. Mi 1 Port
kt ni n cc chn cho php ca 4 b m 3 trng thi khi set. Tt c chng u tch cc
mc thp. PA v PB l 2 Port c 4 bit. chn thanh ghi m bn mun lm vic bn dng
b gii m gii m a ch. Ng ra ca b gii m c dng tch cc chn cho php
c/ghi. Mch hon chnh ca 1 thanh ghi 4x4 (4 thanh ghi mi thanh ghi c rng l 4
bit ) c ch ra hnh 2.49.
Hnh 2. 49 : Mch hon chnh ca thanh ghi 4x4.

on m VHDL cho thanh ghi 4x4 vi 1 Port ghi 2 Port c:
83
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all; -- needed for CONV_INTEGER()
ENTITY regfile IS PORT (
clk: in STD_LOGIC; --clock
WE: in STD_LOGIC; --write enable
WA: in STD_LOGIC_VECTOR(1 DOWNTO 0); --write address
D: in STD_LOGIC_VECTOR(7 DOWNTO 0); --input
RAE, RBE: in STD_LOGIC; --read enable PORTsA&B
RAA, RBA: in STD_LOGIC_VECTOR(1 DOWNTO 0); --read address PORTA&B
A, B: out STD_LOGIC_VECTOR(7 DOWNTO 0)); --output PORTA&B
END regfile;
ARCHITECTURE Behavioral OF regfile IS
SUBTYPE reg IS STD_LOGIC_VECTOR(7 DOWNTO 0);
TYPE regArray IS ARRAY(0 to 3) OF reg;
SIGNAL RF: regArray; --register file contents
BEGIN
WritePort: PROCESS (clk)
BEGIN
IF (clk'EVENT AND clk = '1') then
IF (WE = '0') then
RF(CONV_INTEGER(WA)) <= D; --fn to convert from bit VECTOR to
integer
END IF;
END IF;
END PROCESS;
ReadPortA: PROCESS (RAA, RAE)
BEGIN
-- Read Port A
IF (RAE = '0') then
A <= RF(CONV_INTEGER(RAA)); --fn to convert from bit VECTOR to integer
ELSE
A <= (others => 'Z');
END IF;
END PROCESS;
ReadPortB: PROCESS (RBE, RBA)
84
BEGIN
-- Read Port B
IF (RBE = '0') then
B <= RF(CONV_INTEGER(RBA)); --fn to convert from bit VECTOR to integer
ELSE
B <= (others => 'Z');
END IF;
END PROCESS;
END Behavioral;
Hnh 2.50 cho thy tn hiu m phng cho ghi 4x4 vi 1 Port ghi , 2 Port c
Hnh 2. 50 : Tn hiu m phng cho ghi 4x4 vi 1 Port ghi, 2 Port c.

2.14.3 B nh truy xut ngu nhin (Random Access Memory):
Mt thnh phn quan trng khc ca h thng my tnh l b nh. Phn ny c th xem
nh l RAM hoc ROM. Ta lm b nh cng ging nh lm thanh ghi tp tin nhng vi
nhiu a ch hn. Tuy nhin c nhiu l do ta khng th lm nh vy. Mt l do l
chng ta mun c b nh ln v r tin .V th chng ta phi lm mi nh nh n kh
nng c th c. Mt l do khc l chng ta mun dng chung ng Bus data cho c vic
c v ghi d liu t u/n u ca b nh. iu ny cho thy rng mch nh ch cn c
1 Port d liu m khng cn phi 2 hay 3 nh thanh ghi tp tin. K hiu Logic ch tt c cc
kt ni ca chip RAM thng thng ch hnh 2.51. C cc ng d liu D v cc ng
a ch A.
ng d liu cho c ng vo v ng ra ca d liu v tr t u n u c ch r
bng cc ng a ch. S lng ng d liu ty thuc vo c bao nhiu bit c dng
lu tr d liu trong mi v tr nh. S lng ng a ch ty thuc vo c bao nhiu
v tr trn chip. V d 1 chip c 512 byte b nh s c 8 ng d liu (8 bit =1 byte) v 9
85
ng a ch (29 = 512). c th thm cc ng d liu v a ch, ta thng dng 3

chn iu khin l: chip enable (CE), write enable (WR), v xung clock. C CE v WE
c tch cc mc thp.
Hnh 2. 51 : K hiu logic ca chip RAM.

Mi bit trong RAM c lu tr trong 1 nh ging mch hnh 2.52. Phn t nh chnh
trong nh l b cht D c chn cho php. B m 3 trng thi c ni ng ra ca b
cht D n c th la chn c t u. Tn hiu cho php c dng cho php nh
c c v ghi. c, tn hiu cho php c dng cho php b m 3 trng thi.
ghi, tn hiu cho php cng vi tn hiu cho php ghi c dng cho php b cht
d liu ng vo c cht trong .
Hnh 2. 52 : Mch nh bit trong RAM.

to 1 chip RAM 4x4, chng ta cn 16 nh dng li 4x4 nh hnh 2.53. Mi hng l 1
v tr lu tr ring v s nh trong mi hng quyt nh rng bit mi v tr. V vy tt
c nh trong hng c cng a ch. 1 B gii m c dng gii m cc a ch. Trong
v d ny l b gii m 2-4 gii m 4 v tr a ch. Tn hiu CE cho php chip, c bit
cho php chc nng c v ghi thng qua 2 cng AND. Tn hiu WE ni c tch cc
(khi c 2 tn hiu CE v WR c tch cc) dng xc nh cho php ghi ca tt c cc
nh. D liu i t bus data bn ngoi qua ng vo b m v n ng vo ca mi nh.
86
Mc ch ca vic dng 1 b m ng vo cho mi ng d liu l ch cn tn hiu bn

ngoi vo iu khin ng 1 linh kin (b m) hn l vi linh kin (V d tt c cc
nh trong cng ct). Ty thuc vo a ch c a ra m hng no ca cc nh s c
ghi. Hot ng c yu cu chn CE c tch cc v chn WR khng c tch cc.
iu ny s tch cc tn hiu RE ni, n s cho php ln lt 4 ng ra ca b m 3 trng
thi cui s mch. Nhc l, v tr c c s c chn bng a ch.
Hnh 2. 53 : S cc nh dng li trong chip RAM 4x4.

M VHDL cho chip RAM 16 x 4:
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_arith.ALL;
USE ieee.STD_LOGIC_unsigned.ALL; -- needed for CONV_INTEGER()
ENTITY memory IS PORT (CE, WR: IN STD_LOGIC; --chip enable, write enable
A: IN STD_LOGIC_VECTOR(3 DOWNTO 0); --address
D: BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0) ); --data
END memory;
87
ARCHITECTURE Behavioral OF memory IS

BEGIN
PROCESS (CE, WR)
SUBTYPE cell IS STD_LOGIC_VECTOR(3 DOWNTO 0);
TYPE memArray IS array(0 TO 15) OF cell;
VARIABLE mem: memArray; --memory contents
VARIABLE ctrl: STD_LOGIC_VECTOR(1 DOWNTO 0);
BEGIN
ctrl := CE & Wr; --group signals for CASE decoding
CASE ctrl IS
WHEN "10" =>
-- read
D <= mem(CONV_INTEGER(A));
-- fn TO convert from bit vecTOr TO integer
WHEN "11" =>
-- write
mem(CONV_INTEGER(A)) := D;
-- fn TO convert from bit vecTOr TO integer
WHEN OTHERS =>
-- invalid or not enable
D <= (OTHERS => 'Z');
END CASE;
END PROCESS;
END Behavioral;
2.15
B m (Counters):
Cc b m, nh tn gi, dng m mt chui nhng gi tr. Tuy nhin, c nhiu loi b

m khc nhau ph thuc vo tng s ca cc gi tr m, chui nhng gi tr ng ra , hoc
l m ln hoc m xung. n gin nht l b m modulo n l m dy thp phn 0,
1, 2, ln ti n -1, v sau tr v 0. Mt vi b m tiu biu c m t pha di.
B m Modulo-n: m t s thp phn 0 n n-1v tr v 0. V d, b m Modulo 5 m
thp phn 0,1,2,3,4. B m BCD: ging b m Modulo-n ngoi tr n c nh l 10.
B m n-bit nh phn: ging nh b m Moulo-n nhng phm vi t 0 n 2n-1 v tr v
0 vi n l s bit dng trong b m. V d m 3-bit nh phn tun t trong thp phn l
0,1,2,3,4,5,6,7.
B m m Gray: Chui m ha bt k hai gi tr lin tip phi khc nhau ch 1 bit. V
d 1 b m m Gray 3 bit m ln lt trong nh phn l 000, 001, 011, 010, 110, 111,
101, 100.
88
B m vng: bt u ln lt vi chui bit 0 theo sau l bit 1. B m ch n gin l dch

cc bit qua tri ca mi ln m. V d, b m vng 4 bit tun t trong nh phn l 0001,
0010, 0100, 1000.
2.15.1 B m ln nh phn (Binary Up Counter):
Mt B m nh phn c th c xy dng bng cch sa i li thanh ghi n bit ti d liu
ng vo ca thanh ghi n t b cng cho b m ln v mch tr cho b m xung.
bt u vi 1 gi tr c lu tr trong thanh ghi, tip tc m ln, n gin ta phi thm 1
bit vo n.Ta c th dng b cng ton phn c ni mc 2.3.1 nh ng vo cho thanh
ghi, nhng chng ta c th lm tt hn. B cng ton phn c 2 ton hng cng vi s nh.
Nhng ci m ta mun ch l cng thm mt, v vy ton hng th hai ca b cng ton
phn lun lun l mt. V cng c th cng tn hiu nh ca b cng, v vy, ta tht s
khng cn ng vo cho ton hng th hai. B cng c sa i ny ch cng mt ton
hng vi s nh c gi l b cng bn phn (HA).
Bng chn tr ch hnh 2.54, ta ch c 1 ton hng ng vo l a, cin tng ng vi s nh
ng vo v cout tng ng vi s nh ng ra cn s l tng ca php cng. trong bng chn
tr ta ch n gin cng a vi s nh cin a ra tng s v c th c s nh ng ra cout. T
bng chn tr, ta thu c 2 phng trnh v mch tng ng nh hnh 2.54 v k hiu
logic trong hnh 2.54.
(a)
(b)
(c)
Hnh 2. 54 : B m ln nh phn (a) Bng chn tr; (b) S mch; (c) K hiu logic.
Cc b cng bn phn c th kt hp vng thnh b cng ton phn cng n-bit. Mi ng
vo ton hng n t thanh ghi. Tn hiu nh ng vo c0 ban u dng cho php tn hiu
m (count) v bit 1 trn c0 s dn ti tng mt gi tr trong thanh ghi v 0 s khng c.
Mt mch m ln 4-bit c ch nh hnh 2.55 vi bng chn tr v k hiu logic. Khi
count c tch cc, b m s tng gi tr mi xung clock cho n khi count khng c
tch cc. Khi count t n 2n-1, tng ng vi s nh phn c tt c 1, ln m tip
89
theo s tr li quay tr li 0 v vic thm 1 bit vo mt s nh phn c tt c cc bit l 1

s dn n 1 bit trn v tt c cc bit c reset v 0. Chn Clear cho php reset b m
khng ng b v 0.
Hnh 2. 55 : B m ln 4 bit S mch; bng chn tr; k hiu logic.

M VHDL cho b m ln 4 bit:
ENTITY counter IS PORT (
Clock: IN BIT;
Clear: IN BIT;
Count: IN BIT;
Q : OUT INTEGER RANGE 0 TO 15);
END counter;
ARCHITECTURE Behavioral OF counter IS
BEGIN
PROCESS (Clock, Clear)
90
VARIABLE value: INTEGER RANGE 0 TO 15;

BEGIN
IF Clear = '1' THEN
value := 0;
ELSIF (Clock'EVENT AND Clock='1') THEN
IF Count = '1' THEN
value := value + 1;
END IF;
END IF;
Q <= value;
END PROCESS;
END Behavioral;
Tn hiu m phng hnh sau
Hnh 2. 56 : Tn hiu m phng cho b m ln 4 bit.

2.15.2 B m ln xung nh phn (Binary Up-Down Counter):
Chng ta c th thit k b m ln xung n-bit ging nh b m ln ngoi tr vic cn c
b cng v tr cho d liu ng vo thanh ghi. Bng chn tr, mch, k hiu logic ca b
cng v tr bn phn (HAS) hnh 2.57a, hnh 2.57b, hnh 2.57c. Tn hiu D la chn
m ln hoc xung. Khi D=1 s m xung. Na trn ca bng chn tr l HA, na di l
php tr ca a-cin, s l s kt qu ca php tr v c out =1 nu chng ta cn mn. V d 0-1,
ta cn mn nn cout =1. Khi ta c a=2 v 2-1=1 nn s=a=1. Kt qu 2 php tnh l:
91
Hnh 2. 57 : B cng ,tr bn phn (a) Bng chn tr; (b) S mch; (c) K hiu logic.
Mt b m ln xung 4 bit hnh 2.58a. Bng chn tr v k hiu logic hnh 2.58b v c.
Hnh 2. 58 : B m ln xung 4 bit: (a) S mch; (b) Bng chn tr; (c) K hiu logic.
M VHDL cho 1 b m ln xung 4 bit nh sau:
ENTITY counter IS PORT (
Clock: IN BIT;
Clear: IN BIT;
Count: IN BIT;
92
Down: IN BIT;
Q: OUT INTEGER RANGE 0 TO 15);
END counter;
ARCHITECTURE Behavioral OF counter IS
BEGIN
PROCESS (Clock, Clear)
VARIABLE value: INTEGER RANGE 0 TO 15;
BEGIN
IF Clear = '1' THEN
value := 0;
ELSIF (Clock'EVENT AND Clock='1') THEN
IF Count = '1' THEN
IF Down = '0' THEN
value := value + 1;
ELSE
value := value - 1;
END IF;
END IF;
END IF;
Q <= value;
END PROCESS;
END Behavioral;
Tn hiu m phng hnh 2.59
Hnh 2. 59 : Tn hiu m phng cho b m ln xung 4 bit.

2.15.3 B m ln xung c song song :
b m nh phn linh hot hn, ta cn bt u chui m vi 1 s bt k ln hn 0.
iu ny d dng c thc hin bng vic sa i mch m cho php n mang mt
gi tr ban u. Vi gi tr np vo trong thanh ghi, by gi chng ta c th m bt u
t gi tr mi ny. Sa i mch m nh hnh 2.60a.
93
Ch c 1 khc bit gia mch ny vi mch hnh 2.58a l tng ca 2 ng vo b ghp knh
chnh l ng ra s ca HAS v ng vo Di ca flip-flop. Bng cch lm ny ng vo ca flipflop c th c chn t gi tr ng vo bn ngoi nu Load c tch cc hoc t gi tr
m tip theo ng ra HAS nu Load khng c tch cc. Nu ng ra HAS c chn
khi mch lm vic chnh xc nh trc y. Nu ng vo bn ngoi c chn, khi
bt k gi tr no trn ng vo d liu cng c c vo thanh ghi. Bng hot ng v k
hiu ca mch hnh 2.60b v 2.60c.
Hnh 2. 60 : (a) S mch m ln xung 4 bit c sa i ; (b) Bng chn tr ; (c) k hiu
logic ca m ln xung 4 bit c sa i.
Chng ta phi gi chn Clear b m c th to gi tr ban u n 0 ti bt k thi im
no. Ch rng c s khc bit thi gian gia vic tch cc chn CLear reset b m v
0 khc vi tch cc chn Load c gi tr 0 v t d liu ng vo l 0. Trong trng
hp u tin, b m c reset v 0 ngay lp tc sau khi chn Clear c tch cc trong
khi trng hp sau s reset b m v 0 cnh ln xung clock tip theo .
94
Vi mch ny, vic m s bt u vi 1 gi tr bt k trong thanh ghi. Tuy nhin khi b

m tin ti gi tr cui ca chui m n s tr v 0 v khng bt u vi gi tr mi ny.
Chng ta c th thm mt mch so snh n gin vo b m ny n quay tr li gi tr
ng vo mi ny hn l 0 nh mc tip theo.
2.15.4
B m ln xung BCD (BCD Up-Down Counter):
Vn ca b m ln xung nh phn vi c song song l khi m n tin v gi tr cui

ca b m, th n lun quay tr v 0. Nu chng ta mun chui m quay tr li chu k
vi gi tr c gn ban u sau mi ln nh vy, ta cn tch cc chn Load, ti bt u ca
mi chu k m v gi tr np ban u s vn cn tn ti trn cc chn ng vo d liu.
to ra mt tn hiu tch cc chn Load, ta cn kim tra gi tr m l tr cui ca chui m.
Nu ng ra l 1 tch cc chn Load. iu ny np tr li gi tr ban u v m tip tc
vi gi tr ban u ny. Mch ny ch l mch so snh vi cc ng vo thit lp t thanh ghi
v cc ng khc l cc hng s m ta dng kim tra. Ng ra ca b so snh s tch cc
chn Load.
B m ln xung BCD m t 0 n 9 cho chui ln v ngc li cho chui xung. Cho
chui ln khi m n 9 chng ta cn tch cc chn Load v c v 0. Cho chui xung
khi m n 0 chng ta cn tch cc chn Load v c v 9. m ln BCD hnh 2.61 a,
m ln-xung BCD hnh 2.61b.
Hnh 2. 61 : B m BCD (a) b m ln; (b) b m xung.

2.16
Thanh ghi dch (Shift registers):
Ging nh mch kt hp gia quay v dch chuyn. l cc thnh phn dch v quay tun
t. Mch thc hin chuyn dch v quay c xy dng cng ging nh vy. S khc
nhau duy nht trong phn tun t l nhng thao tc c thc hin trn gi tr c lu tr
trong mt thanh ghi. Cch dng chnh cho mt thanh ghi dch l chuyn i t mt dng
95
d liu ng vo tun t thnh mt ng ra d liu song song hay ngc li. chuyn d
liu ni tip ra song song, cc bit c chuyn vo trong thanh ghi ti mi chu k xung
clock v khi tt c cc bit (thng 8 bits) c chuyn vo trong thanh ghi, thanh ghi 8-bit
c th c c xut 8 bit ng ra song song. chuyn t song song ra ni tip, trc
tin thanh ghi 8 bit c d liu ng vo, cc bit c dch ra ngoi tng bit mt, mi bit l
1 chu k xung clock.
2.16.1 Thanh ghi dch ni tip ra song song:
Hnh 2.62 ch mt b chuyn i 4 bit ni tip ra song song .Cc bit d liu ng vo c
a vo t ng Serial In. Khi chn Shift c tch cc, cc bit d liu c dch vo
trong. Ti xung Clock u, bit u tin c c vo trong Q3. Ti xung Clock th 2, bit
trong Q3 c c vo Q2 trong khi Q3 c bit tip theo ca dng d liu ng vo ni
tip. C tip tc ht 4 xung clock th 4 bits dc dch vo trong 4 flip-flop .
Hnh 2. 62 : B chuyn i 4 bit ni tip ra song song.

M VHDL theo cu trc cho thanh ghi dch 4-bit vo ni tip ra song song nh sau:
-- D flip-flop with enable
LIBRARY ieee;
USE IEEE.std_logic_1164.all;
ENTITY D_flipflop IS
PORT(D, Clock,E:IN STD_LOGIC;
Q : OUT STD_LOGIC);
END D_flipflop;
ARCHITECTURE Behavior OF D_flipflop IS
BEGIN
PROCESS(Clock)
BEGIN
IF Clock'EVENT AND Clock = '1' THEN
IF E = '1' THEN
Q<=D;
END IF;
END IF;
96
END PROCESS;
END Behavior;
-- 4-bit shift register
LIBRARY ieee;
USE IEEE.std_logic_1164.all;
ENTITY ShiftReg IS
PORT(Serialin, Clock, Shift : IN STD_LOGIC;
Q : OUT STD_LOGIC_VECTOR(3 downto 0));
END ShiftReg;
ARCHITECTURE Structural OF ShiftReg IS
SIGNAL N0, N1, N2, N3 : STD_LOGIC;
COMPONENT D_flipflop PORT (D, Clock,E:IN STD_LOGIC;
Q : OUT STD_LOGIC);
END COMPONENT;
BEGIN
U1: D_flipflop PORT MAP (Serialin, Clock, Shift, N3);
U2: D_flipflop PORT MAP (N3, Clock, Shift, N2);
Q(3) <= N3;
Q(2) <= N2;
Q(1) <= N1;
Q(0) <= N0;
END Structural;
Tn hiu m phng hnh 2.63
Hnh 2. 63 : Tn hiu m phng ca mt b chuyn i 4 bit ni tip ra song song.

2.16.2 Thanh ghi dch ni tip ra song song v song song ra ni tip:
C hot ng chuyn ni tip ra song song v song song ra ni tip, chng ta u lm dch
bit t tri qua phi thng qua thanh ghi. im khc bit gia 2 gii thut l khi bn thc
hin c song song sau khi dch hoc ghi song song trc khi dch. chuyn ni tip ra
song song bn phi c song song sau khi bit c dch vo trong. Cn chuyn song
song ra ni tip, bn phi ghi song song trc v sau dch cc bit ra ngoi nh dng ni
97
tip. Chng ta c th thc hin c hai chc nng vo trong mch ni tip ra song song t
phn trc 1 cch n gin bng vic thm mt chc nng Load song song vo mch nh
trong hnh 2.64a.
Bn b ghp knh lm vic vi nhau chn nhng flip-flop m bn mun gi li gi tr
hin ti, c vo mt gi tr mi hay dch nhng bit qua phi 1 v tr bit. Hot ng ca
mch ny ty thuc vo hai chn la chn SHSel1 V SHSel0, n iu khin ng vo ca
nhng b ghp knh c chn. Bng hot ng v k hiu lgic hnh 2.64b v 2.64c.
Hnh 2. 64 : (a) S mch thanh ghi dch ni tip ra song song v song song ra ni tip;
(b) Bng chn tr ; (c) k hiu logic ca thanh ghi dch ni tip ra song song v song song
ra ni tip.
Tn hiu m phng hnh 2.65:
Hnh 2. 65 : Tn hiu m phng thanh ghi dch ni tip ra song song v song song ra ni
tip.
98
M VHDL m t cho thanh ghi dch ni tip ra song song v song song ra ni tip.
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY shiftreg IS PORT (
Clock: IN STD_LOGIC;
SHSel: IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Serial_in: IN STD_LOGIC;
D: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
Serial_out: OUT STD_LOGIC;
Q: OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END shiftreg;
ARCHITECTURE Behavioral OF shiftreg IS
SIGNAL content: STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
PROCESS(Clock)
BEGIN
IF (Clock'EVENT AND Clock='1') THEN
CASE SHSel IS
WHEN "01" => -- load
content <= D;
WHEN "10" => -- shift right, pad with bit from Serial_in
content <= Serial_in & content(3 DOWNTO 1);
WHEN OTHERS =>
NULL;
END CASE;
END IF;
END PROCESS;
Q <= content;
Serial_out <= content(0);
END Behavioral;
99
Chng 3 : Tm hiu Kit FPGA Spartan 3
CHNG 3 : TM HIU KIT FPGA SPARTAN 3

3.1
Tng quan kit FPGA Spartan 3 :
Mch np Xilinx Spartan-3 Starter Kit Board ( ca hng Xilinx) c cung cp vi gi

r, d s dng pht trin v nh gi mch s. Xilinx Spartan-3 Starter Kit Board l
mt mch FPGA.
Hnh 3. 1 : S khi kit Xilinx FPGA Spartan-3 Starter.

Cc thnh phn ca Kit gm c:
200000 cng logic, tng ng 4320 t bo logic (1).
2 Mbit PROM (2).
100
1 Mbyte SDRAM (4).

Cng mn hnh VGA 3 bit, 8 mu (5).
Cng ni tip RS-232 (6).
Cng PS/2 dng cho chut hoc bn phm (9).
H thng 8 cng tc trt, 4 nt nhn v 4 LED 7 on hin th (11, 13, 10).
Xung clock 50 Mhz dng dao ng thch anh (14).
Khe cm cho xung clock t bn ngoi (15).
H thng cc jumper chn ch lm vic cho cc linh kin trn board (3,
8, 16, 30, 31).
3 cng cm m rng, mi cng 40 chn (19, 20, 21).
Cng JTAG kt ni vi my tnh dng np chng trnh vo kit Spartan 3
v g ri (22).
H thng ngun (25).
Hnh 3. 2: Mch in pha trc kit FPGA Xilinx Spartan-3 Starter.
Hnh 3. 3 : Mch in pha sau kit FPGA Xilinx Spartan-3 Starter.

3.2
SRAM bt ng b :
Kt gm c 2 chip Ram 256K x 16 chia s chung cc ng iu khin cho php ghi

(WE), cho php ng ra (OE) v 18 ng a ch. Chng ta c th s dng 2 SRAM mt
cch ring bit 256Kx16 hay cng c th s dng kt hp 2 SRAM ny li thnh 1 SRAM
256Kx32. Mi SRAM 256Kx16 c iu khin bi mt con chip select ring bit thong qua
chn (CE). Cc chn iu khin cn li nh CS, UB, LB c iu khin ring bit.
101
C hai chip 256Kx16 SRAM cng chia s chung 18 ng iu khin a ch. Nhng
ng a ch ny cng c ni n 18 chn ca phn kt ni m rng A1 ca board
mch. S kt ni cc chn c biu hin r trong hnh 2.5.
Hnh 3. 4 : S kt ni gia chn gia FPGA v 2 SRAM 256Kx16.
102
Hnh 3. 5 : Bng kt ni chn gia FPGA vi 18 ng a ch ca SRAM

Tng t nh cch kt ni trn chn WE v OE cng c ni n phn kt ni m
rng A1.
Hnh 3. 6 : Bng kt ni chn gia FPGA vi chn OE v WE ca

Cc chip select IC10 v IC11 cng c kt ni n cc chn ca FPGA theo s
chn nh sau:
103
Hnh 3. 7 : Bng kt ni chn gia IC10 vi cc chn ca FPGA.
104
Hnh 3. 8 : Bng kt ni chn gia IC11 vi cc chn ca FPGA.

3.3
Led 7 on:
Cc k t c th c hin th bng 4 LED 7 on , c iu khin bng cc chn I/O

ca ngi s dng nh hnh 2.9
Hnh 3. 9 : S b tr cc thanh ca LED 7 on.

Mi s chia s 8 ng tn hiu chung lm sng cc on (segment) LED ring bit .
Mi 1 LED c 1 ng vo iu khin anode ring (tch cc mc thp, t AN3 n AN0).
105
bt 1 on trong LED 7 on sng ln, ta cho tn hiu iu khin ring bit cho on
tng ng xung mc 0 (dp = MSB , a = LSB) .
Hnh 3. 10 : Bng kt ni chn gia LED 7 on vi chn ca FPGA.
Hnh 3. 11 : Bng kt ni tn hiu iu khin hin th 4 LED vi chn ca FPGA.
Hnh 3. 12 : Bng hin th LED 7 on tng ng vi 16 k t t 0 n F.
106
Hnh 3. 13 : Tn hiu m t hin th cc LED 7 on bng phng php qut led.

3.4
Cc cng tc trt (SW), cc nt n (PB) v cc Led :
C 8 cng tc trt c nhn SW7 (bn tri) n SW0 (bn phi).
Hnh 3. 14 : Bng kt ni chn gia cc cng tc trt vi cc chn ca FPGA.

Khi UP hoc ON cng tc kt ni chn FPGA ln V cco , logic cao. Khi DOWN hoc
OFF cng tc kt ni chn FPGA xung GOUND , logic thp. Cng tc in hnh biu
th khong 2 ms cho ny git c kh . Mt in tr 4.7 K ni tip cung cp bo v
u vo.
Cc nt n: BTN3 ngoi cng bn tri , BTN0 ngoi cng bn phi. Khi n nt s
to mc cao chn FPGA.
Hnh 3. 15 : Bng kt ni chn gia cc nt nhn vi cc chn ca FPGA.
Hnh 3. 16 : Bng kt ni chn gia 8 n LED vi cc chn ca FPGA.

3.5
Cng VGA :
Cng hin th mn hnh VGA v connector DB15.

Kt ni cng ny trc tip ti hu ht nhng mn hnh PC hay panel hin th mn hnh
LCD s dng mt cp monitor tiu chun
iu khin 5 tn hiu VGA : Red , Green , Blue, Horizontal Sync, Vertical Sync , tt c
c sn trn connector VGA.
107
Hnh 3. 17 : S chn ca cng VGA
Hnh 3. 18 : Bng kt ni chn gia cc tn hiu ca cng vi cc chn ca FPGA.
Hnh 3. 19 : Bng m ha hin th 3 bit cho 8 mu c bn.
3.6
Cng PS/2 Mouse v Keyboard :
Hnh 3. 20 : S chn ca cng PS/2.

108
Chut v bn phm u s dng 2 dy ca Bus ni tip PS/2 trao i thng tin vi

thit b ch (trong trng hp ny l FPGA Spartan III ).
Bus PS/2 bao gm xung clock v data. C 2 u s dng t 11 bit gm : 1 bit start = 0;
8 bit data (LSB trc tin); 1 bit odd parity; 1 bit stop = 1.
Tuy nhin gi data ca Mouse v keyboard l khc nhau.
3.6.1
Bn phm :
Hnh 3. 21 : M qut bn phm.
Hnh 3. 22 : Cc m iu khin c bit ca bn phm.

3.6.2 Mouse :
Mouse to ra tn hiu data v xung clock khi di chuyn, trng hp cn li cc tn hiu
mc cao cho bit trng thi rnh Idle.
Mi ln Mouse di chuyn n gi 3 t 11 bit n host. Mi t 11 bit cha bit start 0,
tip theo l 8 bit data (u tin l LSB), sau l bit parity l, cui cng l stop bit 1.
109
Data ch c gi tr cnh xung ca xung clock , chu k xung clock t 20 Khz n 30

Khz.
Hnh 3. 23 : Cu trc lung bit qun l cng PS/2.

3.6.3 Ngun cp p:
Hu ht Mouse v Keyboard lm vic vi p 3.3 V hoc 5V. Ngun t cng PS/2 c
chn qua ng JP2.
Hnh 3. 24 : Cch kt ni jumper trn board chn ngun p ty ngi thit k.

3.7
Cng ni tip RS-232 :
RS 232 truyn v nhn tn hiu xut hin trn connector DB9 female, nhn J2. S dng
cp ni tip truyn thng t Kit FPGA n cng ni tip PC.
Hnh 3. 25 : S chn ca cng RS-232.
110
Hnh 3. 26 : S kt ni chn gia cng RS-232 vi cc chn ca FPGA.

3.8
Cc ngun xung clock :
FPGA c th s dng xung clock chnh ca n l 50 Mhz hoc s dng tn s khc ly

t cc b qun xung clock s ( Digital Clock Managers DCMs) ca FPGA.
Hnh 3. 27 : Kt ni chn gia ngun dao ng xung clock vi chn ca FPGA.

3.9
Cch thit lp cc mode hot ng cho FPGA :
Trong hu ht cc ng dng ca Spartan 3, FPGA t ng boot khi c cp ngun

hoc n nt PROG. Khi s dng mode cu hnh Master Serial th phi thit lp JP1
111
Hnh 3. 28 : Bng thit lp cc trng thi hot ng cho FPGA thng qua chn J8.
Hnh 3. 29 : V tr nt n reset chng trnh np cho kit v LED hin th.

Khi nt PROG c n th FPGA s cu hnh li v c li d liu cu hnh ca n.
LED DONE kt ni n chn DONE ca FPGA v sng ln khi cu hnh FPGA thnh
cng hay ni cch khc chng trnh c np thnh cng vo kit Spartan 3.
3.10
Thit lp cch lu tr cho Platform :
112
Hnh 3. 30 : S kt ni jumper la chn cc mode lu tr ca FPGA.

3.10.1
Default Option :
Hu ht cc ng dng u s dng thit lp ny. Khi chn DONE ca FPGA LOW th

Platform Flash c cho php trong sut thi gian cu hnh. Khi chn DONE ca FPGA
i n HIGH ti cui qu trnh cu hnh Platform Flash khng c cho php v ch
ngun t.
Hnh 3. 31 : S kt ni chn gia FPGA vi Platform Flash ch Default.

3.10.2
Flash Read option :
Nh ta bit phn tng quan th Platform c 2Mbit, trong ch s dng mt phn

nh trong 1Mbit cho vic cu hnh d liu. 1Mbit cn li dng trong vic lu tr nhng
d liu thay i nh cc s m ni tip, cc h s ton hc, mt s MAC ID, hay on
m cho mt con vi x l c gn vo trong mt con FPGA.
cho php FPGA c d liu t Platform th jumper JP1 phi c kt ni nh trong
hnh 1.32. Sau khi cu hnh hon tt cho FPGA th FPGA s gi mt tn hiu li cho
chn INT_B ln mc cao, tc l chn N9 ca FPGA ln mc cao. Ti thi im ny
Platform s khng c reset. c mt d liu tip theo th Platform phi ch n
xung clock k tip ca tn hiu RCLK c a n t chn A14 ca FPGA. Sau ,
ng ra ca CCLK l 3 trng thi v to ra mt in tr ko ln lm cho p VCCAUX c gi
tr l 2.5V. D liu ni tip c c t Platform s c chuyn n FPGA qua chn
M11.
113
Hnh 3. 32 : S kt ni chn gia FPGA vi Platform Flash ch Flash Read.

3.10.3
Disable Option :
Nu chn JP1 c tho ra th Platform Flash khng c cho php ; iu ny cho php
cu hnh m rng qua 1 board m rng kt ni n 1 trong cc connector m rng ca
Kit.
3.11
S kt ni cc board m rng vo kit Spartan 3 :
Kit spartan 3 c th kt ni vi 3 board mch m rng A1, A2 v B1, c gn vo t

bn ngoi.
Hnh 3. 33 : V tr kt ni thm cc board mch m rng trn board Spartan 3.

Hnh 2.34 l mt bng tng hp cc c tnh ca mi port m rng. Port A1 c ti a 32
chn xut nhp d liu, trong khi hai port cn li th c cung cp n 34 chn xut
nhp. Mt vi chn c chia s s dng mt s cc chc nng khc trn board,
nhng chn m c th c dng cho vic gim bt hiu qu ca vic m xut nhp
cho nhng ng dng c bit. V d nhng chn ca port A1 c dng chia s vi cc
ng a ch ca SRAM, vi cc chn OE v WE ca SRAM.
114
Hnh 3. 34 : Mt s c tnh ca cc port m rng A1, A2, B1.

Mi mt port s m nhn mt nhim v khc nhau trong vic lp trnh cho con FPGA
trn kit Spartan 3. V d port A1 cung cp thm cc php ton logic li con FPGA v
Platform Flash vi dy cp JTAG. Mt cch tng t nh th, port A2 v B1 cung cp
cc s kt ni theo cu hnh Master v Slave mode ni tip (cu hnh board ch - t).
Cui cng port B1 B1 cung cp cc s kt ni theo cu hnh Master v Slave mode
song song.
Hnh 3. 35 : Cu trc chung ca mt port m rng.

Mi mt port m rng c 40 chn, trong chn s 1 lun lun ni t. Chn s 2 to
ra in p 5V DC ng ra c ly t h thng chuyn i ca p ng ngun. Chn s
3 lun to ra mt mc in p 3.3V DC iu chnh.
3.11.1 Port m rng A1:
Port m rng A1 chia s s kt ni vi thit b 256Kx16 SRAM, c bit l nhng
ng a ch ca SRAM, nhng chn iu khin WE v OE, IC10. Tng t nh vy
l cp JTAG c tch cc t chn 36 n 40 ca port. Chn 20 ca port A1 c dng
cho cu hnh tn hiu trng thi DOUT / BUSY v cht n trong sut qu trnh FPGA
x l cu hnh.
115
Hnh 3. 36 : Bng chn kt ni gia port m rng A1 vi con FPGA spartan 3.

3.11.2 Port m rng A2 :
Port A2 ch c kt ni n cc chn ca con FPGA v khng chia s chn vi cc
thit b khc c sn trn kit. Chn 35 ca port A2 ni n mt khe cm ngun xung
clock ph, vi mt dao ng thch anh c gn thm vo khe . Cc chn t 36 n
40 c dng thit lp cho FPGA hot ng theo cu hnh Master Slave mode
ni tip.
116
Hnh 3. 37 : Bng chn kt ni gia port m rng A2 vi con FPGA spartan 3.

3.11.3 Port m rng B1 :
Port B1 ch c kt ni n cc chn ca con FPGA v khng chia s chn vi cc
thit b khc c sn trn kit. Cc chn t 36 n 40 c dng thit lp cho FPGA
hot ng theo cu hnh Master Slave mode ni tip. Cc chn 5, 7, 9, 11, 13, 15,
17, 19 v 20 c dng thit lp cho FPGA hot ng theo cu hnh Master Slave
mode song song.
117
Hnh 3. 38 : Bng chn kt ni gia port m rng B1 vi con FPGA spartan 3.
118
Chng 4 : Cc cng giao tip c s dng trn Kit FPGA Spartan 3
CHNG 4 : CC CNG GIAO TIP DNG TRN

BOARD SPARTAN 3
4.1
Giao tip RS232 (cng COM) :
Mt chun giao tip quan trng c pht trin bi t chc phi li nhun chuyn tr
gip cc nh sn xut in t, gi tt l EIA (The Electronics Industries Association), l
EIA-232, n nh ngha cc c tnh c, in v chc nng ca giao tip gia mt DTE
v mt DCE. Trong DTE l thit b u cui d liu (Data Terminal Equipment) v
DCE l thit b u cui mch d liu (Data Circuit-terminating Equipment). Chun ny
c xut nm 1962 gi l RS-232. Mt trong cc cu hnh p dng c trnh by
trong hnh 3.1.
Hnh 4. 1 : Mt p dng ca RS-232.

Trong hnh 3.1 DTE thng l mt my tnh (PC) cn DCE thng l mt modem hay
mt thit b thu pht d liu c kt ni vi PC thong qua cng COM (cng RS-232).
Trong quy nh v c, chun EIA-232 nh ngha giao tip nh l si cp 25 dy vi cc
u ni c v ci DB-25. Chiu di cp khng nn vt qu 15m (50 feet). Mt cch
thc hin kt ni khc ca EIA-232 l dng cp 9 dy vi cc u ni c v ci DB9.
Ch c 4 dy trong 25 dy giao tip c dng cho cc chc nng d liu. 21 dy cn
li c dng cho cc chc nng khc nh iu khin, iu ha thi gian, t v kim
tra. Trong chun giao tip EIA-232, mt tn hiu v in cng tng t nh ng d
liu, mt tn hiu c gi l ON nu n pht in p t nht +3V v OFF nu n pht
in p vi gi tr nh hn -3V.
Ton b cc chn chc nng c din t cho cc loi connectors DB25 v DB9 c
m t chi tit trong hnh 3.2 v hnh 3.3.
119
Hnh 4. 2 : Cc chn chc nng ca DB25 v DB9 loi u c.
120
Hnh 4. 3 : Cc chn chc nng ca DB25 v DB9 loi u ci.

DB25: th t v chc nng c trnh by trong hnh 3.3, mi u ni ci s l nh
gng ca u c. Nh vy mi chn chc nng u c nh hoc chiu tr li theo
hng ngc li cho php hot ng song cng. Tuy nhin khng phi chn no
cng c chc nng v d chn s 9 v 10 cn dng d phng v chn s 11 cha
c gn chc nng.
DB9: nhiu chn ca DB25 khng cn thit cho kt ni n bt ng b cho nn c th
gim xung cn 9 chn.
Chng ta phi lu v chc nng chn ca u ni c v u ni ci trong 2 loi cp
DB25 v DB9. Ta hy ch cc chn th 2, 3, 4, 5, 13, 14, 16 v 19 ca u ni c v
u ni ci trong loi kt ni DB25 mc d c s th t ging nhau nhng m nhn hai
qu trnh tri ngc nhau trong truyn v nhn d liu. V d chn s 2 ca u c l
121
truyn d liu th chn s 2 ca u ci ng vai tr l chn nhn d liu, tng t nh

vy cho cc chn va nu.
Hnh 4. 4 : Nghi thc truyn v nhn d liu gia DTE v DCE.

4.2
Giao tip bn phm PS/2 :
4.2.1 S chn kt ni:
Hnh 4. 5 : Chn kt ni ca chun PS/2 loi 5 chn v 6 chn.

4.2.2 Cc tn hiu ca PS/2 :
Bn phm AT c chn kt ni ti 4 tn hiu : Clock, Data, +5V, GND . Ngun +5V
c to bi PC v mass GND cng kt ni vi mass ca PC. Tn hiu Clock v Data l
kiu Open Collector . C bn phm v my tnh u c in tr ko ln cho Clock v
Data ln ngun 5V.
4.2.3 Nguyn tc truyn d liu :
122
Khi nhn 1 phm, b x l bn phm gi n PC m qut (scan-code) ca phm c

nhn. Khi phm c nhn, m ny gi l make-code. Khi phm c nh, m ny gi
l break-code.
Break-code gm 2 byte: byte u l F0 (i vi bn phm m rng), byte k l m
make-code.
Scan code c 3 tiu chun: set 1, set 2, set 3. Bn phm hin nay thng s dng set 2.
V d:
Nhn SHIFT:
make-code = 12 .
Nhn A:
make-code = 1C
Nh A:
break-code = F0, 1C .
Nh SHIFT:
break-code = F0, 12 .
Bn phm PS2 giao tip bng giao thc ni tip bt ng b 2 chiu .Xung clock c
pht bi bn phm, tn s khong 10-16.7kHz .Cc trng thi hot ng:
Data=high, clock=high: trng thi rnh .
Data=high, clock=low: trng thi cm giao tip .
Data=low, clock=high: trng thi my ch c yu cu truyn d liu .
4.2.3.1
Truyn d liu t bn phm v my ch .
Cc bc thc hin:
Kim tra bus ang trng thi rnh .
Clock mc cao t nht 50us trc khi bn phm gi data .
Bn phm gi data tng khung d liu 11 bit .
D liu c c ti cnh xung ca clock .
My ch c th cm giao tip bng cch ko clock xung thp .
Khi clock c gii phng, bn phm li truyn tip d liu cha hon chnh .
M c truyn ni tip tng byte, vi khung truyn 11bit. Gi d liu gi t
Keyboard theo th t sau:
1 start bit = 0;
8 data bits (LSB truyn trc);
1 parity bit (if number of ones is even, then parity bit = 1);
1 stop bit = 1.
123
Hnh 4. 6 : Th t truyn data t Keyboard n Host.

4.2.3.2
Truyn d liu t my ch n bn phm :
Cc bc thc hin:
My ch cm truyn t bn phm n bng cch ko clock xung thp.
My ch ko data xung thp v gii phng clock bo hiu bn phm pht xung
clock bt u truyn d liu.
D liu c c ti cnh ln ca clock .
Sau khi bn phm nhn stop bit Keyboard s truyn tn hiu ACK n my ch
kt thc qu trnh truyn d liu.
Data c truyn theo khung d liu gm 11-12bit nh sau:
1 start bit = 0 .
8 data bit (LSB truyn trc) .
1 parity bit .
1 stop bit = 1 .
1 acknowledge bit (host only) .
Hnh 4. 7 : Th t truyn data t Host n Keyboard.

4.2.4 M qut bn phm (Scancode) :
Hnh 4. 8 : M Scancode ca Keyboard.
124
4.3
Giao tip VGA :
4.3.1 S chn kt ni :
Hnh 4. 9 : Chn kt ni ca chun VGA.

4.3.2 Cc tn hiu ca VGA :
Red , Green , Blue : 3 tn hiu mu c bn .
Horizontal Sync : xung ng b qut ngang to thnh cc dng hnh.
Vertical Sync : xung ng b qut dc to thnh cc frame hnh.
4.3.3 Nguyn tc to hnh :
n in t qut cc tia in t theo hng t tri sang phi , t trn xung di to
hnh nh. Mt bc nh c a ln trn mn hnh TV hay my vi tnh bng cch :
qut 1 tn hiu in theo phng nm ngang i qua mn hnh, mi dng qut 1 ln .
cui ca mi dng, c mt tn hiu c qut ngc v bn tri ca mn hnh (tn hiu
xa ngang) v sau bt u qut dng tip theo. Tp hp cc dng hon chnh to
thnh 1 tm nh (cn gi l 1 frame). Mi khi c 1 nh c qut xong th c tn hiu
in khc (tn hiu xa dc) c qut quay ngc ln trn mn hnh v bt u nh
(frame) tip theo . Chui ny c lp li mt tc nhanh cc nh c hin
th c s chuyn ng lin tc.
4.3.4 Nguyn tc qut tn hiu in to nh :
C 2 nguyn tc qut nh khc nhau : qut xen k v qut lin tc .
Cc tn hiu TV s dng kiu qut xen k c in, cn my tnh s dng kiu qut lin
tc (khng xen k). Hai 2 dng qut ny khng ph hp vi nhau.
Qut xen k th mi nh (frame) c chia thnh 2 nh con (cn gi l mnh). 2 mnh
lm thnh 1 nh. nh qut xen k c v trn mn hnh trong 2 ln qut : u tin qut
125
hng ngang ca mnh 1 v sau quay ngc ln trn qut tip cc dng ca mnh 2 .
Mnh 1 gm cc dng t 1 n 262 , mnh 2 gm cc dng t 262 n 525.
Hnh 4. 10 : Tn hiu qut xen k .

Qut lin tc , nh c to trn mn hnh bng cch qut tt c cc dng trong 1 ln
qut t trn xung di .
Hnh 4. 11 : Tn hiu qut lin tc .

4.3.5 Mt vi chun Video in hnh cho TV v PC :
Video Format
NTSC
PAL
HDTV/SDTV
Vertical
Gn 480
dng (tng
s 525
dng)
Gn 575
dng (tng
s 625
dng)
1080 or 720
or 480 (18
nh dng
khc nhau )
480
768
1920 or 704
or 640 (18
nh dng
khc nhau )
640
1024
Resolution Format (s
dng trn 1 frame)
Horizontal
Resolution Format (s
pixel trn 1 dng)
Xc nh
Xc nh
bi bng
bi bng
thng t 320 thng t 320
n 650
n 650
VGA (PC) XGA (PC)
Horizontal Rate(KHz)
15.734
15.625
33.75-45
31.5
60
Vertical Rate (Hz)
30
25
30-60
60-80
60-80
126
4.3.6 Gin thi gian cho cc tn hiu ca chun VGA :

Tn s xung clock chnh (tn s hin th 1 pixel ) l f = 25 Mhz = 0.04 s .
Do mn hnh VGA loi CRT c kch thc theo t l wide/high = 4/3 . Do phn
gii mn hnh VGA nn chn theo t l 4/3 tc l : 512/384 ; 640/480 ; 800/600 ;
1024/768.( mi pixel c vung hnh nh khng b ko dn ra hay nn li) .
Tn s lm ti mn hnh (tn s qut dc ) fV = 60 Hz , tn s qut ngang fH = 31250
Hz .
Hnh 4. 12 : Thi gian thc hin ca tn hiu Vertical Sync v Horizontal Sync.
Hnh 4. 13 : Gin thi gian ca tn hiu Vertical Sync v Horizontal Sync
127
Chng 5 : S khi v lu gii thut
CHNG 5 : S KHI CA CC CORE V LU

GII THUT THC HIN CC CORE
S khi
128
Chng 6 : Cc ng dng thc hin
CHNG 6 : CC NG DNG THC HIN

Cc ng dng thc hin s dng cc ti nguyn trn Kit FpGA Spartan 3 gm :
Cc cng tc trt (SW0 n SW6) .
Nt n Pushbutton (PB0) .
4 Led 7 on .
Giao tip PS/2 .
6.1
ng h v m sn phm :
SW0 : lm cng tc cho php m .

SW1 : cng tc reset ton b ng h v m sn phm .
SW2 : chn ch hin th ng h hoc m sn phm .
SW3 : chn mode hin th gi / pht hoc pht /giy .
SW4 : chn mode hin th m sn phm t ng hoc bng tay (dng nt n PB0) .
SW5 : chn mode hin th ng h dch t phi qua tri hin th gi / pht /giy .
6.2
Giao tip PS/2 :
SW6 : chn mode cho php nhp t bn phm chui k t hin th Led v thc
hin dch chui k t ny t phi qua tri .
129

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MC LC

GII THIU TP LNH TRONG NGN NG VHDL ................... 1

Ton t d liu :................................................................................................ 4

Entity (thc th): ............................................................................................... 6

DNG NGN NG VHDL M T CC MCH S C BN ...... 27

Thnh phn thc hin cc php ton logic s hc (ALU): ............................ 45

2.8 B ghp knh: .......................................................................................... 53

B m ba trng thi: ..................................................................................... 57

B dch v b xoay (shifter / Rotator): ........................................................... 60

2.13 My trng thi hu hn FSM: ....................................................................... 64

V d phn tch 1 Moore FSM: .................................................................. 70

2.14 Cc linh kin tun t: ..................................................................................... 80

TM HIU KIT FPGA SPARTAN 3 ................................................ 100

Tng quan kit FPGA Spartan 3 : ................................................................ 100

SRAM bt ng b : ..................................................................................... 101

Led 7 on:.................................................................................................... 105

Cc cng tc trt (SW), cc nt n (PB) v cc Led : ............................... 107

Cng VGA : ................................................................................................... 107

Cng ni tip RS-232 : .................................................................................. 110

Cc ngun xung clock : ................................................................................. 111

Cch thit lp cc mode hot ng cho FPGA : .......................................... 111

3.10 Thit lp cch lu tr cho Platform : ........................................................... 112

CC CNG GIAO TIP DNG TRN BOARD SPARTAN 3 ..... 119

Giao tip RS232 (cng COM) : ..................................................................... 119

CC NG DNG THC HIN ................................................ 128

ng h v m sn phm :.......................................................................... 129

Giao tip PS/2 :.............................................................................................. 129

Hnh 3. 4 : S kt ni gia chn gia FPGA v 2 SRAM 256Kx16. ............................ 102

Hnh 4. 11 : Tn hiu qut lin tc .................................................................................. 126

Chng 1 : Gii thiu tp lnh trong ngn ng VHDL

CHNG 1 : GII THIU TP LNH TRONG NGN NG

Nhng phn t ngn ng c bn :

Thit k cc ng dng trn Kit FPGA Spartan III

Chng 1 : Gii thiu tp lnh trong ngn ng VHDL

1.1.4 Loi d liu :

Loi Bit v Bit_vector c xc nh trc trong VHDL. i tng ca nhng loi ny l

Loi STD_Logic v STD_Logic_Vector cung cp nhiu gi tr hn loi Bit trong kiu

Loi STD_Logic v STD_Logic_Vector khng c xc nh trc v th phi khai bo 2

Chng 1 : Gii thiu tp lnh trong ngn ng VHDL

USE IEEE.STD_LOGIC_UNSIGNED.ALL; cho s khng du.

Loi Integer c xc nh trc nh ngha cc i tng s nh phn dng vi tnh

Loi Boolean c xc nh trc nh nghi cc i tng ch c 2 gi tr TRUE hoc

Bng lit k Type :

Mt bng lit k cho php ngi dng ch r nhng gi tr m i tng d liu c th c.

TYPE identifier IS ARRAY (range) OF type;

Thit k cc ng dng trn Kit FPGA Spartan III

Chng 1 : Gii thiu tp lnh trong ngn ng VHDL

V d : TYPE byte IS ARRAY(7 DOWNTO 0) OF BIT;

SUBTYPE l tp hp con ca mt loi m loi c s rng buc v phm vi.

SUBTYPE identifier IS type RANGE range;

V d : SUBTYPE integer4 IS INTEGER RANGE 8 TO 7;

VHDL c xy dng t cc ton t c gii thiu bng di y:

Ton t s hc (Arithmetic Operators)

Thit k cc ng dng trn Kit FPGA Spartan III

Chng 1 : Gii thiu tp lnh trong ngn ng VHDL

Php cng (addition)

Php nhn (multiplication (integer or floating point))

Php chia ( division (integer or floating point))

Ly phn d, du theo b ( modulus (integer))

Ly phn d, du theo a (remainder (integer))

Ton t quan h (Relational Operators)

Ton t dch (Shift Operators)

Dch tri logic (shift left logical)