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Li ni u

Ngy nay cng vi s pht trin ca cc ngnh khoa hc k thut, m k thut in t ng vai tr quan trng hu ht cc lnh vc khoa hc k thut, qun l, cng nghip t ng ha, thng tin lin lcvv do l nhng sinh vin ngnh tinh hc, th h tng lai ca t nc cn phi nm vng cc kin thc v vn dng mt cch c hiu qu nhm gp phn vo s pht trin ca khoa hc k thut nc nh rng hn l khoa hc th gii trong ngnh tin hc. Trong phm vi ln ny em c giao ti Tm hiu VK AVR v lp trnh iu khin LED 7 on Vi iu khin AVR l mt trong nhng h vi iu khin v c ng dng rng ri trong thc t. Diu khin LED 7 on ch l mt ng dng nh ca vi iu khin AVR. Mc ch ca ti ny l lm cho sinh vin nh em lm quen vi h vi iu khin AVR v mt trong nhng ng dng ca n c th l iu khin LED 7on. Nhng qua qu trnh thit k v lm ti th em rt ra c nhiu kinh nghim qu bu cho bn thn. Mc d em c nhiu c gng hon thnh ti nhng do kin thc ca bn thn cn km ci, em bit ti ln ny ca em cn rt nhiu thiu xt. Do vy em rt mong nhn c nhng ng gp ca thy c v ton th cc bn ti ca em c hon thin hn. Cui cng em xin gi li cm n c Lu Th Liu ngi tn tnh hng dn em trong xut qu trnh em lm ti ln ny v ton th cc thy c trong trong b mn K Thut my tnh to iu kin em c nghin cu v lm ti ln ny. Em xin chn thnh cm n.

Chng I: Tng Qut V AVR


1.1 Gii thiu v AVR
- AVR l mt h vi iu khin do hng Atmel sn xut c gii thiu ln u vo nm 1996. AVR l mt vi iu khin 8bits vi cu trc tp lnh n gin ha RISC( Reduced Instruction Set Computer), mt vi iu khin ang c u th trong h vi x l. C trong tnh ng dng v c bit l chc nng. Khi s dng AVR gn nh chng ta khng cn mng thm bt k linh kin ph no. Thm ch khng cn to ngun xung clock cho chip. Thit b lp trnh (mch np) cho AVR rt n gin, c loi ch cn vi in tr l c th lm c, mt s AVR cn h ch chp on-Chp bng bootloader khng cn mach np Bn cnh lp trnh vi ASM, cu trc ca AVR c thit k tng thch vi C. - Hu ht Chp AVR c nhng tnh nng sau. C th x dng xung clock ln n 16MHz, hoc s dng xung clock ni ln n 8MHz (sai s 3%). B nh chng trinh Flash c th lp trinh li rt nhiu ln v dung lng ln. C SRAM ln, c bit c b nh lu tr lp trnh c EEPROM. Nhiu ng vo ra (I/O Folt) 2 hng (bi-directional) 8bits, 16bits tiemr/counter tch hp PWM C b chuyn i Analog Digital phn gii 10 bits, nhiu knh. Chc nng Analog comparator. Giao din tip ni URART (Tng thch chun ni tip RS 232) Giao din tip ni TWO Wire Serial (Tng thch chun I2C) Master v slaver - AVR c rt nhiu dng khc nhau bao gm dng Tiny AVR (nh AT tiny 12, AT tiny 22) c kch thc b nh nh, t b phn ngoi vi, ri n dng AVR ( chng hn AT90S8535, AT90S8515) c kch thc b nh vo loi trung bnh v mnh hn l dng Mega (nh Atmega32, Atmega128,) vi b nh c kich thc vi Kbyte n vi Kb cng vi cc b ngoi vi a dng c tch hp trn chp, cng c dng tch hp c LCD trn chip (dng LCD AVR). Tc ca dng mega cng cao hn cc dng khc, S khc nhau c bn gia cc dng chnh l cu trc ngoi vi, cn nhn th vn nh nhau.

1.2

Cu trc ca AVR.

1.2.1 Cc tnh nng ca AVR ATmega128. - ROM: 128 Kbytes - SRAM: 4 Kbytes - 64 thanh ghi I/O - 160 thanh ghi a mc ch - 2 b nh thi 8 bit (0.2) - 2 b nh thi 16 bit - B nh thi watchdog - B dao ng ni RC tn s 1MHz, 2MHz, 4MHz, 8MHz - ADC 8 knh vi phn gii 10bit ( dng Zmega ln n 12 bit)
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- 2 knh PM 8 bit - 6 knh PM c th lp trnh thay phn gii t 2 ti 16 bit - B so sanh tng t c th la chn ng vo - Hai khi USART lp trnh c - Khi truyn nhn ni tip SPI - Khi giao tip ni tip 2 dy TWI - H tr boot loader - 6 ch tit kim nng lng - La chn tn s hot ng bng phn mn - Dng gi 64 chn kiu TQFP - Tn s ti a 16MHz - in th 4,5v 5,5v - . 1.2.2 Cc cng vo ra ca ATmega 128 Cng vo ra l mt trong s cc phng tin vi iu khin giao tip vi cc thit b ngoi vi. ATmega128 c c thy 7 cng ( port ) vo ra 8 bit l : PortA, PortB, PortC, PortD, PortE, PortF, PortG, tng ng vi 56 ng vo ra. Cc cng vo ra ca AVR l cng vo ra hai chiu c th nh hng, tc c th chn hng ca cng l hng vo (input ) hay hng ra (output ). Tt cc cc cng vo ra ca AVR iu c tnh nng c Chnh sa Ghi ( Read Modify write ) khi s dng chng nh l cc cng vo ra s thng thng. iu ny c ngha l khi ta thay i hng ca mt chn no th n khng lm nh hng ti hng ca cc chn khc. Tt c cc chn ca cc cng ( port )iu c in tr ko ln ( pull-up ) ring, ta c th cho php hay khng cho php in tr ko ln ny hot ng. - Cch hot ng. Khi kho st cc cng nh l cc cng vo ra s thng thng th tnh cht ca cc cng ( PortA, PortB,PortG ) l tng t nhau, nn ta ch cn kho st mt cng no trong s 7 cng ca vi iu khin l . Mi mt cng vo ra ca vi iu khin c lin kt vi 3 thanh ghi : PORTx, DDRx, PINx. ( y x l thay th cho A, B,G ). Ba thanh ghi ny s c phi hp vi nhau iu khin hot ng ca cng, chn hn thit lp cng thnh li vo c sdng in tr pull-up, ..v.v.. .Sau y l din t c th vai tr ca 3 thanh ghi trn. Thanh ghi DDRx y l thanh ghi 8 bit ( c th c ghi ) c chc nng iu khin hng ca cng (l li ra hay li vo ). Khi mt bit ca thanh ghi ny c set ln 1 th chn tng ng vi n c cu hnh thnh ng ra. Ngc li, nu bit ca thanh ghi DDRx l 0 th chn tng ng vi n c thit lp thnh ng vo. Ly v d: Khi ta set tt c 8 bit ca thanh ghi DDRA u l 1, th 8 chn tng ng ca portA l PA1, PA2,
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PA7 ( tng ng vi cc chn s 50, 49, 44 ca vi iu khin ) c thit lp thnh ng ra.

Thanh ghi PORTx PORTx l thanh ghi 8 bit c th c ghi. y l thanh ghi d liu ca PORTx, Nu thanh ghi DDRx thit lp cng l li ra, khi gi tr ca thanh ghi PORTx cng l gi tr ca cc chn tng ng ca PORTx, ni cch khc, khi ta ghi mt gi tr logic ln 1 bit ca thanh ghi ny th chn tng ng vi bit cng c cng mc logic. Khi thanh ghi DDRx thit lp cng thnh li vo th thanh ghi PORTx ng vai tr nh mt thanh ghi iu hin cng. C th , nu mt bit ca thanh ghi ny c ghi thnh 1 th in tr treo ( pull-up resistor ) chn tng ng vi n s c kch hot, ngc li nu bit c ghi thnh 0 th in tr treo chn tng ng s khng c kch hot, cng trng thi cao tr ( Hi-Z ).

Thanh ghi PINx PINx khng phi l mt thanh ghi thc s, y l a ch trong b nh I/O kt ni trc tip ti cc chn ca cng. Khi ta c PORTx tc ta c d liu c cht trong PORTx, cn khi c PINx th gi tr logic hin thi chn ca cng tng ng c c. V th i vi thanh ghi PINx ta ch c th c m khng th ghi. Bng 1 th hin cc cc thit lp cch hot c th c ca cng

DDRxn PORTxn PUD (Trong I/O thanh ghi SFIOR) 0 0 x Ng vo 0 1 0 Ng vo 0 1 1 Ng vo 1 0 x Ng ra 1 1 x Ng ra Cu hnh cho cc chn cng DDRxn l bt th n ca thanh ghi DDRx PORTxn l thanh ghi th n ca thanh ghi PORTx Du x cu th ba l ch trng thi logic ty i y l a ch ca tt c cc port. Tn PORT a ch I/O PORTA DDRA PINA PORTB DDRB PINB PORTC DDRC PINC PORTD DDRD PIND PORTE DDRD PINE PORTF DDRF PINF $1B $1A $19 $18 $17 $16 $15 $14 $13 $12 $11 $10 $03 $02 $01 Khng c Khng c $00

Pull/Up Khng C Khng Khng Khng

Ghi ch Cao tr Nh mt ngun dng Cao tr Ng ra thp Ng ra cao

a ch SRAM $3B $3A $39 $38 $37 $36 $35 $34 $33 $32 $31 $30 $23 $22 $21 $62 $61 $20
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PORTG DDRG PING

Khng c Khng c Khng c

$65 $64 $6

i y l a ch ca tt c cc port. Ch y: 3 bit cui (bit 5, 6, 7) ca cc thanh ghi PORTG, DDRG v PING khng s dng c. Khi c ta lun nhn c gi tr 0. - Port A (PA0PA7). Port A l cng I/O 8-bit hai chiu vi cc in tr pull -up bn trong (c la chn cho mi bit). B m u ra ca Port A c c tnh iu kin cn i vi c tn hiu source v sink. Khi l tn hiu u vo, cc chn ca cng A s tiu th dng nu cc in tr pull-up bn trong c kch hot. Port A c s dng lm cc ng a ch thp v d liu khi giao tip vi b nh ngoi theo bng sau: Cc chn Port A cng l ng vo analog ca b chuyn i A/D
PA7PA0 Chc nng b sung

PA7 ADC7 (a ch v d liu bit 7 giao tip vi b nh ngoi) PA6 ADC6 (a ch v d liu bit 6 giao tip vi b nh ngoi) PA5 ADC5 (a ch v d liu bit 5 giao tip vi b nh ngoi) PA4 ADC4 (a ch v d liu bit 4 giao tip vi b nh ngoi) PA3 ADC3 (a ch v d liu bit 3 giao tip vi b nh ngoi) PA2 ADC2 (a ch v d liu bit 2 giao tip vi b nh ngoi) PA1 ADC1 (a ch v d liu bit 1 giao tip vi b nh ngoi) - Port B (PB0PB7): Port B l cng I/O 8-bit hai chiu vi cc in tr pull -up bn trong ( c la chn cho mi bit). B m u ra ca Port B c c tnh iu kin cn i vi c tn hiu source v sink. Khi l tn hi u u vo, cc chn ca cng B s ti u th dng nu cc in tr pull-up bn trong c kch hot.

Port B c s dng vi nhng chc nng b sung theo bng sau:


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PB7PB0 PB7

Chc nng b sung OC2/OC1C( u ra so snh v u ra PWM cho timer/counter2 v u ra so snh v u ra PWM C cho timer/counter1)

PB6

OC1B (u ra so snh v u ra PWM B cho timer/counter1) PB5 OC1A (u ra so snh v u ra PWM A cho timer/counter1) PB4 OC0 (u ra so snh v u ra PWM cho timer/counter0) PB3 MISO (u vo ch/u ra t bus SPI) PB2 MOSI (u ra ch/u v o t bus SPI) PB1 SCK (chn Clock ca SPI) PB0 SS (ng vo chn Slave ca SPI) - Port C (PC0PC7): Port C l cng I/O 8-bit hai chiu vi cc in tr pull -up bn trong ( c la chn cho mi bit). B m u ra ca Port C c c tnh iu kin cn i vi c tn hiu source v sink. Khi l tn hi u u vo, cc chn ca cng C s ti u th dng nu cc in tr pull-up bn trong c kch hot. Port C c s dng vi nhng chc nng b sung theo bng sau: PC7PC0 Chc nng b sung PC7 a ch bit 15 giao tip vi b nh ngoi PC6 a ch bit 14 giao tip vi b nh ngoi PC5 a ch bit 13 giao tip vi b nh ngoi PC4 a ch bit 12 giao tip vi b nh ngoi Pc3 a ch bit 11 giao tip vi b nh ngoi PC2 a ch bit 10 giao tip vi b nh ngoi PC1 a ch bit 9 giao tip vi b nh ngoi PC a ch bit 8 giao tip vi b nh ngoi - Port D (PD0PD7) Port D l cng I/O 8-bit hai chiu vi cc in tr pull -up bn trong (c la chn cho mi bit). B m u ra ca Port D c c tnh iu kin cn i vi c tn hiu source v sink. Khi l tn hi u u vo, cc chn ca cng D s ti u th dng nu cc in tr pull-up bn trong c kch hot.) Port D c s dng vi nhng chc nng b sung theo bng sau.

PD7PD0 PD7

Chc nng b sung T2 (ng vo ca b m ngoi counter 2)


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PD6 PD5 PD4 PD3 PD2 PD1 PD0


-

T1 (ng vo ca b m ngoi counter 1) XCK1 (chn I/O Clock ca USART1) ICP1 (chn bt mu ca Timer/Counter1) INT3/TXD1(ng vo ngt ngoi 3 hoc truyn tn hiu UART1) INT2/RXD1(ng vo ngt ngoi 2 hoc nhn tn hiu UART1) INT1/ SDA (ng vo ngt ngoi 1 hoc Chn data I/O ca giao thc Two-wire) INT0/ SCL (ng vo ngt ngoi 0 hoc Chn Clock ca giao thc

Port E (PE0PE7) Port E l cng I/O 8-bit hai chiu vi cc in tr pull -up bn trong (c lachn cho mi bit). B m u ra ca Port E c c tnh iu kin cn i vi c tn hiu source v sink. Khi l tn hi u u vo, cc chn ca cng E s ti u th dng nu cc in tr pull-up bn trong c kch hot. Cc chc nng khc ca Port E PE7 PD0 Chc nng b sung PE7 INT7/ICP3 (ng vo ngt ngoi 7 hoc chn bt mu ca Timer/ Counter3) PE6 INT6/T3 (ng vo ngt ngoi 6 hoc ng vo ca b m ngoi Timer/Counter 3) PE5 INT5/OC3C (ng vo ngt ngoi 5 hoc ng ra so snh PWM C ca Timer/Counter3) PE4 INT4/OC3B (ng vo ngt ngoi 4 hoc ng ra so snh PWM B ca Timer/Counter3) PE3 AIN1/OC3A (ng vo Negative ca b so snh analog hoc ng ra so snh PWM A ca Timer/Counter3) PE2 AIN0/ XCK0 (ng vo Possitive ca b so snh analog hoc chn I/O Clock ca USART0) PE1 PDO/TXD0 (ng ra d liu hoc ng ra USART0) PE0 PDI/RXD0 (ng vo d liu hoc ng vo USART0)

Port F (PF0PF7):

Port F c chc nng lm u vo cho b chuyn i ADC tch hp sn. Khi khng c s dng vi chc nng l m u vo ca ADC, Port F cng l cng I/O 8-bit hai chiu vi cc in tr pull -up bn trong ( c la chn cho mi bit). B m u ra ca Port F c c tnh iu kin cn i vi c tn hiu so urce v sink. Khi l tn hiu u vo, cc chn ca cng F s tiu th dng nu cc in tr pull -up bn trong c kch hot. Port F c s dng vi nhng chc nng b sung theo bng sau: PF0 PF7 Chc nng b sung PF7 ADC7/TDI (ng vo ADC 7 hoc chn d liu vo Test JTAG) PF6 ADC6/TDO (ng vo ADC 6 hoc chn d liu ng ra Test JTAG) PF5 ADC5/ TMS (ng vo ADC 5 hoc chn chn Mode Test JTAG) PF4 ADC4/ TCK (ng vo ADC 4 hoc chn Clock Test JTAG PF3 ADC3 (ng vo ADC 3) PF2 ADC2 (ng vo ADC 2) PF1 ADC1 (ng vo ADC 1) PF0 ADC0 (ng vo ADC 0) - Port G (PF0 PG7) Port G l cng I/O 5-bit hai chiu vi cc in tr pull -up bn trong (c la chn cho mi bit). B m u ra ca Port G c c tnh iu kin cn i vi c tn hiu source v sink. Khi l tn hi u u vo, cc chn ca cng G s t iu th dng nu cc in tr pull-up bn trong c kch hot) Port G c s dng vi nhng chc nng b sung theo bng sau: Chn Chc nng PG4 TOSC1 (Chn 1 b dao ng ca Timer/Counter 0) PG3 TOSC2 (Chn 2 b dao ng ca Timer/Counter 0) PG2 ALE (cho php ch t a ch ti b nh ngoi) PG1 RD(cho php c b nh ngoi) PG0 WR(cho php vi t ti b nh ngoi)

1.2.3

S chn ca ATMEGA 128.


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- GND: Chn ni mass - VCC: in p ngun

Cu trc b nh ca Atmage 128. - B nh ca ATmega 120.


1.2.4 11

B nh ca AVR c cu trc harvard l cu trc bus ring cho b nh chng trnh v b nh d liu. B nh AVR chia lm 2 phn chnh b nh chng trnh (program memory) v b nh d liu (Data memory). B nh chng trnh. B nh chng trnh ca AVR c cu trc flash c dung lng 128 kbytes. B nh chng trnh c rng 16 bit. ATmega 128 b nh chng trnh c th c chia lm 2 phn: Phn boot loader (Boot loader program section) v phn ng dng (Applcation program section) Phn boot loader cha chng trnh boot loader. Chng trnh boot loader l mt phn mn nh nap trong vi iu khin c chy lc khi ng. Phn mn ny c th ti vo trong vi iu khin chng trnh ca ngi s dng v sau thc thi chng trnh nay. Mi khi reset vi iu khin CPU s nhy ti thc thi chng trnh boot loader ny trc, chng trnh boot loader s d xem chng trnh no cn np vo vi iu khin hay khng, nu c chng trnh cn np, boot loader s np vo vng nh ng dng (Application program section) ri thc thi chng trnh ny. Ngc li boot loader s chuyn sang chng trinh ng dng c sn trong vng nh ng dng thc thi chng trnh nay. Phn ng dng (Application program section ) l vng nh cha chng trnh ng ng ca ngi dng. Kch thc ca phn boot loader v phn ng dng c th y chn. Hnh 2.1 th hin cu trc b nh chng trnh c s dng v khng s ng boot loader, khi s dng phn boot loader ta thy 4 word u tin thay v ch th cho CPU chuyn ti chng trnh ng dng ca ngi dng (l chng trnh c nhn start) th ch th CPU nhy ti phn chng trnh boot loader thc hin trc, ri mi quay tr li thc hin chng trnh ng dng. B nh d liu. B nh d liu ca AVR chia lm 2 phn chnh l b nh SRAM v b nh EEPROM. Tuy cng l b nh d liu nhng hai b nh ny li tch bit nhau v c nh a ch ring B nh SRAM c dng lng 4 K bytes, B nh SRAM c hai ch hot ng l ch thng thng v ch tng thch v ATmega103, mun thit lp b nh SRAM hot ng theo ch no ta s dng bit cu ch M103C ( M103C fuse bit(9) ) B nh SRAM ch bnh thng : ch bnh thng b nh SRAM c Chia thnh 5 phn: Phn u l 32 thanh ghi chc nng chung (General Purpose Register ) R0 n R31 c a ch t $0000 ti $001F. Phn th 2 l khng gian nh vo ra vi 64 thanh ghi vo ra ( I/O Register ) c a ch t $0020 ti $005F. Phn th 3 dng cho vng nh dnh cho cc thanh ghi vo ra m rng ( Extended I/O Registers ) c a ch t $0060 ti $00FF. Phn th 4 l vng SRAM ni vi 4096 byte c a ch t $0100 ti $10FF. Phn th 5 l vng nh SRAM ngoi ( External
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SRAM ) bt u t a ch $1100, vng SRAM m rng ny c th m rng ln n 64 K byte. Khi ni b nh SRAM c dung lng 4 K byte l ni ti phn th 4 ( SRAM ni ). Nu tnh c cc thanh ghi th b nh SRAM trong ch bnh thng s l 4.25 K byte = 4352 byte. B nh SRAM ch tng thch ATmega103 : ch ny b nh SRAM cbn cng ging ch bnh thng, ngoi tr phn th 3 l vng nh dnh chocc thanh ghi vo ra m rng khng tn ti, ngoi ra kch thc ca phn SRAMni ( internal SRAM ) ch c 4000 byte so vi 4096 byte ch bnh thng. - B nh nh thi ca ATmega 128. ATmega 128 c 4 b nh nh thi, b nh 1 v 3 l b nh 16 bit, b nh nh thi 0 v 2 l b nh nh thi 8 bit. Di y l m t chi tit ca 4 b nhi nh thi. B NH THI TIMER/COUTER 0: Timer/Counter0 l Timer/Counter 8 bit vi cc c im chnh PWM Pht tn s B nh trc t l ng h 10bit Cc ngun ngt bo trn v bo so snh ph hp (OCFO v TOVO) Cho pht ng t bo ng 32kHz bn ngoi bn ngoi ng lp vi ng h I/O B NH THI TIMER/COUTER 2: Timer/Counter2 l Timer/Counter 8 bits, v i cc c im chnh: PWM Pht tn s B nh trc t l ng h 10bit Cc ngun ngt bo trn v bo so snh ph hp (OCFO v TOVO) B NH THI TIMER/COUTER 1 V TIMER/COUNTER 3: Timer/Counter1v Timer/Count er3 l cc Timer/Counter 16 bits, vi cc c imchnh Thit k 16bit thc s (cho php to ra xung PWM 16bit) 2 b so snh ng ra c lp 1 b bt mu t ng vo 1 b gim nhiu ng vo Ch d xa times khi t ti gi tr so snh. To tn s To xung PWM c th thay i gi tr m s kin ngoi Cc cht hot ng
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Ch bnh thng. Ch xa times khi t ti gi tr so snh. Ch PWM khi t tn s cao Ch PWM hiu chnh ba pha Ch PWM hiu chnh ba pha v tn s. 1.2.5 . IC gii m 7447 L IC c chc nng gi m nh phn BCD ra m led 7 on loi A chung. Nh vy u vo c 4bit u ra c 7bit. u l dng song song.

Chc nng cc chn nh sau. A,B,C,D: Chn u vo m BCD vi trng s bit tng dn t A D EBI: Ripple Blanking Input RBO: Ripple Blanking Output QA QF: u ra ca m 7 on Bng chn l: LED A 0 0 0 0 0 0 0 0 1 1 B 0 0 0 0 1 1 1 1 0 0 C 0 0 1 1 0 0 1 1 0 0 D 0 1 0 1 0 1 0 1 0 1 a 0 1 0 0 1 0 1 0 0 0 b 0 0 0 0 0 1 1 0 0 0 c 0 0 1 0 0 0 0 0 0 0 d 0 1 0 0 1 0 0 1 0 1 e 0 1 0 1 1 1 0 1 0 1 f 0 1 1 1 0 0 0 1 0 0 g 1 1 0 0 0 0 0 1 0 0 0 1 2 3 4 5 6 7 8 9

Chng II: Ngn ng lp trnh cho AVR


2.1 Gii thiu.
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C rt nhiu phn mn h tr ngn ng bc cao nh BascomAVR (Basic) hay codevisionAVR (C) m bn c th khng cn bit v cu trc ca AVR. Tuy nhin hiu thu o v AVR bn phai lp trnh bng ngn ng ca n, ASM. Lp trnh bng ASM gip bn hiu tng tn v AVR, v tt nhin lp trnh bng ASM bn phi hiu tng tn v AVR. 2.2 Cc ch th hp dich. Chng trnh dch Assembly lm vic trn file chng trnh ngun v mt file ngun bao gm: cc lnh , cc nhn v cc ch dn.Chng c xp tun t trong file ngun. Mt dng lnh c chiu di cc i l: 120 k t. Mi dng lnh u c th t trc bi mt nhn, n l mt chui k t v kt thc bng du 2 chm. Nhn c s dng nh l ch cho cc lnh nhy, v cc ch th r nhnh.V cn c s dng nh l tn bin trong b nh chng trnh v b nh d liu. Mt dng lnh c th l mt trong bn dng sau: 1. [nhan: ] ch_th [ton_hng] [;li ch thch] 2. [nhan: ] lnh [ton_hng] [;li ch thch] 3. ;ch thch 4. dng trng (khng cha k t no) Mt li ch thch lun i sau du chm phy(;)v n khng c dch sang m my ch c tc dng cho ngi c chng trnh d hiu. Chng trnh Assembly h tr mt s cc ch th.Cc ch th ny khng c dch ra m nh phn (m my).V n c s dng iu khin qu trnh dch v c th l: iu khiu ghi lnh vo b nh chng trnh, nh ngha cc bin Di y l bng cc ch th: Ch th M t BYTE nh ngha mt bin kiu byte CSEG on m chng trnh DB nh ngha mt hng s kiu byte DEF nh ngha mt tn gi nh cho mt thanh ghi DEVICE nh ngha loi VK cho chng trnh DSEG on d liu DW nh ngha mt hng s kiu 2 byte (word) ENDMACRO Kt thc ca mt macro EQU Thay mt biu thc bng mt k t. ESEG on EEPROM EXIT Thot ra t mt file INCLUDE S dng m ngun t mt file khc LIST Cho php to ra trong file list
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LISTMAC Cho php thm macro vo list khi c gi MACRO Bt u macro NOLIST Cho php thm macro vo list khi c gi ORG Cho php thm macro vo list khi c gi SET Cho php thm macro vo list khi c gi Tt c cc ch th u t sau du chm (.). 1.1.BYTE : Ch th ny ginh trc ti nguyn b nh trong SRAM.Ch th ny phi i sau mt nhn v c mt tham s, n ch ra s byte c ginh trc.Ch th ny ch dng trong on d liu. C php : LABEL: .BYTE expression V d: .DSEG var1: .BYTE 1 ; var2 : .BYTE 10; .CSEG ldi r30,low(var1); Nu nh bn no hc qua mt ngn ng cp cao no th thc ra vng nh ny cng nh l mt bin. D liu s khng t ng c ghi vo v ch khi bn dng cc lnh tc ng n n m thi.Nhn chnh l a ch u ca on b nh c ginh trc. 1.2.Ch th CSEG: Ch th ny nh ngha im bt u ca on m chng trnh. Mt file ngun assembly c th cha nhiu on m chng trnh, v chng li c lin kt thnh mt on m lnh khi dch. Ch th BYTE khng c s dng trong on ny. Mt on chng trnh nu khng c nh ngha l m lnh hay d liu th u c mc nh l on m lnh.Mi on m linh th c mt a ch ring 16 bit (hay l mt t). Ch th ORG c th c s dng t v tr ca cc on m lnh v hng s trong b nh chng trnh. Ch th ny khng km theo bt k mt tham s no. C php: .CSEG V d: .DSEG var1: .BYTE 1 .CSEG CONST: .DW 2 MOV R1,R0 1.3.DB: nh ngha cc hng s kiu byte c lu trong b nh chng trnh hac
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b nh EEPROM.V ch th ny lun theo sau mt nhn. Ch th ny thng c s dng trong vic lu gi cc bng v cc biu thc (nhng c th tnh ra gi tr cui cng). Cc nhn chnh l a ch khi u cho gi tr ban u ca bng. Ch dn ny ch c th t c trong on m hoc on b nh EEPROM. Cc phn t trong bng c phn bit bng du phy. C php: Label: .DB danh_sach_biu_thc V d: .CSEG Sin: .DB 0,1,2,3,4,6,7 .ESEG const: .DB 1,2,3 Ch : Mt s hay mt biu thc (phi c kt qu) nm trong khong 128 n 255.Nu s l s m th s c lu di dng 8bit m b 2. 1.4.DEF: Ch th ny c tc dng cho php lp trnh vin t tn cho mt thanh ghi. Thay bng nh thanh ghi lp trnh vin c th t tn cho n vi ci tn gi nh hn. C php: .DEF tn_gi_nh=thanh_ghi V d: .DEF xh=R28 .DEF xl=R29 Ch : Mt thanh ghi c th c rt nhiu tn gi nh gn cho n nhng iu s rt nguy him c th v tnh bn lm mt d liu trong thanh ghi m bn khng mong mun. 1.5.DEVICE: Ch th ny ch cho chng trnh dch bit loi vi iu khin m ta ang vit chng trnh. C php: .DEVICE Loi_vi_iu_khin V d: .DEVICE AT90S8535 Ch th ny s bo cho chng ta nhng li sinh ra khi m chng trnh dch tm thy nhng lnh cng nh nhng thitb ngoi vi khng c h tr trong loi vi iu khin ny. 1.6.DSEG: Ch th ny nh ngha im bt u ca on d liu.Mt file ngun c th c nhiu on d liu nhng khi dch chng th chng c gp lin kt vo

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mt on.Mt on d liu bnh thng ch cha duy nht ch th BYTE. Mi on d liu u c mt con tr v tr ring v l con tr 8 bit (v chng trong b nh RAM). Ch th ORG c th c s dng t cc bin ti cc v tr xc nh trong RAM (ch th ny s c ni sau). C php: .DSEG var1: .BYTE 1 table: .BYTE table_size 1.7.DW: y l ch th cho php ngi s dng nh ngha cc hng s dng 2 byte trong b nh chng trnh hoc bn nh EEPROM n hon ton tng t nh ch th DB. C php: Label: .DW danh_sch_biu_thc V d: Var: .DW 12,354,3434,31345 1.8.ENDMACRO: Kt thc ca mt macro.Ch th ny khng i km mt tham s no c. C php: .Endmacro V d: .Macro subi16 subi r16,low(@0) subi r17,high(@0) .Endmacro 1.9.EQU: Ch th EQU gn gi tr ca mt biu thc cho mt nhn.Nhn sau khi gn gi tr tr thnh mt hng s v khng c nh li gi tr. C php: .EQU const=expression V d: .EQU io=0x23 .EQU ios=io-10 1.10. ESEG: Hon ton ging vi CSEG 1.11. EXIT: Ch th EXIT bo cho chng trnh dch bit dng vic c file li. Bnh thng th chng trnh dch s chy cho ti khi ht file th kt thc. Nhng nu nh trong file c cha ch th ny th khi no chng trnh dch gp ch th ny th s kt thc qa trnh c. C php: . EXIT
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1.12.INCLUDE Ch th ny bo cho chng trnh dch bit bt u c t mt file xc nh cho ti khi ht file hoc mt ch th ngng c (EXIT). C php: .Include tn_file; i khi c tn file v ng dn. V d: ;Ni dung ca file iodef.asm .EQU sreg = 0x3f .EQU sphigh=0x3e .EQU splow=0x3d ;Trong chng trnh .INCLUDE iodef.asm in r0,sreg ; c thanh ghi trang thi. 1.13.LIST: Cho php chng trnh dch to ra file list. C php: .LIST Ch :Mc nh ca chng trnh dch l cho php to ra file list v ch th ny lun i km vi ch th NOLIST. 1.14.LISTMAC: Hon ton ging vi LIST nhng vi macro. 1.15.MACRO: Ch dn khai bo macro.Vy macro l g? Macro thc ra l mt on chng trnh .Khi m macro c gi th on chng trnh s c dn vo v tr gi macro. Tham s i theo ngay sau ch th ny l tn ca macro. Mt macro c th c ti 10 tham s. C php: .Macro macro_name V d: .Macro sub16 ..;lnh g .;lnh no .Endmacro .CSEG sub16 ;goi macro 1.16.NOLIST: 1.17. ORG: Ch th ORG thit lp mt con tr tuyt i .Gi tr c thit lp chnh l tham s cho ch th ny. Nu nh ch th ny nm trong on d liu th v tr c thit lp chnh l mt v tr trong SRAM v c th l v tr bt u ca bin c khai bo sau ch th BYTE.
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Cn khi ch th ny c khai bo trong on chng trnh th v tr tuyt i nm trong b nh chng trnh v on m lnh theo sau n s c ghi vo bin nh chng trnh t con tr .V i vi on ESEG cng tng t.Nu nh ch th ny i sau mt nhn th nhn c gi tr chnh bng tham s ca ch th ny. C php: . org tham_s hoc Label: . org tham_s V d: .DSEG . org 0x60 var1: .BYTE 2 . ESEG . org 0x20 evar: .DB 0xff .CSEG . org 0x10 mov r0,r1 1.18.SET: Gn mt gi tr cho mt nhn. Nhn ny c th s dng thay cho gi tr v n hon ton c th b thay i ph thuc vo chng trnh.( y l im khc bit ca n so vi ch th EQU). Mt s ch th khc : .IFDEF <symbol> .IFNDEF <symbol> .IF <expression> .IFDEF <symbol> |.IFNDEF <symbol> ... .ELSE | .ELIF<expression> ... .ENDIF V d: .MACRO SET_BAT .IF @0>0x3F .MESSAGE "Address larger than 0x3f" lds @2, @0 sbr @2, (1<<@1) sts @0, @2 .ELSE .MESSAGE "Address less or equal 0x3f" .ENDIF
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.ENDMACRO 2.3 Assembly cho AVR. - Instruction ch dng cho Register Files LDI (Load Immediate): Load mt hng s K vo thanh ghi Rd (Thanh ghi ngun v cng l thanh ghi ich thuc Register File) MOV (MOVE): Copy gi tr trong thanh ghi Rr (Thanh ghi ngun thuc Register File v thanh ghi Rd) CLR (CLEAR Register): SER (SET Register): set tt c cc bit tronh thanh ghi Rd ln 1, sau lnh ny thanh ghi Rd=0xFF. CBR (CLEAR Bit in Register): xa cc bit trong thanh ghi Rd vi mt n K, nu Bit no trong K l 1 th Bit tng ng trong Rd s b xa. SBR (S Bit in Register): set cc bit trong thanh ghi Rd vi mt n K, nu Bit no trong K l 1 th Bit tng ng trong Rd s c set ln 1. BLD (Bit load from T Flag): Load gi tr trong c T ca thanh ghi SREG vo bit th b trong thanh ghi Rd. y cng chnh l chc nng chnh ca c T. BST (Bit Storage from T Flag): Copy bit th b trong thanh ghi Rd vo trong c T ca thanh ghi SREG. y cng chnh l chc nng chnh ca c T. CPI (COMPARE with Immediate): so snh thanh ghi Rd vi hng s K, lnh ny lm thay i nhiu bit trong thanh ghi SREG trong s thay i ca c Zero l quan trng nht, nu Rd = K c Z=1, ngc li Z=0, s dng c im thay i ca c Z kt hp vi lnh BRNE hoc BREQ chng ta c th to thnh mt lnh r nhnh. ANDI (AND with Immediate): thc hin php Logic AND gia thanh ghi Rd vi hng s K v kt qu t li trong Rd. AND ( (Logical AND): thc hin php Logic AND gia 2 thanh ghi Rd v Rr , kt qu t li trong Rd. ORI (Logical OR with Immediate): thc hin php Logic OR gia thanh ghi Rd vi hng s K v kt qu t li trong Rd. OR (Logical OR): thc hin php Logic OR gia 2 thanh ghi Rd v Rr , kt qu t li trong Rd. LSL(Logical Shift Left): dch tt thanh ghi Rd sang tri 1 v tr, Bit 7 (bit ln nht) ca Rd s c cha trong c nh C, bit 0 ca Rd b xa thnh 0. Thc cht LSL tng ng vi php nhn thanh ghi Rd vi 2. Bn xem hnh minh ha bn di. LSR (Logical Shift Right). dch tt thanh ghi Rd sang phi 1 v tr, Bit 0 (bit nh nht) ca Rd s c cha trong c nh C, bit 7 ca Rd b xa thnh 0. Thc cht LSR tng ng vi php chia thanh ghi Rd cho 2. Bn xem hnh minh ha bn di. SUBI (SUBtract Immediate): thc hin php tr thanh ghi Rd vi hng s K, kt qu t li trong Rd.
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DEC (DECrement). gim thanh ghi Rd 1 n v v kt qu t li trong Rd. Lnh ny c bit thch hp cho cc ng dng lp, kt hp vi BREQ hay BRNE c th to thnh 1 vng lp FOR. MUL (MULtiply unsigned): thc hin php nhn khng du 2 thanh ghi 8 bit Rd, Rr, kt qu l 1 s 16 bit t trong 2 thanh ghi R1:R0. Ch nu Rd v Rr l cc thanh ghi R1 v R0 th kt qu sau khi tnh c s c vit ln. Xem hnh minh ha instruction MUL bn di.

- Instruction cho cc thanh ghi I/O Bn instruction sau y c thit k ring truy cp vng nh I/O, cc Instruction ny s dng a ch I/O ca cc thanh ghi trong vng nh ny. V l thit k ring cho vng nh I/O, bn khng th s dng cc thanh ghi ny truy cp RF hay SRAM. Trong cc c php ca instruction ny, khi nim a ch A l a ch I/O 0 A 63, nu trong v d A = 0x00 th l thanh ghi u tin ca vng I/O, khng phi l thanh ghi R0 OUT (OUTPUT Data): Xut gi tr thanh ghi Rr ra thanh ghi c a ch A trong vng nh I/O. y l cch ph bin nht xut gi tr ra vng I/O IN (INPUT Data): Load gi tr t thanh ghi c a ch A trong vng nh I/O vo thanh ghi Rr. y l cch ph bin nht nhn gi tr t vng I/O SBI (Set Bit in I/O Register): Set bit th b trong thanh ghi c a ch A trong vng nh I/O. Tuy nhin lnh ny khng c tc dng trn ton b vng I/O m ch c tc i vi 32 thanh ghi u (a ch t 0 n 31) CBI (Clear Bit in I/O Register): Xa bit th b trong thanh ghi c a ch A trong vng nh I/O. Tuy nhin lnh ny khng c tc dng trn ton b vng I/O m ch c tc i vi 32 thanh ghi u. - R nhnh v vng lp. Khng ging nh cc ng ng cp cao khc, khi lp trnh bng ASM bn khng c h tr cc cu trc iu khin nh if, forngi lp trnh ASM phi xy dng cho mnh cu trc ny t nhng instruction c bn.

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Chng III: Thit k chng trnh iu kin LED 7 on.


3.1. Trnh bin dich C rt nhiu trnh bin dch c th s dng bin dich code thnh file intel hex np vo chip. y em s dng trnh bin dch AVR Studio. Giao din ca AVR Studio nh sau.

Giao din ca AVR Studio rt d s dng. to Project mi: t menu project, chn Project/ New Project

Mt dialog mi xut hin cho php bn setting Project ca bn, trong vng Project Type Chn Atmel AVR assembler tc lp trnh bng ngn ng Assemblay v trnh dch l Atmel AVR assemler (Trnh dch tch hp trong
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AVR Studio); Location chn ni cha Project Project name tn Project ca ban.

Nhn Next tip tc chn Platform v device, vic ny phc v cho mc ch bebug chng trnh hay m phng bng avr simlator. Bn chn AVR Simulator trong Platform v Atmega 128 trong device. V nhn finish kt thc.

Vic cn li l vit code vo ca s Editor sau dch chng trnh bng phm F7.

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3.2. Code lp trnh.

.INCLUDE "M8DEF.INC" .CSEG. .ORG 0x0000 RJMP BATDAU .ORG 0x0020 BATDAU: ;KHOI DONG STACK POINTER LDI R17, HIGH(RAMEND) LDI R16, LOW(RAMEND) OUT SPL, R16 OUT SPH,R17 ; KHOI DONG CAC PORT CLR R16; OUT DDRB, R16; LDI R16, 0xFF; OUT PORTB,R16 OUT DDRD, R16; =;STS 0x0031, R16 CLR R25 SER R20 ; R21 LA THANH GHI TAM CHUA GIA TRI TRUOC DO CUA PINB MAIN: IN R21,PINB RCALL SOSANH OUT PORTD,R25 SBRS R21,0 RCALL TANG SBRS R21,1 RCALL GIAM MOV R20,R21 RJMP MAIN ;**********************CHUONG CON******************************** SOSANH: CPI R25, 10 BREQ RESET0 CPI R25, 255
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TRINH

BREQ RESET9 RJMP QUAYVE RESET0: LDI R25,$0 RJMP QUAYVE RESET9: LDI R25,$9 QUAYVE: RET TANG: SBRS R20,0 RET INC R25 RET GIAM: SBRS R20,1 RET DEC R25 RET 3.3. Mch m phng. 3.3.1 Tm hiu phn mm m phng Proteus. - Gii thiu phn mm Proteus Proteus ca Labcenter Electronics l phn mn m phng mch n rt c a thch hin nay. So vi phn mn m phng mch in khc, Protues c rt nhiu u im ni tri nh: m phng c rt nhiu linh kin in t v thit b hin th, kt qu m phng rt trc quan nh mt mch in tht, v mt tnh nng m chng ta nhng ngi hc vi iu khin qun tm nht l kh nng m phng cc chp iu khin vi chng trnh do ngi dng nap. Protues h tr rt nhiu cc chip vi iu khin nh 8051, AVR, PIC, Nu bn mun hc AVR m khng c iu kin hoc kinh nghim lm cc mch pht trin hoc bn mun kim tra chng trnh trc khi np vo mch pht trin th Protues l mt la chn khng th b qua. - Hng n s dng phn mn Protues. Khi ng chng trnh Start> All Program> Proteus 6 pro fessional> ISIS 6 Progessional

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Chng trnh khi ng vi giao din nh sau.

Giao din chng trinh. Thanh thc n: Bao gm cc Menu quen thuc nh File, View, Edil Ta c th thc hin hu ht cc lnh ca ISIS ti ay (tr cc lnh ca thanh cng cu).

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Thanh tc v: Cha cc s lnh ca thanh trnh n dng Shortcut nh New, Save, Open v cc nt sau. Cc ni m phng:

Vng hin thi: Hin th khi qut vng lm vic hin hnh, khung mu xanh dng biu hin cho ton bn v, khung xanh l biu hin cho phn bn v ang hin th trn vng lm vic chnh. Khi ta chn mt linh kin, k hiu nguyn l ca n cng c hin th ln vng ny. Cc thao tc c bn trong vng lm vic chnh. - Chn i tng: Nhp chut phi ln i tng. - B chn : Nhp chut phi ln vng trng. - Xa i tng : Nhp i chut phi ln i tng. - Di chuyn : Chon, ko r bng chut tri n v tr mi. - a i tng vo gia vng lm vic, ch cn a con tr n v tr v nhn F5, Hoc dng nt Re-center trn thanh tc v.

- Dng bnh xe ca chut phng to hoc thu nh n tng i tng. o F6 phng to o F7 thu nh o F8 xem ton mn hinh. - phng to mt phn mch: shift v ko chn vng cn thao tc (Sht zoom)
-

Shift v r chut n l ca vng lm vic di chuyn n v tr khc (Shift pan), hay n gin hn, hy click ln phn trn vng hin th. S dng th vin ISIS m th vin ISIS ta chn nt Component nhp tri ln nt P (Pick Devices):
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Th vin ISIS c m

Ch : Bn c th tm nhanh n mt th vin bng cch nhp vo vng th vin sau g k t u tin ca tn th vin (nu c hn 1 th vin cng k t u th bn cn nhn n khi gp ng th vin cn) Tng t th cho vng cc linh kin. Ta ln lt nhp i vo cc linh kin cn dng , cc linh kin ny s xut hin vng thit b. Khi ly linh kin, bm close ng th vin. Trn vng la chn, nhp tri chn linh kin, sau nhp tri ln vng lm vic t ln mch.

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Trong khi ang chn linh kin, ta c th s dng cc nt xoay cc gc o 90 , v cc nt ly i xng ngang, dc cho linh kin. Ngoi ra, ISIS cn h tr cng c tm kim linh kin kh nhanh. Trong lc anh v mch, bn bm phm P xut hin ca s Pick/Replace library Prat:

Trong ca s Pick/Replace library Prat ta c cc chn la sau:

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Sau khi chn cc thng s, bn nhp tn hoc mt phn tn linh kin vo Name or text to search for, cc linh kin tm thy s hin th lp tc trong khung Matches. Nhp chn linh kin bn cn, sau nhp OK linh kin s xut hin trong vng lu chn.

IC 555 c xut hin trong khung lu chn linh kin.

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3.3.2 M phng iu khin LED 7 on. - Chn linh kin. Trong dialog Pick Divices, keywords nhp atmega128, bn s thy mt linh kin c tn l ATMEGA128 bn ca s Results, double click vo linh kin mang vo ca s Object selector

Tng t ta ly cc linh kin RES: in tr, ly leb 7 on ta dng t kho 7SEG

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Sau khi chn linh kin cn thit hy nhn Ok v quay v ca s chinh. Khi bn s thy ca s Object selection nh sau.

Chng t c mnh hon chnh nh sau.

- Np chng trnh v m phng. chng trnh vo chp ATmega128: Hy hin ca s thuc tnh vo chp ATmega128, trong Program file hy kick v tm file .hex ma bn to m phng.

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- Cui cng ta c mach m phng. S dng thanh cng c Play chy m phng mch in ca bn, Kt qu nh sau.

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Kt Lun
Trong thi gian thc tp nghin cu v lm n thc tp chuyn ngnh, em hon thnh c cng vic c giao. C th em t c nhng kt qu sau y. - Tm hiu tng qut Vi iu khin AVR, c th l AVR ATmega128 - Tm hiu c ngn ng lp trnh Assmebly cho AVR - Thit k c chng trnh n gin iu khin LED 7 on. - Mch m phng chng trnh iu khin LED 7 on. Ti khin tham kho. - Vi iu khin AVR ATmega128 - Internet http://www.scribd.com http://www.hocavr.com/ http://Google.com.vn

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