A .

GII THIU V VI IU KHIN 89S52

1. Tng quan v 89S52
AT89S52 l h IC vi iu khin do hng Atmel sn xut. Cc sn phm AT89S52 thch hp cho nhng ng dng iu khin. Vic x l trn byte v cc ton s hc cu trc d liu nh c thc hin bng nhiu ch truy xut d liu nhanh trn RAM ni. Tp lnh cung cp mt bng tin dng ca nhng lnh s hc 8 bit gm c lnh nhn v lnh chia. N cung cp nhng h tr m rng trn chip dng cho nhng bin mt bit nh l kiu d liu ring bit cho php qun l v kim tra bit trc tip trong h thng iu khin. AT89S52 cung cp nhng c tnh chun nh: 8 KByte b nh ch c c th xa v lp trnh nhanh (EPROM), 128 Byte RAM, 32 ng I/O, 3 TIMER/COUNTER 16 Bit, 5 vect ngt c cu trc 2 mc ngt, mt Port ni tip bn song cng, 1 mch dao ng to xung Clock v b dao ng ON-CHIP. Cc c im ca chip AT89S52 c tm tt nh sau: 8 KByte b nh c th lp trnh nhanh, c kh nng ti 1000 chu k ghi/xo Tn s hot ng t: 0Hz n 24 MHz 3 mc kha b nh lp trnh 3 b Timer/counter 16 Bit 128 Byte RAM ni. 4 Port xut /nhp I/O 8 bit. Giao tip ni tip. 64 KB vng nh m ngoi 64 KB vng nh d liu ngoi.

4 s cho hot ng nhn hoc chia

S khi ca AT89S52

2. M t chn 89S52
2.1. S chn 89S52 Mc d cc thnh vin ca h d 8751, 89S52, 89C51, DS5000) u c cc kiu ng v khc nhau, chng Line Pakage), dng v dt vung QPF (Quad Flat Pakage) v dng chip khng c chn LLC (Leadless Chip Carrier) th chng u c 40 chn cho cc chc nng khc nhau nh vo ra I/O, c RD , ghi WR , a ch, d liu v ngt. Cn phi lu mt hng cung cp mt phin bn 8051 c 20 chn s vi s cng hn nh hai hng chn DIP (Dual In8051(v

vo ra t hn cho cc ng dng yu cu thp hn. Tuy nhin v hu ht cc nh pht trin s dng chp ng v 40 chn vi hai hng chn DIP nn ta ch tp trung m t phin bn ny. 2.2. Chc nng ca cc chn 89S52 Port 0: t chn 32 n chn 39 (P0.0 _P0.7). Port 0 c 2 chc nng: trong cc thit k c nh khng dng b nh m rng n c chc nng nh cc ng IO, i vi thit k ln c b nh m rng n c kt hp gia bus a ch v bus d liu. Port 1: t chn 1 n chn 9 (P1.0 _ P1.7). Port 1 l port IO dng cho giao tip vi thit b bn ngoi nu cn. Port 2: t chn 21 n chn 28 (P2.0 _P2.7). Port 2 l mt port c tc dng kp dng nh cc ng xut/nhp hoc l byte cao ca bus a ch i vi cc thit b dng b nh m rng. Port 3: t chn 10 n chn 17 (P3.0 _ P3.7). Port 3 l port c tc dng kp. Cc chn ca port ny c nhiu chc nng, c cng dng chuyn i c lin h n cc c tnh c bit ca 89S52 nh bng sau:

AT89S52

Bit P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7

Tn RXD TXD INT0 INT1 T0 T1 WR RD

Chc nng chuyn i Ng vo d liu ni tip. Ng xut d liu ni tip. Ng vo ngt cng th 0. Ng vo ngt cng th 1. Ng vo TIMER/ COUNTER th 0. Ng vo ca TIMER/ COUNTER th 1. Tn hiu ghi d liu ln b nh ngoi. Tn hiu c b nh d liu ngoi.

PSEN (Program store enable): PSEN l tn hiu ng ra c tc dng cho php c b nh chng trnh m rng v thng c ni n chn OE ca Eprom cho php c cc byte m lnh. PSEN mc thp trong thi gian 89S52 ly lnh. Cc m lnh ca chng trnh c c t Eprom qua bus d liu, c cht vo thanh ghi lnh bn trong 89S52 gii m lnh. Khi 89S52 thi hnh chng trnh trong ROM ni, PSEN mc cao. ALE (Address Latch Enable): Khi 89S52 truy xut b nh bn ngoi, Port 0 c chc nng l bus a ch v d liu do phi tch cc ng d liu v a ch. Tn hiu ra ALE chn th 30 dng lm tn hiu iu khin gii a hp cc ng a ch v d liu khi kt ni chng vi IC cht. Tn hiu chn ALE l mt xung trong khong thi gian port 0 ng vai tr l a ch thp nn cht a ch hon ton t ng.

EA (External Access): Tn hiu vo EA (chn 31) thng c mc ln mc 1 hoc mc 0. Nu mc 1, 89S52 thi hnh chng trnh t ROM ni. Nu mc 0, 89S52 thi hnh chng trnh t b nh m rng. Chn EA c ly lm chn cp ngun 21V khi lp trnh cho Eprom trong 89S52. RST (Reset): Khi ng vo tn hiu ny a ln mc cao t nht 2 chu k my, cc thanh ghi bn trong c np nhng gi tr thch hp khi ng h thng. Khi cp in mch phi t ng reset. Cc gi tr t v in tr c chn l: R1=10, R2=220, C=10 F. Cc ng vo b dao ng X1, X2: B to dao ng c tch hp bn trong Khi s dng 89S52, ngi ta ch cn ni thm anh v cc t. Tn s thch anh ty thuc vo ch ca ngi s dng, gi tr t thng chn l 33p. 89S52. thch mc c

3. T chc b nh bn trong 89S52

B nh trong 89S52 bao gm ROM v RAM. RAM trong 89S52 bao gm nhiu thnh phn: phn lu tr a dng, phn lu tr a ch ha tng bit, cc bank thanh ghi v cc thanh ghi chc nng c bit. AT89S52 c b nh c t chc theo cu trc Harvard: c nhng vng b nh ring bit cho chng trnh v d liu. Chng trnh v d liu c th cha bn trong 89S52 nhng 89S52 vn c th kt ni vi 64K byte b nh chng trnh v 64K byte d liu bn ngoi.

a ch byte

Bn b nh Data bn trong a ch 89S52 c t chc nh sau: Chip

a ch bit
byte

a ch bit

RAM bn trong AT89S52 c phn chia nh sau:

 Cc bank thanh ghi c a ch t 00H n 1FH. RAM a ch ha tng bit c a ch t 20H n 2FH. RAM a dng t 30H n 7FH. Cc thanh ghi chc nng c bit t 80H n FFH 3.1. RAM a dng RAM a dng c a ch t 30h 7Fh c th truy xut mi ln 8 bit bng cch dng ch nh a ch trc tip hay gin tip. Cc vng a ch thp t 00h 2Fh cng c th s dng cho mc ch nh trn, ngoi cc chc nng c bit c cp phn sau. 3.2. RAM c th nh a ch bit Vng a ch t 20h -2Fh gm 16 byte c th thc hin nh vng RAM a dng (truy xut mi ln 8 bit) hay thc hin truy xut mi ln 1 bit bng cc lnh x l bit. 3.3. Cc bank thanh ghi Vng a ch 00h 1Fh c chia thnh 4 bank thanh ghi: bank 0 t 00h 07h, bank 1 t 08h 0Fh, bank 2 t 10h 17h v bank 3 t 18h 1Fh. Cc bank thanh ghi ny c i din bng cc thanh ghi t R0 n R7. Sau khi khi ng th h thng bank 0 c chn s dng. Do c 4 bank thanh ghi nn ti mt thi im ch c mt bank thanh ghi c truy xut bi cc thanh ghi R0 n R7. Vic thay i bank thanh ghi c thc hin thng qua thanh ghi t trng thi chng trnh (PSW). 3.4. Cc thanh ghi c chc nng c bit Cc thanh ghi trong 89S52 c nh dng nh mt phn ca RAM trn chip v vy mi thanh ghi s c mt a ch (ngoi tr thanh ghi b m chng trnh v thanh ghi lnh v cc thanh ghi ny him khi b tc ng trc tip). Cng nh R0 n R7, 89S52 c 21 thanh ghi c chc nng c bit (SFR: Special Function Register) vng trn ca RAM ni t a ch 80H n 0FFH.

Sau y l mt vi thanh ghi c bit thng c s dng: 3.4.1. Thanh ghi trng thi chng trnh (PSW: Program Status Word) BIT PSW.7 PSW.6 PSW.5 PSW4 PSW.3 SYMBOL CY AC F0 RS1 RS0 ADDRESS D7H D6H D5H D4H D3H Cary Flag Auxiliary Cary Flag Flag 0 Register Bank Select 1 Register Bank Select 0 00=Bank 0; address 00H 07H 01=Bank 1; address 08H 0FH 10=Bank 2; address 10H 17H 11=Bank 3; address 18H 1FH PSW.2 PSW.1 PSW.0 OV P D2H D1H DOH Overlow Flag Reserved Even Parity Flag DESCRIPTION

Chc nng tng bit trng thi chng trnh - C Carry CY (Carry Flag):C nh thng n c dng cho cc lnh ton hc: C =1 nu php ton cng c s trn hoc php tr c mn v ngc li C = 0 nu php ton cng khng trn v php tr khng c mn. - C Carry ph AC (Auxiliary Carry Flag): Khi cng nhng gi tr BCD

(Binary Code Decimal), c nh ph AC c set nu kt qu 4 bit thp nm trong phm vi iu khin 0AH - 0FH. Ngc li AC = 0 - C 0 (Flag 0): C 0 (F0) l 1 bit c a dng dng cho cc ng dng ca ngi dng. - Nhng bit chn bank thanh ghi truy xut: RS1 v RS0 quyt nh dy thanh ghi tch cc. Chng c xa sau khi reset h thng v c thay i bi phn mm khi cn thit.

Ty theo RS1, RS0 = 00, 01, 10, 11 s c chn Bank tch cc tng ng l Bank 0, Bank1, Bank2 v Bank3.

RS1 0 0 1 1

RS0 0 1 0 1

BANK 0 1 2 3

- C trn OV (Over Flag): C trn c set sau mt hot ng cng hoc tr nu c s trn ton hc. - Bit Parity (P): Bit t ng c set hay Clear mi chu k my lp Parity chn vi thanh ghi A. S m cc bit 1 trong thanh ghi A cng vi bit Parity lun lun chn. V d A cha 10101101B th bit P set ln mt tng s bit 1 trong A v P to thnh s chn. Bit Parity thng c dng trong s kt hp vi nhng th tc ca Port ni tip to ra bit Parity trc khi pht i hoc kim tra bit Parity sau khi thu.

3.4.2. Thanh ghi TIMER Vi iu Khin 89S52 c 3 timer 16 bit, mi timer c bn cch lm vic. Ngi ta s dng cc timer : o nh khong thi gian.
o

m s kin.

o To tc baud cho port ni tip trong 89S52.

Trong cc ng dng nh khong thi gian, ngi ta lp trnh timer nhng khong u n v t c trn timer. C c dng ng b ha chng trnh thc hin mt tc ng nh kim tra trng thi ca cc ng vo hoc gi s kin ra cc ng ra. Cc ng dng khc c th s dng vic to xung nhp u n ca timer o thi gian tri qua gia hai s kin (v d o rng xung). 3.4.3. Thanh ghi ngt (INTERRUPT) Mt ngt l s xy ra mt iu kin, mt s kin m n gy ra treo tm thi thi chng trnh chnh trong khi iu kin c phc v bi mt chng trnh khc. Cc ngt ng mt vai tr quan trng trong thit k v ci t cc ng dng vi iu khin. Chng cho php h thng p ng bt ng b vi mt s kin v gii quyt s kin trong khi mt chng trnh khc ang thc thi. - T chc ngt ca 89S52: C 5 ngun ngt 89S52: 2 ngt ngoi, 2 ngt t timer v 1 ngt port ni tip. Tt c cc ngt theo mc nhin u b cm sau khi reset h thng v c cho php tng ci mt bng phn mm. Mc u tin ca cc ngt c lu trong thanh ghi IP (Interrupt Priority) hay ni cch khc thanh ghi IP cho php chn mc u tin cho cc ngt (gi tr thanh ghi IP khi reset l 00h).

Bit IP.7 IP.6 IP.5

K hiu _ _ ET2

a ch bit _ _ BDH

M t Khng c m t Khng c m t Chn mc u tin cao (=1) hay thp (=0) ti timer 2

IP.4

ES

BCH

Chn mc u tin cao (=1) hay thp (=0) ti cng ni tip.

IP.3

ET1

BBH

Chn mc u tin cao (=1) hay thp (=0) ti timer 1

IP.2

EX1

BAH

Chn mc u tin cao (=1) hay thp (=0) ti ngt ngoi 1

IP.1

ET0

B9H

Chn mc u tin cao (=1) hay thp (=0) ti timer 0

IP.0

EX0

B8H

Chn mc u tin cao (=1) hay thp (=0) ti ngt ngoi 0 Tm tt thanh ghi IP

Nu 2 ngt xy ra ng thi th ngt no c no c mc u tin cao hn s c phc v trc. Nu 2 ngt xy ra ng thi c cng mc u tin th th t u tin c thc hin t cao n thp nh sau: ngt ngoi 0 timer 0 ngt ngoi 1 timer 1 cng ni tip timer 2. Nu chng trnh ca mt ngt c mc u tin thp ang chy m c mt ngt xy ra vi mc u tin cao hn th chng trnh ny tm dng chy mt chng trnh khc c mc u tin cao hn.

- Cho php v cm ngt: Mi ngun ngt c cho php hoc cm ngt qua mt thanh ghi chc nng t bit c nh a ch bit IE (Interrupt Enable: cho php ngt) a ch A8H.

Bit IE.7 IE.6 IE.5 IE.4 IE.3 IE.2 IE.1 IE.0

K hiu EA _ ET2 ES ET1 EX1 ET0 EX0

a ch bit AFH AEH ADH ACH ABH AAH A9H A8H

M t Cho php / Cm ton b Khng c m t Cho php ngt t Timer 2 (8052) Cho php ngt port ni tip Cho php ngt t Timer 1 Cho php ngt ngoi 1 Cho php ngt t Timer 0 Cho php ngt ngoi 0

Tm tt thanh ghi IE - Cc c ngt: Khi iu kin ngt xy ra th ng vi tng loi ngt m loi c c t ln mc cao xc nhn ngt.

Ngt Bn ngoi 0 Bn ngoi 1 Timer 1 Timer 0 Port ni tip Port ni tip

C IE0 IE1 TF1 TF0 TI RI

Thanh ghi SFR v v tr bit TCON.1 TCON.3 TCON.7 TCON.5 SCON.1 SCON.0

Cc loi c ngt - Cc vect ngt: Khi chp nhn ngt, gi tr c np vo PC gi l vector ngt. N l a ch bt u ca ISR cho ngun to ngt, cc vector ngt c cho bng sau : Ngt Reset h thng Bn ngoi 0 Timer 0 Bn ngoi 1 Timer 1 Port ni tip Timer 2 IE0 TF0 IE1 TF1 TI v RI 0003H 000BH 0013H 001BH 0023H 002BH C RST a ch vector 0000H

Vector reset h thng (RST a ch 0000H) c trong bng ny v theo ngha ny, n ging ngt: n ngt chng trnh chnh v np cho PC gi tr mi.

B. IC ghi dch 74HC595 .

Hnh dng thc t:

1, Chc nng : L ic ghi dch 8bit kt hp cht d liu , u vo ni tip u ra song song . Chc nng: Thng dng trong cc mch qut led 7 , led matrix tit kim s chn VDK ti a (3 chn) . C th m rng s chn vi iu khin bao nhiu ty thch bng vic mc ni tip u vo d liu cc ic vi nhau . 2,S chn: Gii thch ngha hot ng ca mt s chn quan trng: Chn 14 : u vo d liu ni tip . Ti 1 thi im xung clock ch a vo c 1 bit QA=>QH : trn cc chn (15,1,2,3,4,5,6,7)

 Xut d liu khi chn chn 13 tch cc mc thp v c mt xung tch cc sn m ti chn cht 12 Chn 13 : Chn cho php tch cc mc thp (0) .Khi mc cao, tt c cc u ra ca 74595 tr v trng thi cao tr, khng c u ra no c cho php. Chn 9: Chn d liu ni tip . Nu dng nhiu 74595 mc ni tip nhau th chn ny a vo u vo ca con tip theo khi dch 8bit. Chn 11: Chn vo xung clock . Khi c 1 xung clock tch cc sn dng(t 0 ln 1) th 1bit c dch vo ic. Chn 12 : xung clock cht d liu . Khi c 1 xung clock tch cc sn dng th cho php xut d liu trn cc chn output . lu c th xut d liu bt k lc no bn mun ,v d u vo chn 14 dc 2 bit khi c xung clock chn 12 th d liu s ra chn Qa v Qb (ch chiu dch d liu t Qa=>Qh) Chn 10: khi chn ny mc thp(mc 0) th d liu s b xa trn chip) S hot ng ca chp :

3, Bng thng s chip:

y l ic u ra hot ng 2 mc 0 &1 dng ra tm 35mA . in p hot ng <=7V . Cng sut trung bnh 500m Da vo bng tnh ton c cc thng s khi thit k mch

4, Tn s p ng:

Ti 6V th tn s vo p ng khong 400ns . Da vo chng ta se a c ra tn s qut hp l.

6, Cu to chip :

+ Nguyn tc hot ng: Khi a mt bt d liu vo u vo Serial Input (chn 14) cn c mt xung t thp ln cao trn chn SCK (chn 11). Khi bt d liu ny s c dch vo trong thanh ghi dch (8-stage shift register). Khi dch 8 bt v c 1 xung t thp ln cao trn chn RCK (chn 12) th 8 bt d liu s c cht vo thanh ghi cha (8-bit storage register). ng thi 8 bt d liu ny vn tn ti trong thanh ghi dch. Khi d liu c cht vo thanh ghi cha m chn G (chn 13) mc thp th d liu ny s c y vo vng m 3 trng thi v d liu s xut hin u ra song song QAQH Chn SCLR dng xa thanh ghi dch, nu SCLR mc thp, ni dung ca thanh ghi dch s b xa. Khi trong thanh ghi dch 8 bt m a thm vo bt th 9 th bt u tin s b y ra u ra QH v bt th 9 s nhy vo thanh ghi dch.

C. GII THIU V MA TRN LED

a. Cu to _ Ma trn led bao gm nhiu led n b tr thnh hng v ct trong mt v. Cc tn hiu iu khin ct c ni vi Anode trn tt c cc led trn cng mt ct. Cc tn hiu iu khin hng cng c ni vi Cathode ca tt c cc led trn cng 1 hng nh hnh v :

b. C s l thuyt Da trn nguyn tc qut hnh, ta c th thc hin vic hin th ma trn n bng cch qut theo ct. Mi led trn ma trn LED c th coi nh mt im nh. a ch ca mi im nh ny c xc nh ng thi bi b m hng v b m ct, im nh ny s c xc nh trng nh d liu a ra t b vi iu khin 89C51. Nh vy ti mi thi im ch c trng thi ca mt im nh c xc nh. Tuy nhin khi xc nh a ch v trng thi ca im nh tip theo th cc im nh cn li s chuyn v trng thi tt (nu led sng th s tt dn ). V th hin th c ton b hnh nh ca ma trn LED, ta c th qut ma trn nhiu ln vi tc qut rt ln, ln hn nhiu ln so vi thi gian kp tt ca n. Mt ngi ch nhn bit c ti a 24hnh/s do nu tc qut rt ln th s khng nhn ra c s thay i nh ca led m s thy c ton b hnh nh cn hin th. c. Nguyn l hot ng Khi c mt tn hiu iu khin ct v hng, cc chn Anode ca cc led trn ct tng ng c cp in p cao, ng thi cc chn Cathode ca cc led trn hng tng ng c cp in p thp. Tuy nhin lc ch c mt led sng, v n c ng thi in th cao trn Anode v in th thp trn Cathode. Nh vy khi c mt tn hiu iu khin hng v ct th ti mt thi im ch c duy nht mt led ti ch gp nhau ca hng v ct l sng. Cc bng quang bo vi s lng led ln hn cng c kt ni theo cu trc nh vy. Trong trng hp ta mun cho sng ng thi mt s led ri rc trn ma trn, hin th mt k t no , nu trong hin th tnh ta phi cp p cao cho Anode v p thp cho Cathode, cho led tng ng m ta mun sng . Nhng khi mt s led ta khng mong mun cng s sng , min l n nm ti v tr gp nhau ca cc ct v hng m ta cp ngun . V vy trong iu khin led ma trn ta khng th s dng phng php hin th tnh m phi s dng phng php qut (hin th ng), c ngha l ta phi tin hnh cp tn hiu iu khin theo dng xung qut trn cc hng v ct cn hin th. cho mt nhn thy cc led khng b nhy , th tn s qut nh nht cho mi chu k l khong 20HZ (50ms). Trong lp trnh iu khin led ma trn bng vi x l ta cng phi s dng phng php qut nh vy. Ma trn led c th l loi ch hin th c mt mu hoc hin th c 2 mu trn mt im , khi led c s chn ra tng ng : i vi ma trn led 8x8 hin th mt mu ,th s chn ra l 16 , trong 8 chn dng iu khin hng v 8 chn cn li dng iu khin ct . i vi loi 8x8 c 2 mu th s chn ra ca

led l 24 chn , trong c 8 chn dng iu khin ct ( hoc hng ) chung cho c hai mu , 16 chn cn li th 8 chn dng iu khin hng ( hoc ct ) mu th nht , 8 chn cn li dung iu khin mu th 2.

D. IC ULN2803
ULN2803 l IC m o c 16 chn trong c 8 ng vo v 8ng ra, doi y l hnh dng v cu to bn trong ca 2803:

B m o dng IC ULN2803 nhm o bt nu ng vo mc cao qua 2803 ra s l mc thp v ngc li. ULN2803 chu ng mc in p t 6V-15V.

E. M t bi ton qut ma trn led

Kt ni AT89S52 vi 3 ma trn LED 8x8 hai mu. Lp trnh hin th ch trn ma trn LED vi hiu ng chy tri 2. nh hng gii quyt a. V mt phn cng Cc chn Anot chung ca 3 ma trn LED c ni chung nhau mt cch tng ng. Cc chn Katot chung ca c 3 ma trn LED s c iu khin ring r. Nh vy sau khi ni 3 ma trn LED 8x8x2 s c mt ma trn LED mi c 8 ng Anot chung v 48 ng Katot chung. Mch m ngun cho ma trn LED ny s dng transistor C945. C 8 ng Anot chung cho nn cn s dng 8 transistor.

Mch m cho cc chn Katot chung s dng thanh ghi dch 74HC595. Mi thanh ghi dch ny c th m c 8 ng Katot chung (1bytes) ca mt ma trn LED v th m cho 3 ma trn LED th cn 6 thanh ghi dch 74HC595. b. V mt phn mm: - To d liu cho vic hin th: + Cn c vo cc im sng ti trn ma trn LED to ra d liu: + D liu ny s c a ra chn Katot ca cc ma trn LED, mc logic 0 th LED sng, mc logic 1 th LED ti. + V d d liu ca ch E:

Hin th d liu ng yn: Ta t ma trn LED sao cho khi cp ngun vo chn Anot chung th LED sng theo hng. Nh th 4 ma trn ghp li s c 8 hng v 32 ct. S dng phng php qut tng t nh qut LED 7 thanh. Ti mt thi im ch c 1 trong 8 hng c cp ngun cho LED sng, cc hng khc khng c cp. Trnh t qut tin hnh nh sau: a d liu ra cc chn Katot to cc im LED sng ti Cp ngun cho hng tng ng Tr sng trong mt thi gian Ct ngun tt hng tng ng

 Tip tc 4 bc trn vi hng tip theo. Hin th d liu vi cc hiu ng dch tri, phi

Nh th th : Thc t ca cc hiu ng dch tri, phil hin th tnh vi cc d liu khc nhau. D liu hin th c lu trong mt vng nh tm gi l vng Buffer. Cc bc tin hnh to ra hiu ng dch tri nh sau: Hin th tnh d liu hin ti ra ma trn LED Tr sng trong mt thi gian Dch ton b d liu trong vng Buffer sang tri mt v tr Hin th tnh d liu mi ra ma trn LED Thc hin li t bc 2. Cc bc tin hnh vi hiu ng khc cng tng t, ch khc thut ton cp nht li d liu.

F. Xy dng gii thut chng trnh

a. Hin th d liu ng yn:

b: X l hiu ng.

G. GIAO TIP MY TNH VI VI IU KHIN AT89S52 S dng giao thc truyn thng ni tip b UART ca vi iu khin AT89s52 v s dng chip chuyn i chuyn dng t giao thc UART sang giao thc USB kt ni my tnh qua cng USB. Chp PL2303 l chip chuyn dng chuyn i t UART sang USB, cu ca nh sau:

to n

S khi bn trong PL2303

S chn cng PL2303

Mt s chn quan trng : Chn 1:TXD d liu ra cng ni tip UART ni ti vi iu khin Chn 5:RXD d liu a ti cng ni tip UART ni ti vi iu khin

Chn 20 : cp ngun 5 v cho chip hot ng

Chn 21 : ni ti cc m ca ngun Chn 27,28: ni ti thch anh to dao ng cho chip hot ng 12Mhz Chn 15,6: hai chn d liu ni vo cng USB ca my tnh chuyn i giao tip t USB sang UART.

Thit k mch :
U18 EN1 MOSI1 MISO1 SCK1 MOSI MISO SCK RXD1 TXD1 EN1 MOSI1 MISO1 SCK1 VCC 40 41 42 43 44 1 2 3 5 7 8 9 10 11 12 13 4 14 15 16 17 38 P1.0 (T2) P1.1 (T2 EX)P1.1 (T2 EX) P1.2 P1.3 P1.4 (MOSI) P1.5 (MISO) P1.6 (SCK) P1.7 (RXD) P3.0 (TXD) P3.1 (INT0) P3.2 (INT1) P3.3 (T0) P3.4 (T1) P3.5 (WR) P3.6 (RD) P3.7 RST XTAL2 XTAL1 GND GND VCC AT89s52TQFP EA/VPP ALE/PROG PSEN NC NC NC 29 27 26 39 6 28 VCC P0.0 (AD0) P0.1 (AD1) P0.2 (AD2) P0.3 (AD3) P0.4 (AD4) P0.5 (AD5) P0.6 (AD6) P0.7 (AD7) P2.7 (A15) P2.6 (A14) P2.5 (A13) (A12) P2.4 (A11) P2.3 (A10) P2.2 (A9) P2.1 (A8) P2.0 37 36 35 34 33 32 31 30 25 24 23 22 21 20 19 18

VCC VCC 19 1 2 3 4 5 6 7 8 9 10 GND U17 OE DIR A1 A2 A3 A4 A5 A6 A7 A8 GND 74HC245AD VCC B1 B2 B3 B4 B5 B6 B7 B8 VCC 20 18 17 16 15 14 13 12 11 R2 1K R3 1K

GND

SCL SDA

L B4 B3 B2 B1

OE DATA LATCH CLOCK

D2 R18 1K LED L RESET XT1 XT2 GND VCC

Mch chp ch v m u ra iu khin ma trn led

12MHz 1 OSC2 OSC1 PLL_TEST GND_PLL VDD_PLL LD_MODE TRI_MODE GND1 VDD1 RESET GND_3V3 VDD_3V3 DM DP 28 27 26 25 24 23 22 21 20 19 18 17 16 15 Y1C1 10p

U19

GND

RXD1 +5 TXD1

1 2 3 4 5 6 7 8 9 10 11 12 13 14

TXD DTR_N RTS_N VDD_232 RXD RI_N GND VDD DSR_N DCD_N CTS_N SHTD_N EE_CLK EE_DATA
PL2303

2 C210p VCC +5 C4 0.1u R6 27 R7 27 R8GND 1.5K VCC DD+ C3 0.1u GND

GND 1 2 3 4 J3 GND

USB Interface

Mch chuyn i t USB sang UART dng chip PL2303

GND C5 22p C6 22p VCC GND 2 XT1 Y2 xxxMHz XT2 R12 8k2 RESET C7 10uF J4 GND VCC RESET SCK MISO MOSI 1 2 3 4 5 6 JUMPER 6

Reset, Clock & Programmer

Hinh 1 Mch to dao ng v mch reset

U1 13 OE VCC 12 RCLK QA 10 VC C SR C L R Q B C L OC K 11 SR C L K Q C QD DA T A1 14 SE R QE QF QG QH 8 G ND G ND QH' U4 OE 1 3 7 4 H C 59 5 B 1 R OE VCC L AT CH 12 RCLK QA 10 VC C SR C L R Q B C L OC K 11 SR C L K Q C QD DA T A0 14 SE R QE QF QG QH 8 G ND G ND QH' OE L AT CH 7 4 H C 59 5 B 1 R

16 15 1 2 3 4 5 6 7 9 16 15 1 2 3 4 5 6 7 9

VC C 1 2 3 4 5 6 7 8 DAT A2 9 VC C G ND 1 2 3 4 5 6 7 8 DAT A1 9 G ND

U2 IN 1 IN 2 IN 3 IN 4 IN 5 IN 6 IN 7 IN 8 O UT 1 O UT 2 O UT 3 O UT 4 O UT 5 O UT 6 O UT 7 O UT 8 18 17 16 15 14 13 12 11 10 18 17 16 15 14 13 12 11 10 VC C VC C U3 11 8 5 2 14 17 20 23 10 7 4 1 15 18 21 24 22 C 8G H1 19 C 7G H2 16 C 6G H3 13 C 5G H4 3 C 4G H5 6 C 3G H6 9 C 2G H7 12 C 1G H8 C 8R C 7R 8X8 - 60M M C 6R 2C OL O UR C 5R C 4R C 3R C 2R C 1R M a t ri x -8 x 8 -6 0 m m -2 c o l o u r H2 Q2

VC C H1

GND COM D U L N 2 8 0 3A 5 IN 1 IN 2 IN 3 IN 4 IN 5 IN 6 IN 7 IN 8 O UT 1 O UT 2 O UT 3 O UT 4 O UT 5 O UT 6 O UT 7 O UT 8

Q1

VC C

GND COM D U L N 2 8 0 3A

U6 OE L AT CH 13 OE VCC 12 RCLK QA 10 VC C SR C L R Q B C L OC K 11 SR C L K Q C QD DA T A3 14 SE R QE QF QG QH 8 G ND G ND QH' U9 OE 1 3 7 4 H C 59 5 B 1 R OE VCC L AT CH 12 RCLK QA 10 VC C SR C L R Q B C L OC K 11 SR C L K Q C QD DA T A2 14 SE R QE QF QG QH 8 G ND G ND QH' 7 4 H C 59 5 B 1 R U11 13 OE VCC 12 RCLK QA 10 VC C SR C L R Q B C L OC K 11 SR C L K Q C QD DA T A5 14 SE R QE QF QG QH 8 G ND G ND QH' U14 OE 1 3 7 4 H C 59 5 B 1 R OE VCC L AT CH 12 RCLK QA 10 VC C SR C L R Q B C L OC K 11 SR C L K Q C QD DA T A4 14 SE R QE QF QG QH 8 G ND G ND QH' OE L AT CH 7 4 H C 59 5 B 1 R G ND U16 OE L AT CH 13 OE VCC 12 RCLK QA 10 VC C SR C L R Q B C L OC K 11 SR C L K Q C QD DA T A 14 SE R QE QF QG QH 8 G ND QH' GND 7 4 H C 59 5 B 1 R VCC 16 15 H1 1 H2 2 H3 3 H4 4 H5 5 H6 6 H7 7 H8 9 DAT A0 16 15 1 2 3 4 5 6 7 9 16 15 1 2 3 4 5 6 7 9 VC C 1 2 3 4 5 6 7 8 DAT A4 VC C G ND 1 2 3 4 5 6 7 8 DAT A3 9 G ND 16 15 1 2 3 4 5 6 7 9 16 VC C G ND 1 2 3 4 5 6 7 8 9 VC C 1 2 3 4 5 6 7 8 9 15 1 2 3 4 5 6 7 9 DAT A5 9 U7 IN 1 IN 2 IN 3 IN 4 IN 5 IN 6 IN 7 IN 8 O UT 1 O UT 2 O UT 3 O UT 4 O UT 5 O UT 6 O UT 7 O UT 8 18 17 16 15 14 13 12 11 10 18 17 16 15 14 13 12 11 10 VC C VC C H3 U8 11 8 5 2 14 17 20 23 10 7 4 1 15 18 21 24 22 C 8G H1 19 C 7G H2 16 C 6G H3 13 C 5G H4 3 C 4G H5 6 C 3G H6 9 C 2G H7 12 C 1G H8 C 8R C 7R 8X8 - 60M M C 6R 2C OL O UR C 5R C 4R C 3R C 2R C 1R M a t ri x -8 x 8 -6 0 m m -2 c o l o u r H6

VC C Q3

VC C H4

Q4

GND COM D U L 0N 2 8 0 3A 1 IN 1 IN 2 IN 3 IN 4 IN 5 IN 6 IN 7 IN 8 O UT 1 O UT 2 O UT 3 O UT 4 O UT 5 O UT 6 O UT 7 O UT 8

VC C H5 Q5

VC C Q6

GND COM D U L N 2 8 0 3A

U12 IN 1 IN 2 IN 3 IN 4 IN 5 IN 6 IN 7 IN 8 O UT 1 O UT 2 O UT 3 O UT 4 O UT 5 O UT 6 O UT 7 O UT 8 18 17 16 15 14 13 12 11 10 18 17 16 15 14 13 12 11 10 VC C V C CV C CV C C VCC R1 R4 R5 R 9 1K 1K 1K 1K OE L AT CH C L OCK DAT A VC C H7 11 8 5 2 14 17 20 23 10 7 4 1 15 18 21 24 U13 22 C 8G H1 19 C 7G H2 16 C 6G H3 13 C 5G H4 3 C 4G H5 6 C 3G H6 9 C 2G H7 12 C 1G H8 C 8R C 7R 8X8 - 60M M C 6R 2C OL O UR C 5R C 4R C 3R C 2R C 1R

VC C Q7

VC C H8 Q8

GND COM D U L 5N 2 8 0 3A 1 IN 1 IN 2 IN 3 IN 4 IN 5 IN 6 IN 7 IN 8 O UT 1 O UT 2 O UT 3 O UT 4 O UT 5 O UT 6 O UT 7 O UT 8

M a t ri x -8 x 8 -6 0 m m -2 c o l o u r

GND COM D U L N 2 8 0 3A

Mch ng lc led ma trn

H. CHNG TRNH LP TRNH

//--------------------------------------------------/************* Hm ngat *********************************** void main (void) /=================================================== void{ ngat_noi_tiep(void) interrupt 4 using 0 #include <regx52.h> unsigned { enable=0; char toltal [7]={0x55,0x00,0x55,0x00,0xff,0x55,0x00}; #define latch P1_6 char if (RI) ES=1;code temp[8]={0x80,0x40,0x20,0x10,0x08,0x04,0x02,0x01}; #define data1 P1_5 //---------------------------------------------------------{ EA=1; #define clock P1_7 unsigned if (SBUF=='*'){count_data=0;} uart_init(); char data_pc[80]={" ***DIEN TU HUY HOANG*** "}; #define enable P1_4 elseunsigned char data_convert[24]; while(1)code NUM[]={ // bang ma du lieu char unsigned char count_data=31,bien24,speed=1; { { 0xFF, 0xDF, 0xAB, 0xAB, 0xAB, 0x87,//a unsigned if (SBUF!='#')int origin; HienThi(speed); 0xB7, 0xBB, 0xBB, 0xC7,//b 0xFF, 0x80, unsigned char colour=0; { //putchar(8) //---------------------------------------------------0xFF, 0xC7, 0xBB, 0xBB, 0xBB, 0xDF,//c //---------------------------------------------------------if (SBUF !='>') void}HienThi(unsigned char speed) 0xFF, 0xC7, 0xBB, 0xBB, 0xB7, 0x80,//d {{ } 0xFF, 0xC7, 0xAB, 0xAB, 0xAB, 0xE7,//e unsigned char m,k,t,n; void delay(unsigned SBUF; data_pc[count_data] = int x) //--------------------------------------------------for (origin=0;origin<count_data*6;origin++) 0xFE, 0xFD,//f 0xFF, 0xF7, 0x81, 0xF6, { {count_data++; 0xFF, 0xF3, 0xAD, 0xAD, 0xAD, 0xC3,//g while (x--){;} } Lay24Byte(origin); ; 0xFF, 0x80, 0xF7, 0xFB, 0xFB, 0x87,//h } for}(n=0;n<speed;n++) { P2_5=~P2_5; 0xFF, 0xFF, 0xBB, 0x82, 0xBF, 0xFF,//i //---------------------------------------------------------} for (bien24=0;bien24<24;bien24++) 0xFF, 0xDF, 0xBF, 0xBB, 0xC2, 0xFF,//j { void Lay24Byte(unsigned int point) if (SBUF=='#') speed ++; 0xFF, 0x80, 0xEF, 0xD7, 0xBB, 0xFF,//k { if (speedtoltal[4]=~data_convert[bien24]; >10) speed =1; //--------------------------------0xFF, 0xFF, 0xBD, 0x81, 0xBF, 0xFF,//l unsigned char i,k,l=0; if (SBUF =='>')colour ++; if (colour==0) 0xFF, 0x83, 0xFB, 0xE7, 0xFB, 0x87,//m { unsigned char m if (colour>2)colour=0; = point%6; // byte con lai 0xFF, 0x83, 0xF7, 0xFB, 0xFB, 0x87,//n if (bien24<8){toltal[1]=temp[bien24%8];toltal[0]=toltal[2]=toltal[3]=toltal[5]=toltal[6]=0;} unsigned char n = point/6; // du lieu da lay } if (bien24>=8 0xC7, 0xBB, 0xBB, 0xBB, 0xC7,//o 0xFF, & bien24<16){toltal[3]=temp[bien24%8];toltal[1]=toltal[0]=toltal[2]=toltal[5]=toltal[6]=0;} //-------------------RI=0; if (bien24>=16 & bien24<24){toltal[6]=temp[bien24%8];toltal[1]=toltal[2]=toltal[3]=toltal[0]=toltal[5]=0;} 0xFF, 0x83, 0xEB, 0xEB, 0xEB, 0xF7,//p } for (k=m;k<6;k++) } 0xFF, 0xF7, 0xEB, 0xEB, 0xE7, 0x83,//q else { //----------------------------------------------------) (colour==1) 0xFF, 0x83,if0xF7, 0xFB, 0xFB, 0xF7,//r data_convert[l]=NUM[(data_pc[n]-32)*6+k];truyen thong void uart_init(){ // Ham thiet lap { 0xFF, 0xB7, 0xAB, 0xAB, 0xAB, 0xDF,//s if (bien24<8){toltal[0]=temp[bien24%8];toltal[1]=toltal[2]=toltal[3]=toltal[5]=toltal[6]=0;} l++; TMOD = 0x20; // Thiet lap Timer1, che do 2 tu nap. 0xFF, 0xF7, 0xC1, 0xB7, 0xBF, 0xDF,//t if (bien24>=8 & bien24<16){toltal[2]=temp[bien24%8];toltal[1]=toltal[0]=toltal[3]=toltal[5]=toltal[6]=0;} } TH1 = -(0x05); // Thiet lap bau rate = 9600 if (bien24>=16 & bien24<24){toltal[5]=temp[bien24%8];toltal[1]=toltal[2]=toltal[3]=toltal[0]=toltal[6]=0;} 0xFF, 0xC3, 0xBF, 0xBF, 0xDF, 0x83,//u n++; =A 0x50;} SCON // 8bit du lieu, 1 start,1 stop 0xFF, 0xE3, 0xDF, 0xBF, 0xDF, 0xE3,//v else //-------------------TR1 = 1; // Khoi dong bo tao clock (timer 1) 0xFF, 0xC3, 0xBF,if0xCF, 0xBF, 0xC3,//w (colour==2) for (i=0;i<3;i++) } 0xFF, 0xBB, 0xD7, {0xEF, 0xD7, 0xBB,//x { //---------------------------------------------------if 0xFF, 0xf3,(bien24<8){toltal[0]=toltal[1]=temp[bien24%8];toltal[2]=toltal[3]=toltal[5]=toltal[6]=0;} 0xAF, 0xAF, 0xC3, 0xFF,//y if for (k=0;k<6;k++) void putchar(char a){ (bien24>=8 & bien24<16) 0xFF, 0xBB, 0x9B, 0xAB, 0xB3, 0xBB,//z {toltal[2]=toltal[3]=temp[bien24%8];toltal[1]=toltal[0]=toltal[5]=toltal[6]=0;} {TI=0; if (bien24>=16 & bien24<24) data_convert[l]=NUM[(data_pc[n]-32)*6+k]; SBUF= a; {toltal[5]=toltal[6]=temp[bien24%8];toltal[1]=toltal[2]=toltal[3]=toltal[0]=0;} if (n>=count_data)data_convert[l]=255; while (!TI){}; // Neu co }TI =0 thi dung lai }; l++; 0; //--------------------------------- TI TI = // Xoa co //enable=1; } } for (k=0;k<7;k++) { n++; } t=toltal[k]; for (m=0;m<8;m++) //-------------------{
data1=t&0x01;t=t>>1; clock=0;clock=1; } } latch=0;latch=1; // enable=0;