Giao Trinh Vi Dieu Khien Pic 16F877A

Gio trnh Vi i u Khi n
M CL C
CHNG 1: T NG QUAN V VI I U KHI N PIC 16F877A .................2
1. T NG QUAN V H VI I U KHI N PIC ..................................................................2 2. GI I THI U V PIC16F8XX v PIC16F877A ...............................................................4
CHNG 2: T CH C B NH - CC THANH GHI CH C NNG ..... 6

2.1. S CHN VI I U KHI N PIC16F877A .............................................................7 2.2. M T VI THNG S V VI I U KHI N PIC16F877A.........................................9 2.3. S KH I VI I U KHI N PIC16F877A .............................................................11 2.4. T CH C B NH ......................................................................................................12 2.4.1. B NH CHNG TRNH .............................................................................12 2.4.2. B NH D LI U ...........................................................................................13 2.5. CC THANH GHI NNG C BI T .......................................................................14 2.6. STACK ...........................................................................................................................16
CHNG 3: T P L NH - C U TRC CHNG TRNH..........................17

3.1. T P L NH .....................................................................................................................17 3.1.1. NHM L NH DI CHUY N ............................................................................17 3.1.2. NHM L NH S H C ....................................................................................18 3.1.3. NHM L NH LOGIC .....................................................................................19 3.1.4. NHM L NH R NHNH ..............................................................................22 3.2. T O TR B NG DNG L P ......................................................................................25 3.3. C U TRC CHNG TRNH .....................................................................................26 3.4. CC KH I GIAO TI P .................................................................................................31 3.4.1. GIAO TI P V I LED 7 OAN .........................................................................31 3.4.2 GIAO TI P V I BN PHM HEX ...................................................................35 3.4.3 GIAO TI P V I LED MA TR N .....................................................................37 3.4.4 GIAO TI P V I LCD ........................................................................................40
CHNG 4: CC KH I CH C NNG .......................................................46

4.1.B NH TH I ..............................................................................................................46 4.1.1. TIMER 0 ..............................................................................................................46 4.1.2. TIMER1 ...............................................................................................................49 4.1.3. TIMER2 ...............................................................................................................52 4.2. ADC ..............................................................................................................................53 4.3.PMW_ I U CH R NG XUNG ...........................................................................58
CHNG 5: C NG N I TI P......................................................................67
5.1. USART ...........................................................................................................................67 5.2.CH LM VI C.......................................................................................................68 5.2.1. TRUY N D LI U B T NG B ................................................................68 5.2.2. NH N D LI U B T NG B .....................................................................71
CHNG 6: NG T INTERRUPT ............................................................80

6.1 KHI NI M ....................................................................................................................80 6.2 NG T RB0 ......................................................................................................................82 6.3. NG T PORTB ...............................................................................................................84 6.4. NG T TIMER ...............................................................................................................85 6.5. NG T ADC....................................................................................................................86 6.6. NG T PORT N I TI P ................................................................................................88 * PH L C: GI I THIU L P TRNH CCS ................................ 94
* PH L C: CC THANH GHI CH C NNG ............................ 105
CHNG 1
T NG QUAN V VI I U KHI N PIC

1.1. T NG QUAN V H VI I U KHI N PIC PIC l m t h vi i u khi n RISC c s n xu t b i cng ty Microchip Technology. Dng PIC u tin l PIC1650 c pht tri n b i Microelectronics Division thu c General_Instrument. PIC b t ngu n t ch vi t t t c a Programmable Intelligent Computer (My tnh kh trnh thng minh) l m t s n ph m c a hng General Instruments t cho dng s n ph m u tin c a h l PIC1650. Lc ny, PIC 1650 c dng giao ti p v i cc thi t b ngo i vi cho my ch 16 bit CP1600, v v y, ng i ta cng g i PIC v i tn Peripheral Interface Controller (B i u khi n giao ti p ngo i vi). CP1600 l m t CPU t t, nhng l i km v cc ho t ng xu t nh p, v v v y PIC 8-bit c pht tri n vo kho ng nm 1975 h tr ho t ng xu t nh p cho CP1600. PIC s d ng microcode n gi n t trong ROM, v m c d, c m t RISC cha c s d ng th i b y gi , nhng PIC th c s l m t vi i u khi n v i ki n trc RISC, ch y m t l nh m t chu k my (4 chu k c a b dao ng). Nm 1985 General Instruments bn b ph n vi i n t c a h , v ch s h u m i h y b h u h t cc d n lc qu l i th i. Tuy nhin, PIC c b sung EPROM t o thnh 1 b i u khi n vo ra kh trnh. Ngy nay r t nhi u dng PIC c xu t x ng v i hng lo t cc module ngo i vi tch h p s n (nh USART, PWM, ADC), v i b nh chng trnh t 512 Word 1.1.1 M t s c tnh c a Vi i u khi n PIC n 32K Word.
Hi n nay c kh nhi u dng PIC v c r t nhi u khc bi t v ph n c ng, nhng chng ta c th i m qua m t vi nt nh sau : 8/16 bit CPU, xy d ng theo ki n truc Harvard c s a Flash v ROM c th tu ch n t 256 byte Cc c ng Xu t/ Nh p (I/ O) (m c logic th ng t 0V v i logic 0 v logic 1) 8/16 bit Timer Cc chu n giao ti p n i ti p B chuy n ng b / khung ng b USART i ADC Analog-to-digital converters, 10/12 bit i n 5.5V, ng n 256 Kbyte
B so snh i n p (Voltage Comparator) Cc module Capture/ Compare/ PWM LCD MSSP Peripheral d ng cho cc giao ti p I2C, SPI. B nh n i EPROM c th ghi/ xo l n t i 1 tri u l n Module i u khi n H tr giao ti p USB
2
ng c,
c encoder
H tr giao ti p CAN H tr giao ti p LIN H tr giao ti p IrDA M t s dng c tch h p b RF (PIC16f639, v RFPIC) KEELOQ m ho v gi i m DSP nh ng tnh nng x l tn hi u s (dsPIC) c i m th c thi t c c a RISC CPU c a h vi di u khi n PIC16F87XA : Ch g m 35 l nh n. T t c cc l nh l 1chu k ngo i tr chng trnh con l 2 chu k. T c ho t ng : + DC- 20MHz ng vo xung clock. + DC- 200ns chu k l nh. r ng c a b nh chng trnh Flash l 8K x 14word, c a b nh d li u (RAM) l 368 x 8bytes, c a b nh d li u l EPROM l 256 x 8bytes. c tnh ngo i vi cao
1.1.2. Nh ng
- Timer0 : 8- bit nh th i/ m v i 8- bit prescaler - Timer1 : 16- bit nh th i/ m v i prescaler, c th c tng ln trong su t ch Sleep qua th ch anh/ xung clock bn ngoi. - Timer2 : 8- bit nh th i/ m v i 8- bit, prescaler v postscaler - Hai module Capture, Compare, PWM * Capture c r ng 16 bit, phn gi i 12.5ns * Compare c r ng 16 bit, phn gi i 200ns * phn gi i l n nh t c a PWM l 10bit. - C 13 ng I/O c th i u khi n tr c ti p - Dng vo v dng ra l n : * 25mA dng vo cho m i chn * 20mA dng ra cho m i chn 1.1.3. c i m v tng t - 10 bit, v i 8 knh c a b chuy n i tng t sang s (A/D). - Brown out Reset (BOR). - Module so snh v tng t . * Hai b so snh tng t . * Module i n p chu n VREF c th l p trnh trn PIC. - C th l p trnh ng ra vo n t nh ng ng vo c a PIC v trn i n p bn trong. - Nh ng ng ra c a b so snh c th s d ng cho bn ngoi. 1.1.4. Cc c i m c bi t :
3
- C th ghi/ xo 100.000 l n v i ki u b nh chng trnh Enhanced Flash.
- 1.000.000 ghi/ xo v i ki u b nh EPROM. - EPROM c th lu tr d li u hn 40 nm. - C th t l p trnh l i d i s i u khi n c a ph n m m. - M ch l p trnh n i ti p qua 2 chn. - Ngu n n 5V c p cho m ch l p trnh n i ti p. - Watchdog Timer (WDT) v i b dao ng RC tch h p s n trn Chip cho ho t ng ng tin c y. - C th l p trnh m b o v . - Ti t ki m nng l ng v i ch Sleep. - C th l a ch n b dao ng. - M ch d sai (ICD : In- Circuit Debug) qua 2 chn 1.1.5. Cng ngh CMOS - Nng l ng th p, t c cao Flash/ cng ngh EPROM - Vi c thi t k hon ton tnh -Kho ng i n p ho t ng t 2V n 5.5V -Tiu t n nng l ng th p. 1.2. GI I THI U V PIC16F8XX v PIC16F877A PIC16F8X l nhm PIC trong h PIC16XX c a h Vi i u khi n 8-bit, tiu hao nng l ng th p, p ng nhanh, ch t o theo cng ngh CMOS, ch ng tnh i n tuy t i. Nhm bao g m cc thi t b sau: PIC16F83 PIC16CR83 PIC16F84 PIC16CR84 - T t c cc PIC16/17 u c c u trc RISC. PIC16CXX cc c tnh n i b c, 8 m c ngn x p Stack, nhi u ngu n ng t tch h p bn trong l n ngoi. C c u trc Havard v i cc bus d li u v bus th c thi chng trnh ring bi t nhau cho php di 1 l nh l 14-bit v bus d li u 8-bit cch bi t nhau. T t c cc l nh u m t 1 chu k l nh ngo i tr cc l nh r nhnh chng trnh m t 2 chu k l nh. Ch c 35 l nh v 1 l ng l n cc thanh ghi cho php p ng cao trong ng d ng. - H PIC16F8X c nhi u tnh nng c bi t lm gi m thi u cc thi t b ngo i vi, v v y kinh t cao, c h th ng n i b t ng tin c y v s tiu th nng l ng th p. y c 4 s l a ch n b dao d ng v ch c 1 chn k t n i b dao ng RC nn c gi i php ti t ki m cao. Ch SLEEP ti t ki m ngu n v c th c nh th c b i cc ngu n reset. V cn nhi u ph n khc c gi i thi u bn trn s c ni r cc ph n k ti p. - PIC16F877A c 40/44 chn v i s phn chia c u trc nh sau : + C 5 port xu t/nh p
4
+ C 8 knh chuy n + C 2 b PWM
i A/D 10-bit
+ C 3 b nh th i: Timer0, timer1 v timer2 + C giao ti p truy n n i ti p: chu n RS 232, I2C + C giao ti p LCD
CHNG 2
T CH C B NH - CC THANH GHI CH C NNG

2.1 S CHN VI I U KHI N PIC16F877A
Hnh 2.1: S chn v hnh d ng c a Pc 16F877A
Ch c nng cc chn : Chn 1 Tn /VPP Ch c nng
2 3 4
10
: Ho t ng Reset m c th p - VPP : ng vo p l p trnh - RA0 : xu t/nh p s RA0/AN0 - AN0 : ng vo tng t - RA1 : xu t/nh p s RA1/AN1 - AN1 : ng vo tng t - RA2 : xu t/nh p s RA2/AN2/VREF-/CVREF - AN2 : ng vo tng t - VREF -: ng vo i n p chu n (th p) c a b A/D - RA3 : xu t/nh p s RA3/AN3/VREF+ - AN3 : ng vo tng t - VREF+ : ng vo i n p chu n (cao) c a b A/D - RA4 : xu t/nh p s RA4/TOCKI/C1OUT - TOCKI : ng vo xung clock bn ngoi cho timer0 - C1 OUT : Ng ra b so snh 1 - RA5 : xu t/nh p s RA5/AN4/ /C2OUT - AN4 : ng vo tng t 4 - SS : ng vo ch n l a SPI ph - C2 OUT : ng ra b so snh 2 - RE0 : xu t nh p s RE0/ /AN5 - RD : i u khi n vi c c port nhnh song song - AN5 : ng vo tng t - RE1 : xu t/nh p s RE1/ /AN6 - WR : i u khi n vi c ghi port nhnh song song - AN6 : ng vo tng t - RE2 : xu t/nh p s RE2/ /AN7 - CS : Chip l a ch n s i u khi n port nhnh song song - AN7 : ng vo tng t VDD VSS OSC1/CLKI Chn ngu n c a PIC. Chn n i t
11 12 13
14
OSC2/CLKO
Ng vo dao ng th ch anh ho c xung clock bn ngoi. - OSC1 : ng vo dao ng th ch anh ho c xung clock bn ngoi. Ng vo Schmit trigger khi c c u t o ch RC ; m t cch khc c a CMOS. - CLKI : ng vo ngu n xung bn ngoi. Lun c k t h p v i ch c nng OSC1. Ng vo dao ng th ch anh ho c xung clock - OSC2 : Ng ra dao ng th ch anh. K t n i n th ch anh ho c b c ng h ng.
7
15
RC0/T1 OCO/T1CKI RC1/T1OSI/CCP2
16
17
RC2/CCP1 RC3/SCK/SCL
18
19 20 21 22 23
RD0/PSP0 RD1/PSP1 RD2/PSP2 RD3/PSP3 RC4/SDI/SDA RC5/SDO RC6/TX/CK RC7/RX/DT RD4/PSP RD5/PSP5 RD6/PSP6 RD7/PSP7 VSS
24 25
26
27 28 29 30 31
- CLKO : ch RC, ng ra c a OSC2, b ng t n s c a OSC1 v ch ra t c c a chu k l nh. - RC0 : xu t/nh p s - T1OCO : ng vo b dao ng Timer 1 - T1CKI : ng vo xung clock bn ngoi Timer 1 - RC1 : xu t/nh p s - T1OSI : ng vo b dao ng Timer 1 - CCP2 : ng vo Capture 2, ng ra compare 2, ng ra PWM2 - RC2 : xu t/nh p s - CCP1 : ng vo Capture 1, ng ra compare 1, ng ra PWM1 - RC3 : xu t/nh p s - SCK : ng vo xung clock n i ti p ng b /ng ra c a ch SPI - SCL : ng vo xung clock n i ti p ng b / ng ra c a ch I2C - RD0 : xu t/nh p s - PSP0 : d li u port nhnh song song - RD1 : xu t/nh p s - PSP1 : d li u port nhnh song song - RD2 : xu t/nh p s - PSP2 : d li u port nhnh song song - RD3: xu t/nh p s - PSP3 : d li u port nhnh song song - RC4 : xu t/nh p s - SDI : d li u vo SPI - SDA : xu t/nh p d li u vo I2C - RC5 : xu t/nh p s - SDO : d li u ra SPI - RC6 : xu t/nh p s - TX : truy n b t ng b USART - CK : xung ng b USART - RC7 : xu t/nh p s - RX : nh n b t ng USART - DT : d li u ng b USART - RD4: xu t/nh p s - PSP4 : d li u port nhnh song song - RD5: xu t/nh p s - PSP5 : d li u port nhnh song song - RD6: xu t/nh p s - PSP6 : d li u port nhnh song song - RD7: xu t/nh p s - PSP7 : d li u port nhnh song song Chn n i t
32 33 34 35 36 37 38 39
VDD RB0/INT RB1 RB2 RB3 RB4 RB5 RB6/PGC RB7/PGD
Chn ngu n c a PIC. - RB0 : xu t/nh p s - INT : ng t ngoi xu t/nh p s xu t/nh p s - RB3 : xu t/nh p s - Chn cho php l p trnh i n p th p ICPS - xu t/nh p s - Ng t PortB - xu t/nh p s - Ng t PortB - RB6 : xu t/nh p s - PGC : m ch vi sai v xung clock l p trnh ICSP - Ng t PortB - RB7 : xu t/nh p s - PGD : m ch vi sai v d li u l p trnh ICSP - Ng t PortB
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2.2 M T VI THNG S
V VI I U KHI N PIC16F877A
y l vi i u khi n thu c h PIC16Fxxx v i t p l nh g m 35 l nh c di 14 bit. M i l nh u c th c thi trong m t chu k xung clock. T c ho t ng t i a cho php l 20 MHz v i m t chu k l nh l 200ns. B nh chng trnh 8Kx14 bit, b nh d li u 368x8 byte RAM v b nh d li u EEPROM v i dung l ng 256x8 byte. S PORT I/O l 5 v i 33pin I/O. Cc c tnh ngo i vi bao g mcc kh i ch c nng sau: Timer0: b m 8 bit v i b chia t n s 8 bit. Timer1: b m 16 bit v i b chia t n s , c th th c hi n ch c nng xung clock ngo i vi ngay khi vi i u khi n ho t ng ch sleep. Timer2: b m 8 bit v i b chia t n s , b postcaler. m d a vo
Hai b Capture/so snh/ i u ch rng xung. Cc chu n giao ti p n i ti p SSP (Synchronous Serial Port), SPI v I2C. Chu n giao ti p n i ti p USART v i 9 bit a ch . C ng giao ti p song song PSP (Parallel Slave Port) v i cc chn i u khi n RD, WR, CS bn ngoi. Cc c tnh Analog: 8 knh chuy n i ADC 10 bit. Hai b so snh. Bn c nh l m t vi c tnh khc c a vi i u khi n nh:
9
B nh flash v i kh nng ghi xa c 100.000 l n. B nh EEPROM v i kh nng ghi xa c 1.000.000 l n. D li u b nh EEPROM , c 256 byte (c a ch 00hFFh), c th lu tr trn 40 nm. Kh nng t n p chng trnh v i s i u khi n c a ph n m m. N p c chng trnh ngay trn m ch i n ICSP (In Circuit Serial Programming) thng qua 2 chn. Watchdog Timer v i b dao ng trong. Ch c nng b o m t m chng trnh. Ch Sleep. C th ho t ng v i nhi u d ng Oscillator khc nhau.
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2.3 S
KH I VI I U KHI N PIC16F877A
Hnh 2.2: C u trc bn trong c a Pic 16F877A
Nh ni trn , vi i u khi n PIC c ki n trc Harvard, trong CPU truy c p chng trnh v d li u c trn hai bus ring bi t, nn lm tng ng k bng thng so v i ki n trc Von Neumann trong CPU truy c p chng trnh v d li u trn cng m t bus. Vi c tch ring b nh chng trnh v b nh d li u cho php s bit c a t l nh c th khc v i s bit c a d li u. PIC 16F877A, t l nh di 14 bit , t d li u 8 bit. PIC 16F877A ch a m t b ALU 8 bit v thanh ghi lm vi c WR (working register). ALU l n v tnh ton s h c v logic, n th c hin cc php tnh s v i s Boole trn thanh ghi lm vi c WR v cc thanh ghi d li u. ALU c th th c hi n cc php c ng, tr , d ch bit v cc php ton logic
11
2.4 T
a.B
CH C B
NH
NH
CHNG TRNH
B nh chng trnh c a vi i u khi n PIC16F877A l b nh flash, dung l ng b nh 8K word (1 word = 14 bit) v c phn thnh nhi u trang (t page0 n page 3) .Nh v y b nh chng trnh c kh nngch a c 8*1024 = 8192 l nh (v m t l nh sau khi m ha s c dung l ng 1 word (14bit). m ha c a ch c a 8K word b nh chng trnh, b c dung l ng 13 bit (PC<12:0>). Khi vi i u khi n c reset, b m chng trnh s ch n a ch 0000h (Resetvector). Khi c ng t x y ra, b m chngtrnh s ch n a ch 0004h (Interruptvector). B nh chng trnh khng bao g m b nh stack v khng c b m chng trnh. B nh stack s c c p c th trong ph n sau. a ch ha b i m chng trnh
Hnh 2.3: B nh chng trnh c a Pic

b. B NH D LI U
B nh d li u c a PIC l b nh EEPROM c chia ra lm nhi u bank. i v i PIC16F877A b nh d li u c chia ra lm 4 bank. M i bank c dung l ng 128 byte, bao g m cc thanh ghi c ch c nng c bi t SFG (Special Function Register) n m cc vng a ch th p v cc thanh ghi m c ch chung GPR (General Purpose Register) n m
12
vng
a ch cn l i trong bank. Cc thanh ghi SFR th ng xuyn c s d ng (v d c t t t c cc bank c a b nh d li u gip thu n ti n c th c a b nh
nh thanh ghi STATUS) s
trong qu trnh truy xu t v lm gi m b t l nh c a chng trnh. S d li u PIC16F877A nh sau:
Hnh 2.4: B nh b nh c a Pic
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2.5 CC THANH GHI C BI T - THANH GHI FSR V INDF
Hnh 2.5: S
thanh ghi FSR n, thanh ghi INDF ch a n i dung c a ch
Thanh ghi FSR ch a a ch con tr ch n m trong thanh ghi FSR.
V d : Thanh ghi 22H c gi tr l 10. N u FSR =22H th INDF =10. Tm l i, Thanh ghi INDF khng ph i l m t thanh ghi v t l. N ch a gi tr c a thanh ghi c a ch n m thanh ghi FSR. -THANH GHI STATUS
Thanh ghi tr ng thi ch a cc tr ng thi s h c c a b ALU, tr ng thi Reset v cc bit ch n Bank c a b nh d li u. Bit 7 IRP: Bit l a ch n bank thanh ghi (S d ng cho 1 = Bank 2, 3 (100h 1FFh ) 0 = Bank 0, 1 (00h FFh) Bit 6 5: RP1 RP0: Bit l a ch n bank thanh ghi (Dng trong 11 = Bank 3 ( 180h 1FFh) 10 = Bank 2 (100h 17Fh) 01 = Bank 1 (80h FFh) 00 = Bank 0 (00h 7Fh) Each bank is 128 bytes
14
nh
a ch gin ti p).
nh i ch tr c ti p).
Bit 4 TO: Bit bo hi u ho t
ng c a WDT.
1: L nh xa WDT ho c Sleep x y ra. 0: WDT ho t ng. Bit 3 PD: Bit bo cng su t th p ( Power down bit). 1: Sau khi ngu n tng ho c c l nh xa WDT. 0: Th c thi l nh Sleep. Bit 2 Z: bit Zero 1: Khi k t qu c a m t php ton b ng 0. 0: Khi k t qu c a m t php ton khc 0. Bit 1 DC: Digit Carry 1: C m t s nh sinh ra b i php c ng ho c php tr 4 bit th p. 0: Khng c s nh sinh ra. Bit 0 C: c nh (Carry Flag)/ borrow 1: C m t s nh sinh ra b i php c ng ho c php tr 4 bit cao. 0: Khng c s nh sinh ra. V d : N u A B < 0 th C = 0 ng c l i C = 1 - THANH GHI I U KHI N NG T INTCON (Interrupt Control Register)
Bit 7 GIE: Bit cho php ng t ton c c 1: Cho php ng t ton c c 0: Khng cho php ng t Bit 6 PEIE: Bit cho php ng t khi ghi vo EEPROM hon t t. 1: Cho php ng t ghi vo EEPROM ho t ng 0: Khng cho php ng t ghi vo EEPROM ho t Bit 5 TMR0IE: Bit cho php ng t khi timer 0 trn 1: Cho php ng t khi timer 0 trn 0: Khng cho php ng t khi timer 0 trn Bit 4 INTE: Bit cho php ng t ngo i vi trn chn RB0/INT 1: Cho php ng t ngo i vi 0: Khng cho php ng t ngo i vi Bit 3 RBIE: Cho php ng t khi tr ng thi PORTB thay 1: Cho php 0: Khng cho php Bit 2 TMR0IF: C bo ng t Timer 0
15
ng
1: Timer 0 trn 0: Timer 0 cha trn Bit 1 INTF:C bo ng t ngoi RB0/INT 1: C ng t 0: Khng x y ra ng t. Bit 0 RBIF:C bo ng t khi c thay i tr ng thi PORTB 1: C thay i 0: Khng c thay i x y ra trn PORTB * Ngoi ra cn m t s thanh ghi ch c nng khc nh: Thanh ghi PIE1 ( a ch 8Ch): ch a cc bit i u khi n chi ti t cc ng t c a cc kh i ch c nng ngo i vi. Thanh ghi PIR1 ( a ch 0Ch) ch a c ng t c a cc kh i ch c nng ngo i vi, cc ng t ny c cho php b i cc bit i u khi n ch a trong thanh ghi PIE1. Thanh ghi PIE2 (8Dh): ch a cc bit i u khi n cc ng t c a cc kh i ch c nng CCP2, SSP bus, ng t c a b so snh v ng t ghi vo b nh EEPROM. Thanh ghi PIR2 ( 0Dh): ch a cc c ng t c a cc kh i ch c nng ngo i vi, cc ng t ny c cho php b i cc bit i u khi n ch a trong thanh ghi PIE2. Thanh ghi PCON ( 8Eh): ch a cc c hi u cho bi t tr ng thi cc ch i u khi n. bi t them chi ti t xem ph n Ph luc 2.6 STACK Stack cho php 8 l nh g i chng trnh con v ng t ho t ng. Stack ch a a ch reset c a vi
m chng trnh chnh s quay v th c hi n t sau chng trnh con hay ng t. i v i PIC16F877A Stack c su 8 l p. Stack khng n m trong b nh chng trnh hay b nh d li u m l m t vng nh c bi t khng cho php c hay ghi. Khi l nh CALL c th c hi n hay khi m t ng t x y ra lm chng trnh b r nhnh, gi tr c a b m chng trnh PC t ng c vi i u khi n c t vo trong stack. Khi m t trong cc l nh RETURN, RETLW hat RETFIE c th c thi, gi tr PC s t ng c l y ra t trong stack, vi i u khi n s th c hi n ti p chng trnh theo ng qui trnh nh tr c. B nh Stack trong vi i u khi n PIC h 16F87xA c kh nng ch a c 8 a ch v ho t ng theo c ch xoay vng. Ngha l gi tr c t vo b nh Stack l n th 9 s ghi ln gi tr c t vo Stack l n u tin v gi tr c t vo b nh Stack l n th 10 s ghi ln gi tri6 c t vo Stack l n th 2. C n ch l khng c c hi u no cho bi t tr ng thi stack, do ta khng bi t c khi no stack trn. Bn c nh t p l nh c a vi i u khi n dng PIC cng khng c l nh POP hay PUSH, cc thao tc v i b nh stack s hon ton c i u khi n b i CPU.
16
CHNG 3
T P L NH - C U TRC CHNG TRNH

3.1. T P L NH 3.1.1. NHM L NH DI CHUY N 1. L nh MOVLW C php: MOVLW k (0 k 255) Tc d ng: em gi tr k vo thanh ghi W V d : gin cho thanh ghi W m t gi tr c th l 20H ta lm nh sau: MOVLW 20H MOVLW B0010 0000 MOVLW D32 2. L nh MOVWF C php: MOVWF f (0 f 255) Tc d ng: em gi tr c a thanh ghi W vo thanh ghi f gin cho thanh ghi m t gi tr c th , sau ta th c hin l nh MOVWF c n gin. V d : MOVLW D15; W=15 MOVWF PORTB; PORTB =15 Tuy nhin, cn c cch khc thng qua thanh ghi con tr FSR, khi thanh ghi con tr FSR tr n byte c a ch no th n i dung c a thanh ghi di chuy n vo thanh ghi INDF. hi u m t cch n gi n ta hi u thanh ghi FSR ch a a ch cn thanh ghi INDF ch a n i dung. V d : MOVLW 30H MOVWF FSR MOVLW D20 MOVWF INDF l nh u tin W=30H, sau gin gi tr 30H vo thanh ghi FSR t c l con tr ch n byte c a ch 30H. Khi gi tr c a thanh ghi c a ch 30H c ch a trong thanh ghi INDF. Nh v y sau khi gin gi tr 20 vo thanh ghi INDF t c l gin gi tr vo thanh ghi c a ch 30H. V y sau khi th c hin o n chng trnh trn (30H) = 20, t c l byte c gi tr l 20. c th hn chng ta xt v d sau:
17
u tin a gi tr c n gin cho thanh ghi W,
di chuy n gi tr trong thanh ghi W sang thanh ghi
a ch 30H c
MOVLW D5 MOVWF PORTB Thng qua 2 l nh trn PORTB = 5, nhng ta c th vi t l i: MOVLW 06H MOVWF FSR MOVLW D5 MOVWF INDF V y sau khi th c hin o n chng trnh trn (06H) = 5, t c l byte c (PORTB) c gi tr l 5. 3. L nh MOVF C php: MOVF f,W f (0 f 255) Tc d ng: em gi tr c a thanh ghi f vo thanh ghi W di chuy n gi tr thanh ghi COUNT1 sang thanh ghi COUNT2 th ta b t bu c qua thanh ghi trung gian W thng qua l nh MOVF. Vid : MOVF COUNT1,W MOVWF CONT2 u tin em gi tr c c thanh ghi COUNT1 vo W, sau thng qua l nh MOVWF em gi tr c c thanh ghi W vo COUNT2. 3.1.2. NHM L NH S H C 4. L nh ADDLW C php: ADDLW k Tc d ng: C ng gi tr k vo thanh ghi W,k t qu Bit tr ng thi: C, DC, Z V d : MOVLW D200; ADDLW D55 MOVWF PORTB; 5.L nh ADDWF C php: ADDWF W=200 PORTB = 255 f,d c ch a trong thanh ghi c ch a trong thanh ghi W.
a ch 06H
Tc d ng: C ng gi tr hai thanh ghi W v thanh ghi f. K t qu W n u d = 0 ho c thanh ghi f n u d =1. Bit tr ng thi: C, DC, Z 6. L nh SUBLW C php: SUBLW k
(d
[0,1]).
18
Tc d ng: L y gi tr k tr gi tr trong thanh ghi W. K t qu W. Bit tr ng thi: C, DC, Z V d : MOVLW D100; SUBLW D155 MOVWF PORTB; W=100 PORTB =55
c ch a trong thanh ghi
7. L nh SUBWF C php: SUBWF f,d Tc d ng: L y gi tr trong thanh ghi f em tr cho thanh ghi W. K t qu thanh ghi W n u d=0 ho c thanh ghi f n u d=1. Bit tr ng thi: C, DC, Z 8. L nh INCF C php: INCF f,d Tc d ng: Tng gi tr thanh ghi f ln 1 n v . K t qu d = 0 ho c thanh ghi f n u d = 1. Bit tr ng thi: Z V d : MOVLW D10 MOVWF COUNT; INCF COUNT,1; 9. L nh DECF C php: DECF f,d Tc d ng: Gi tr thanh ghi f c gi m i 1 n v . K t qu W n u d = 0 ho c thanh ghi f n u d = 1. Bit tr ng thi: Z V d : MOVLW D10 MOVWF COUNT; DECF COUNT,1;
3.1.3. NHM L NH LOGIC 10. L nh BCF C php: BCF f,b (0b7) Tc d ng: Xa bit b trong thanh ghi f v gi tr 0.
19
(d
(d
(d
[0,1]) c lu trong
[0,1]) c a vo thanh ghi W n u
COUNT =10 COUNT =11
[0,1]). c a vo thanh ghi
COUNT =10 COUNT =9
Bit tr ng thi: khng c. V d : BCF PORTB,2; RB2 =0
11. L nh BSF C php: BSF f,b (0b7) Tc d ng: Set bit b trong thanh ghi f. Bit tr ng thi: khng c V d : BSF PORTB,2; 12. L nh CLRW C php CLRW Tc d ng: Xa thanh ghi W v bit Z c set. Bit tr ng thi: Z 13. L nh CLRF C php CLRF f Tc d ng: Xa thanh ghi f v bit Z c set. Bit tr ng thi: Z 14. L nh CLRWDT C php: CLRWDT Tc d ng: Reset Watchdog Timer, set ln 1. ng th i prescaler cng c reset, cc bit v c RB2 =1
15. L nh ANDLW C php: ANDLW k Tc d ng: Th c hi n php ton AND gi a thanh ghi v gi tr k, k t qu trong thanh ghi W. Bit tr ng thi: Z Ch : And cc bit tng ng V d : MOVLW ANDLW B1111 0000 B0011 1111; W = B0011 0000
c ch a
16. L nh ANDWF C php: ANDWF f,d Tc d ng: Th c hi n php ton AND gi a cc gi tr ch a trong hai thanh ghi W v f. K t qu c a vo thanh ghi W n u d=0 ho c thanh ghi f n u d = 1. Bit tr ng thi: Z
(d
[0,1]).
20
17. L nh IORLW C php: IORLW k Tc d ng: Th c hi n php ton OR gi a thanh ghi W v gi tr k. K t qu trong thanh ghi W. Bit tr ng thi: Z 18. L nh IORWF C php: IORWF f,d (d [0,1]) Tc d ng: Th c hi n php ton OR gi a hai thanh ghi W v f. K t qu thanh ghi W n u d = 0 ho c thanh ghi f n u d=1. Bit tr ng thi: Z 19. L nh XORLW C php: XORLW k Tc d ng: Th c hi n php ton XOR gi a gi tr k v gi tr trong thanh ghi W. K t qu c lu trong thanh ghi W. Bit tr ng thi: Z 20. L nh XORWF C php: XORWF f,d Tc d ng: Th c hi n php ton XOR gi a hai gi tr ch a trong thanh ghi W v thanh ghi f. K t qu c lu vo trong thanh ghi W n u d=0 ho c thanh ghi f n u d=1. Bit tr ng thi: Z 21. L nh SWAPF C php: SWAPF f,d (d [0,1]) Tc d ng: o 4 bit th p v i 4 bit cao trong thanh ghi f. K t qu ghi W n u d = 0 ho c thanh ghi f n u d = 1. Bit tr ng thi: khng c 22. L nh RLF C php: RLF f,d (d [0,1]) Tc d ng: D ch tri cc bit trong thanh ghi f qua c carry. K t qu ghi W n u d=0 ho c thanh ghi f n u d=1. Bit tr ng thi: C 23. L nh RRF C php: RRF f,d (d [0,1]) Tc d ng: D ch ph i cc bit trong thanh ghi f qua c carry. K t qu
21
c ch a
c a vo
c ch a trong thanh
c lu trong thanh
c lu trong
thanh ghi W n u d = 0 ho c thanh ghi f n u d = 1. Bit tr ng thi: C 24. L nh COMF C php: COMF f,d (d [0,1]). Tc d ng: o cc bit trong thanh ghi f. K t qu ho c thanh ghi f n u d=1. Bit tr ng thi: Z 3.1.4.NHM L NH R NHNH 25. L nh BTFSS C php: BTFSS f,b (0b7) Tc d ng: Ki m tra bit b trong thanh ghi f. N u bit b b ng 0, l nh ti p theo c th c thi. N u bit b b ng 1, l nh ti p theo c b qua v thay vo l l nh NOP. Bit tr ng thi: khng c V d : BTFSS PORTB,1 L NH 1 L NH 2 1 y l v tr bt c ki m tra c a portB. N u bt ny th c thi l nh 2. Ng c lai, m c th p s th c thi l nh 1 26. L nh BTFSC C php: BTFSC f,b (0b7) Tc d ng: ki m tra bit b trong thanh ghi f. N u bit b b ng 1, l nh ti p theo c th c thi. N u bit b b ng 0, l nh ti p theo c b qua v thay vo l l nh NOP. Bit tr ng thi: khng c 27. L nh DECFSZ C php: DECFSZ f,d Tc d ng: ga tr thanh ghi f c gi m 1 n v . N u k t qu sau khi gi m khc 0, l nh ti p theo c th c thi, n u k t qu b ng 0, l nh ti p theo khng c th c thi v thay vo l l nh NOP. K t qu c a vo thanh ghi W n u d = 0 ho c thanh ghi f n u d = 1. Bit tr ng thi: khng c V d : DECFSZ DEM,1
22
(d
c a vo thanh ghi W n u d =0
m c cao th s b qua l nh 1
[0,1])
L NH 1 L NH 2 Sauk khi gi m gi tr trong thanh ghi DEM xu ng 1 n v , n u cha b ng 0 th th c thi L NH 1. Ng c l i, th c thi L NH 2 28. L nh INCFSZ C php: INCFSZ f,d Tc d ng: tng gi tr thanh ghi f ln 1 n v . N u k t qu khc 0, l nh ti p theo c th c thi, n u k t qu b ng 0, l nh ti p theo c thay b ng l nh NOP. K t qu s c a vo thanh ghi f n u d=1 ho c thanh ghi W n u d = 0. Bit tr ng thi: khng c. 29. L nh GOTO C php: GOTO k (0k2047) Tc d ng: nh y t i m t label c Bit tr ng thi: khng c. 30. L nh CALL C php: CALL k (0k2047) Tc d ng: g i m t chng trnh con. Tr c h t (PC+1) c c t vo trong Stack, gi tr bi n k v 2 bit PCLATH<4:3>. Bit tr ng thi: khng c 31. L nh RETURN C php: RETURN Tc d ng: quay tr v chng trnh chnh t m t chng trnh con Bit tr ng thi:khng c Ngoai cac lenh tren con co mot so lenh dung trong chng trnh nh: 32 L nh #DIFINE C php: #DEFINE <text1> <text2> Tc d ng: thay th m t chu i k t ny b ng m t chu i k t khc, c ngha l m i khi chu i k t text1 xu t hi n trong chng trnh, trnh bin d ch s t t b ng chu i k t <text2>. 33. L nh INCLUDE C php: #INCLUDE <filename> ho c #INCLUDE "filename" Tc d ng: nh km m t file khc vo chng trnh, tng t nh vi c ta copy file vo v tr xu t hi n l nh INCLUDE. N u dng c php <filename> th file nh km l file h th ng (stem file), n u dng c php "filename" th file nh km l file c a ng i s d ng. Thng th ng chng trnh c nh km theo m t "header file" ch a cc
23
(d
[0,1])
nh ngha b i tham s k v 2 bit PCLATH <4:3>.
a ch quay tr v t chng trnh con m g m 11 bit c a
a ch m i c a vo b
ng thay th chu i k
thng tin kh
nh ngh a cc bi n (thanh ghi W, thanh ghi F,..) v cc
a ch c u cc thanh
ghi ch c nng
c bi t trong b nh d li u. N u khng c header file, chng trnh s
c v kh hi u hn.
34 .L nh CONSTANT C php: CONSTANT <name>=<value> Tc d ng: Khai bo m t h ng s , c ngha l khi pht hi n chu i k t "name" trong chng trnh, trnh bin d ch s t ng thay b ng chu i k t b ng gi tr "value" c nh ngha tr c . 35. L nh VARIABLE C php: VARIABLE <name>=<value> Tc d ng: Tng t nh l nh CONSTANT, ch c i m khc bi t duy nh t l gi tr "value" khi dng l nh VARIABLE c th thay trnh cn l nh CONSTANT th khng. 36. L nh SET C php: <name variable> SET <value> Tc d ng: Gn gi tr cho m t tn bi n. Tn c a bi n c th thay trnh th c thi chng trnh. 37 L nh EQU C php: <name constant> EQU <value> Tc d ng: Gn gi tr cho tn c a tn c a h ng s . Tn c a h ng s khng thay trong qu trnh th c thi chng trnh. 38. L nh ORG C php: ORG <value> Tc d ng: nh ngha m t i u khi n. i i c trong qu i c trong qu trnh thc thi chng
a ch ch a chng trnh trong b nh chng trnh c a vi
39. L nh END C php: END Tc d ng: nh d u k t thc chng trnh. 40. L nh __CONFIG Tc d ng: Thi t l p cc bit i u khi n cc kh i ch c nng c a vi i u khi n c ch a trong b nh chng trnh (Configuration bit). 41. L nh PROCESSOR C php: PROCESSOR <processor type> Tc d ng: nh ngha vi i u khi n no s d ng chng trnh.
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3.2. T O TR B NG VNG L P Th c ch t c a chng trnh DELAY l cho vi i u khi n lm m t cng vi c v ngha no trong m t kho ng th i gian nh tr c. Kho ng th i gian ny c tnh ton d a trn qu trnh th c thi l nh, hay c th hn l d a vo th i gian c a m t chu k l nh. C th vi t chng trnh DELAY d a trn o n chng trnh sau: DELAY MOVLW D5 MOVWL DEM LOOP DECFSZ GOTO DEM LOOP u xem nh
RETURN By gi ta tnh ton xem o n chng trnh trn t o tr bao lu? (Hai l nh b qua, tnh t ngay nhn LOOP cho 5 4 ; 3 chu k my 4 3; 3 chu k my 3 2; 3 chu k my 2 1; 3 chu k my 1 0; 4 chu k my n l nh RETURN)
i v i cc l nh trong Pic nh ng l nh thng th ng khi th c thi t n 1 chu k my, cc l nh nh y t n 2 chu k my. Ring cc l nh: BTFSS, BTFSC, DECFSZ Khi cha nh y cng t n 1 chu k my, khi th a i u ki n th nh y th t n 2 chu k my. Do , vng l p u tin l nh DECFSZ t n 1 chu k my, l nh GOTO t n 2 chu k my. vng l p cu i, sau khi th c thi xong l nh DECFSZ gi tr trong thanh ghi DEM gi m t 1 0 th nh y qua kh i l nh GOTO t n 2 chu k my nhng g p l nh RETURN l l nh nh y t n 2 chu k my. Do , vng l p cu i t n 4 chu k my. Td = (3DEM+1)Ti 3DEM. V i: Ti = 4/ fOSC DEM 255: Gi tr cy vo Td: Th i gian t o tr . V d : Vi t chng trnh t o tr 500s, th ch anh 4Mhz Tac: Td = 500s, Ti = 4/fOSC =1s => DEM = 500/3 = 167 DELAY MOVLW MOVWL LOOP
25
D167 DEM
DECFSZ GOTO
DEM LOOP t gi tr t i a l 765 s. V y tng th i
RETURN Nh n xt: N u dng th ch anh 4Mhz th Td
gian Td chng ta dng 2 vng l p l ng vo nhau: DELAY MOVLW D255 MOVWF DEM1 LOOP DECFSZ GOTO GOTO LOOP1 MOVLW MOVWF LOOP2 DECFSZ GOTO GOTO THOAT NOP RETURN V i o n chng trnh trn ta tnh c: Td 3*DEM2*DEM1. = 3.255.255= 172125 s 0.196S 3.3. C U TRC CHNG TRNH ; Khng c s d ng ng t, n u c s d ng ng t xem chng 6 PROCESSOR 16F877A ; Khai bo dng VI I U KHI N g? # INCLUDE ORG <P 16F877A.INC> 0000H - CH N BANK - CH N I/O ; nh km file c s n trong th vin. ; a ch Vect Reset ; D a vo thanh ghi Status ch n bank ph h p ;D a vo m c ch thi t k , ch n ng vo/ra ; ph h p. ;B t u vi t chng trnh DEM2 LOOP2 LOOP D255 DEM2 DEM1 LOOP1 THOAT
MAIN
; Th c thi chng trnh

26
GOTO $ ; Vng l p v h n END ; K t thc chng trnh V d : Vi t chng trnh xu t ra chn RB7 m c cao. PROCESSOR 16F877A #INCLUDE <P16F877A.INC> ORG 0000H BCF STATUS,6 ; Ch n bank0 BCF CLRF BSF BCF BCF BSF GOTO STATUS,5 ; Ch n bank0 PORTB ; Xa PORTB STATUS,5 ; Ch n bank1 TRISB,7 ; Khai bo RB7 l output STATUS,5 ; Tr l i bank0 PORTB,7 ; Set RB7 m c cao $ ; T o vng l p v h n
END bi t khai bo I/O nh th no? chng ta c th n m cch th c khai bo I/O c th nh sau: Thanh ghi TRISA ch n tnh I/O cho PORTA Thanh ghi TRISB ch n tnh I/O cho PORTB Thanh ghi TRISC ch n tnh I/O cho PORTC Thanh ghi TRISD ch n tnh I/O cho PORTD
- Thanh ghi TRISE ch n tnh I/O cho PORTE Cch ch n cng kh n gi n: Mu n xc l p ch c nng c a m t chn trong PORTA l input, ta "set" bit i u khi n tng ng v i chn trong thanh ghi TRISA v ng c l i, mu n xc l p ch c nngc a m t chn trong PORTA l output, ta "clear" bit i u khi n tng ng v i chn trong thanh ghi TRISA. Thao tc ny hon ton tng t i v i cc PORT v cc thanh ghi i u khi n tng ng TRIS ( PORTB l TRISB, i v i PORTC l TRISC, i v i PORTD l TRISD v V d : Chng ta mu n RA1 l output, RA0 l input BCF BSF TRISA,1 TRISA,0 i v i PORTA l TRISA, iv i
i v i PORTE l TRISE).
Tng t , RB5 l input, RB7 l output BSF TRISB,5

27
BCF
TRISB,7
BI T P THAM KH O Bi t p 1: Vi t chng trnh t o xung vung t i chn RB7, c t n s f = 50hz (th ch anh 4Mhz) Ta c: T= 1/f = 20.000S =>Td = 10.000 S PROCESSOR 16F877A #INCLUDE <P16F877A.INC> DEM2 EQU 20H DEM1 EQU 21H ORG 0000H BCF STATUS,6 BCF STATUS,5 CLRF PORTB BSF STATUS,5 BCF TRISB,7 BCF STATUS,5 MAIN BSF PORTB,7 CALL DELAY BCF PORTB,7 CALL DELAY GOTO MAIN DELAY MOVLW D'33' MOVWF DEM1 LOOP DECFSZ DEM1 GOTO LOOP1 GOTO THOAT LOOP1 MOVLW D'100' MOVWF DEM2 LOOP3 DECFSZ DEM2 GOTO LOOP3 GOTO LOOP THOAT NOP RETURN END Bi t p 2: Vi t chng trnh i u khi n n: tr ng thi ban u n t t, nh n N bung ra n sang. N u n ang sang nh n N bung ra n t t v ng c l i.
28

5V
R1 R LED N RB0 RB7 R PIC 16F877A
Hnh 3.1 PROCESSOR 16F877A #INCLUDE <P16F877A.INC> ORG 0000H BCF STATUS,6 BCF STATUS,5 CLRF PORTB BSF STATUS,5 BSF TRISB,0 BCF TRISB,7 BCF STATUS,5 MAIN BTFSS PORTB,0 GOTO LOOP1 GOTO MAIN LOOP1 BTFSC PORTB,0 GOTO LOOP2 GOTO LOOP1 LOOP2 BTFSS PORTB,7 GOTO ON GOTO OFF OFF BCF PORTB,7 GOTO MAIN ON BSF PORTB,7 GOTO MAIN END Bi t p 3: Vi t chng trnh i u khi n n c u thang: N u n ang t t nh n N1(ho c N2), r i bung ra n sng v ng c l i.
29
HI
Vcc
5V
LAMP
R R N1 RA0 RA2 PIC 16F877A N2 RA1 R Q1
220V
Hnh 3.2 PROCESSOR 16F877A #INCLUDE <P16F877A.INC> ORG 0000H BCF BCF CLRF BSF BSF BSF BCF BCF MAIN BTFSC GOTO GOTO LOOP1 BTFSS GOTO GOTO KT_1 BTFSS GOTO GOTO KT_2 BTFSS GOTO GOTO ON/OFF BTFSS GOTO GOTO
STATUS,6 STATUS,5 PORTA STATUS,5 TRISA,0 TRISA,1 TRISA,2 STATUS,5 PORTA,0 LOOP1 KT_1 PORTA,1 KT_2 MAIN PORTA,0 KT_1 ON/OFF PORTA,1 KT_2 ON/OFF PORTA,2 ON OFF
30
ON BSF GOTO OFF BCF GOTO END Trong cc thi t b , PORTA,2 MAIN PORTA,2 MAIN
3.4. CC KH I GIAO TI P 3.4.1. GIAO TI P V I LED 7 OAN
bo tr ng thi ho t
ng c a thi t b
cho ng i s d ng v i
thng s ch l cc dy s n thu n, th ng ng i ta s d ng "led 7 o n". Led 7 o n c s d ng khi cc dy s khng i h i qu ph c t p, ch c n hi n th s l , ch ng h n led 7 o n c dng hi n th nhi t phng, trong cc ng h treo t ng b ng i n t , hi n th s l ng s n ph m c ki m tra sau m t cng o n no ... Led 7 o n c c u t o bao g m 7 led n c d ng thanh x p theo hnh v c thm m t led n hnh trn nh th hi n d u ch m trn gc d i, bn ph i c a led 7 o n. Tm led n trn led 7 o n c Anode(c c +) ho c Cathode(c c -) c n i chung v i nhau vo m t i m, c a chn ra ngoi k t n i v i m ch i n. 8 c c cn l i trn m i led n c a thnh 8 chn ring, cng c a ra ngoi k t n i v i m ch i n. N u led 7 o n c Anode(c c +) chung, u chung ny c n i v i +Vcc, cc chn cn l i dng i u khi n tr ng thi sng t t c a cc led n, led ch sng khi tn hi u t vo cc chn ny m c 0. N u led 7 o n c Cathode(c c -) chung, u chung ny c n i xu ng Ground (hay Mass), cc chn cn l i dng i u khi n tr ng thi sng t t c a cc led n, led ch sng khi tn hi u t vo cc chn ny m c 1.
A chung
K chung
Hnh 3.3 V led 7 o n ch a bn trong n cc led n, do khi k t n i c n qua m i led n trong kho ng 10mA-20mA b o v led. N u k t n i v i ngu n 5V c th h n dng b ng i n tr 330 tn hi u i u khi n S v tr cc led c trnh by nh hnh bn: Cc i n tr 330 ngoi c k t n i
m b o dng
tr c cc chn nh n l cc i n tr bn
gi i h n dng i n qua led n u led 7 o n c n i v i ngu n 5V.

31
Chn nh n tn hi u a i u khi n led a sng t t, ng vo b v i cc chn v cc led cn l i
i u khi n led b. Tng t
Hnh 3.4:K hi u Led 7 o n
Hnh 3.5: D ng s hi n th ln Led 7 o n
Hnh 3.6: Hnh d ng Led 7 o n Bi t p 1: Vi t chng trnh hi n th s 3
32
Vcc
HI
VCC
PIC16F877A
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 MCLR/VPP RB7/PGD RA0/AN0 RB6/PGC RA1/AN1 RB5 RA2/AN2/VRef -/CVRef RB4 RA3/AN3/VRef + RB3/PGM RA4/T0CKI/C1OUT RB2 RA5/AN4/SS/C2OUT RB1 RE0/RD/AN5 RB0/INT RE1/WR/AN6 VDD GND RE2/CSAN7 VDD RD7/PSP7 GND RD6/PSP6 OSC1/CLKI RD5/PSP5 OSC2/CLKO RD4/PSP4 RC0/T1OSO/T1CKI RC7/RX/DT RC1/T1OSI/CCP2 RC6/TX/CK RC2/CCP1 RC5/SDO RC3/SCK/SCL RC4/SDI/SDA RD0/PSP0 RD3/PSP3 RD1/PSP1 RD2/PSP2 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
g f e d c b a
Hnh 3.7 PROCESSOR 16F877A #INCLUDE <P16F877A.INC> ORG 0000H BCF BCF CLRF CLRF BSF CLRF BCF BCF MAIN BSF MOVLW MOVWF GOTO END Bi t p 2: Tuy nhin, PORTC,4 B011 0000 PORTB $
STATUS,6 STATUS,5 PORTB PORTC STATUS,5 TRISB TRISC,4 STATUS,5
hi n th 2 s v d nh 37 chng ta khng nh t thi t ph i dng 2 port, m hi n th s 37, t i m t th i i m ta cho m t con
c th ghp song song 2 led 7 o n.
Led sng. Th i gian ch p t t lin t c (t n s kho ng 40 Hz) lm cho m t ta c c m gic nh 2 Led ang sng lin t c. Phng php ny g i l qut led
33
A B C D E F G H
VCC

HI
Vcc
VCC
VCC
VCC
PIC16F877A
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 MCLR/VPP RB7/PGD RA0/AN0 RB6/PGC RA1/AN1 RB5 RA2/AN2/VRef -/CVRef RB4 RA3/AN3/VRef + RB3/PGM RA4/T0CKI/C1OUT RB2 RA5/AN4/SS/C2OUT RB1 RE0/RD/AN5 RB0/INT VDD RE1/WR/AN6 RE2/CSAN7 GND VDD RD7/PSP7 RD6/PSP6 GND OSC1/CLKI RD5/PSP5 RD4/PSP4 OSC2/CLKO RC0/T1OSO/T1CKI RC7/RX/DT RC1/T1OSI/CCP2 RC6/TX/CK RC2/CCP1 RC5/SDO RC3/SCK/SCL RC4/SDI/SDA RD0/PSP0 RD3/PSP3 RD1/PSP1 RD2/PSP2 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
g f e d c b a
A B C D E F G H
Hnh 3.8 PROCESSOR 16F877A #INCLUDE <P16F877A.INC>

DEM1 DEM2 EQU EQU 20H 21H
ORG 0000H BCF BCF CLRF CLRF BSF CLRF BCF BCF BCF MAIN BSF BCF MOVLW MOVWF PORTC,4 PORTC,5 B0110000 PORTB
34
STATUS,6 STATUS,5 PORTB PORTC STATUS,5 TRISB TRISC,4 TRISC,5 STATUS,5
A B C D E F G H
VCC
CALL BCF BSF MOVLW MOVWF CALL GOTO DELAY_10ms MOVLW MOVWF LOOP DECFSZ GOTO GOTO LOOP1 MOVLW MOVWF LOOP3 DECFSZ GOTO GOTO THOAT NOP RETURN END
DELAY_10ms PORTC,4 PORTC,5 B1111000 PORTB DELAY_10ms MAIN D'33' DEM1 DEM1 LOOP1 THOAT D'100' DEM2 DEM2 LOOP3 LOOP
3.4.2. GIAO TI P V I BN PHM HEX
Khi giao ti p v i bn phm Hex nh hnh 3.9 ta ch n RB0RB3 l output, RB4RB7 l input. Ban RB4RB7 u ta cho RB3RB2RB1RB0=1110 sau chng ta ki m tra ng vo t xc nh t i v tr no m c th p tng ng v i nt nh n c tc ng.
N u RB4=0 t c l vi tr s 0 c nh n, tng t RB5=0 th s 1 c nh n. .... Ti p theo ta cho RB3RB2RB1RB0=1101, khi ki m tra n u RB4 =0 th nt s 4 th c nh n.....
35
R1
470
R2
470
R3
470
R4
470
RB0 4 5 6 7 RB1 8 9 A B RB2 C D E F
RB3
RB4
RB5
RB6
Hnh 3.9
RB7
DOC_BP MOVLW MOVWF BTFSS RETLW BTFSS RETLW BTFSS RETLW BTFSS RETLW B1110 PORTB PORTB,4 D'0' PORTB,5 D'1' PORTB,6 D'2' PORTB,7 D'3'
36
Gio trnh Vi i u Khi n MOVLW MOVWF BTFSS RETLW BTFSS RETLW BTFSS RETLW BTFSS RETLW MOVLW MOVWF BTFSS RETLW BTFSS RETLW BTFSS RETLW BTFSS RETLW MOVLW MOVWF BTFSS RETLW BTFSS RETLW BTFSS RETLW BTFSS RETLW RETURN B1101 PORTB PORTB,4 D'4' PORTB,5 D'5' PORTB,6 D'6' PORTB,7 D'7' B1011 PORTB PORTB,4 D'8' PORTB,5 D'9' PORTB,6 0AH PORTB,7 0BH B0111 PORTB PORTB,4 0CH PORTB,5 0DH PORTB,6 0EH PORTB,7 0FH
37
Gio trnh Vi i u Khi n 3.4.3. GIAO TI P V I LED MA TR N
Hnh 3.10
H1 H2 H3 H4 H5 H6 H7 H8
C1 C2
C3
Hnh 3.11
C4
C5
C6
C7
C8
Led matr n hi n th 1 k t chng ta dng phng php qut, cng nh qut led 7 o n, y chng ta dng cch qut c t. T c l t i m t th i i m ch cho 1 c t c t sng b ng cch tc ng cho hng v c t tch c c h p l.
38
V d : i u khi n hng l portb (RB0H1, RB1H2 ........ RB7H8), i u khi n c t l portd (RD0C1, RD1C2 ........ RD7C8). hi n ch N ta vi t nh sau: MAIN MOVLW B11111111 MOVWF PORTB MOVLW B11111110 MOVWF PORTD CALL DELAY MOVLW MOVWF MOVLW MOVWF CALL MOVLW MOVWF MOVLW MOVWF CALL MOVLW MOVWF MOVLW MOVWF CALL MOVLW MOVWF MOVLW MOVWF CALL MOVLW MOVWF MOVLW MOVWF CALL MOVLW MOVWF MOVLW MOVWF CALL MOVLW MOVWF B11111111 PORTB B11111101 PORTD DELAY B00000011 PORTB B11111011 PORTD DELAY B00000110 PORTB B11110111 PORTD DELAY B00001100 PORTB B11101111 PORTD DELAY B00011000 PORTB B11011111 PORTD DELAY B11111111 PORTB B10111111 PORTD DELAY B11111111 PORTB
39
MOVLW MOVWF CALL GOTO ; TAO TRE 2.5mS = 2500uS DELAY MOVLW MOVWF LOOP DECFSZ GOTO GOTO LOOP1 MOVLW MOVWF LOOP3 DECFSZ GOTO GOTO THOAT NOP RETURN END
3.4.4 GIAO TI P V I LCD
B01111111 PORTD DELAY MAIN D'8' DEM1 DEM1 LOOP1 THOAT D'104' DEM2 DEM2 LOOP3 LOOP
Hnh 3.12 40
Bn trong LCD c 2 thanh ghi 8 bit quan tr ng : Thanh ghi l nh IR (Instructor Register) v thanh ghi d li u DR (Data Register) Thanh ghi IR : i u khi n LCD Nh v y i u khi n LCD chng ta c n a m l nh i u khi n thch h p vo thanh ghi IR thng qua b ng m sau: B ng m l nh
M S Hex 01 02 04 06 05 07 08 0A 0C 0E 0F 10 14 18 1C 80 C0 38 L nh n Thanh Ghi C a LCD Xa mn hnh hi n th Tr v u dng Gi m con tr (d ch con tr sang tri) Tng con tr (d ch con tr sang ph i) D ch hi n th sang ph i D ch hi n th sang tri T t con tr , t t hi n th B t con tr , t t hi n th T t con tr , b t hi n th Nh p nhy con tr , b t hi n th T t con tr , nh p nhy con tr D ch v tr con tr sang tri D ch v tr con tr sang ph i D ch ton b hi n th sang tri D ch ton b hi n th sang ph i a con tr v u dng th nh t a con tr v u dng th hai Ci LCD ch y ch 2 dng v dng ma tr n 5 x 7
V d : Mu n xa mn hnh chng ta c n a gi tr 01H vo IR Thanh ghi DR : Thanh ghi DR dng ch a d li u 8 bit ghi vo vng RAM DDRAM ho c CGRAM (ch ghi) ho c dng ch a d li u t 2 vng RAM ny g i ra cho MCU ( ch c). DR cng l thanh Ram ch a d li u c n hi n th ln LCD. V d : hi n th ln LCD ch A chng ta a gi tr 65 vo DR (m ascii c a A l 65) a gi tr thch h p vo IR hoc DR thng qua 3 chn i u khi n: E, RS v RW B ng ch c nng chn
S Chn 1 2 3 Tn G i VSS VDD VEE Ch c Nng Chn n i t cho LCD, khi thi t k m ch ta n i chn ny v i GND c a m ch i u khi n. Chn c p ngu n cho LCD, khi thi t k m ch ta n i chn ny v i VCC=5V c a m ch i u khi n. Chn ny dng i u ch nh tng ph n c a LCD. Khi thi t k n i chn ny v i chn i u ch nh c a bi n tr kho ng 5K n 10k. Chn ch n thanh ghi (Register select). N i chn RS v i logic 0 (GND) ho c logic 1 (VCC) ch n thanh ghi. 41
RS
Gio trnh Vi i u Khi n + Logic 0: Bus DB0-DB7 s n i v i thanh ghi l nh IR c a LCD ( ch ghi - write) ho c n i v i b m a ch c a LCD ( ch c - read) + Logic 1: Bus DB0-DB7 s n i v i thanh ghi d li u DR bn trong LCD. Chn ch n ch c/ghi (Read/Write). N i chn R/W v i logic 0 LCD ho t ng ch ghi, ho c n i v i logic 1 LCD ch c. Chn cho php (Enable). Sau khi cc tn hi u c t ln bus DB0-DB7, cc l nh ch c ch p nh n khi c 1 xung cho php c a chn E (xung ny c r ng hn >= 4us). + ch ghi: D li u bus s c LCD chuy n vo (ch p nh n) thanh ghi bn trong n khi pht hi n m t xung (high-to-low transition) c a tn hi u chn E. + ch c: D li u s c LCD xu t ra DB0DB7 khi pht hi n c nh ln (low-to-high transition) chn E v c LCD gi bus n khi no chn E xu ng m c th p. Tm ng c a bus d li u dng trao i thng tin v i MPU. C 2 ch s d ng 8 ng bus ny : + Ch 7 --> 14 D0 --> D7 8 bit : D li u c truy n trn c 8 ng, v i bit MSB l bit DB7. + Ch 4 bit : D Chi ti t s sau. 15 16 A K Chn dng (+) c a n n n LCD. Chn m (-) c a n n n LCD. li u c truy n trn 4 ng ph n t DB4 t i DB7, bit MSB l DB7. d ng 2 giao th c ny c c p
R/W
V d : Cho s nh t.
nh hnh 3.13. Vi t chng trnh cho LCD hi n th s 0
gi a hng th
42
LCD2
LM016L
VSS VD D VEE
RS R W E 4 5 6
1 2 3
U1
13 14 2 3 4 5 6 7 8 9 10 1 OSC1/CLKIN OSC2/CLKOUT RB0/INT RB1 RB2 RB3/PGM RB4 RB5 RB6/PGC RB7/PGD 33 34 35 36 37 38 39 40 15 16 17 18 23 24 25 26 19 20 21 22 27 28 29 30
RA0/AN0 RA1/AN1 RA2/AN2/VREF-/CVREF RA3/AN3/VREF+ RA4/T0CKI/C1OUT RA5/AN4/SS/C2OUT RC0/T1OSO/T1CKI RE0/AN5/RD RC1/T1OSI/CCP2 RE1/AN6/WR RC2/CCP1 RE2/AN7/CS RC3/SCK/SCL RC4/SDI/SDA MCLR/Vpp/THV RC5/SDO RC6/TX/CK RC7/RX/DT RD0/PSP0 RD1/PSP1 RD2/PSP2 RD3/PSP3 RD4/PSP4 RD5/PSP5 RD6/PSP6 RD7/PSP7 PIC16F877A
Hnh 3.13
PROCESSOR 16F877A #INCLUDE <P16F877A.INC> TAM EQU 20H DEM1 EQU 21H DEM2 EQU 22H DEM3 EQU 23H ORG 0000H BSF BCF CLRF CLRF BCF CLRF CLRF MAIN MOVLW MOVWF CALL 01h ; Dua 01h vo IR, xa mn hnh TAM KHOITAO
43
STATUS,5 STATUS,6 TRISB TRISE STATUS,5 PORTB PORTE
7 8 9 10 11 12 13 14
D0 D1 D2 D3 D4 D5 D6 D7
CALL MOVLW MOVWF CALL CALL MOVLW MOVWF CALL CALL MOVLW MOVWF CALL CALL MOVLW MOVWF CALL CALL GOTO XUATLCD MOVLW MOVWF MOVF MOVWF MOVLW MOVWF RETURN KHOITAO MOVLW MOVWF MOVF MOVWF MOVLW MOVWF RETURN DELAY MOVLW MOVWF LOOP DECFSZ GOTO GOTO LOOP1
DELAY; Tao tre 38h; Dua 38h vo IR, khoi tao LCD 2 hang TAM KHOITAO DELAY 0Eh ; ; Dua 0eh vo IR, nhap nhay con tro, bat hien thi TAM KHOITAO DELAY 87h TAM KHOITAO DELAY D'48' TAM XUATLCD DELAY $ B'101' ; E=1, RW=0, RS=1 PORTE TAM,0 PORTB B'001' ; E=0 tao canh xuong PORTE B'100'; ; E=1, RW=0, RS=0 PORTE TAM,0 PORTB B'000' PORTE D'20' DEM1 DEM1 LOOP1 THOAT
44
MOVLW MOVWF LOOP3 DECFSZ GOTO GOTO THOAT NOP RETURN END
D'100' DEM2 DEM2 LOOP3 LOOP
45
CHNG 4
CC KH I CH C NNG
4.1.B NH TH I 4.1.1.TIMER 0
y l m t trong ba b m ho c b nh th i c a vi i u khi n PIC16F877A. Timer0 l b m 8 bit c k t n i v i b chia t n s (prescaler) 8 bit. C u trc c a Timer0 cho php ta l a ch n xung clock tc ng v c nh tch c c c a xung clock. Ng t Timer0 s xu t hi n khi Timer0 b trn. Bit TMR0IE (INTCON<5>) l bit i u khi n c a Timer0.TMR0IE=1 cho php ng t Timer0 tc Timer0 tc ng. S kh i c a Timer0 nh sau: ng, TMR0IF= 0 khng cho php ng t
Hnh 4.7: C u trc bn trong c a b
nh th i Timer0
Mu n Timer0 ho t ng ch Timer ta clear bit TOSC (OPTION_REG<5>), khi gi tr thanh ghi TMR0 s tng theo t ng chu k xung ng h (t n s vo Timer0 b ng t n s oscillator). Khi gi tr thanh ghi TMR0 t FFh tr v 00h, ng t Timer0 s xu t hi n.Thanh ghi TMR0 cho php ghi v xa c gip ta n nh th i i m ng t Timer0 xu t hi n m t cch linh Mu n Timer0 ho t ng ch ng. counter ta set bit TOSC (OPTION_REG<5>). Khi
46
xung tc
ng ln b
m c l y t chn RA4/TOCK1. Bit TOSE ng vo b t m. C nh tc ng s l
(OPTION_REG<4>) cho php l a ch n c nh tc
c nh ln n u TOSE=0 v c nh tc ng s l c nh xu ng n u TOSE=1. Khi thanh ghi TMR0 b trn, bit TMR0IF (INTCON<2>) s c set. y chnh l c ng t c a Timer0. C ng t ny ph i c xa b ng chng trnh tr c khi b mb t u th c hi n l i qu trnh m. Ng t Timer0 khng th " nh th c" vi i u khi n t ch sleep. B chia t n s (prescaler) c chia s gi a Timer0 v WDT (Watchdog Timer). i u c ngha l n u prescaler c s d ng cho Timer0 th WDT s khng c c h tr c a prescaler v ng c l i. Prescaler c i u khi n b i thanh ghi OPTION_REG. Bit PSA (OPTION_REG<3>) xc nh i t ng tc ng c a prescaler. Cc bit PS2:PS0 (OPTION_REG<2:0>) xc nh t s chia t n s c a prescaler. Xem l i thanh ghi OPTION_REG xc nh l i m t cch chi ti t v cc bit i u khi n trn. Cc l nh tc ng ln gi tr thanh ghi TMR0 s xa ch ho t ng c a prescaler. Khi i t ng tc ng l Timer0, tc ng ln gi tr thanh ghi TMR0 s xa prescaler nhng khng lm thay i i t ng tc ng c a prescaler. Khi i t ng tc ng l WDT,l nh CLRWDT s xa prescaler, WDT Ch : * Thanh ghi lin quan ng th i prescaler s ngng tc v h tr cho
n Timer0: TMR0 ( a ch 01h, 101h) : ch a gi tr
c a Timer0. (chi ti t xem b ng ph l c trang 96 ) *Thanh ghi i u khi n Timer0: OPTION_REG ( a ch 81h, 181h): i u khi n prescaler. Thanh ghi ny cho php c v ghi, cho php i u khi n ch c nng pull-up c a cc chn trong PORTB, xc l p cc tham s v xung tc ng, c nh tc ng c a ng t ngo i vi v b m Timer0.Thanh ghi ty ch n ch a cc bit i u khi n c u hnh cho cc ch a nng nh: ng t ngoi, Timer 0 ch c nng ko ln Vdd c a cc chn Port B, v th i gian ch c a WDT.
Bit 7 RBPU : Bit cho php PORTB c ko ln ngu n. 1: Khng cho php PORTB ko ln ngu n. 0: Cho php PORTB ko ln ngu n. Bit 6 INTEDG: Bt l a ch n c nh tc ng ng t (INTERRUPT EDGE) 1: Ng t s c tc ng b i c nh ln c a chn RB0/INT
47
0: Ng t s
c tc
ng b i c nh xu ng c a chn RB0/INT
Bit 5 T0CS: Bit l a ch n ngu n xung Clock cho Timer 0 1: Xung Clock cung c p b i ngu n ngoi qua chn RA4/T0CKI 0: Xung Clock cung c p b i ngu n dao ng n i. Bit 4 T0SE: Bit l a ch n c nh no c a xung clock (bn ngoi) tc ng ln timer 0 1: C nh xu ng 0: C nh ln Bit 3 PSA: Bit quy t nh t c m PS2:PS0 s tc ng ln Timer 0 hay WDT 1: T c 0: T c Bit 2-0 PS2:PS0: Dng m PS2:PS0 s tc m PS2:PS0 s tc l a ch n t c ng ln WDT ng ln Timer 0 m c a timer hay WDT
Ch 1: Cc b c vi t chng trnh Delay dng Timer0 + Ch n chia t n OPTION_REG <20 > + t gi tr vo thanh ghi TMR0 + Cho php b nh th i Timer0 ho t ng (cho bit OPTION_REG <5> =0) + Ki m tra m xong cha? Ki m tra c trn. Ch 2: Cc b c vi t chng trnh c xung dng Timer0
a. khng c chia t n (c 1 xung th gi tr trong TRM0 tng 1 n v ) BSF OPTION_REG,4; ch n tc ng c nh xu ng BSF OPTION_REG,5 BSF OPTION_REG,3 b. c chia t n (c nhi u xung th gi tr trong TRM0 tng 1 n v , ty thu c vo gi tr chia t n. n u chia t n 1:8 th c 8 xung c v TM0 tng 1 n v ) BSF OPTION_REG,4; ch n tc ng c nh xu ng BCF OPTION_REG,3
48
+ th c hi n chia t n OPTION_REG <20 > BSF OPTION_REG,5; cho php c xung V du1: Vi t chng trnh con t o tr 40ms, th ch anh 4Mhz
DELAY BSF BCF BCF BCF BCF BSF BCF MOVLW MOVWF BATDAU MOVLW MOVWF BSF BCF BCF LOOP BTFSS GOTO BCF DECFSZ GOTO RETURN INTCON,2; LOOP INTCON,2; DEM,1; BATDAU m xong cha? Xa c trn Gi m gi tr m 1 n v D'55' TMR0; TMR0= 55 STATUS,5 OPTION_REG,5; Cho php b nh th i ho t ng STATUS,5 STATUS,5; Ch n bank 1 STATUS,6; Ch n bank1 OPTION_REG,3 ; K t qu tc ng ln TMR0 OPTION_REG,2; Ch n chia t n 1:4 OPTION_REG,1 OPTION_REG,0 STATUS,5; Tr l i bank0 D'50' DEM; Gin gi tr DEM=50
4.1.2.TIMER1 Timer1 l b nh th i 16 bit, gi tr c a Timer1 s c lu trong hai thanh ghi (TMR1H:TMR1L). C ng t c a Timer1 l bit TMR1IF (PIR1<0>). Bit i u khi n c a Timer1 s l TMR1IE (PIE<0>).Tng t nh Timer0, Timer1 cng c hai ch ho t ng: ch nh th i (timer)v i xung kch l xung clock c a oscillator (t n s c a timer b ng t n s c a oscillator) v ch m (counter) v i xung kch l xung ph n nh cc s ki n c n m l y t bn ngoi thng qua chn RC0/T1OSO/T1CKI (c nh tc ng l c nh ln). Vi c l a ch n xung tc ng (tng ng v i vi c l a ch n ch ho t timer hay counter) c i u khi n b i bit TMR1CS (T1CON<1>). Sau y l s c a Timer1: ng l kh i
49
Hnh 4.8: C u trc bn trong c a b nh th i Timer1 Ngoi ra Timer1 cn c ch c nng reset input bn trong c i u khi n b i m t trong hai kh i CCP (Capture/Compare/PWM). Khi bit T1OSCEN (T1CON<3>) c set, Timer1 s l y xung clock t hai chn RC1/T1OSI/CCP2 v RC0/T1OSO/T1CKI lm xung m. Timer1 s b t u m sau c nh xu ng u tin c a xung ng vo. Khi PORTC s b qua s tc ng c a hai bit TRISC<1:0> v PORTC<2:1> c gn gi tr 0. Khi clear bit T1OSCEN Timer1 s l y xung m t oscillator ho c t chn RC0/T1OSO/T1CKI. Timer1 c hai ch m l ng b (Synchronous) v b t ng b (Asynchronous). Ch m c quy t nh b i bit i u khi n (T1CON<2>). Khi =1 xung m l y t bn ngoi s khng c ng b ha v i xung clock bn trong, Timer1 s ti p t c qu trnh m khi vi i u khi n ang ch sleep v ng t do Timer1 t o ra khi b trn c kh nng " nh th c" vi i u khi n. ch m b t ng b ,Timer1 khng th c s d ng lm ngu n xung clock cho kh i CCP(Capture/Compare/Pulse width modulation). Khi =0 xung m vo Timer1 s c ng b ha v i xung clock bn trong. ch vi i u khi n ang ch sleep. ny Timer1 s khng ho t ng khi
Ch : *Cc thanh ghi lin quan n Timer1 bao g m: INTCON ( a ch 0Bh, 8Bh, 10Bh, 18Bh): cho php ng t ho t PIR1 ( a ch 0Ch): ch a c ng t Timer1 (TMR1IF). PIE1( a ch 8Ch): cho php ng t Timer1 (TMR1IE). TMR1L ( a ch 0Eh): ch a gi tr 8 bit th p c a b TMR1H ( a ch 0Eh): ch a gi tr 8 bit cao c a b Cc thanh ghi trn chi ti t xem b ng ph l c trang 96 *Thanh i u khi n Timer1:
50
ng (GIE v PEIE).
m Timer1. m Timer1.
T1CON ( a ch 10h): xc l p cc thng s cho Timer1.
Bit 7,6 Khng s d ng,
c l 0.
Bit 5,4 T1CKPS1 : T1CKPS0 : Cc bit ch n t l xung ng vo cho Timer1. 11 1 : 8 gi tr t l 10 01 1 : 4 gi tr t l 1 : 2 gi tr t l ng Timer 1 Oscillator
00 1 : 1 gi tr t l Bit 3 T10SCEN : Bit cho php b dao 1 : Cho php dao ng 0 : Khng cho php dao Bit 2 T1SYNC : Bit l a ch n ng
ng b ha xung clock ngoi c a Timer 1
(Ch : Bit ny ch c tc d ng khi bit TMR1CS = 1) 1: Khng ng b ha xung clock ngo i 0: ng b ha xung clock ngo i. Bit 1 TMR1CS : Bit ch n ngu n xung clock cho Timer 1 1: Ch n xung clock ngoi qua chn T1OSC/T1CKI ( tc 0: Ch n xung clock n i (Fosc/4) Bit 0 TMR1ON: Bit cho php ngo c ngng Timer 1 1: Cho php 0: Khng cho php Chi ti t v cc thanh ghi khc s c trnh by c th trong ph l c 2. Ch : Cc b c vi t chng trnh Delay dng Timer1: + Ch n chia t n thng qua thanh ghi T1CON + t gi tr vo thanh ghi TMR1 ( 8 bit cao a vo TMR1H, 8 bit th p a vo TMR1L) + Cho php b nh th i Timer0 ho t ng (set bit T1CON<0>) + Ki m tra m xong cha? Ki m tra c trn. V du: Vi t chng trnh con t o tr 1s, th ch anh 4Mhz DELAY BCF MOVLW STATUS,5 b'00000000';
51 Ch n chia t n 1:1
ng c nh ln)
MOVWF MOVLW MOVWF BATDAU MOVLW MOVWF MOVLW MOVWF BSF LOOP BTFSS GOTO BCF DECFSZ GOTO RETURN
T1CON d'20'; DEM 3CH TMR1H; AFH TMR1L; T1CON,0; PIR1,0 LOOP PIR1,0 DEM,1; BATDAU DEM=20
TMR1H=B0011 1100 TMR1L=B1010 1111 => TMR1=15535 Cho php b nh th i ho t ng
m xong cha? m 1 n v
Gi m gi tr
4.1.3.TIMER2 Timer2 l b nh th i 8 bit v c h tr b i hai b chia t n s prescaler va postscaler. Thanh ghi ch a gi tr m c a Timer2 l TMR2. Bit cho php ng t Timer2 tc ng l TMR2ON (T2CON<2>). C ng t c a Timer2 l bit TMR2IF (PIR1<1>). Xung ng vo (t n s b ng t n s oscillator) c a qua b chia t n s prescaler 4 bit (v i cc t s chia t n s l 1:1, 1:4 ho c 1:16 v c i u khi n b i cc bit T2CKPS1:T2CKPS0 (T2CON<1:0>)).
Hnh 4.9: C u trc bn trong c a b

52
nh th i Timer2
Timer2 cn c h tr b i thanh ghi PR2. Gi tr t 00h
m trong thanh ghi TMR2 s tng
n gi tr ch a trong thanh ghi PR2, sau c reset v 00h. Khi reset thanh ghi n
PR2 c nh n gi tr m c nh FFh. Ng ra c a Timer2 c a qua b chia t n s postscaler v i cc m c chia t 1:1
1:16. Postscaler c i u khi n b i 4 bit T2OUTPS3:T2OUTPS0. Ng ra c a postscaler ng vai tr quy t nh trong vi c i u khi n c ng t. Ngoi ra ng ra c a Timer2 cn c k t n i v i kh i SSP, do Timer2 cn ng vai tr t o ra xung clock ng b cho kh i giao ti p SSP. Ch : *Cc thanh ghi lin quan n Timer2 bao g m: INTCON ( a ch 0Bh, 8Bh, 10Bh, 18Bh): cho php ton b cc ng t (GIE v PEIE). PIR1 ( a ch 0Ch): ch a c ng t Timer2 (TMR2IF). PIE1 ( a ch 8Ch): ch a bit i u khi n Timer2 (TMR2IE). TMR2 ( a ch 11h): ch a gi tr m c a Timer2. Cc thanh ghi trn chi ti t xem b ng ph l c trang 96 *Thanh i u khi n Timer2: T2CON ( a ch 12h): xc l p cc thng s cho Timer2.
Bit 7: khng s d ng Bit 6:3 TOUTPS3:TOUTPS0: Bit ch n t l ng ra c a Timer 2 0000: 1:1 T l ng ra 0001: 1:2 T l ng ra . 1111: 1:16 T l ng ra Bit 2 TMR2ON: Bit cho php ho t 1: Cho php 0: Khng cho php. Bit 1:0 T2CKPS1:T2CKPS0: Bit ch n t l ng vo c a Timer 2 00 : Prescaler 1 01 : Prescaler 4 1x : Prescaler 16 4.2. ADC ADC (Analog to Digital Converter) l b chuy n i tn hi u gi a hai d ng tng t v s . PIC16F877A c 8 ng vo analog (RA4:RA0 v RE2:RE0). Hi u i n th chu n
53
ng c a Timer 2
VREF c th
c l a ch n l VDD, VSS hay hi u i n th chu n c xc l p trn hai i t tn ti u tng t sang tn hi u s l 10 bit s
chn RA2 v RA3. K t qu chuy n
tng ng v c lu trong hai thanh ghi ADRESH:ADRESL. Khi khng s d ng b chuy n i ADC, cc thanh ghi ny c th c s d ng nh cc thanh ghi thng th ng khc. Khi qu trnh chuy n i hon t t, k t qu s c lu vo hai thanh ghi ADRESH:ADRESL, bit ADCON0<2>) c xa v 0 v c ng t ADIF c set.
Hnh 4.10: S
kh i b chuy n
i ADC:
54
Hnh 4.11: cch lu k t qu chuy n
i AD:
Qui trnh chuy n i t tng t sang s bao g m cc b c sau: B c 1: Ch n s ng vo, i n p chu n Uc. B c 2: Ch n ng vo c th . B c 3: Ch n t n s chuy n i B c 4: Ch n ni ch a k t qu chuy n i. B c 5: B t b chuy n B c 6 :Ki m tra chuy n b c 5. Ch : * Cc thanh ghi lin quan n b chuy n i ADC bao g m: INTCON ( a ch 0Bh, 8Bh, 10Bh, 18Bh): cho php cc ng t (cc bit GIE, PEIE). PIR1 ( a ch 0Ch): ch a c ng t AD (bit ADIF). PIE1 ( a ch 8Ch): ch a bit i u khi n AD (ADIE). ADRESH ( a ch 1Eh) v ADRESL ( a ch 9Eh):thanh ghi ch a k t qu . PORTA ( a ch 05h) v TRISA ( a ch 85h): lin quan PORTE ( a ch 09h) v TRISE ( a ch 89h): lin quan Cc thanh ghi trn chi ti t xem b ng ph l c trang 96 n I/O n I/O i, cho php b chuy n i xong cha? i ho t ng c k t qu v . N u mu n ti p t c th tr l i
* Thanh ghi i u khi n ADC: ADCON0 ( a ch 1Fh) v ADCON1 ( a ch 9Fh): xc l p cc thng s cho b chuy n i AD. Thanh ghi i u khi n ADCON0:
55
Bit 7:6 ADCS1:ADCS0: Cc bit l a ch n t n s chuy n 00 =FOSC/2 01 =FOSC/4 10 =FOSC/32
i A/D
11 =FRC (xung clock c l y t dao ng n i RC) Bit 5:3 CHS2:CHS0: Cc bit l a ch n knh Analog 000: Knh 0, (AN0) 001: Knh 1, (AN1) 010: Knh 2, (AN2) 011: Knh 3, (AN3) 100: Knh 4, (AN4) 101: Knh 5, (AN5) 110: Knh 6, (AN6) 111: Knh 7, (AN7) Bit 2 GO/ DONE: Bit bo tr ng thi chuy n i A/D
Khi bit ADON = 1 1: Qu trnh A/D ang th c hi n (Khi chng ta set bit ny ln th qu trnh chuy n i s x y ra, khi qu trnh k t thc n s t ph n m m). 0: Qu trnh A/D khng x y ra ho c hon t t. Bit 1 Khng s d ng, gi tr l 0 Bit 0 ADON : Bit cho php module A/D ho t 1: Ngu n c cung c p cho A/D 0: Ngng cung c p ngu n cho A/D - Thanh ghi i u khi n ADCON1: ng. ng c xa b ng
Bit 7 ADFM: Bit l a ch n nh d ng k t qu A/D 1: Canh ph i, 6 bit cao nh t c a thanh ghi ADRESH c gi tr 0 0: Canh tri, 6 bit th p nh t c a thanh ghi ADRESL c gi tr 0 Bit 6 ADCS2: Bit l a ch n clock chuy n i A/D
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Bit 5,4 khng s d ng Bit 3:0 PCFG3:PCFG0: Cc bit i u khi n c u hnh cc chn ADC
Chi ti t v cc thanh ghi khc s
c trnh by c th
ph l c trang 94.
V du: Vi t chng trnh con c ADC t ng RA1, K t qu c v (8 bit c lu trong ADRESH) Uc =5v, t c chuy n i 1Mhz, th ch anh 4Mhz. DOC_ADC BSF BCF STATUS,5 STATUS,6
;.Ch n s ng vo BCF ADCON1,3 BSF ADCON1,2 BCF BCF ADCON1,1 ADCON1,0

57
BCF
STATUS,5
;.Ch n ng vo BCF ADCON0,5 BCF ADCON0,4 BSF ADCON0,3 ;Ch n t n s l y m u. BCF ADCON0,7 BCF ADCON0,6 BSF STATUS,5 BSF ADCON1,6 ;...Ch n ni lu k t qu BCF ADCON1,7 BCF STATUS,5 ; Cho php b chuy n BSF ADCON0,0 i ADC ho t ng.
BSF ADCON0,2 ;.Chuy n i xong cha? LOOP BCF STATUS, 5 BTFSC ADCON0 ,2 GOTO LOOP RETURN 4.3. PWM_ I U CH R NG XUNG Khi ho t ng ch PWM (Pulse Width Modulation _ kh i i u ch r ngxung), tn hi u sau khi i u ch s c a ra cc pin c a kh i CCP (c n n nh cc pin ny l output). Cc b c ci t b PWM: 1. Thi t l p th i gian c a 1 chu k c a xung i u ch cho PWM (period) b ng cch a gi tr thch h p vo thanh ghi PR2. 2. Thi t l p r ng xung c n i u ch (duty cycle) b ng cch a gi tr vo thanh ghi CCPRxL v cc bit CCP1CON<5:4>.. 3. Thi t l p gi tr b chia t n s prescaler c a Timer2 v cho php Timer2 ho t b ng cch a gi tr thch h p vo thanh ghi T2CON. 4. Cho php CCP ho t ng ch PWM ng
58
Hnh 4.12: S c a b PWM Trong gi tr 1 chu k (period) c a xung i u ch
c tnh b ng cng th c:
PWM period = [(PR2)+1]*4*TOSC*(gi tr b chia t n s c a TMR2). B chia t n s prescaler c a Timer2 ch c th nh n cc gi tr 1,4 ho c 16 (xem l i Timer2 bi t thm chi ti t). Khi gi tr thanh ghi PR2 b ng v i gi tr thanh ghi TMR2 th qu trnh sau x y ra: Thanh ghi TMR2 t ng c xa. Pin c a kh i CCP c set. Gi tr thanh ghi CCPR1L (ch a gi tr n nh r ng xung i u ch duty cycle) c a vo thanh ghi CCPRxH. r ng c a xung i u ch (duty cycle) c tnh theo cng th c: PWM duty cycle = (CCPRxL:CCPxCON<5:4>)*TOSC*(gi tr b chia t n s TMR2) Nh v y 2 bit CCPxCON<5:4> s ch a 2 bit LSB. Thanh ghi CCPRxL ch a byte cao c a gi tr quy t nh r ng xung. Thanh ghi CCPRxH ng vai tr l buffer cho kh i PWM. Khi gi tr trong thanh ghi CCPRxH b ng v i gi tr trong thanh ghi TMR2 v hai bit CCPxCON<5:4> b ng v i gi tr 2 bit c a b chia t n s prescaler, pin c a kh i CCP l i c a v m c th p, nh v y ta c c hnh nh c a xung i u ch t i ng ra c a kh i PWM nh hnh 4.12 M t s i m c n ch khi s d ng kh i PWM: Timer2 c hai b chia t n s prescaler v postscaler. Tuy nhin b postscaler khng c s d ng trong qu trnh i u ch r ng xung c a kh i PWM. N u th i gian duty cycle di hn th i gian chu k xung period th xung ng ra ti p t c c gi Ch : *Cc thanh ghi lin quan:
59
m c cao sau khi gi tr PR2 b ng v i gi tr TMR2.
Thanh ghi PIR2: a ch 0Dh TMR2 ( a ch 11h): ch a gi tr m c a Timer2. T2CON ( a ch 12h): xc l p cc thng s cho Timer2 Cc thanh ghi trn chi ti t xem b ng ph l c trang 96 * Thanh ghi i u khi n b PWM Thanh ghi CCP1CON v thanh ghi CCP2CON: a ch 17h (CCP1CON) va 1Dh
(CCP2CON)
CCPXX CCPXY CCPXMP3 CCPXMP2 CCPXMP1 CCPXMP0 0 nh mang gi tr 0.
Bit 7,6 Khng c tc d ng v m c
Bit 5,4 CCPxX:CCPxY: PWM least Significant bits (cc bit ny khng c tc d ng ch Capture v Compare). ch PWM, y l 2 bit MSB ch a gi tr tnh r ng xung (duty cycle) c a kh i PWM (8 bit cn l i c ch a trong thanh ghi CCPRxL). Bit 3-0 CCPxM3:CCPxM0 CCPx Mode Select bit Cc bit dng xc l p cc ch ho t ng c a kh i CCPx 0000 khng cho php CCPx (ho c dng reset CCPx) 0100 CCPx ho t ng ch Capture, "hi n t ng" c thi t l p l m i c nh xu ng t i pin dng cho kh i CCPx. 0101 CCPx ho t ng ch Capture, "hi n t ng" c thi t l p l m i c nh ln t i pin dng cho kh i CCPx. 0110 CCPx ho t ng ch Capture, "hi n t ng" c thi t l p l m i c nh ln th 4 t i pin dng cho kh i CCPx. 0111 CCPx ho t ng ch Capture, "hi n t ng" c thi t l p l m i c nh ln th 16 t i pin dng cho kh i CCPx. 1000 CCPx ho t ng ch Compare, ng ra c a ln m c cao v bit CCPxIF c set khi cc gi tr c n so snh b ng nhau. 1001 CCPx ho t ng ch Compare, ng ra c xu ng m c th p v bit CCPxIF c set khi cc gi tr c n so snh b ng nhau. 1010 CCPx ho t ng ch Compare, khi cc gi tr c n so snh b ng nhau, ng t x y ra, bit CCPxIF c set v tr ng thi pin output khng b nh h ng. 1011 CCPx ho t ng ch Compare, khi cc gi tr c n so snh b ng nhau, xung trigger c bi t (Trigger Special Event) s c t o ra, khi c ng t CCPxIF c set, cc pin output khng thay
60
i tr ng thi, CCp1 reset
Timer1, CCP2 reset Timer1 v kh i 11xx CCPx ho t ng ch PWM.
ng kh i ADC.
V d 1: Vi t chng trnh xu t ra xung vung t i chn RC2 c t n s 1Khz (th ch anh 4Mhz) PWM period = [(PR2)+1]*4*TOSC*(gi tr b chia t n s c a TMR2). = 1000S Ta c: TOSC = 0.25 S, ch n gi tr b chia t n s c a TMR2 =1: 4 => PR2 = 250 PWM duty cycle = (CCPR1L:CCP1CON<5:4>)*TOSC*(gi tr b chia t n s TMR2) = 500S => (CCPR1L:CCP1CON<5:4>) = 500= B0111110100 => (CCP1CON<5:4>) = B00 => CCP1L =B01111101 PROCESSOR 16F877A #INCLUDE <P16F877A.INC> ORG 0000H BCF BCF CLRF STATUS,6 STATUS,5 PORTC
;..B c 1.. BSF STATUS,5 BCF TRISC,2 ;..B c 2.. MOVLW D250 MOVWF PR2 ;..B c 3. MOVLW B01111101 MOVWF BCF BCF CCPR1L CCP1CON,5 CCP1CON,4
;..B c4.. BCF T2CON,1 BSF BSF T2CON,0 T2CON,2;
;B c5.. BSF CCP1CON,3

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BSF GOTO END
CCP1CON,2 $
BI T P THAM KH O CHNG 4 Bi 1: Vi t chng trnh i u khi n xung vung t i chn RC2 nh sau:N u nh n nt N1 th xu t ra chn RC2 t n s 1Khz, nh n N2 th xu t ra chn RC2 t n s 2Khz, nh n N3 th t n s xu t ra l 3Khz. (th ch anh 4Mhz).
5V
R N1 RB0
PIC 16F877A RB1 N2 RC2
N3
RB2
Hnh 4.13 PROCESSOR 16F877A #INCLUDE <P16F877A.INC> DEM DEM1 ORG 0000H EQU EQU 20H 21H
BCF BCF CLRF CLRF BSF BCF BSF BSF BSF MAIN
STATUS,6 STATUS,5 PORTC PORTB STATUS,5; TRISC,2 TRISB,0 TRISB,1 TRISB,2 BANK1
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BCF BTFSS GOTO BTFSS GOTO BTFSS GOTO GOTO KT_0 BTFSS GOTO MOVLW MOVWF MOVLW MOVWF GOTO KT_1 BTFSS GOTO MOVLW MOVWF MOVLW MOVWF GOTO KT_2 BTFSS GOTO MOVLW MOVWF MOVLW MOVWF GOTO TAO_XUNG
STATUS,5; PORTB,0 KT_0 PORTB,1 KT_1 PORTB,2 KT_2 MAIN PORTB,0 KT_0 D'250' DEM D'127' DEM1 TAO_XUNG PORTB,1 KT_1 D'125' DEM D'64' DEM1 TAO_XUNG PORTB,2 KT_2 D'63' DEM D'32' DEM1 TAO_XUNG
BANK0
;.BUOC2. BCF STATUS,5; MOVF BSF DEM,0 STATUS,5

63
BANK1
MOVWF
PR2 BANK0
;.BUOC3. BCF STATUS,5; MOVF DEM1,0 MOVWF BCF BCF CCPR1L CCP1CON,5 CCP1CON,4
; BUOC4. BCF T2CON,1 BSF T2CON,0 BSF T2CON,2; CHO TIMER2 HOAT DONG ;.. BUOC5. BSF CCP1CON,3 BSF GOTO END Bi 2: Vi t chng trnh m xung (t chn RA4),sau mi giy r i xu t ra portB PROCESSOR 16F877A #INCLUDE <P16F877A.INC> DEM EQU ORG 0000H BCF BCF CLRF BSF CLRF BCF CLRF BSF MAIN BSF BSF BSF LOOP CALL BCF DELAY_1S STATUS,5
64
CCP1CON,2 MAIN
22H STATUS,6 STATUS,5 PORTB STATUS,5 TRISB STATUS,5 TMR0 STATUS,5 OPTION_REG,4 ; tac dong canh xuong OPTION_REG,5 OPTION_REG,3
MOVF MOVWF CLRF GOTO DELAY_1S BCF MOVLW MOVWF MOVLW MOVWF BATDAU MOVLW MOVWF MOVLW MOVWF BSF LOOP1 BTFSS GOTO BCF DECFSZ GOTO RETURN END Bi 3: Vi t chng trnh
TMR0,W PORTB TMR0 LOOP STATUS,5 B'00100000' T1CON D'20' DEM 3CFH TMR1H 0AFH TMR1L T1CON,0 PIR1,0 LOOP1 PIR1,0 DEM,1 BATDAU
c ADC t ng RA0, K t qu chuy n
c v (8 bit cao c lu trong
ADRESH, Uc = 4.5V, t c PROCESSOR 16F877A
i 1Mhz, th ch anh 4Mhz) xu t ra portB.
#INCLUDE <P16F877A.INC> ORG 0000H BCF BCF CLRF BSF CLRF MAIN CALL DOC_ADC
65
STATUS,6 STATUS,5 PORTB STATUS,5 TRISB
MOVF MOVWF GOTO DOC_ADC BSF BCF
ADRESH,0 PORTB MAIN STATUS,5 STATUS,6
;.Ch n s ng vo BCF ADCON1,3 BCF BCF BSF BCF ADCON1,2 ADCON1,1 ADCON1,0 STATUS,5
;.Ch n ng vo BCF ADCON0,5 BCF ADCON0,4 BCF ADCON0,3 ;Ch n t n s l y m u. BCF ADCON0,7 BCF ADCON0,6 BSF BSF STATUS,5 ADCON1,6
;...Ch n ni lu k t qu BCF ADCON1,7 BCF STATUS,5 ; Cho php b chuy n i ADC ho t BSF ADCON0,0 BSF ;.Chuy n LOOP BCF BTFSC GOTO RETURN END STATUS, 5 ADCON0 ,2 LOOP ng.
ADCON0,2 i xong cha?
66
CHNG 5
CC C NG N I TI P
5.1. USART USART (Universal Synchronous Asynchronous Receiver Transmitter) la mot trong hai chuan giao tiep noi tiep.USART con c goi la giao dien giao tiep noi tiep noi tiep SCI (Serial Communication Interface). Co the s dung giao dien nay cho cac giao tiep vi cac thiet b ngoai vi, vi cac vi ieu khien khac hay vi may tnh. Cac dang cua giao dien USART ngoai vi bao gom: Bat ong bo (Asynchronous). ong bo_ Master mode. ong bo_ Slave mode. Hai pin dung cho giao dien nay la RC6/TX/CK va RC7/RX/DT, trong o RC6/TX/CK dung e truyen xung clock (baud rate) va RC7/RX/DT dung e truyen data. Trong trng hp nay ta phai set bit TRISC<7:6> va SPEN (RCSTA<7>) c0e cho phep giao dien USART. PIC16F877A c tch hp san bo tao toc o baud BRG (Baud Rate Genetator) 8 bit dung cho giao dien USART. BRG thc chat la mot bo em co the c s dung cho ca hai dang ong bo va bat ong bo va c ieu khien bi thanh ghi PSBRG. dang bat ong bo, BRG con c ieu khien bi bit BRGH ( TXSTA<2>). dang ong bo tac ong cua bit BRGH c bo qua. Toc o baud do BRG tao ra c tnh theo cong thc sau:
Trong o X la gia tr cua thanh ghi RSBRG ( X la so nguyen va 0<X<255). Cac thanh ghi lien quan en BRG bao gom: TXSTA (a ch 98h): chon che o ong bo hay bat ong bo ( bit SYNC) va chon mc toc o baud (bit BRGH). RCSTA (a ch 18h): cho phep hoat ong cong noi tiep (bit SPEN). RSBRG (a ch 99h): quyet nh toc o baud.
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5.2. CH
LM VI C
5.2.1. TRUY N D LI U B T NG B Thnh ph n quan tr ng nh t c a kh i truy n d li u l thanh ghi d ch d li u TSR (Transmit Shift Register). Thanh ghi TSR s l y d li u t thanh ghi m dng cho qu trnh truy n d li u TXREG. D li u c n truy n ph i c a tr c vo thanh ghi TXREG. Ngay sau khi bit Stop c a d li u c n truy n tr c c truy n xong, d li u t thanh ghi TXREG s c a vo thanh ghi TSR, thanh ghi TXREG b r ng, ng t x y ra v c hi u TXIF (PIR1<4>) c set. Ng t ny c i u khi n b i bit TXIE (PIE1<4>). C hi u TXIF v n c set b t ch p tr ng thi c a bit TXIE hay tc ng c a chng trnh (khng th xa TXIF b ng chng trnh) m ch reset v 0 khi c d li u m i c a vo thanhh ghi TXREG.
Hnh 5.1: S c a b truy n n i ti p Trong khi c hi u TXIF ng vai tr ch th tr ng thi thanh ghi TXREG th c hi u TRMT (TXSTA<1>) c nhi m v th hi n tr ng thi thanh ghi TSR. Khi thanh ghi TSR r ng, bit TRMT s c set. Bit ny ch c v khng c ng t no c g n v i tr ng thi c a n. M t i m c n ch n a l thanh ghi TSR khng c trong b nh d li u v ch c i u khi n b i CPU. Kh i truy n d li u c cho php ho t ng khi bit TXEN (TXSTA<5>) c set. Qu trnh truy n d li u ch th c s b t u khi c d li u trong thanh ghi TXREG v xung truy n baud c t o ra. Khi kh i truy n d li u c kh i ng l n u tin, thanh ghi TSR r ng. T i th i i m , d li u a vo thanh ghi TXREG ngay l p t c c load vo thanh ghi TSR v thanh ghi TXREG b r ng. Lc ny ta c th hnh thnh m t chu i d li u lin t c cho qu trnh truy n d li u. Trong qu trnh truy n d li u n u bit TXEN b reset v 0, qu trnh truy n k t thc, kh i truy n d li u c reset v pin RC6/TX/CK chuy n n tr ng thi high-impedance.
68
Trong tr ng h p d li u c n truy n l 9 bit, bit TX9 (TXSTA<6>) c set v bit d li u th 9 s c lu trong bit TX9D (TXSTA<0>). Nn ghi bit d li u th 9 vo tr c, v khi ghi 8 bit d li u vo thanh ghi TXREG tr c c th x y ra tr ng h p n i dung thanh ghi TXREG s c load vo thanh ghi TSG tr c, nh v y d li u truy n i s b sai khc so v i yu c u. Tm l i, truy n d li u theo giao di n USART b t ng b , ta c n th c hi n tu n t cc b c sau: 1. T o xung truy n baud b ng cch a cc gi tr c n thi t vo thanh ghi SPBRG v bit i u khi n m c t c baud BRGH. 2. Cho php c ng giao di n n i ti p n i ti p b t set bit PSEN. 3. a 8 bit d li u c n truy n v o thanh ghi TXREG. 4. Set bit TXIE n u c n s d ng ng t truy n. 5. Set bit TX9 n u nh d ng d li u c n truy n l 9 bit. 6. Set bit TXEN cho php truy n d li u (lc ny bit TXIF cng s c set). ng b b ng cch clear bit SYNC v
7. N u nh d ng d li u l 9 bit, a bit d li u th 9 vo bit TX9D. 8. N u s d ng ng t truy n, c n ki m tra l i cc bit GIE v PEIE (thanh ghi INTCON) Ch : * Cc thanh ghi lin quan: Thanh ghi INTCON ( a ch 0Bh, 8Bh, 10Bh, 18Bh): cho php t t c cc ng t. Thanh ghi PIE1 ( a ch 8Ch): ch a bit cho php ng t truy n TXIE. Thanh ghi RCSTA ( a ch 18h): ch a bit cho php c ng truy n d Thanh ghi TXREG ( a ch 19h): thanh ghi ch a d li u c n truy n. Thanh ghi SPBRG ( a ch 99h): quy t nh t c baud. Chi ti t xem b ng ph l c trang 96 * Thanh ghi i u khi n b truy n n i ti p: Thanh ghi PIR1 ( a ch 0Ch): ch a c hi u TXIF Thanh ghi TXSTA ( a ch 98h): Thanh ghi ch a cc bit tr ng thi v i u khi n vi c truy n d li u thng qua chu n giao ti p USART. CSRC Bit 7 Bit 7 CSRC Clock Source Select bit ch b t ng b : khng c n quan tm. ch ng b : CSRC = 1 Master mode (xung clock c l y t b t o xung BRG). CSRC = 0 Slave mode (xung clock c nh n t bn ngoi).
69
TX-9
TXEN
SYNC
BRGH
TRMT
TX9D Bit 0
Bit 6 TX-9 9-bit Transmit Enable bit TX-9 = 1 truy n d li u 9 bit. TX-9 = 0 truy n d li u 8 bit. Bit 5 TXEN Transmit Enable bit TXEN = 1 cho php truy n. TXEN = 0 khng cho php truy n. Bit 4 SYNC USART Mode Select bit SYNC = 1 d ng ng b SYNC = 0 d ng b t ng b . Bit 3 Khng c n quan tm v m c nh mang gi tr 0. Bit 2 BRGH High Baud Rate Select bit, Bit ny ch c tc d ng BRGH = 1 t c BRGL = 0 t c cao. th p. ch b t ng b .
Bit 1 TRMT Transmit Shift Register Status bit TRMT = 1 thanh ghi TSR khng c d li u. TRMT = 0 thanh ghi TSR c ch a d li u. Bit 0 TX9D Bit ny ch a bit d li u th 9 khi d li u truy n nh n l 9 bit. V d : Vi t o n chng trnh nh n d li u t PORTB sau xu t ra Port n i ti p, ch bit, Baud rate =9600, Fosc = 4Mhz. TRUYEN_NOI_TIEP ;Ch n baud rate BSF TXSTA, BRGH MOVLW MOVWF D25 SPBRG ng.. 8
;Cho php c ng n i ti p ho t BCF TXSTA, SYNC BSF LOOP MOVF MOVWF PORTB,W TXREG RCSTA, SPEN
;Xu t gi tr c n truy n vo thanh ghi TXREG.
;Cho php truy n BSF TXSTA, TXEN ;Truy n xong cha?

70
LOOP1 BTFSS GOTO NOP GOTO RETURN PIR1,TXIF LOOP1 LOOP
5.2.2. NH N D LI U B T NG B D li u c a vo t chn RC7/RX/DT s kch ho t kh i ph c h i d li u. Kh i ph c h i d li u th c ch t l m t b d ch d li u ct c cao va c t n s ho t ng g p 16 l n ho c 64 l n t n s baud. Trong khi t c d ch c a thanh thanh ghi nh n d li u s b ng v i t n s baud ho c t n s c a oscillator.
Hnh 5.2: S c a b truy n n i ti p Bit i u khi n cho php kh i nh n d li u l bit RCEN (RCSTA<4>). Thnh ph n quan tr ng nh t c a kh i nh n d li u l thsnh ghi nh n d li u RSR (Receive Shift Register). Sau khi nh n di n bit Stop c a d li u truy n t i, d li u nh n c trong thanh ghi RSR s c a vo thanh ghi RCGER, sau c hi u RCIF (PIR1<5>) s c set v ng t nh n c kch ho t. Ng t ny c i u khi n b i bit RCIE (PIE1<5>). Bit c hi u RCIF l bit ch c v khng th c tc ng b i chng trnh. RCIF ch reset v 0 khi d li u nh n vo thanh ghi RCREG c c v khi thanh ghi RCREG r ng. Thanh ghi RCREG l thanh ghi c b m kp (double-buffered register) v ho t ng theo c ch FIFO (First In First Out) cho php nh n 2 byte v byte th 3 ti p t c c a vo thanh ghi RSR. N u sau khi nh n c bit Stop c a byte d li u th 3 m thanh ghi RCREG v n cn y, c hi u bo trn d li u (Overrun Error bit)
71
OERR(RCSTA<1>) s
c set, d li u trong thanh ghi RSR s b m t i v qu trnh
a d li u t thanh ghi RSR vo thanh ghi RCREG s b gin o n. Trong tr ng h p ny c n l y h t d li u thanh ghi RSREG vo tr c khi ti p t c nh n byte d li u ti p theo. Bit OERR ph i c xa b ng ph n m m v th c hi n b ng cch clear bit RCEN r i set l i. Bit FERR (RCSTA<2>) s c set khi pht hi n bit Stop d a d li u c nh n vo. Bit d li u th 9 s c a vo bit RX9D (RCSTA<0>). Khi c d li u t thanh ghi RCREG, hai bit FERR v RX9D s nh n cc gi tr m i. Do c n c d li u t thanh ghi RCSTA tr c khi tu n t cc b c sau: 1. Thi t l p t c baud ( a gi tr thch h p vo thanh ghi SPBRG v bit BRGH. 2. Cho php c ng giao ti p USART b t ng b (clear bit SYNC v set bit SPEN). 3. N u c n s d ng ng t nh n d li u, set bit RCIE. 4. N u d li u truy n nh n c nh d ng l 9 bit, set bit RX9. 5. Cho php nh n d li u b ng cch set bit CREN. 6. Sau khi d li u c nh n, bit RCIF s RCIE c set). 7. c gi tr thanh ghi RCSTA d li u c b l i khng. c set v ng t c kch ho t (n u bit c d li u t thanh ghi RCREG trnh b m t d li u. ng b c n ti n hnh Tm l i, khi s d ng giao di n nh n d li u USART b t
c bit d li u th 9 v ki m tra xem qu trnh nh n
8. c 8 bit d li u t thanh ghi RCREG. 9. N u qu trnh truy n nh n c l i x y ra, xa l i b ng cch xa bit CREN. 10. N u s d ng ng t nh n c n set bit GIE v PEIE (thanh ghi INTCON). Ch : * Cc thanh ghi lin quan: Thanh ghi INTCON ( a ch 0Bh, 8Bh, 10Bh, 18Bh): ch a cc bit cho php ng t Thanh ghi PIE1 ( a ch 8Ch): ch a bit cho php ng t RCIE. Thanh ghi RCREG ( a ch 1Ah): ch a d li u nh n c. Thanh ghi TXSTA ( a ch 98h): ch a cc bit i u khi n SYNC v BRGH. Thanh ghi SPBRG ( a ch 99h): i u khi n t c Chi ti t cc thanh ghi xem b ng ph l c trang 96 baud.
* Thanh ghi i u khi n b nh n n i ti p: Thanh ghi PIR1 ( a ch 0Ch): ch a c hi u RCIE. Thanh ghi RCSTA: ( a ch 18h)Thanh ghi ch a cc bit tr ng thi v cc bit i u khi n qu trnh nh n d li u qua chu n giao ti p USART. SPEN Bit 7
72
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D Bit 0
Bit 7 SPEN Serial Port Enable bit SPEN = 1 Cho php c ng giao ti p USART (pin RC7/RX/DT v RC6/TX/CK). SPEN = 0 khng cho php c ng giao ti p USART. Bit 6 RX9 9-bit Receive Enable bit RX9 = 1 nh n 9 bit d li u. RX9 = 0 nh n 8 bit d li u. Bit 5 SREN Single Receive Enable bit ch USART b t ng b : bit ny khng c n quan tm. ch USART Master ng b : SREN = 1 cho php ch c nng nh n 1 byte d li u (8 bit ho c 9 bit). SREN = 0 khng cho php ch c nng nh n 1 byte d li u. Bit 4 CREN Continous Receive Enable bit ch b t ng b : CREN = 1 cho php nh n 1 chu i d li u lin t c. CREN = 0 khng cho php nh n 1 chu i d li u lin t c. ch b t ng b : CREN = 1 cho php nh n d li u cho t i khi xa bit CREN. CREN = 0 khng cho php nh n chu i d li u. Bit 3 ADDEN Address Detect Enable bit ch USART b t ng b 9 bit ADDEN = 1 cho php xc nh n a ch , khi bit RSR<8> c set th ng t c cho php th c thi v gi tr trong buffer c nh n vo. ADDEN = 0 khng cho php xc nh n iz5 ch , cc byte d li u c nh n vo v bit th 9 c th c s d ng nh l bit parity. Bit 2 FERR Framing Eror bit FERR = 1 xu t hi n l i "Framing" trong qu trnh truy n nh n d li u. FERR = 0 khng xu t hi n l i "Framing" trong qu trnh truy n nh n d li u. Bit 1 OERR Overrun Error bit, OERR = 1 xu t hi n l i "Overrun" OERR = 0 khng xu t hi n l i "Overrun" Bit 0 RX9D Bit ny ch a bit d li u th 9 c a d li u truy n nh n V d : Vi t o n chng trnh c d li u t Port n i ti p, sau xu t g tr c v ra PORTD Baud rate =9600, Fosc = 4Mhz.
73
NHAN_NOI_TIEP ; Ch n baud rate . BSF TXSTA, BRGH MOVLW D25 MOVWF SPBRG ng ; Cho php c ng n i ti p ho t BCF TXSTA, SYNC BSF RCSTA, SPEN BAT_DAU BSF LOOP BTFSS GOTO PIR1, RCIF LOOP RCSTA,CREN ;Nh n xong cha?..
;Cho php nh n d li u
;C l i khng? BTFSS RCSTA, OERR GOTO BCF GOTO ; DOC_VE MOVF MOVWF GOTO RETURN RCREG,W PORTD LOOP DOC_VE RCSTA, CREN BAT_DAU c k t qu v
BI T P THAM KH O CHNG 5 Bi 1: Vi t chng trnh c d li u t Port n i ti p ( Baud rate =9600, ch 8 bit, th ch anh = 4Mhz), ki m tra k t qu c v . N u l s l th xu t ra PortB, ng c l i khng xu t. PROCESSOR 16F877A #INCLUDE <P16F877A.INC> TEMP EQU ORG 0000H 20H BCF BCF STATUS,6 STATUS,5
74
CLRF CLRF BSF CLRF BCF BCF MAIN CALL BTFSS GOTO MOVF MOVWF GOTO LOOP1 CLRF GOTO DOC_NOI_TIEP
PORTB PORTC STATUS,5 TRISB TRISC,6 TRIC,7 DOC_NOI_TIEP TEMP,0 LOOP1 TEMP,0 PORTB MAIN RCREG MAIN
; Ch n baud rate . BSF TXSTA, BRGH MOVLW MOVWF D25 SPBRG ng
; Cho php c ng n i ti p ho t BCF TXSTA, SYNC BSF RCSTA, SPEN BAT_DAU BSF LOOP BTFSS GOTO PIR1, RCIF LOOP RCSTA,CREN
;Cho php nh n d li u
;Nh n xong cha?..
;C l i khng? BTFSS RCSTA, OERR GOTO BCF GOTO ; DOC_VE RCSTA, CREN BAT_DAU c k t qu v
75
DOC_VE MOVF MOVWF RETURN END Bi 2: Vi t o n chng trnh xu t 30byte trong Ram n i, byte u tin c n i ti p (Baud rate =9600, ch 8 bit, th ch anh = 4Mhz) PROCESSOR 16F877A #INCLUDE <P16F877A.INC> DEM EQU 20H 21H BCF BCF CLRF CLRF BSF BCF BCF BCF
MAIN MOVLW MOVWF MOVLW MOWF BAT_DAU MOVF MOVWF CALL DECFSZ GOTO GOTO TIEP INCF GOTO THOAT NOP GOTO $ 76 FSR,1 MAIN INDF,0 TEMP TRUYEN_NOI_TIEP DEM TIEP THOAT D30 DEM 22H FSR
RCREG,W TEMP
a ch 22H ra Port
TEMP EQU ORG 0000H
STATUS,6 STATUS,5 PORTB PORTC STATUS,5 TRISC,6 TRIC,7 STATUS,5
Gio trnh Vi i u Khi n TRUYEN_NOI_TIEP
;Ch n baud rate BSF TXSTA, BRGH MOVLW MOVWF D25 SPBRG ng..
;Cho php c ng n i ti p ho t BCF TXSTA, SYNC BSF RCSTA, SPEN
;Xu t gi tr c n truy n vo thanh ghi RCREG MOVF TEMP,0 MOVWF TXREG ;Cho php truy n BSF TXSTA, TXEN LOOP1 ;Truy n xong cha? BTFSS PIR1,TXIF GOTO LOOP1 NOP RETURN
END
Bi 3: Vi t chng trnh xu t ki m tra trong Ram n i (bank0) n u k t ch hoa (A, B,CZ) th xu t ra Port n i ti p ( Baud rate =19200, ch 8 bit, th ch anh = 4Mhz).Ng c l i, khng xu t. Bi t ch A c m ASCH l 65. PROCESSOR 16F877A #INCLUDE <P16F877A.INC> TEMP EQU A1H DEM EQU A0H BCF BCF CLRF CLRF BSF CLRF BSF BSF
MAIN MOVLW D97 77
ORG 0000H STATUS,6 STATUS,5 PORTB PORTC STATUS,5 TRISB TRISC,6 TRIC,7
Gio trnh Vi i u Khi n MOVWF MOVLW MOVWF LOOP DECFSZ GOTO GOTO BAT_DAU MOVF MOVWF MOVLW SUBWF BTFSS GOTO INCF GOTO TIEP MOVLW SUBWF BTFSS GOTO GOTO BO_QUA INCF GOTO XUAT FSR,1 LOOP D92 TEMP,0 STATUS,0 BO_QUA XUAT INDF,0 TEMP D65 TEMP,0 STATUS,0 TIEP FSR,1 LOOP DEM 20H FSR DEM BAT_DAU $
BCF MOVLW MOVWF
TXSTA, BRGH D12 SPBRG ng..
;Cho php c ng n i ti p ho t BCF TXSTA, SYNC BSF RCSTA, SPEN
;Xu t gi tr c n truy n vo thanh ghi RCREG MOVF TEMP,0 MOVWF TXREG ;Cho php truy n BSF TXSTA, TXEN ;Truy n xong cha?
78
LOOP1 BTFSS GOTO INCF GOTO END PIR1,TXIF LOOP1 FSR,1

LOOP
79
CHNG 6
NG T - INTERRUPT
6.1 KHI NI M 6.1.1. GI I THI U u tin, Ng t (interrupt) l ci g?, n th t s c ngha gi ng nh tn g i c a n, m t Interrupt l m t tc v x l hay l m t tn hi u x l m n c th b t con Pic d ng l i nh ng g ang lm lm m t cng vi c khc. M t v d d hi u, hy l y sinh ho t hng ngy c a b n, gi s b n ang ng i nh, r i b n ang tn g u v i ai ,thnh lnh chung i n tho i reo, b n ngng cu c ni chuy n l i, nh t i n tho i ln v ni chuy n v i ng i g i n. Khi b n k t thc cu c ni chuy n b ng i n tho i b n l i quay tr v v ti p t c tn g u v i ng i ni chuy n v i b n tr c khi i n tho i reo.By gi b n hy t ng t ng, chng trnh chnh l qu trnh tn g u c a b n v i ng i b n ng i nh, i n tho i reo t o ra m t Interrupt v th t c (routine) Interrups l cu c ni chuy n v i ng i u dy bn kia, khi k t thc cu c ni chuy n b ng i n tho i b n quay v chng trnh chnh ti p t c tn g u. V d ny gi i thch chnh xc m t Interrups t o ra m t ti n trnh x l nh th no. M t chng trnh chnh ang ch y, th c hi n m t vi ch c nng no trn m ch i n, nhng khi Interrupt x y ra chng trnh chnh s t m ngng v ngay lc m t th t c khc c th c hi n, khi th t c ny k t thc con Pic s l i quay v chng trnh chnh. Con Pic c 15 ngu n ng t, khi ng t c x y ra c n: khai bo ng t (Set cc bit i u khi n IE tng ng) v c c ng t tc ng (IF), bi t ng t nh th no chng ta c n xem s sau:
Hnh 6.1: Gi n
80
ng t
Ch thch: Cc Bt i u khi n ng t + Bt GIE: INTCON<7> Cho php ng t ton c c + Bt PEIE: INTCON<6> Cho php ng t ngo i vi + Bt RBIE: INTCON<3> Cho php ng t PortB + Bt INTE: INTCON<4> Cho php ng t RB0 + Bt TMR0IE: INTCON<3> Cho php ng t Timer0 + Bt FEIE: PIE2<4> Cho php ng t EFROM + Bt PSPIE: PIE1<7> Cho php ng t truy n song song + Bt ADIE: PIE1<6> Cho php ng t chuy n i ADC + Bt RCIE: PIE1<5> Cho php ng t nh n n i ti p + Bt TXIE: PIE1<4> Cho php ng t truy n n i ti p + Bt SSPIE: PIE1<3> Cho php ng t truy n nh n n i ti p ang b n + Bt CCP1IE: PIE1<2> Cho php ng t b CCP1 + Bt TMR1IE: PIE1<0> Cho php ng t Timer1 + Bt TMR2IE: PIE1<1> Cho php ng t Timer2 + Bt CCP2IE: PIE2<0> Cho php ng t b CCP2 + Bt BCLIE: PIE2<3> Cho php ng t truy n nh n n i x y ra + Bt CMIE: PIE2<6> Cho php ng t b so snh Cc Bt c ngt + Bt RBIF: INTCON<0> C ng t PortB + Bt INTF: INTCON<1> C ng t RB0 + Bt TMR0IF: INTCON<2> C ng t Timer0 + Bt FEIF: PIR2<4> C ng t EFROM + Bt PSPIF: PIR1<7> C ng t truy n song song + Bt ADIF: PIR1<6> C ng t chuy n i ADC + Bt RCIF: PIR1<5> C ng t nh n n i ti p + Bt TXIF: PIR1<4> C ng t truy n n i ti p + Bt SSPIF: PIR1<3> C ng t truy n nh n n i ti p ang b n + Bt CCP1IF: PIR1<2> C ng t b CCP1 + Bt TMR1IF: PIR1<0> C ng t Timer1 + Bt TMR2IF: PIR1<1> C ng t Timer2 + Bt CCP2IF: PIR2<0> C ng t b CCP2 + Bt BCLIF: PIR2<3> C ng t truy n nh n n i x y ra + Bt CMIF: PIR2<6> C ng t b so snh Gi s trong chng trnh chnh chng ta c s d ng Timer0. khi chng trnh ang th c thi, n u b nh th i Timer0 m xong s bo cho chng ta bi t thng qua c trn
81
TR0IF. V y n chng ta dng ng t Timer0 th chng ta c n SET bit TMR0IE v SET bit GIE. Tng t n u chng ta c n dng ng t ngo i vi RB th c n SET bit RBIE v SET bit GIE. Tuy nhin, chng ta c n ng t Timer1 th ngoi vi c c n SET bit TMR1IE v SET bit GIE v c n SET thm bit PEIE =>D a vo s ORG 0000H ; GOTO MAIN ; trn chng ta c n Set bit no khi khai bo ng t. a ch RESET Nh y vo chng trinh chnh
6.1.2. C U TRC CHNG TRNH C DNG NG T
;..INTERRUPT ROUTINE. ORG 04H ; a ch vect ng t Lu cc gi tr t m th i vo Ram n i ( N u cc gi tr ny thay thi chng trnh ng t) i khi th c
Th c thi chng trnh ng t Thot ng t - Tr cc gi tr t Ram n i vo cc thanh ghi lu - Xa c ng t RETFIE ; k t thc chng trnh ng t ; MAIN PROGRAM.
MAIN

END
Khai bo ng t (Chng ta khai bo l ng t g? Ng t ngo i vi, ng t timer hay ng t ADC.) Th c thi chng trnh chnh Vng l p v h n u ngay i m nh p RESET g p l nh Goto
o n chng trnh trn ta th y, khi b t
MAIN khi chng trnh th c thi chng trnh chnh. Trong su t qu trnh th c thi n u c ng t x y ra ( gi ng nh b n ang tn g u v i ai ,thnh lnh chung i n tho i reo) th chng trnh l p t c t m ng ng tr v a ch vect ng t ORG 04H th c thi chng trnh ng t (b n ngng cu c ni chuy n l i, nh t i n tho i ln vni chuy n v i ng i g i n). Khi k t thc chng trnh ng t g p l nh RETFIE th chng trnh tr l i ni n ra i (gi ng nh b n nghe i n tho i xong tr l i v i tn g u ti p cu chuy c dang d ). 6.2 NG T RB0 Ng t ny d a trn s thay i tr ng thi c a pin RB0/INT. C nh tc ng gy ra ng t c th l c nh ln hay c nh xu ng v c i u khi n b i bit INTEDG (thanh ghi OPTION_REG <6>). Khi c c nh tc ng thch h p xu t hi n t i pin RB0/INT, c ng t INTF c set b t ch p tr ng thi cc bit i u khi n GIE v PEIE.
82
Thanh ghi OPTION chnh l thanh ghi thi t l p ch
cho Interrupt tch c c
c nh
ln hay c nh xu ng c a tn hi u vo, Bit 6 c a thanh ghi OPTION c g i l INTEDG, n u Set Bit6 s thi t l p interrupt tch c c c nh ln c a tn hi u vo (tr ng thi default), n u Clear Bit6 s thi t l p interrupt tch c c c nh xu ng c a tn hi u vo. M c nhin sau khi b t ngu n con Pic s thi t l p ch Interrupt c nh ln, c ngha l interrup x y ra khi tn hi u vo thay i t th p ln cao (c nh ln). V d : Cho s nh hnh v , vi t chng trnh cho th a: Mi l n nh n nt N, bung ra gi tr trn Led 7 o n tng 1 n v
Hnh 6.2 PROCESSOR 16F877A #INCLUDE <P16F877A.INC> DEM EQU 20H ORG 0000H GOTO ORG 04H MOVWF INCF MOVLW XORWF BTFSC CLRF MOVF TEMP DEM,1 D'10' DEM,0 STATUS,2 DEM TEMP,W
83
MAIN
BCF RETFIE MAIN BSF BSF BCF BSF CLRF BCF CLRF LOOP MOVF MOVWF GOTO END
6.3. NG T PORTB
INTCON,1
INTCON,7 INTCON,4 STATUS,6 STATUS,5 TRISD STATUS,5 DEM DEM,W PORTD LOOP
Tng t nh ng t RB0, nhng d a vo s bi n
i tr ng thi c a cc chn t
RB4RB7. T c l khi RB4RB7 c s bi n i tr ng thi th c ng t RBIF tch c c m c cao. V y s d ng ng t PortB trong chng trnh chnh chng ta c n Set bit RBIE (INTCON<4>) v Set bit GIE (INTCON<7>) V d : Vi t chng trnh cho m ch ch ng tr m, 4 ng vo (RB4RB7), 1 ng ra (RA0). M t trong 4 ng vo c tc ng ng ra tch c c m c cao. PROCESSOR 16F877A #INCLUDE <P16F877A.INC> ORG 0000H GOTO ORG 04H GOTO MAIN BSF BSF BCF BSF BCF INTCON,7 INTCON,3 STATUS,6 STATUS,5 TRISA,0
84
MAIN NGAT
GOTO NGAT BCF BCF BSF BCF RETFIE END

6.4. NG T TIMER
$ STATUS,6 STATUS,5 PORTA,0 INTCON,0
Nh chng ta bi t, gi tr trong b Timer s tng theo mi xung nh p tc ng, i v i Timer0 v Timer2 th khi thanh ghi TMR0 ho c TMR2 t gi tr FFH (255) th khi c trn TMR0IF ho c TMR2IF s tch c c m c cao. Ring i v i Timer1 c trn TMR1IF t gi tr tch c c m c cao th gi tr trong thanh TMR1 (16 Bit g m 2 thanh ghi TMR1H v TMR1L) ph i t gi tr l FFFFH (65535) s d ng ng t TIMER chng ta bi t r mnh s d ng Timer no m Set Bit TMRXIE tng ng khi khai bo, ng th i Set Bit PEIE v Bit GIE (ring i Timer0 th khng c n Set Bit PEIE) V d : Vi t chng trnh t o xung vung t i chn RD0, t n s f=10hz, dng ng t PROCESSOR 16F877A #INCLUDE <P16F877A.INC> ORG 0000H GOTO MAIN ORG 04H BCF BCF MOVLW XORWF BCF MOVLW MOVWF MOVLW MOVWF RETFIE MAIN BSF BSF INTCON,7 INTCON,6
85
STATUS,6 STATUS,5 B'00000001' PORTD,1 PIR1,0 3CH TMR1H 0AFH TMR1L
BCF BSF BSF BCF BCF CLRF BSF BCF BCF LOOP MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF BSF GOTO END
6.5. NG T ADC
STATUS,6 STATUS,5 PIE1,0 STATUS,6 STATUS,5 PORTD STATUS,5 TRISD,0 STATUS,5 B'00000000' T1CON 3CH TMR1H 0AFH TMR1L T1CON,0 $
i v i b chuy n i ADC sau khi thi t l p cc ch chu n, t n s chuy n i) xong, sau cho b chuy n
(Ch n ng vo, i n p i ADC b t u ho t ng
thng qua bit ADON (ADCON0 <2>). M t th i gian sau, kho ng vi trm S th qu trnh chuy n i hon t t, khi c ng t ADIF c Set ln m c cao. N u chng ta Set cc Bit ADIE, PEIE v Bit GIE th khi ng t s x y ra. V d : Lm l i bi t p 3 chng 4 (trang 67), dng ng t PROCESSOR 16F877A #INCLUDE <P16F877A.INC> ORG 0000H GOTO ORG 04H GOTO MAIN BSF BSF INTCON,7 INTCON,6
86
MAIN NGAT_ADC
BSF BSF BCF
PIE1,6 STATUS,5 STATUS,6
;.Ch n s ng vo BCF ADCON1,3 BCF ADCON1,2 BCF ADCON1,1 BSF ADCON1,0 ;.Ch n ng vo BCF STATUS,5 BCF BCF BCF ADCON0,5 ADCON0,4 ADCON0,3
;Ch n t n s l y m u. BCF ADCON0,7 BCF BSF BSF ADCON0,6 STATUS,5 ADCON1,6
;...Ch n ni lu k t qu BCF ADCON1,7 BCF STATUS,5 ; Cho php b chuy n i ADC ho t ng. STAR BSF ADCON0,2 BSF ADCON0,0 ;.Chuy n i xong cha? BCF STATUS, 5 LOOP BTFSC GOTO NOP GOTO NGAT_ADC MOVF MOVWF BCF RETFIE END
87
PIR1,6 LOOP STAR ADRESH,0 PORTB PIR1,6
Gio trnh Vi i u Khi n 6.6. NG T PORT N I TI P
Tng t nh ng t ADC, c ng t Set ln m c cao.
i v i truy n nh n n i ti p, khi truy n (nh n) xong 1 byte th ng t x y ra ta Set cc Bit i u khi n tng ng, i v i
truy n n i ti p chng ta c n Set 3 Bit i u khi n trong khi khai bo:GIE, PEIE v TXIE. Cn i v i nh n n i ti p th cc Bt c n Set: GIE, PEIE v RCIE V d : Lm l i bi t p 2 chng 5 (trang 78), dng ng t PROCESSOR 16F877A #INCLUDE <P16F877A.INC> DEM EQU TEMP ORG 0000H GOTO ORG 04H GOTO
MAIN
20H 21H
EQU
MAIN NGAT_TRUYEN INTCON,7 INTCON,6 PIE1,4 STATUS,6 STATUS,5 PORTC STATUS,5 TRISC,6 TRIC,7 STATUS,5
D30 DEM 22H FSR
BSF BSF BSF BCF BCF CLRF BSF BCF BCF BCF
MOVLW MOVWF MOVLW MOWF TRUYEN_NOI_TIEP
;Ch n baud rate.. BSF TXSTA, BRGH MOVLW D25 MOVWF SPBRGN ; Cho php c ng n i ti p ho t ng.. BCF TXSTA, SYNC
88
BSF
RCSTA, SPEN
;Xu t gi tr c n truy n vo thanh ghi RCREG MOVF TEMP,0 MOVWF TXREG ;Cho php truy n BSF TXSTA, TXEN ;Truy n xong cha? N u truy n xong th vo ng t, r i tr l i, truy n ti p. LOOP1 BTFSS GOTO NOP GOTO NGAT_TRUYEN
DECFSZ GOTO GOTO TIEP INCF MOVF MOVWF BCF RETFIE END FSR,1 INDF,0 TEMP PIR1,4 TRUYEN_NOI_TIEP DEM TIEP $
PIR1,TXIF LOOP1
BI T P THAM KH O CHNG 6 Bi 1: N u RB0 tc 3 giy. ng c nh ln th xu t ra chn RC2 m t chu i xung c t n s f=1Khz trong
PROCESSOR 16F877A #INCLUDE <P16F877A.INC> DEM EQU 22H ORG 0000H GOTO ORG 04H GOTO MAIN BCF BCF BSF STATUS,6 STATUS,5 INTCON,7
89
MAIN NGAT
BSF GOTO NGAT
INTCON,4 $
;T o xung dng kh i PWM, c t n s 1Khz ;.........Buoc 1.......... BSF STATUS,5 BCF TRISC,2 ;.........Buoc 2.......... MOVLW D'250' MOVWF PR2 ;..........Buoc 3......... BCF MOVLW MOVWF BCF BCF STATUS,5 D'127' CCPR1L CCP1CON,5 CCP1CON,4
;..........Buoc4.......... BCF T2CON,1 BSF T2CON,0 BSF T2CON,2; CHO TIMER2 HOAT DONG ;...........Buoc5......... BSF CCP1CON,3 BSF CCP1CON,2 ;.........TAO TRE......... MOVLW D'100' MOVWF DEM MOVLW MOVWF STAR MOVLW MOVWF MOVLW MOVWF BSF TEMPS BTFSS GOTO PIR1,0 TEMPS
90
B'00000000' T1CON 3CH TMR1H 0AFH TMR1L T1CON,0
BCF DECFSZ GOTO
PIR1,0 DEM STAR
;.........T T XUNG........ BCF STATUS,5 CLRF CCPR1L BCF CCP1CON,5 BCF CCP1CON,4 BSF BSF BCF RETFIE END Bi 2: Vi t chng trnh i u khi n
5V
CCP1CON,3 CCP1CON,2 INTCON,1
ng c: (hnh 6.3)
Vcc
R N1 RB0
PIC 16F877A RB4 N2 RB4
RB5 N3 RB5
Q1
Q2
Hnh 6.3 Nt N1 (nt ON/OFF): Khi nh n N1 n u ng c ang ho t Nt N2 (thu n): Nh n nt N2
ng th ng ng v ng c l i ng h . ng h .
ng c quay thu n, cng chi u kim
Nt N3 (ng c): Nh n nt N3 ng c quay ng c, ng c chi u kim Khi ng c ng ng (khng ho t ng, nt N2, N3 khng c tc d ng
PROCESSOR 16F877A #INCLUDE <P16F877A.INC> DEM ORG 0000H EQU GOTO 20H MAIN 91
Gio trnh Vi i u Khi n ORG 04H GOTO MAIN BSF BSF BSF BCF BSF BCF BCF BCF CLRF CLRF STAR BTFSS GOTO GOTO ON BSF GOTO STOP BCF BCF BCF GOTO NGAT BTFSC GOTO MOVLW XORWF BCF RETFIE NGAT_2 BTFSS GOTO BTFSS GOTO GOTO THUAN 92 DEM,1 X PORTB,5 THUAN NGHICH INTCON,0 NGAT_2 B'00000001' DEM,1 INTCON,1 PORTD,0 PORTD,7 DEM,1 STAR DEM,1 STAR DEM,0 STOP ON INTCON,7 INTCON,4 INTCON,3 STATUS,6 STATUS,5 TRISD,0 TRISD,7 STATUS,5 PORTD DEM NGAT
Gio trnh Vi i u Khi n BSF BCF GOTO NGHICH BCF BSF X Y BTFSS GOTO BTFSS GOTO BCF RETFIE END PORTD,7 PORTD,0 PORTB,4 X PORTB,5 Y INTCON,0 PORTD,7 PORTD,0 X
93
PH L C: GI I THIU L P TRNH CCS
Chong I: T p L nh Trong CCS

I.1. Cc Php Ton Trong CCS
I.1.1. Cch Khai Bo Bi n, H ng, M ng I.1.1.1.Cac loai bien sau c ho tr : int1 so 1 bit = true hay false ( 0 hay 1) int8 so nguyen 1 byte ( 8 bit) int16 so nguyen 16 bit int32 so nguyen 32 bit char ky t 8 bit float so thc 32 bit short mac nh nh kieu int1 byte mac nh nh kieu int8 int mac nh nh kieu int8 long mac nh nh kieu int16 Them signed hoac unsigned pha trc e ch o la so co dau hay khong dau .Khai bao nh tren mac nh la khong dau . 4 khai bao cuoi khong nen dung v de nham lan . Thay vao o nen dung 4 khai bao au . VD : Signed int8 a ; // so a la 8 bit dau ( bit 7 la bit dau ). Signed int16 b , c , d ; Signed int32 , . . . Pham vi bien : Int8 :0 , 255 signed int8 : -128 , 127 Int16 : 0 ,215-1 signed int16 : -215 , 215-1 Int32 : 0 , 232-1 signed int32 : -231 , 231-1 Khai bao hang : VD : Int8 const a=231 ; I.1.1.1.Khai bao 1 mang hang so : VD : Int8 const a[5] = { 3,5,6,8,6 } ; //5 phan t , ch so mang bat au t 0 : a[0]=3 Mot mang hang so co kch thc toi a tuy thuoc loai VK: NeuVK la PIC 14 ( VD :16F877 ) : ban ch c khai bao 1 mang hang so co kch thc toi a la256 byte .Cac khai bao sau la hp le. Int8 const a[5]={ . . .}; // s dung 5 byte , dau . . . e ban ien so vao Int8 const a[256]={ . . .}; // 256 phan t x 1 byte = 256 byte Int16 const a[12] = { . . . }; // 12 x 2= 24 byte Int16 const a[128] = { . . . }; // 128 x 2= 256 byte I.1.2. Cc php ton s h c + C ng ++ Tng 1 n v Tr -Gi m 1 n v
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* Nhn / Chia % Chia l y d = B ng, th c hi n gin I.1.3. Cc php ton Logic && Php ton AND || Php ton OR >> D ch ph i << D ch tri ! o bit ~ L y b & AND t ng bit | Or t ng bit I.1.4. Cc php ton so snh == So snh b ng > L n hn. >= L n hn ho c b ng. < Nh hn <= Nh hn ho c b ng != Khc
I.2. Cc Ki u i u Khi n Trong CCS

I.2.1. Ki u: If Else C php: If ( i u ki n) { Nh ng l nh th a i u ki n; } Else { Nh ng l nh th a i u ki n; } I.2.2. Ki u: While C php: While ( i u ki n) { Nh ng l nh th a i u ki n; } Ch : Trong vng l p While i u ki n lun c ki m tra I.2.3. Ki u: Do While C php: Do { Nh ng l nh ; } While ( i u ki n) I.2.4. Ki u: For C php: For (bi u th c kh i t o; bi u th c i u ki n;bi u th c tc ng)
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{ l nh;} I.2.5. Ki u: witchcase switch (bi u th c) { case gi tr 1: { l nh 1; break; } case gi tr 2: { l nh 2; break; } . default: { l nh ; break ; } } I.3. C u Trc Chng Trnh V D : Vi t chng trnh t i RB0 m c cao #include <16f877a.h> #fuses nowdt,noprotect,nolvp,xt,put #use delay(clock=4000000) #use fast_io(b) #byte portb = 0x6 #bit b0 = portb.0 void main( ) { set_tris_b(0b0); while (true) { b0=1; } }
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Chng II: S D ng Cc Kh i Ch c Nng.

II.1. S D ng Hm Delay III.1.1. Delay_cycles (count ) Count : hang so t 0 255 , la so chu ky lenh .1 chu ky lenh bang 4 chu ky may . ham khong tra ve tr . Ham dung delay 1 so chu ky lenh cho trc . VD : delay_cycles ( 25 ) ; // vi OSC = 20 Mhz , ham nay delay 5 us III.1.2.Delay_us ( time ) Time : la bien so th = 0 255 , time la 1 hang so th = 0 -65535 . Ham khong tra ve tr .Ham nay cho phep delay khoang thi gian dai hn theo n v us .Quan sat trong C / asm list ban se thay vi time dai ngan khac nhau , CSS sinh ma khac nhau . III.1.3.Delay_ms (time ) Time = 0-255 neu la bien so hay = 0-65535 neu la hang so . Ham khong tra ve tr . Ham nay cho phep delay dai hn na . VD : Int a = 215; Delay_us ( a ) ; // delay 215 us Delay_us ( 4356 ) ; // delay 4356 us Delay_ms ( 2500 ) ; // delay 2 . 5 s II.2. S D ng Kh i ADC. B ng khai bo s d ng s ng vo Analog: - ALL_ANALOGS : dung tat ca chan sau lam analog : A0 A1 A2 A3 A5 E0 E1 E2 (Vref=Vdd) - NO_ANALOG : khong dung analog , cac chan o se la chan I /O . - AN0_AN1_AN2_AN4_AN5_AN6_AN7_VSS_VREF : A0 A1 A2 A5 E0 E1 E2 VRefh=A3 - AN0_AN1_AN2_AN3_AN4 : A0 A1 A2 A3 A5 - AN0_AN1_AN3 : A0 A1 A3 , Vref = Vdd - AN0_AN1_VSS_VREF : A0 A1 VRefh = A3 - AN0_AN1_AN4_AN5_AN6_AN7_VREF_VREF : A0 A1 A5 E0 E1 E2 VRefh=A3 , VRefl=A2 . - AN0_AN1_AN2_AN3_AN4_AN5 : A0 A1 A2 A3 A5 E0 - AN0_AN1_AN2_AN4_AN5_VSS_VREF : A0 A1 A2 A5 E0 VRefh=A3 - AN0_AN1_AN4_AN5_VREF_VREF : A0 A1 A5 E0 VRefh=A3 VRefl=A2 - AN0_AN1_AN4_VREF_VREF : A0 A1 A5 VRefh=A3 VRefl=A2 - AN0_AN1_VREF_VREF : A0 A1 VRefh=A3 VRefl=A2 - AN0 : A0 - AN0_VREF_VREF : A0 VRefh=A3 VRefl=A2
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* Chng trnh s d ng c ADC: Void Doc_ADC() { setup_ADC(ADC_clock_internal); // div_by_2 setup_ADC_ports(AN0); set_ADC_channel(0); delay_us(800); } II.3. S D ng PWM. Void Xuat_xung() { setup_ccp1(CCP_PWM); set_pwm1_duty(150); // TH=150*4 setup_timer_2(t2_div_by_4,200,1); // T=200*4 } II.4. Truy n N i Ti p II.4.1. Chu n RS232 a. GETC(), GETCH(), GETCHAR(): Hm ny c dng i nh n 1 k t t pin RS232 RCV. N u khng mu n i k t g iv . + C php:: ch = getc() ch = getch() ch = getchar() + Tr tr v : k t 8 bit + Yu c u: #use rs232 V d : #include <16f877.h> #use delay(clock=20000000) #use rs232(baud=9600,parity=N,xmit=PIN_C6,rcv=PIN_C7) char answer; void main() { printf("Continue (Y,N)?"); answer=getch(); } while(answer!='Y' && answer!='N'); b. GETS(), Hm ny c dng c cc k t (dng GETC()) trong chu i cho n khi g p l nh RETURN + C php:: gets(char *string) + Tham s : string l con tr (pointer) ch n dy k t + Yu c u: #use rs232 V d : #include <16f877.h> #include <string.h> #use delay(clock=20000000) #use rs232(baud=9600,parity=N,xmit=PIN_C6,rcv=PIN_C7) char string[30];
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void main() { printf("Input string: "); gets(string); printf("\n\r"); printf(string); } c. PUTC(), PUTCHAR(): Hm ny c dng g i m t k t thng qua pin RS232 XMIT. Ph i dng #USE RS232 tr c khi th c hi n l nh ny xc nh t c (baud rate) v pin truy n. + C php: putc(cdata) putchar(cdata) + Tham s : cdata l k t 8 bit + Tr tr v : khng + Yu c u: #use rs232 V d : #include <16f877.h> #use delay(clock=20000000) #use rs232(baud=9600,parity=N,xmit=PIN_C6,rcv=PIN_C7) int i; char string[10]; void main() { strcpy(string,"Hello !"); //copy Hello ! to string for(i=0; i<10; i++) putc(string[i]); //put each charater of string onto screen } d. PUTS(): Hm ny c dng g i m i k t trong chu i n pin RS232 dng PUTC(). Sau khi chu i c g i i th RETURN (13) v LINE-FEED (10) u c g i i. L nh printf() th ng dng hn l nh puts(). + C php: puts(string) + Tham s : string l chu i h ng (constant string) hay dy k t (character array) + Tr tr v : khng + Yu c u: #use rs232 V d : Dng PUTS() #include <16f877.h> #use delay(clock=20000000) #use rs232(baud=9600,parity=N,xmit=PIN_C6,rcv=PIN_C7) void main() { puts(" ------------- "); puts(" | Hello | "); puts(" ------------- "); } Dng PRINTF() #include <16f877.h>
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#use delay(clock=20000000) #use rs232(baud=9600,parity=N,xmit=PIN_C6,rcv=PIN_C7) void main() { printf(" ------------- \n\r"); printf(" | Hello | \n\r"); printf(" ---------------"); } e. KBHIT(): Hm ny c dng bo nh n c bit start. + C php:: value = kbhit() + Tham s : khng + Tr tr v : 0 (hay FALSE) n u getc() c n ph i i nh n 1 k t t bn Phm 1 (hay TRUE) n u c 1 k t s n sng nh n b ng getc(). + Yu c u: #use rs232 f. PRINTF(): Hm ny c dng xu t m t chu i theo chu n RS232 ho c theo m t hm xc nh. D li u c nh d ng ph h p v i i s c a chu i. Cc nh d ng d li u nh sau: C Ki u k t S Chu i ho c k t U S nguyn khng d u x Hex int (xu t ch th ng) X Hex int (xu t ch hoa) D s nguyn c d u e S th c nh d ng ki u s m f Ki u d u ch m ng Lx Hex long int (ch th ng) LX Hex long int (ch hoa) Iu s th p phn khng d u Id S th p phn c d u. %D u% + C php: printf(string) printf(cstring, values...) printf(fname, cstring, values...) + Tham s : String l m t chu i h ng Ho c m t m ng k t khng xc nh. Values l danh sch cc bi n phn cch nhau b i d u , , fname is l tn hm dng xu t d li u (m c nhin l putc()). + Tr tr v : khng + Yu c u: #use rs232 g. SET_UART_SPEED(): Hm ny c dng tt c truy n d li u thng qua c ng RS232. + C php:: set_uart_speed(baud) + Tham s : baud l h ng s t c truy n (bit/giy) t 100 n 115200. + Tr tr v : khng + Yu c u: #use rs232 V d : // Set baud rate based on setting of pins B0 and B1 switch(input_b() & 3)
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{ case 0 : set_uart_speed(2400); break; case 1 : set_uart_speed(4800); break; case 2 : set_uart_speed(9600); break; case 3 : set_uart_speed(19200); break; } II.4.2. Chu n I2C a. #USE I2C(): Th vi n I2C g m cc hm dng cho I2C bus. #USE I2C dng v i cc l nh I2C_START,I2C_STOP, I2C_READ, I2C_WRITE and I2C_POLL. Cc hm ph n m m c t o ra tr khi dng l nh FORCE_HW. + C php: #use i2c(mode,SDA=pin,SCL=pin[options]) + Tham s : mode: master/slave - t master/slave mode SCL=pin ch nh pin SCL (pin l bit address) SDA=pin ch nh pin SDA options nh sau ADDRESS=nn : ch nh a ch slave mode FAST : s d ng fast I2C specification SLOW : s d ng slow I2C specification RESTART_WDT : kh i ng l i WDT trong khi ch c I2C_READ FORCE_HW : s d ng ch c nng I2C ph n c ng (hardware I2C functions) b. I2C_START(): Hm ny c dng Kh i ng start bit (bit kh i ng) I2C master mode. Sau khi kh i ng start bit, xung clock m c th p ch n khi l nh I2C_WRITE() c th c hi n. Ch I2C protocol ph thu c vo thi t b slave. + C php:: i2c_start() + Tham s : khng + Tr tr v : khng + Yu c u: #use i2c V d : i2c_start(); i2c_write(0xa0); //Device address i2c_write(address); //Data to device i2c_start(); //Restart i2c_write(0xa1); //to change data direction data=i2c_read(0); //Now read from slave i2c_stop(); c. I2C_STOP(): Hm ny c s d ng t t s d ng I2C master mode. + C php: i2c_stop() + Tham s : khng + Tr tr v : khng + Yu c u: #use i2c V d : i2c_start(); //Start condition i2c_write(0xa0); //Device address i2c_write(5); //Device command i2c_write(12); //Device data i2c_stop(); //Stop condition d. I2C_POLL():
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Hm ny c dng h i vng I2C, hm ny ch c dng khi SSP c dng. Hm ny tr v gi tr TRUE n u nh n c gi tr b m. Khi hm ny ln TRUE, n u dng hm I2C_READ th ta c gi tr cv . + C php: i2c_poll() + Tham s : khng + Tr tr v : 1 (TRUE) hay 0 (FALL) + Yu c u: #use i2c V d : i2c_start(); //Start condition i2c_write(0xc1); //Device address/Read count=0; while(count!=4) { while(!i2c_poll()) ; buffer[count++]= i2c_read(); //Read Next } i2c_stop(); // Stop condition e. I2C_READ(), I2CREAD(ACK): Hm ny c dng c m t byte qua c ng I2C thi t b master: l nh ny t o xung clock v thet b claver, l nh ny ch c xung clock. There is no timeout for the slave, use I2C_POLL to prevent a lockup. Use ESTART_WDT in the #USE I2C to strobe the watch-dog timer in the slave mode while waiting. C php: i2c_stop() i2c_stop(ack) Tham s : ty ch n, m c nh l 1 ack = 0: khng ki m tra tr ng thi thu g i tn hi u (ack: acknowlegde) ack = 1: ki m tra tr ng thi thu g i tn hi u Tr tr v : 8 bit int Yu c u: #use i2c V d : i2c_start(); i2c_write(0xa1); data1 = i2c_read(); data2 = i2c_read(); i2c_stop(); f. I2C_WRITE(): Hm ny c dng G i t ng byte thng qua giao di n I2C. ch ch s pht ra xung Clock v i d li u v ch Slave s ch xung Clock t con ch truy n v . Khng t ng m ngoi l i u ki n c a l nh ny. L nh ny s tr v bit ACK. Pht LSB tr c khi truy n khi xc nh h ng truy n c a d li u truy n (0 cho master sang slave). Ch chu n giao ti p I2C ph thu c vo thi t b slave. + C php: i2c_write(data) + Tham s : data: 8 bit int + Tr tr v : L nh ny tr v bit ACK ack = 0: khng ki m tra tr ng thi thu g i tn hi u (ack: acknowlegde) ack = 1: ki m tra tr ng thi thu g i tn hi u + Yu c u: #use i2c V d : long cmd; ...
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i2c_start(); //Start condition i2c_write(0xa0); //Device address i2c_write(cmd); //Low byte of command i2c_write(cmd>>8); //High byte of command i2c_stop(); //Stop condition
Chng III: S D ng Ng t
III.1. C u Trc Chng Trnh C S D ng Ng t.
III.1.1. Khai Bo Ng t. Enable_interrupts(int_EXT);// Cho php ng t ngoi Enable_interrupts(global); // Cho php ng t ton c c #INT_AD : chuyen oi A /D a hoan tat , thng th khong nen dung #INT_CCP1 : co Capture hay compare tren CCP1 #INT_CCP2 : co Capture hay compare tren CCP2 #INT_COMP : kiem tra bang nhau tren Comparator #INT_EXT : ngat ngoai #INT_I2C : co hoat ong I 2C #INT_LCD : co hoat ong LCD #INT_PSP : co data vao cong Parallel slave #INT_RB : bat ky thay oi nao tren chan B4 en B7 #INT_RDA : data nhan t RS 232 san sang #INT_RTCC : tran Timer 0 #INT_SSP : co hoat ong SPI hay I 2C #INT_TBE : bo em chuyen RS 232 trong #INT_TIMER0 : mot ten khac cua #INT_RTCC #INT_TIMER1 : tran Timer 1 #INT_TIMER2 : tran Timer 2 III.1.2 C u Trc Chng Trnh #include <16F877a.h> #fuses XT,NOWDT,NOPROTECT,NOLVP #use delay(clock=4000000) #INT_x void ngat(); void main() { enable_interrupts(int_x);// Khai bo ng t g? enable_interrupts(global); // Cho php ng t ton c c Chng trnh chnh; } void ngat() { X l ng t; } III.2. S D ng Ng t III.2.1. Ng t RB0 #include <16F877a.h> #fuses XT,NOWDT,NOPROTECT,NOLVP
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#use delay(clock=4000000) #use fast_io(b) #byte portb=0x6 #bit b7=portb.7 #INT_EXT void ngat() { b7=!b7; } void main() { enable_interrupts(int_EXT); enable_interrupts(global); set_tris_b(0b00000001); portb=0; While (1) {} } III.2.2. Ng t Timer #include <16F877a.h> #fuses XT,NOWDT,NOPROTECT,NOLVP #use delay(clock=4000000) #use fast_io(b) #byte portb=0x6 #bit b0=portb.0 int16 time; #INT_TIMER1 void Ngat_timer1(); void main() { enable_interrupts(int_timer1);//Ngat Timer1 enable_interrupts(global); // Ngat toan cuc setup_timer_1(t1_INTERNAL|t1_div_by_4); // Chia tan set_timer1(55535);//Cai gia tri cho Timer1 set_tris_b(0b0); While (1) {} } #INT_TIMER1 void Ngat_timer1() { set_timer1(55535);//Cai gia tri cho Timer1 b0=!b0; }
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PH L C: CC THANH GHI CH C NNG

1. Thanh ghi TMR0: a ch 01h, 101h. Thanh ghi 8 bit cha gia tr cua bo nh thi Timer0. 2. Thanh ghi PCL: a ch 02h, 82h, 102h, 182h. Thanh ghi cha 8 bit thap cua bo em chng trnh (PC) 3. Thanh ghi STATUS: a ch 03h, 83h, 103h, 183h
IPR Bit 7
RP1
RP0
TO
PD
DC
C Bit 0
Thanh ghi tr ng thi ch a cc tr ng thi s h c c a b ALU, tr ng thi Reset v cc bit ch n Bank c a b nh d li u. Bit 7 IRP: Bit l a ch n bank thanh ghi (S d ng cho 1 = Bank 2, 3 (100h 1FFh ) 0 = Bank 0, 1 (00h FFh) Bit 6 5 RP1 RP0: Bit l a ch n bank thanh ghi (Dng trong 11 = Bank 3 ( 180h 1FFh) 10 = Bank 2 (100h 17Fh) 01 = Bank 1 (80h FFh) 00 = Bank 0 (00h 7Fh) Each bank is 128 bytes Bit 4 TO: Bit bo hi u ho t ng c a WDT. 1: L nh xa WDT ho c Sleep x y ra. 0: WDT ho t ng. Bit 3 PD: Bit bo cng su t th p ( Power down bit). 1: Sau khi ngu n tng ho c c l nh xa WDT. 0: Th c thi l nh Sleep. Bit 2 Z: bit Zero 1: Khi k t qu c a m t php ton b ng 0. 0: Khi k t qu c a m t php ton khc 0. Bit 1 DC: Digit Carry 1: C m t s nh sinh ra b i php c ng ho c php tr 4 bit th p. 0: Khng c s nh sinh ra. Bit 0 C: c nh (Carry Flag)
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nh
a ch gin ti p).
nh i ch tr c ti p).
1: C m t s nh sinh ra b i php c ng ho c php tr 4 bit cao. 0: Khng c s nh sinh ra.

4. Thanh ghi FSR: a ch 04h. Thanh ghi cha con tro a ch gian tiep cua bo nh d lieu. 5. Thanh ghi PORTA: a ch 05h. Thanh ghi cha gia tr nhan vao hay xuat ra PORTA. 6. Thanh ghi PORTB: a ch 06h, 106h. Thanh ghi cha gia tr nhan vao hay xuat ra PORTB. 7. Thanh ghi PORTC: a ch 07h. Thanh ghi cha gia tr nhan vao hay xuat ra PORTC 8. Thanh ghi PORTD: a ch 08h. Thanh ghi cha gia tr nhan vao hay xuat ra PORTD. 9. Thanh ghi PORTE: a ch 09h. Thanh ghi cha gia tr nhan vao hay xuat ra PORTE. 10. Thanh ghi PCLATCH: a ch 0Ah, 8Ah, 10Ah, 18Ah. Thanh ghi ong vai tro la buffer em trong qua trnh ghi gia tr len 5 bit cao cua bo em chng trnh PC. 11. Thanh ghi INTCON: a ch 0Bh, 8Bh, 10Bh, 18Bh.
Thanh ghi INTCON (0Bh, 8Bh,10Bh, 18Bh):thanh ghi cho php interrputon-change t i cc chn c a PORTB. GIE Bit 7 Bit 7: GIE Global Interrupt Enable bit GIE = 1 cho php t t c cc ng t. GIE = 0 khng cho php t t c cc ng t. Bit 6: PEIE Pheripheral Interrupt Enable bit PEIE = 1 cho php t t c cc ng t ngo i vi PEIE = 0 khng cho php t t c cc ng t ngo i vi Bit 5: TMR0IE Timer0 Overflow Interrupt Enable bit TMR0IE = 1 cho php ng t Timer0 TMR0IE = 0 khng cho php ng t Timer0 Bit 4: INTE RB0/INT External Interrupt Enable bit INTIE = 1 cho php ng t ngo i vi RB0/INT
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c v ghi, ch a cc bit
i u khi n v cc bit c hi u khi timer0 b trn, ng t ngo i vi RB0/INT v ng t
PEIE
TMR0IE
INTE
RBIE
TMR0IF
INTF
RBIF Bit 0
INTIE = 0 khng cho php ng t ngo i vi RB0/INT Bit3: RBIE RB Port change Interrupt Enable bit RBIE = 1 cho php ng t RB Port change RBIE = 0 khng cho php ng t RB Port change Bit 2: TMR0IF Timer0 Interrupt Flag bit TMR0IF = 1 thanh ghi TMR0 b trn (ph i xa b ng chng trnh) . TMR0IF = 0 thanh ghi TMR0 cha b trn. Bit 1: INTF BR0/INT External Interrupt Flag bit INTF = 1 ng t RB0/INT x y ra (ph i xa c hi u b ng chng trnh). INTF = 0 ng t RB0/INT cha x y ra. Bit 0: RBIF RB Port Change Interrupt Flag bit RBIF = 1 t nh t c m t chn RB7:RB4 c s thay i tr ng thi.Bit ny ph i c xa b ng chng trnh sau khi ki m tra l icc gi tr c a cc chn t i PORTB. RBIF = 0 khng c s thay i tr ng thi cc chn RB7:RB4
12. Thanh ghi PIR1: a ch 0Ch Thanh ghi cha c ngat cua cac khoi ngoai vi.
PSPIF
ADIF
RCIF
TXIF
SSPIF
CCP1IF TMR2IF TMR1IF Bit 0
Bit 7 Bit 7: PSPIF Parallel Slave Port Read/Write Interrupt Flag bit
PSPIF = 1 v a hon t t thao tc c ho c ghi PSP (ph i xa b ngchng trnh). PSPIF = 0 khng c thao tc c ghi PSP no di n ra. Bit 6: ADIF ADC Interrupt Flag bit ADIF = 1 hon t t chuy n i ADC. ADIF = 0 cha hon t t chuy n i ADC. Bit 5: RCIF USART Receive Interrupt Flag bit RCIF = 1 buffer nh n qua chu n giao ti p USART RCIF = 0 buffer nhn qua chu n giao ti p USART r ng. Bit 4: TXIF USART Transmit Interrupt Flag bit TXIF = 1 buffer truy n qua chu n giao ti p USART r ng. TXIF = 0 buffer truy n qua chu n giao ti p USART y. Bit 3: SSPIF Synchronous Serial Port (SSP) Interrupt Flag bit SSPIF = 1 ng t truy n nh n SSP x y ra. SSPIF = 0 ng t truy n nh n SSP cha x y ra. Bit 2: CCP1IF CCP1 Interrupt Flag bit Khi CCP1 ch Capture
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y.
CCP1IF=1 c p nh t gi tr trong thanh ghi TMR1. CCP1IF=0 cha c p nh t gi tr trong thanh ghi TMR1. Khi CCP1 ch Compare CCP1IF=1 gi tr c n so snh b ng v i gi tr ch a trong TMR1 CCP1IF=0 gi tr c n so snh khng b ng v i gi tr trong TMR1. Bit 1: TMR2IF TMR2 to PR2 Match Interrupt Flag bit TRM2IF = 1 gi tr ch a trong thanh ghi TMR2 b ng v i gi tr ch a trong thanh ghi PR2. TRM2IF = 0 gi tr ch a trong thanh ghi TMR2 cha b ng v i gi tr ch a trong thanh ghi PR2. Bit 0: TMR1IF TMR1 Overflow Interrupt Flag bit TMR1IF = 1 thanh ghi TMR1 b trn (ph i xa b ng chng trnh). TMR1IF = 0 thanh ghi TMR1 cha b trn
13. Thanh ghi PIR2: a ch 0Dh
Bit 7
CMIF
EEIF
BCLIF
CCP2IF Bit 0
Bit 7, 5, 2, 1: khng quan tm v m c
nh mang gi tr 0. i. i.
Bit 6: CMIF Comparator Interrupt Flag bit CMIF = 1 tn hi u ng vo b so snh thay
CMIF = 0 tn hi u ng vo b so snh khng thay Bit 4: EEIF EEPROM Write Operation Interrupt Flag bit
EEIF = 1 qu trnh ghi d li u ln EEPROM hon t t. EEIF = 0 qu trnh ghi d li u ln EEPROM cha hon t t ho c cha b t Bit 3: BCLIF Bus Collision Interrupt Flag bit u.
BCLIF = 1 Bus truy n nh n ang b n khi ( ang c d li u truy n i trong bus) khi SSP h t ng ch I2C Master mode. BCLIF = 0 Bus truy n nh n cha b trn (khng c d li u truy n itrong bus). Bit 0: CCP2IF CCP2 Interrupt Flag bit ch Capture CCP2IF = 1 c p nh t gi tr trong thanh ghi TMR1. CCP2IF = 0 cha c p nh t gi tr trong thanh ghi TMR1. ch Compare CCP2IF = 1 gi tr c n so snh b ng v i gi tr ch a trong TMR1. CCP2IF = 0 gi tr c n so snh cha b ng v i gi tr ch a trong TMR1
14. Thanh ghi TMR1L: a ch 0Eh 108
Gio trnh Vi i u Khi n Thanh ghi cha 8 bit thap cua bo nh thi TMR1. 15. Thanh ghi TMR1H: a ch 0Fh Thanh ghi cha 8 bit cao cua bo nh thi TMR2. 16. Thanh ghi T1CON: a ch 10h Thanh ghi ieu khien Timer1.
Bit7
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON

Bit 0
Bit 7,6 Khng s d ng,
c l 0.
Bit 5,4 T1CKPS1 : T1CKPS0 : Cc bit ch n t l xung ng vo cho Timer1. 11 1 : 8 gi tr t l 10 01 1 : 4 gi tr t l 1 : 2 gi tr t l ng Timer 1 Oscillator
00 1 : 1 gi tr t l Bit 3 T10SCEN : Bit cho php b dao 1 : Cho php dao ng 0 : Khng cho php dao Bit 2 T1SYNC : Bit l a ch n ng
ng b ha xung clock ngoi c a Timer 1
(Ch : Bit ny ch c tc d ng khi bit TMR1CS = 1) 1: Khng ng b ha xung clock ngo i 0: ng b ha xung clock ngo i. Bit 1 TMR1CS : Bit ch n ngu n xung clock cho Timer 1 1: Ch n xung clock ngoi qua chn T1OSC/T1CKI ( tc 0: Ch n xung clock n i (Fosc/4) Bit 0 TMR1ON: Bit cho php ngo c ngng Timer 1 1: Cho php 0: Khng cho php
17. Thanh ghi TMR2: a ch 11h Thanh ghi cha gia tr bo em Timer2. 18. Thanh ghi T2CON: a ch 12h Thanh ghi ieu khien Timer2.
Bit 7
ng c nh ln)
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1
T2CKPS0
Bit0
Bit 7: khng s d ng
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Bit 6:3 TOUTPS3:TOUTPS0: Bit ch n t l ng ra c a Timer 2 0000: 1:1 T l ng ra 0001: 1:2 T l ng ra . 1111: 1:16 T l ng ra Bit 2 TMR2ON: Bit cho php ho t 1: Cho php 0: Khng cho php. ng c a Timer 2
Bit 1:0 T2CKPS1:T2CKPS0: Bit ch n t l ng vo c a Timer 2 00 : Prescaler 1 01 : Prescaler 4 1x : Prescaler 16

19. Thanh ghi SSPBUF: a ch 13h Thanh ghi em d lieu 8 bit cho chuan giao tiep MSSP. 20. Thanh ghi SSPCON: a ch 14h Thanh ghi i u khi n chu n giao ti p MSSP.
WCOL Bit 7 Khi MSSP
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0 Bit 0
ch
SPI:
Bit 7 WCOL Write Collition Detect bit WCOL = 1 d li u m i c a vo thanh ghi SSPBUF trong khi cha truy n xong d li u tr c . WCOL = 0 khng c hi n t ng trn x y ra. Bit 6 SSPOV Receive Overflow Indicalor bit (bit ny ch c tc d ng ch SPI
Slave mode). SSPOV = 1 d li u trong bufer m (thanh ghi SSPBUF) b trn (d li u c cha c c th c d li u m i gi ln). SSPOV = 0 khng c hi n t ng trn x y ra. Bit 5 SSPEN Synchronous Serial Port Enable bit SSPEN = 1 cho php c ng giao ti p MSSP (cc pin SCK, SDO, SDI v ). SSPEN = 0 khng cho php c ng giao ti p MSSP. Bit 4 CKP Clock Polarity Select bit CKP = 1 tr ng thi ch c a xung clock l m c logic cao. CKP = 0 tr ng thi ch c a xung clock l m c logic th p. Bit 3-0 SSPM3:SSPM0 Synchronous Serial Mode Select bit
110
Cc bit ny ng vai tr l a ch n cc ch
ho t
ng c a MSSP.
0101 Slave mode, xung clock l y t pin SCK, khng cho php pin i u khi n ( l pin I/O bnh th ng). 0100 SPI Slave mode, xung clock l y t pin SCK, cho php pin i u khi n . 0011 SPI Master mode, xung clock b 0010 SPI Master mode, xung clock b 0001 SPI Master mode, xung clock b 0000 SPI Master mode, xung clock b ng (ng ra TMR2)/2. ng (FOSC/64). ng (FOSC/16). ng (FOSC/4).
Cc tr ng thi khng c li t k ho c khng c tc d ng i u khi n ho c ch c tc d ng i v i ch I2C mode. Khi MSSP ch I2C Bit 7 WCOL Write Collition Detect bit Khi truy n d li u ch I2C Master mode: WCOL = 1 a d li u truy n i vo thanh ghi SSPBUF trong khi ch truy n d li u c a I2C cha s n sng. WCOL = 0 khng x y ra hi n t ng trn. khi truy n d li u ch I2C Slave mode: WCOL = 1 d li u m i c a vo thanh ghi SSPBUF trong khi d li u c cha c truy n i. WCOL = 0 khng c hi n t ng trn x y ra. ch nh n d li u (Master ho c Slave): Bit ny khng c tc d ng ch thi cc tr ng thi. Bit 6 SSPOV Receive Overflow Indicator Flag bit. Khi nh n d li u: SSPOV = 1 d li u m i c nh n vo thanh ghi SSPBUF trong khi d li u c cha c c. SSPOV = 0 khng c hi n t ng trn x y ra. Khi truy n d li u: Bit ny khng c tc d ng ch th cc tr ng thi. Bit 5 SSPEN Synchronous Serial Port Enable bit SSPEN = 1 cho php c ng giao ti p MSSP (cc pin SDA v SCL). SSPEN = 0 khng cho php c ng giao ti p MSSP. C n ch l cc pin SDA v SCL ph i c i u khi n tr ng thi b ng cc bit tng ng trong thanh ghi TRISC tr c ). Bit 4 CKP SCK Release Control bit ch Slave mode: CKP = 1 cho xung clock tc ng. CKP = 0 gi xung clock m c logic th p (
111
b o
m th i gian thi t l p d li u).
Bit 3,0 SSPM3:SSPM0 Cc bit ny ng vai tr l a ch n cc ch 1111 I2C Slave mode 10 bit bit Stop. ho t ng c a MSSP. a ch v cho php ng t khi pht hi n bit Start v
1110 I2C Slave mode 7 bit a ch v cho php ng t khi pht hi n bit Start v bit Stop. 1011 I2C Firmwave Controlled Master mode (khng cho php ch Slave). 1000 I2C Master mode, xung clock = FOSC/(4*(SSPADD+1)). 0111 I2C Slave mode 10 bit a ch . Cc tr ng thi khng c li t k ho c khng c tc d ng i u khi n ho c ch c tc d ng i v i ch SPI mode.
21. Thanh ghi CCPR1L: a ch 15h Thanh ghi cha 8 bit thap cua khoi CCP1. 22. Thanh ghi CCPR1H: a ch 16h Thanh ghi cha 8 bit cao cua khoi CCP1. 23. Thanh ghi CCP1CON va thanh ghi CCP2CON: a ch 17h (CCP1CON) va 1Dh (CCP2CON) Thanh ghi ieu khien khoi CCP1.
CCPXX CCPXY CCPXMP3 CCPXMP2 CCPXMP1 CCPXMP0 0 nh mang gi tr 0.
Bit 7,6 Khng c tc d ng v m c
Bit 5,4 CCPxX:CCPxY: PWM least Significant bits (cc bit ny khng c tc d ng ch Capture v Compare). ch PWM, y l 2 bit MSB ch a gi tr tnh r ng xung (duty cycle) c a kh i PWM (8 bit cn l i c ch a trong thanh ghi CCPRxL). Bit 3-0 CCPxM3:CCPxM0 CCPx Mode Select bit Cc bit dng xc l p cc ch ho t ng c a kh i CCPx 0000 khng cho php CCPx (ho c dng reset CCPx) 0100 CCPx ho t ng ch Capture, "hi n t ng" c thi t l p l m i c nh xu ng t i pin dng cho kh i CCPx. 0101 CCPx ho t ng ch Capture, "hi n t ng" c thi t l p l m i c nh ln t i pin dng cho kh i CCPx. 0110 CCPx ho t ng ch Capture, "hi n t ng" c thi t l p l m i c nh ln th 4 t i pin dng cho kh i CCPx. 0111 CCPx ho t ng ch Capture, "hi n t ng" c thi t l p l m i
112
c nh ln th 16 t i pin dng cho kh i CCPx. 1000 CCPx ho t ng ch Compare, ng ra c a ln m c cao v bit CCPxIF c set khi cc gi tr c n so snh b ng nhau. 1001 CCPx ho t ng ch Compare, ng ra c xu ng m c th p v bit CCPxIF c set khi cc gi tr c n so snh b ng nhau. 1010 CCPx ho t ng ch Compare, khi cc gi tr c n so snh b ng nhau, ng t x y ra, bit CCPxIF c set v tr ng thi pin output khng b nh h ng. 1011 CCPx ho t ng ch Compare, khi cc gi tr c n so snh b ng nhau, xung trigger c bi t (Trigger Special Event) s c t o ra, khi c ng t CCPxIF c set, cc pin output khng thay Timer1, CCP2 reset Timer1 v kh i 11xx CCPx ho t ng ch PWM. i tr ng thi, CCp1 reset ng kh i ADC.
24. Thanh ghi RCSTA: a ch 18h Thanh ghi ch a cc bit tr ng thi v cc bit i u khi n qu trnh nh n d li u qua chu n giao ti p USART. SPEN Bit 7 Bit 7 SPEN Serial Port Enable bit SPEN = 1 Cho php c ng giao ti p USART (pin RC7/RX/DT v RC6/TX/CK). SPEN = 0 khng cho php c ng giao ti p USART. Bit 6 RX9 9-bit Receive Enable bit RX9 = 1 nh n 9 bit d li u. RX9 = 0 nh n 8 bit d li u. Bit 5 SREN Single Receive Enable bit ch ch USART b t ng b : bit ny khng c n quan tm. USART Master ng b : RX9 SREN CREN ADDEN FERR OERR RX9D Bit 0
SREN = 1 cho php ch c nng nh n 1 byte d li u (8 bit ho c 9 bit). SREN = 0 khng cho php ch c nng nh n 1 byte d li u. Bit 4 CREN Continous Receive Enable bit ch b t ng b : CREN = 1 cho php nh n 1 chu i d li u lin t c. CREN = 0 khng cho php nh n 1 chu i d li u lin t c. ch b t ng b : CREN = 1 cho php nh n d li u cho t i khi xa bit CREN.
113
CREN = 0 khng cho php nh n chu i d li u. Bit 3 ADDEN Address Detect Enable bit ch USART b t ng b 9 bit ADDEN = 1 cho php xc nh n a ch , khi bit RSR<8> c set th ng t c cho php th c thi v gi tr trong buffer c nh n vo. ADDEN = 0 khng cho php xc nh n iz5 ch , cc byte d li u c nh n vo v bit th 9 c th c s d ng nh l bit parity. Bit 2 FERR Framing Eror bit FERR = 1 xu t hi n l i "Framing" trong qu trnh truy n nh n d li u. FERR = 0 khng xu t hi n l i "Framing" trong qu trnh truy n nh n d li u. Bit 1 OERR Overrun Error bit, OERR = 1 xu t hi n l i "Overrun" OERR = 0 khng xu t hi n l i "Overrun" Bit 0 RX9D Bit ny ch a bit d li u th 9 c a d li u truy n nh n.
25. Thanh ghi TXREG:
a ch 19h Thanh ghi ng vai tr l buffer m 8 bit trong qu trnh truy n d li u thng qua chu n giao ti p USART. a ch 1Ah m trong qu trnh nh n d li u qua chu n giao ti p
26. Thanh ghi RCREG:
Thanh ghi ng vai tr l buffer USART.
27. Thanh ghi CCPR2L: a ch 1Bh Thanh ghi ch a 8 bit th p c a kh i CCP2. 28. Thanh ghi CCPR2H: a ch 1Ch Thanh ghi ch a 8 bit cao c a kh i CCP2. 29. Thanh ghi ADRESH: a ch 1Eh Thanh ghi ch a byte cao c a k t qu qu trnh chuy n 30. Thanh ghi ADCON0: a ch 1Fh y l m t trong hai thanh ghi i u khi n kh i chuy n thanh ghi ADCON1 ( a ch 9Fh) i ADC. i ADC. Thanh ghi cn l i l
Bit 7:6 ADCS1:ADCS0: Cc bit l a ch n t n s chuy n 00 =FOSC/2 01 =FOSC/4

114
i A/D
10 =FOSC/32 11 =FRC (xung clock c l y t dao ng n i RC) Bit 5:3 CHS2:CHS0: Cc bit l a ch n knh Analog 000: Knh 0, (AN0) 001: Knh 1, (AN1) 010: Knh 2, (AN2) 011: Knh 3, (AN3) 100: Knh 4, (AN4) 101: Knh 5, (AN5) 110: Knh 6, (AN6) 111: Knh 7, (AN7) Bit 2 GO/ DONE: Bit bo tr ng thi chuy n Khi bit ADON = 1 i A/D
1: Qu trnh A/D ang th c hi n (Khi chng ta set bit ny ln th qu trnh chuy n i s x y ra, khi qu trnh k t thc n s t ng c xa b ng ph n m m). 0: Qu trnh A/D khng x y ra ho c hon t t. Bit 1 Khng s d ng, gi tr l 0 Bit 0 ADON : Bit cho php module A/D ho t 1: Ngu n c cung c p cho A/D 0: Ngng cung c p ngu n cho A/D 31. Thanh ghi ADCON1: a ch 9Fh Thanh ghi ch a cc bit i u khi n b chuy n khi n l ADCON1 v ADCON0). ng.
i ADC (ADC c hai thanh ghi i u
Bit 7 ADFM: Bit l a ch n nh d ng k t qu A/D 1: Canh ph i, 6 bit cao nh t c a thanh ghi ADRESH c gi tr 0 0: Canh tri, 6 bit th p nh t c a thanh ghi ADRESL c gi tr 0 Bit 6 ADCS2: Bit l a ch n clock chuy n i A/D
115
Bit 5,4 khng s d ng Bit 3:0 PCFG3:PCFG0: Cc bit i u khi n c u hnh cc chn ADC
32. Thanh ghi OPTION_REG:
a ch 81h, 181h
Thanh ghi nay cho phep oc va ghi, cho phepieu khien chc nang pull-up cua cac chan trong PORTB, xac lap cac tham so ve xung tacong, canh tac ong cua ngat ngoai vi va bo em Timer0.
Thanh ghi ty ch n ch a cc bit i u khi n
c u hnh cho cc ch a nng nh:
ng t ngoi, Timer 0 ch c nng ko ln Vdd c a cc chn Port B, v th i gian ch c a WDT.
Bit 7RBPU : Bit cho php PORTB c ko ln ngu n. 1: Khng cho php PORTB ko ln ngu n.
116
0: Cho php PORTB ko ln ngu n. Bit 6 INTEDG: Bt l a ch n c nh tc 1: Ng t s 0: Ng t s c tc c tc ng ng t (INTERRUPT EDGE) ng b i c nh ln c a chn RB0/INT ng b i c nh xu ng c a chn RB0/INT
Bit 5 T0CS: Bit l a ch n ngu n xung Clock cho Timer 0 1: Xung Clock cung c p b i ngu n ngoi qua chn RA4/T0CKI 0: Xung Clock cung c p b i ngu n dao ng n i. Bit 4 T0SE: Bit l a ch n c nh no c a xung clock tc ng ln timer 0 1: C nh xu ng 0: C nh ln Bit 3 PSA: Bit quy t 1: T c 0: T c Bit 2-0 PS2:PS0: Dng nh t c m PS2:PS0 s tc ng ln Timer 0 hay WDT m PS2:PS0 s tc m PS2:PS0 s tc l a ch n t c ng ln WDT ng ln Timer 0 m c a timer hay WDT
33. Thanh ghi TRISA: a ch 85h Thanh ghi i u khi n xu t nh p c a cc pin trong PORTA. 34. Thanh ghi TRISB: a ch 86h, 186h Thanh ghi i u khi n xu t nh p c a cc pin trong PORTB. 35. Thanh ghi TRISC: a ch 87h Thanh ghi i u khi n xu t nh p c a cc pin trong PORTC. 36. Thanh ghi TRISD: a ch 88h Thanh ghi i u khi n xu t nh p c a cc pin trong PORTD. 37. Thanh ghi TRISE: a ch 89h Thanh ghi i u khi n xu t nh p c a cc pin trong PORTE, i u khi n c ng giao ti p song song PSP (Parallel Slave Port).
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IBF
OBF
IBOV
SPPMODE
0 Bit 0
Bit 7 Bit 7 BIF Input Buffer Full Status bit BIF = 1 m t Word d li u v a c nh n v ang ch CPU BIF = 0 cha c Word d li u no c nh n. c vo.
Bit 6 OBF Output Buffer Full Status bit OBF = 1 Buffer truy n d li u v n cn ch a d li u c v v n cha c OBF = 0 Buffer truy n d li u c Bit 5 IBOV Input Buffer Overflow Detect bit c.
c.
IBOV = 1 d li u c ghi ln buffer trong khi d li u c v n cha c IBOV = 0 buffer cha b trn.
c.
Bit 4 PSPMODE Parallel Slave Port Mode Select bit PSPMODE = 1 Cho php PSP, PORTD ng vai tr l c ng giao ti p song song PSP. PSPMODE = 0 Khng cho php PSP. Bit 3 Khng c n quan tm v m c nh mang gi tr 0. Bit 2 Bit2 Direction Control for pin . Bit2 = 1 Input Bit2 = 0 Output Bit 1 Bit1 Direction Control for pin Bit1 = 1 Input Bit1 = 0 Output Bit 0 Bit0 Direction Control for pin Bit0 = 1 Input Bit0 = 0 Output 38. Thanh ghi PIE1: a ch 8Ch Thanh ghi ch a cc bit cho php cc ng t ngo i vi. PSPIE Bit 7 Bit 7 PSPIE Parallel Slave Port Read/Write Interrupt Enable bit PSPIE = 1 cho php ng t PSP read/write. PSPIE = 0 khng cho php ng PSP read/write. Bit 6 ADIE ADC (A/D converter) Interrupt Enable bit ADIE = 1 cho php ng t ADC. ADIE = 0 khng cho php ng t ADC.
118
ADIE
RCIE
TXIE
SSPIE
CCPIE1 TMR2IE TMR1IE Bit 0
Bit 5 RCIE USART Receive Interrupt Enable bit RCIE = 1 cho php ng t nh n USART RCIE = 0 khng cho phpn g t nh n USART Bit 4 TXIE USART Transmit Interrupt Enable bit TXIE = 1 cho php ng t truy n USART TXIE = 0 khng cho php ng t truy n USART Bit 3 SSPIE Synchronous Serial Port Interrupt Enable bit SSPIE = 1 cho php ng t SSP SSPIE = 0 khng cho php ng t SSP Bit 2 CCP1IE CCP1 Interrupt Enable bit CCP1IE = 1 cho php ng t CCP1 CCP1IE = 0 khng cho php ng t CCP1 Bt 1 TMR2IE TMR2 to PR2 Match Interrupt Enable bit TMR2IE = 1 cho php ng t. TMR2IE = 0 khng cho php ng t. Bit 0 TMR1IE TMR1 Overflow Interrupt Enable bit TMR1IE = 1 cho php ng t. TMR1IE = 0 khng cho php ng t. 39. Thanh ghi PIE2: a ch 8Dh Thanh ghi ch a cc bit cho php cc ng t ng ai vi. Bit 7 Bit 7, 5, 2, 1 Khng c n quan tm v m c nh mang gi tr 0. CMIE EEIE BCLIE CCP2IE Bit 0
Bit 6: CMIE Comparator Interrupt Enable bit CMIE = 1 Cho php ng t c a b so snh. CMIE = 0 Khng cho php ng t. Bit 4: EEIE EEPROM Write Operation Interrupt Enable bit EEIE = 1 Cho php ng t khi ghi d li u ln b nh EEPROM. EEIE = 0 Khng cho php ng t khi ghi d li u ln b nh EEPROM. Bit 3: BCLIE Bus Collision Interrupt Enable bit BCLIE = 1 Cho php ng t. BCLIE = 0 Khng cho php ng t. Bit 0: CCP2IE CCP2 Interrupt Enable bit CCP2IE = 1 Cho php ng t. CCP2IE = 0 Khng cho php ng t
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40. Thanh ghi PCON: khi n.
a ch 8Eh reset c a vi i u
Thanh ghi i u khi n ch a cc c hi u cho bi t tr ng thi cc ch

Bit 7, 6, 5, 4, 3, 2 Khong can quan tam va mac nh mang gia tr 0.
Bit 1 Power-on Reset Status bit = 1 khng c s tc ng c a Power-on Reset. = 0 c s tc ng c a Power-on reset. Bit 0 Brown-out Reset Status bit = 1 khng c s tc ng c a Brown-out reset. = 0 c s tc ng c a Brown-out reset. 41. Thanh ghi SSPCON2: a ch 91h Thanh ghi i u khi n cc ch ho t ng c a chu n giao ti p I2C. GCEN Bit 7 Bit 7 GCEN General Call Enable bit GCEN = 1 Cho php ng t khi a ch 0000h c nh n vo thanh ghi SSPSR ( a ch c a ch General Call Address). GCEN = 0 Khng cho php ch a ch trn. Bit 6 ACKSTAT Acknowledge Status bit (bit ny ch c tc d ng khi truy n d li u ch I2C Master mode). ACKSTAT = 1 nh n c xung t I2C Slave. ACKSTAT = 0 chaq nh n c xung . Bit 5 ACKDT Acknowledge Data bit (bit ny ch c tc d ng khi nh n d li u I2C Master mode). ACKDT = 1 cha nh n c xung . ACKDT = 0 nh n c xung . Bit 4 ACKEN Acknowledge Sequence Enable bit (bit ny ch c tc d ng khi nh n d li u ch I2C Master mode) ACKEN = 1 cho php xung xu t hi n 2 pin SDA v SCL khi k t thc qu trnh nh n d li u. ACKEN = 0 khng cho php tc ng trn. ch ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN Bit 0
Bit 3 RCEN Receive Enable bit (bit ny ch c tc d ng ch I2C Master mode). RCEN = 1 Cho php nh n d li u ch I2C Master mode. RCEN = 0 Khng cho php nh n d li u. Bit 2 PEN Stop Condition Enable bit
120
PEN = 1 cho php thi t l p i u ki n Stop PEN = 0 khng cho php tc ng trn.
2 pin SDA v SCL.
Bit 1 RSEN Repeated Start Condition Enable bit RSEN = 1 cho php thi t l p i u ki n Start l p l i lin t c RSEN = 0 khng cho php tc ng trn. Bit 0 SEN Start Condition Enable/Stretch Enable bit ch Master mode: SEN = 1 cho php thi t l p i u ki n Start SEN = 0 khng cho php tc ch Slave mode: Khng cho php tc ng trn. 42. Thanh ghi PR2: a ch 92h ng trn.
2 pin SDA v SCL.
2 pin SDA v SCL.
SEN = 1 cho php kha xung clock t pin SCL c a I2C Master.
Thanh ghi dng n nh tr c gi tr m cho Timer2. Khi vi i u khi n c reset, PR2 mang gi tr FFh. Khi ta a m t gi tr vo thanh ghi PR2, Timer2 s 00h cho n khi gi tr b m c a Timer2 b ng v i gi tr c a b PR2. Nh v y m c nh Timer2 s m t 00h n FFh. 43. Thanh ghi SSPADD: a ch 93h Thanh ghi ch a a ch c a vi i u khi n khi ho t mode. Khi khng dng gi tr t o ra xung clock ng
mt
m trong thanh ghi
chu n giao ti p I2C Slave ch a
ch a a ch (I2C Master mode) SSPADD c dng ng b t i pin SCL. a ch 94h
44. Thanh ghi SSPSTAT:
Thanh ghi ch a cc bit tr ng thi c a chu n giao ti p MSSP. SMP Bit 7 Khi MSSP ho t ng ch Bit 7 SMP Sample bit SPI: CKE D/A P S R/W UA BF Bit 0
SPI Master mode: SMP = 1 d li u c l y m u (xc clock.
nh trang thi logic) t i th i i m cu i xung
SMP = 0 d li u c l y m u t i th i i m gi a xung clock. SPI Slave mode: bit ny ph i c xa v 0. Bit 6 CKE SPI Clock Select bit CKE = 1 SPI Master truy n d li u khi xung clock chuy n t tr ng thi tch c c n tr ng thi ch .
121
CKE = 0 SPI Master truy n d li u khi xung clock chuy n t tr ng thi ch tr ng thi tch c c.(tr ng thi ch Bit 5 bit. Bit ny ch c tc d ng ch c xc I2C mode. nh b i bit CKP (SSPCON<4>).
Bit 4 P Stop bit Bit ny ch s d ng khi MSSP ch I2C. Bit 3 S Start bit Bit ny ch c tc d ng khi MSSP ch I2C. Bit 2 bit information Bit ny ch c tc d ng khi MSSP Bit 1 UA Update Address bit Bit ny ch c tc d ng khi MSSP Bit 0 BF Buffer Status bit BF = 1 thanh ghi BF = 0 thanh ghi ch I2C. ch I2C.
m SSPBUF c d li u. m SSPBUF cha c d li u.
Khi ho t ng ch I2C Bit 7 SPM Slew Rate Control bit SPM = 1 dng t c SPM = 0 dng t c chu n (100 KHz v 1 MHz). cao ( 400 KHz).
Bit 6 CKE MSBus Select bit CKE = 1 cho php MSBus. CKE = 0 khng cho php MSBus. Bit 5 bit I2C Master mode: khng quan tm. = 1 byte v a truy n i ho c nh n c l d li u. = 0 byte v a truy n i ho c nh n c l a ch . Bit 4 P Stop bit P = 1 v a nh n c bit Stop. P = 0 cha nh n c bit Stop. Bit 3 S Start bit S = 1 v a nh n c bit Start. S = 0 cha nh n c bit Start. Bit 2 bit information I2C Slave mode: = 1 c d li u. = 0 ghi d li u. I2C Master mode:
122
= 1 ang truy n d li u. = 0 khng truy n d li u. Bit 1 UA Update Address Bit ny ch c tc d ng i v i ch I2C Slave mode10 bit a ch .
UA = 1 vi i u khi n c n c p nh t thm a ch t thanh ghi SSPADD. UA = 0 khng c n c p nh t thm a ch . Bit 0 BF Buffer Full Status bit BF = 1 Thanh ghi SSPBUF ang ch a d li u truy n i ho c nh n c. BF = 0 thanh ghi SSPBUF khng c d li u. 45. Thanh ghi TXSTA: a ch 98h Thanh ghi ch a cc bit tr ng thi v i u khi n vi c truy n d li u thng qua chu n giao ti p USART. CSRC Bit 7 Bit 7 CSRC Clock Source Select bit ch b t ng b : khng c n quan tm. TX-9 TXEN SYNC BRGH TRMT TX9D Bit 0
ch
ng b :
CSRC = 1 Master mode (xung clock c l y t b t o xung BRG). CSRC = 0 Slave mode (xung clock c nh n t bn ngoi). Bit 6 TX-9 9-bit Transmit Enable bit TX-9 = 1 truy n d li u 9 bit. TX-9 = 0 truy n d li u 8 bit. Bit 5 TXEN Transmit Enable bit TXEN = 1 cho php truy n. TXEN = 0 khng cho php truy n. Bit 4 SYNC USART Mode Select bit SYNC = 1 d ng ng b SYNC = 0 d ng b t ng b . Bit 3 Khng c n quan tm v m c nh mang gi tr 0. Bit 2 BRGH High Baud Rate Select bit, Bit ny ch c tc d ng BRGH = 1 t c cao. BRGL = 0 t c th p. Bit 1 TRMT Transmit Shift Register Status bit TRMT = 1 thanh ghi TSR khng c d li u. TRMT = 0 thanh ghi TSR c ch a d li u. Bit 0 TX9D
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ch
b t
ng b .
Bit ny ch a bit d li u th 9 khi d li u truy n nh n l 9 bit. 45. Thanh ghi SPBRG: a ch 99h Thanh ghi ch a gi tr t o xung clock cho b t o xung BRG (Baud Rate Generator). T n s xung clock do BRG t o ra c tnh theo cc cng th c trong b ng sau:
46.Thanh ghi CMCON: a ch 9Ch Thanh ghi i u khi n v ch th cc tr ng thi cng nh k t qu c a b so snh. C2OUT C1OUT Bit 7 Bit 7 C2OUT Comparator 2 (C2) Output bit Khi C2INV = 0 C2OUT = 1 khi (pin VIN+ c a C2)> (pin VIN- c a C2). C2OUT = 0 khi (pin VIN+ c a C2) < (pin VIN- c a C2). Khi C2INV = 1 C2OUT = 1 khi (pin VIN+ c a C2)< (pin VIN- c a C2). C2OUT = 0 khi (pin VIN+ c a C2) > (pin VIN- c a C2). Bit 6 C1OUT Comparator 1 (C1) Output bit Khi C1INV = 0 C1OUT = 1 khi (pin VIN+ c a C1)> (pin VIN- c a C1). C1OUT = 0 khi (pin VIN+ c a C1) < (pin VIN- c a C1). Khi C1INV = 1 C1OUT = 1 khi (pin VIN+ c a C1)< (pin VIN- c a C1). C1OUT = 0 khi (pin VIN+ c a C1) > (pin VIN- c a C1). Bit 5 C2INV Comparator 2 Output Conversion bit C2INV = 1 ng ra C2 c o tr ng thi. C2INV = 0 ng ra C2 khng o tr ng thi. Bit 4 C1INV Comparator 1 Output Conversion bit C1INV = 1 ng ra C1 c o tr ng thi. C1INV = 0 ng ra C1 khng o tr ng thi. Bit 3 CIS Comparator Input Switch bit Bit ny ch c tc d ng khi CM2:CM0 = 110 C2INV C1INV CIS CM2 CM1 CM0 Bit 0
124
CIS = 1 khi pin VIN- c a C1 n i v i RA3/AN3 v pin VIN- c a C2 n i v i RA2/AN2 CIS = 0 khi pin VIN- c a C1 n i v i RA0/AN0 v pin VIN- c a C2 n i v i RA1/AN1 Bit 2-0 CM2:CM0 Comparator Mode bit Cc bit ny ng vai tr trong vi c thi t l p cc c u hnh ho t Comparator. 47. Thanh ghi CVRCON: a ch 9Dh Thanh ghi i u khi n b t o i n p so snh khi b Comparator CVREN CVROE Bit 7 Bit 7 CVREN Comparator Voltage Reference Enable bit. CVREN = 1 b t o i n p so snh c c p i n p ho t ng. CVREN = 0 b t o i n p so snh khng c c p i n p ho t ng. CVRR CVR3 CVR2 CVR1 CVR0 Bit 0 ng c a b
Bit 6 CVROE Comparator VREF Output Enable bit CVROE = 1 i n p do b t o i n p so snh t o ra c a ra pin RA2. CVROA = 0 i n p do b t o i n p so snh t o ra khng c a ra ngoi. Bit 5 CVRR Comparator VREF Range Selection bit CVRR = 1 m t m c i n p c gi tr VDD/24 ( i n p do b t o i n p so snh t o ra c gi tr t 0 n 0.75VDD). CVRR = 0 m t m c i n p c gi tr VDD/32 ( i n p do b t o i n p so snh t o ra c gi tr t 0.25 n 0.75VDD). Bit 4 Khng c n quan tm v m c nh mang gi tr 0. Bit 3-0 CVR3:CVR0 Cc bit ch n i n p ng ra c a b t o i n p so snh. Khi CVRR = 1: i n p t i pin RA2 c gi tr CVREF = (CVR<3:0>/24)*VDD. Khi CVRR = 0 i n p t i pin RA2 c gi tr CVREF = (CVR<3:0>/32)*VDD + VDD. 48. Thanh ghi ADRESL: a ch 9Eh i A/D (8 bit cao ch a trong Thanh ghi ch a cc bit th p c a k t qu b chuy n thanh ghi ADRESH a ch 1Eh).
50. Thanh ghi EEDATA: a ch 10Ch Thanh ghi ch a byte th p c a d li u trong qu trnh ghi EEPROM. 51. Thanh ghi EEADR: a ch 10Dh
125
c trn b nh d li u
Thanh ghi ch a byte th p c a EEPROM.
a ch trong qu trnh ghi
c trn b nh d li u
52. Thanh ghi EEDATH: a ch 10Eh Thanh ghi ch a byte cao c a d li u trong qu trnh ghi EEPROM (thanh ghi ny ch s d ng 6 bit th p). 53. Thanh ghi EEADRH: a ch 10Fh Thanh ghi ch a byte cao c a a ch trong qu trnh ghi EEPROM (thanh ghi ny ch s d ng 4 bit th p). 54. Thanh ghi EECON1: a ch 18Ch Thanh ghi i u khi n b nh EEPROM.
EEPGD
c trn b nh d li u
c trn b nh d li u
WRERR
WREN
WR
RD Bit 0
Bit 7
Bit 7 EEPGD Program/Data EEPROM Select bit
EEPGD = 1 truy xu t b nh chng trnh. EEPGD = 0 truy xu t b nh d li u. Bit 6-4 Khng c n quan tm v m c nh mang gi tr 0. Bit 3 WRERR EEPROM Error Flag bit WRERR = 1 qu trnh ghi ln b nh b gin o n v khng th ti p t c (do cc ch Reset WDT ho c ). WRERR = 0 qu trnh ghi ln b nh hon t t. Bit 2 WREN EEPROM Write Enable bit WREN = 1 cho php ghi. WREN = 0 khng cho php ghi. Bit 1 WR Write Control bit WR = 1 ghi d li u. Bit ny ch c set b ng chng trnh v t ng xa v 0
khi qu trnh ghi d li u hon t t. WR = 0 hon t t qu trnh ghi d li u. Bit 0 RD Read Control bit RD = 1 c d li u. Bit ny ch c set b ng chng trnh v t khi qu trnh c d li u hon t t. RD = 0 qu trnh c d li u khng x y ra. 55.Thanh ghi EECON2: a ch 18Dh. y l m t trong 2 thanh ghi i u khi n b nh EEPROM. Tuy nhin y khng ph i l thanh ghi v t l thng th ng v khng cho php ngi1 s d ng truy xu t d li u trn thanh ghi.
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ng xa v 0

Giao Trinh Vi Dieu Khien Pic 16F877A

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Giao Trinh Vi Dieu Khien Pic 16F877A

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Gio trnh Vi i u Khi n

CHNG 2: T CH C B NH - CC THANH GHI CH C NNG ..... 6

CHNG 3: T P L NH - C U TRC CHNG TRNH..........................17

CHNG 4: CC KH I CH C NNG .......................................................46

CHNG 6: NG T INTERRUPT ............................................................80

* PH L C: CC THANH GHI CH C NNG ............................ 105

Gio trnh Vi i u Khi n

T NG QUAN V VI I U KHI N PIC

Gio trnh Vi i u Khi n

- C th ghi/ xo 100.000 l n v i ki u b nh chng trnh Enhanced Flash.

Gio trnh Vi i u Khi n

Gio trnh Vi i u Khi n

+ C 8 knh chuy n + C 2 b PWM

Gio trnh Vi i u Khi n

T CH C B NH - CC THANH GHI CH C NNG

Hnh 2.1: S chn v hnh d ng c a Pc 16F877A

Gio trnh Vi i u Khi n

Ch c nng cc chn : Chn 1 Tn /VPP Ch c nng

Gio trnh Vi i u Khi n

RC0/T1 OCO/T1CKI RC1/T1OSI/CCP2

Gio trnh Vi i u Khi n

VDD RB0/INT RB1 RB2 RB3 RB4 RB5 RB6/PGC RB7/PGD

Gio trnh Vi i u Khi n

Gio trnh Vi i u Khi n

Hnh 2.2: C u trc bn trong c a Pic 16F877A

Gio trnh Vi i u Khi n

Hnh 2.3: B nh chng trnh c a Pic

Gio trnh Vi i u Khi n

a ch cn l i trong bank. Cc thanh ghi SFR th ng xuyn c s d ng (v d c t t t c cc bank c a b nh d li u gip thu n ti n c th c a b nh

nh thanh ghi STATUS) s

trong qu trnh truy xu t v lm gi m b t l nh c a chng trnh. S d li u PIC16F877A nh sau:

Hnh 2.4: B nh b nh c a Pic

Gio trnh Vi i u Khi n

2.5 CC THANH GHI C BI T - THANH GHI FSR V INDF

thanh ghi FSR n, thanh ghi INDF ch a n i dung c a ch

Thanh ghi FSR ch a a ch con tr ch n m trong thanh ghi FSR.

Gio trnh Vi i u Khi n

Bit 4 TO: Bit bo hi u ho t

Gio trnh Vi i u Khi n

Gio trnh Vi i u Khi n

T P L NH - C U TRC CHNG TRNH

u tin a gi tr c n gin cho thanh ghi W,

di chuy n gi tr trong thanh ghi W sang thanh ghi

Gio trnh Vi i u Khi n

Gio trnh Vi i u Khi n

c ch a trong thanh ghi

[0,1]) c a vo thanh ghi W n u

COUNT =10 COUNT =11

[0,1]). c a vo thanh ghi

COUNT =10 COUNT =9

Gio trnh Vi i u Khi n

Bit tr ng thi: khng c. V d : BCF PORTB,2; RB2 =0

Gio trnh Vi i u Khi n

Gio trnh Vi i u Khi n

Gio trnh Vi i u Khi n

nh ngha b i tham s k v 2 bit PCLATH <4:3>.

a ch quay tr v t chng trnh con m g m 11 bit c a

Gio trnh Vi i u Khi n

nh ngh a cc bi n (thanh ghi W, thanh ghi F,..) v cc

c bi t trong b nh d li u. N u khng c header file, chng trnh s

a ch ch a chng trnh trong b nh chng trnh c a vi

Gio trnh Vi i u Khi n

Gio trnh Vi i u Khi n

DEM LOOP t gi tr t i a l 765 s. V y tng th i