1 Cho, Sang-Young: Sycho@hufs - Ac.kr

S3C2440
S3C2440
2007. 3. 1 Cho, Sang-Young

sycho@hufs.ac.kr
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Contents
S3C2440 Features Memory Controller Clock & Power Management IO Port Watch Dog Timer UART PWM Timer Interrupt Controller LCD Controller ADC & Touch Screen Interface RTC
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S3C2440 Applications
Smartphones Cellular Printer
S3C2440 RISC Microprocessor Palm PC GPS
Digital STB and NCs PDA / Organizers e-Book
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S3C2440 Block Diagram
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S3C2440 Features
Integrated System for hand-held devices and general embedded applications
ARM920T + IP (Intellectual Property)
IPs
Memory Controller 8 banks each of which 128Mbyte 1Gbyte
6 memory banks for ROM, SRAM 2 memory banks for ROM, SRAM, SDRAM
Complete Programmable size and access cycles External wait signals NAND Flash Boot Loader Supports booting from NAND Flash memory 4KB internal buffer for booting Supports storage memory for NAND Flash memory after booting Caches 64-way 16KB instruction and 16KB data cache 8-word line, WT/WB
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S3C2440 Features
IPs
Clock & Power Manager MPLL generates the clock at maximum 533Mhz @ 1.35V Clock can be fed selectively to each block by software Power mode
Normal mode Slow mode: low frequency mode without PLL Idle mode: stop the clock to only CPU Sleep mode: disconnect internal power except wake-up logic
Wake up by EINT[15:0] or RTC alarm interrupt Interrupt Controller 60 Interrupt source

WDT, 5 timers, 9 UARTs, 24 External interrupt, 4 DMA, 2 RTC, 2 ADC, 1 IIC, 2 SPI, 1 SDI, 2 USB, 1 LCD, 1 Battery Fault, 1NAND and 2 Camera, 1 AC97
Timer with PWM (Pulse Width Modulation) 4-ch 16-bit Timer with PWM, 1-ch 16-bit internal Timer
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S3C2440 Features
IPs
RTC (Real Time Clock) Full clock feature, 32.768 KHz operation Alarm interrupt and Time tick interrupt General Purpose Input/Output Ports 24 external interrupt ports 130 multiplexed input/output ports UART 3-channel UART with DMA-based/interrupt-based operation Supports IrDA 1.0 64B Tx FIFO, 64B Rx FIFO DMA Controller 4-ch DMAC with burst transfer mode A/D Converter 8-ch multiplexed ADC Max. 500KSPS and 10-bit resolution, Internal FET
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S3C2440 Features
IPs
LCD Controller STN LCD support TFT LCD support
1, 2, 4, 8 bpp palette color displays 16, 24 bpp non-palette true-color displays 640x480, 320x240, 160x160, etc. Maximum 4MB frame buffer
AC97 Audio-CODEC Interface Support 16-bit samples 1-ch stereo PCM inputs/ 1-ch stereo PCM outputs 1-ch MIC input Camera Interface ITU-R BT 601/656 8-bit mode support DZI (Digital Zoom In) capability Max 4096x4096 pixels input Image mirror or rotation Output (RGB 16/24 bit or YCbCr 4:2:0/4:2:2 format)
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S3C2440 Features
IPs
Watchdog Timer 16-bit with interrupt request or system reset at time-out IIC-BUS interface 1-ch multi-master IIC-Bus IIS-BUS interface 1-ch IIS-bus for audio interface with DMA-based operation USB 1.1 2-port host, 1-port device SD Host interface Support SD/MMC Controller reset register DMA burst4 access support SD Memory Card Protocol version 1.0 compatible SDIO Card Protocol version 1.0 compatible Multimedia Card Protocol version 2.11 compatible SPI interface 2-ch Serial Peripheral Interface Protocol version 2.11 compatible
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S3C2440 Features
Operating Voltage Range
Core 1.20V for 300MHz 1.30V for 400MHz 1.35V for 533MHz Memory: 1.8V/ 2.5V/3.0V/3.3V I/O : 3.3V
Operating Frequency
Fclk Up to 533MHz Hclk Up to 136MHz Pclk Up to 68MHz
Package
289-FBGA
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Memory Controller
OM[1:0]=01,10 0x4000_0000 0x3800_0000 0x3000_0000 0x2800_0000 0x2000_0000 0x1800_0000 0x1000_0000 0x0800_0000 0x0000_0000
Boot Internal SRAM(4KB)
SROM/SDRAM (nGCS7) SROM/SDRAM (nGCS6) SROM (nGCS5) SROM (nGCS4) SROM (nGCS3) SROM (nGCS2) SROM (nGCS1) SROM (nGCS0)
Not using NAND flash for boot ROM
OM[1:0]=00 SROM/SDRAM (nGCS7) SROM/SDRAM (nGCS6) SROM (nGCS5) SROM (nGCS4) SROM (nGCS3) SROM (nGCS2) SROM (nGCS1)
Boot Internal SRAM(4KB)
2/4/8/16/32/64/128MB 2/4/8/16/32/64/128MB 128MB 128MB 128MB 128MB 128MB 128MB 1GB HADDR[29:0]
Using NAND flash for boot ROM
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Memory Controller
Bank6 and Bank7 must have the same memory size
2MB: 0x3000_0000 ~ 0x301F_FFFF, 0x3020_0000 ~ 0x303F_FFFF 4MB: 0x3000_0000 ~ 0x303F_FFFF, 0x3040_0000 ~ 0x307F_FFFF 8MB: 0x3000_0000 ~ 0x307F_FFFF, 0x3080_0000 ~ 0x30FF_FFFF 16MB: 0x3000_0000 ~ 0x30FF_FFFF, 0x3100_0000 ~ 0x31FF_FFFF 32MB: 0x3000_0000 ~ 0x31FF_FFFF, 0x3200_0000 ~ 0x33FF_FFFF 64MB: 0x3000_0000 ~ 0x33FF_FFFF, 0x3400_0000 ~ 0x37FF_FFFF 128MB: 0x3000_0000 ~ 0x37FF_FFFF, 0x3800_0000 ~ 0x3FFF_FFFF
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Memory Controller Example

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Byte with Byte Word with Byte
Halfword with Byte
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Memory Controller Example

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Halfword with Halfword Word with Halfword
Halfword with Halfword
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Memory Control Registers

BWSCON: Bus Width & Wait Control Register (0x0000_0000)
31 28 27 24 23 21 20 19 16 15 12 11 8 7 6 5 4 3 0
Bank7
Bank6
Bank5
Bank4
Bank3
Bank2
Bank1
0 Bank0 0 DW0
ST4 WS4 SRAM using UB LB 0: not use -> nWBE[3:0] 1: use -> nBE[3:0] nBE[3:0] = nWBE[3:0] & nOE
DW4 Bus width 00: 8-bit 01: 16-bit 10: 32-bit
Wait states 0: disable 1: enable
Bus width 00: NAND Flash Mode 01: 16-bit 10: 32-bit by OM[1:0] pins
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BANKCON0~5: Bank Control Register (0x0700)
14 13 12 11 10 8 7 6 5 4 3 2 1 0
Tacs
Tcos
Tacc
Toch
Tcah
Tacp
PMC
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BANKCON6~7: Bank Control Register (0x1_8008)
16 15 14 0
MT Memory Type 00: ROM or SRAM 01: Reserved 10: Reserved 11: SDRAM
Bank Control
Same to the BANKCON0~5

3 2 1 0
Trcd
SCAN Column address number 00: 8-bit, 01: 9-bit 10: 10-bit, 11: 11-bit
RAS to CAS delay 00: 2 clocks, 01: 3 clocks 10: 4 clocks, 11: 5 clocks
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REFRESH: Refresh Control Register (0xAC_0000)
23 22 21 20 19 18 17 16 11 10 0
E M Trp Tsrc Refresh enable 0: disable, 1: enable Refresh mode 0: CBR/auto, 1: self SDRAM RAS pre-charge time 00: 2 clocks, 01: 3 clocks, 10: 4 clocks, 11: Not support
Reserved
Refresh Count Refresh count value = 211 + 1 - Ref_period*HCLK
SDRAM semi row cycle time 00: 4 clocks, 01: 5 clocks 10: 6 clocks, 11: 7 clocks
BANKSIZE: Bank Size Register (0x0)

7 5 4 3 2 0
Burst
SKE SCE
BK76MAP BANK6/7 memory map 010: 128M/128M, 001: 64M/64M, 000: 32M/32M, 111: 16M/16M, 110: 8M/8M, 101: 4M/4M, 100: 2M/2M
SCLKE_EN 0: power down mode disable 1: power down mode enable SCLK_EN 0: SCLK always active 1: SCLK active only during access
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MRSR: SDRAM Mode Register Set Register (xxx)
11 10 9 8 7 6 4 3 2 0
Res. WL Write burst length 0: burst(Fixed), 1: reserved
TM
CL
BT
BL Burst length 000: 1(Fixed) Others: reserved
Test mode 00: mode register set(Fixed) Others: reserved
Burst type 0: sequential(Fixed) 1: reserved CAS latency 000: 1 clock 010: 2 clocks 011: 3 clocks Others: reserved
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Clock & Power Management(2440)

16.9344MHz
20
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Clock When Power-On Reset
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Clock Change When Normal Mode
22
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Clock & Power Special Registers

LOCKTIME: Lock Time Count Register (0xFFFF_FFFF)
31 16 15 0
U_LTIME UPLL lock time count value For UCLK (t_lock > 300uS) * t_lock = LTIME/Fin
M_LTIME MPLL lock time count value For FCLK, HCLK, PCLK (t_lock > 300uS)
PLLCON: MPLL/UPLL Control Register (0x0009_6030/0x0004_d030)

19 12 11 10 9 4 3 2 1 0
MDIV Main divider control
PDIV
SDIV Post divider control
Pre-divider control Mpll = (2*m*Fin) / (p * 2s)=(2*Fvco) / (2s) Upll = (m*Fin) / (p*2s) m = MDIV+8, p = PDIV+2, s = SDIV 1<=MDIV<=248, 1<=PDIV<=62 600MHz <= Fvco <= 1.2GHz 200MHz <= Fout <= 600MHz
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CLKCON: Clock generator control Register (0xFFFFF0)
20 4 3 2 1 0
DEVCON SLEEP Enters SLEEP mode when 1 IDLE_BIT Enters IDLE mode when 1
AC97, Camera, SPI, IIS, IIC, ADC, RTC, GPIO, UART2, UART1, UART0, SDI, PWMTIMER, USBD, USBH, LCDC, NAND Flash 0: disable, 1: enable
CLKSLOW: Clock Slow Control Register (0x0000_0004)

7 6 5 4 3 2 0
UF UCLK OFF 0: UCLK ON 1: UCLK OFF MPLL OFF 0: MPLL ON 1: MPLL OFF
MF
SB
SLOW_VAL Divider value when SB is on
SLOW_BIT 0: FCLK = Mpll 1: FCLK = input clock/(2*SLOW_VAL), when SLOW_VAL > 0 FCLK = input clock, when SLOW_VAL = 0
24
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Power Management State
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CLKDIVN: Clock divider control Register (0x0000_0000)
3 2 1 0
DIVN_UPLL
HDIV
PDIV PCLK Divider 0: PCLK = HCLK 1: PCLK = HCLK/2
DIVN_UPLL 0 : UCLK = UPLL clock 1 : UCLK = UPLL clock / 2 Set to 0, when UPLL clock is set as 48Mhz. Set to 1, when UPLL clock is set as 96Mhz.
HCLK Divider 00 : HCLK = FCLK/1. 01 : HCLK = FCLK/2. 10 : HCLK = FCLK/4 when CAMDIVN[9] = 0. HCLK= FCLK/8 when CAMDIVN[9] = 1. 11 : HCLK = FCLK/3 when CAMDIVN[8] = 0. HCLK = FCLK/6 when CAMDIVN[8] = 1.
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CAMDIVN: Camera Clock divider control Register (0x0000_0000)
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CLKDIVN & CAMDIVN
HDIVN 0 0 1 1 3 3 3 3 2 2 2 2
PDIVN 0 1 0 1 0 1 0 1 0 1 0 1
HCLK3_HALF/ HCLK4_HALF 0/0 0/0 1/0 1/0 0/0 0/0 0/1 0/1
FCLK FCLK FCLK FCLK FCLK FCLK FCLK FCLK FCLK FCLK FCLK FCLK FCLK
HCLK FCLK FCLK FCLK/2 FCLK/2 FCLK/3 FCLK/3 FCLK/6 FCLK/6 FCLK/4 FCLK/4 FCLK/8 FCLK/8
PCLK FCLK FCLK/2 FCLK/2 FCLK/4 FCLK/3 FCLK/6 FCLK/6 FCLK/12 FCLK/4 FCLK/8 FCLK/8 FCLK/16
Divide Ratio 1:1:1 1:1:2 1:2:2 1:2:4 1:3:3 1:3:6 1:6:6 1 : 6 : 12 1:4:4 1:4:8 1:8:8 1 : 8 : 16
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I/O Ports
Features
130 multi-functional input/output pins Port A (GPA): 25-output ports/Memory signals Port B (GPB): 11-input/output ports/DMA, Timer signals Port C (GPC), Port D (GPD): 16-input/output ports/ LCD Controller Port E (GPE): 16-input/output ports/IIC, IIS, SPI, SD interface Port F (GPF): 8-input/output ports/External Int Port G (GPG): 16-input/output ports/External Int, SPI Port H (GPH): 9-input/output port/UART Port J (GPJ): 13-input/output port/Camera interface If the multiplexed functions on a pin are not used
Registers
Port Configuration Register (GPACON ~ GPJCON) Port Data Register (GPADAT ~GPJDAT) Port Pull-Up Register (GPBUP ~ GPJUP) External Interrupt Control Register
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I/O Ports Registers

GPCCON: Port C Control Register (0x00000000)
31 30 29 28 4 3 2 1 0
PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 Funciton 00: Input, 01: Output, 10: LCD_LPCREVB 11: Reserved
GPCDAT: Port C Data Register

15 0
PC[15:0]
GPCUP: Port C Pull-Up Register

15 0
Each bit 0: pull-up function attached 1: pull-up function disabled
30
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I/O Ports Registers

EXTINT: External Interrupt Control Register (0x00000000)
31 30 28 271 26 24 23 22 20 19 18 16 15 14 12 11 10 8 7 6 4 3 2 0
0 EINT7 0 EINT6 0 EINT5 0 EINT4 0 EINT3 0 EINT2 0 EINT1 0 EINT0 Setting the signaling method of the EINT4 000: Low level, 001: High level 01X: Falling edge triggered 10X: Rising edge triggered 11X: Both edge triggered
31 30 28 27 26 24 23 22 20 19 18 16 15 14 12 11 10 8 7 6 4 3 2 0
FLTEN15EINT15 FLTEN14EINT14 FLTEN13EINT13 FLTEN12EINT12 FLTEN11 EINT11 FLTEN10 EINT10 FLTEN9 EINT9 FLTEN8 EINT8
31
30
28
27
26 24
23
22 20
19
18 16
15
14 12
11
10
FLTEN23 EINT23 FLTEN22EINT22 FLTEN21EINT21 FLTEN20EINT20 FLTEN19 EINT19 FLTEN18 EINT18FLTEN17 EINT17FLTEN16 EINT16
FLTENn : Filter Enable for EINTn 0 = Filter Disable 1 = Fileter Enable
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I/O Ports Registers

EINTMSK: External Interrupt Mask Register (0x000FFFFF)
31 24 23 4 3 0
0 Each bit 0: enable interrupt, 1: interrupt service is masked
EINTPND: External Interrupt Pending Register (0x00000000)

31 24 23 4 3 0
0 Each bit It is cleard by writing 1 0 = not occur, 1 = occur interrupt
32
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I/O Ports Example

GPF[4] GPF[5] GPF[6] GPF[7] GPF[0]
GPF[2]
rGPFCON = 0b0101010110101010; rGPFUP = 0xFF; rGPFDAT = 0x0F;
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Watchdog Timer
To resume the controller operation when it had been disturbed by malfunctions such as noise and system errors.
generates the reset signal for 128 MCLK cycles when timeout.
Can be used as a normal 16-bit interval timer to request interrupt Timer Period Calculation
Timer Clock [Hz] = PCLK/(Prescaler+1)/(Divider value) Min: 50M/256/128 = 1.526KHz (655.36uS) Max: 50M/1/16 = 3.125MHz (0.32uS) Timer Duration[sec] = (WTCNT+1) X Timer Clock Period Max: 65536X655.36uS = 42.95 sec
WTDAT 1/16 PCLK 8-bit Prescaler WTCON[15:8] 1/32 Clock divider 1/64 1/128 MUX WTCNT (down Counter) Timer Clock WTCON[4:3]
Interrupt Reset Signal Generator RESET
WTCON[0] WTCON[2]
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Watchdog Timer Control Registers

WTCON: Watchdog Timer Configuration Register0 (0x8021)
15 8 7 6 5 4 3 2 1 0
Prescaler
0 0
0 Reset signal enable 0: disable, 1: enable Interrupt enable 0: disable, 1: enable
Watchdog timer enable 0: disable, 1: enable Clock select 00: 1/16, 01: 1/32 10: 1/64, 11: 1/128
WTDAT: Watchdog Timer Data Register (0x8000)

15 0
Count reload value
WTCNT: Watchdog Timer Count Register (0x8000)

15 0
Count value At initialization, must be set to an initial value before enabling
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UART
Universal Asynchronous Receiver and Transmitter
3 independent serial IO ports with interrupt-based or DMA-based Support bit rates of up to 115.2K bps, but more with external clock Two 64 bytes FIFOs for receive and transmit Programmable baud-rates, infra-red(IR) Tx/Rx support
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UART Operations
Data transmission
Start bit, 5~8 data bits, optional parity bit, 1 ~ 2 stop bits Break condition: 0 state for 1 frame transmission time
Data reception
Start bit, 5~8 data bits, optional parity bit, 1 ~ 2 stop bits Set error flags Overrun error: when received data has overwritten Parity error: unexpected parity condition Frame error: No valid stop bit Break condition Receive time-out condition
Does not receive data during the 3 word time and Rx FIFO is not empty in FIFO mode
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UART Operations
Auto Flow Control
With nRTS and nCTS
Transmission in UART A UART A TxD nCTS UART B RxD nRTS Receive in UART A UART A RxD nRTS UART B TxD nCTS
No Auto Flow Control

Controlling nRTS and nCTS by software Rx operation with FIFO Select receive mode Check Rx FIFO count. If the value < 32, activate nRTS Tx operation with FIFO Select transmit mode Check if nCTS is actvated, then write data to Tx FIFO register
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UART Operations
Interrupt Request Generation
Type Rx interrupt FIFO mode Non-FIFO mode 1. RFIFO reaches trigger level receive data becomes full 2. RFIFO does not reaches trigger level and no data during 3 word time TFIFO reaches trigger level Transmit data becomes empty All errors
Tx interrupt
Frame error, Parity error, break Error interrupt signal Overrun when RFIFO is full
Baud-Rate Generation
Baud rate divisor UBRDIV = (round-off)(UART clock/(bps*16))-1 UART clock : PCLK, FCLK/n or UEXTCLK PCLK: UART reference clock Baud rate: 110, 1200, 2400, 9600, 14400, 19200, 38400, 57600, 76800, 115200 Ex) baud-rate: 115200 bps, PCLK = 40MHz UBRDIVn = (int)(40000000/(115200x16) + 0.5)-1 =(int)(22.2)-1=21
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UART Registers
ULCON: UART Line Control Register (0x00)
7 6 5 3 2 1 0
Parity Mode
Word Len Data bit size 00: 5, 01: 6, 10: 7, 11: 8 Stop bit size 0: 1, 1: 2
Infra-Red Mode 0: Normal mode, 1: IR mode Parity Mode 0xx: No parity, 100: Odd, 101: Even, 110: parity forced as 1 111: parity forced as 0
40
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UART Registers
UCON: UART Control Register (0x00)
15 12 11 10 9 8 7 6 5 3 2 1 0
FCLK divider
CS
TIT
RIT RTO REI
LB
SB
T Mode
R Mode
Send break Loop back mode Rx error state interrupt Rx time out enable Rx interrupt type 0: pulse, 1: level Tx interrupt type 0: pulse, 1: level Clock Selection 00,10: PCLK, 01: UEXTCLK, 11: FCLK/n Divider value when the Uart clock source is Selected as FCLK/n. UCON0/1[15:12], UCON2[14:12]. UCON2[15] is FCLK/n CLOCK Enable/Disable bit. For tramsmit/receive buffer register n = 7 ~ 21, use UCON0[15:12] 00: diable, n = 22 ~ 36, use UCON1[15:12] 01: interrupt request or polling n = 37 ~ 43, use UCON2[14:12] 10: DMA0 request for UART0 DMA3 request for UART2 11: DMA1 request for UART1
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UART Registers
UFCON: UART FIFO Control Register (0x00)
7 6 5 4 3 2 1 0
TFTL
RFTL
TFR RFR FE FIFO Enable RFIFO Reset TFIFO Reset
TFIFO Trigger Level 00: empty, 01:16B, RFIFO Trigger Level 10: 32B, 11: 48B 00:1B, 01: 8B, 10: 16B, 11: 32B
UMCON: UART Modem Control Register (0x00)

7 6 5 3 1 0
AFC
RTS Request to Send 0: inactivate nRTS 1: activate nRTS When AFC is disabled
Auto Flow Control 0: disable 1: enable
UBRDIV: UART Baud Rate division Register (0x0000)

15 0
>0
42
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UART Registers
UTRSTAT: UART Tx/Rx Status Register (0x6)
2 1 0
TE TBE RBR Receive buffer data ready for Non-FIFO Transmit buffer empty for Non-FIFO Transmitter empty 1: Transmit buffer & shifter register empty
UERSTAT: UART Error Status Register (0x00)

3 2 1 0
BD
FE
PE
OE Overrun error Parity error
Frame error Break Detect
UMSTAT: UART Modem Status Register (0x00)

4 3 2 1 0
DCTS 0
CTS Clear To Send 0: CTS is not activated, 1: activated
Delta CTS 0: nCTS has not changed state since it was read 1: changed
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UART Registers
UFSTAT: UART FIFO Status Register (0x00)
15 14 13 8 7 6 5 0
TFF
Tx FIFO Count
RFF
Rx FIFO Count
Number of data in Rx FIFO Rx FIFO Full 0: not full, 1: full Number of data in Tx FIFO Tx FIFO Full 0: not full, 1: full
UTXH: UART Transmit Buffer Register (0x00) URXH: UART Receive Buffer Register (0x00)
7 0
44
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Timer
Features
5 16-bit timers 4 timers with PWM (Pulse Width Modulation) + 1 internal timer
Timer Period Calculation

Timer Clock [Hz] = PCLK/(Prescaler+1)/Division Factor Min: 50M/256/16 = 12.207KHz (81.92 uS) Max: 50M/1/2 = 25MHz (0.04uS) Timer Duration[sec] = (TCNT+1) X Timer Clock Period Max: 65536X81.92uS = 5.37 sec Low Duration = (TCNT+1 TCMP) X Timer Clock Period
TCMPB TCNTB 1/2 PCLK MUX 8-bit Prescaler 1/4 Clock divider1/8 1/16 TCLK
TCMP Timer Clock
TCNT
MUX
TOUT
Control Logic
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Timer Operations
Basic Timer Operation
Start bit=1 Timer is started TCNTn=TCMPn Auto-reload TCNTn=TCMPn Timer is stopped
TCMPn TCNTn 3 3 2
1 1 0 2 1
0 0 0
TCNTBn=3 TCMPBn=1 Manual update=1 Auto-reload=1
TCNTBn=2 TCMPBn=0 Manual update=0 Auto-reload=1
Auto-reload=0 Interrupt request Interrupt request
TOUTn
Auto-reload & Double Buffering
46
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Timer Operations
PWM
TCNTB = 99, TCMPB = 9 TCMPB 10
Start TCMPB = 19 TCMPB = 29 TCMPB = 39 TCMPB = 49 TCMPB = 59 TCMPB = 69 TCMPB = 79 TCMPB = 89 TCMPB = 99
TOUT 100 100 100 100 100 100 100 100 100
T0 Dead Zone
TOUT nTOUT PWM Dead zone dead zone
TOUT nTOUT * High
TOUT
Dead Zone
nTOUT
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Timer Control Registers

TCFG0: Timer Configuration Register0 (0x00000000)
31 24 23 16 15 8 7 0
Reserved
Dead zone length
Prescaler for T2, 3, 4
Prescaler for T0,1
TCFG1: Timer Configuration Register1 (0x00000000)

31 24 23 20 19 16 15 12 11 8 7 4 3 0
Reserved
DMA mode
MUX4
MUX3
MUX2
MUX1
MUX0
Select DMA request channel 0000: No, 0001: T0, 0010: T1 0011: T2, 0100: T3, 0101:T4 0110: Reserved
Select MUX input for Timer 3 0000: 1/2, 0001: 1/4, 0010: 1/8 0011: 1/16, 01XX: External TCLK1
48
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Timer Control Registers

TCON: Timer Control Register (0x00000000)
22 20 19 16 15 12 11 8 7 5 4 3 0
Timer4
Timer3 R
Timer2 I M
Timer1 S
0 0 0 D
Timer0
Dead zone enable Start/Stop 0: Stop, 1: Start Manual update 0: No operation, 1: Udate TCNT, TCMP Inverter 0: Off, 1: On Reload 0: Off, 1: On
TCNTB: Timer Count Buffer Register (0x0000) TCMPB: Timer Compare Buffer Register (0x0000) TCNTO: Timer Count Observation Register (0x0000)
15 0
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Interrupt Controller
Features
FIQ or IRQ to ARM920T after arbitration 60 interrupt source (24 external, 36 internal) Fixed or Rotate Priority
F-bit and I-bit of PSR

To enable interrupt reception F = I = 0 and corresponding bit of INTMSK = 0
INTPND Request Source SRCPND MASK OFFSET PRIORITY Request Source
SUBSRCPND SUBMASK
nIRQ
MODE nFIQ
50
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Interrupt Controller Registers

SRCPND: Source Pending Register (0x00000000)
31 6 5 0
Internal Each bit 1: if source generates interrupt Should be cleared by writing a data of specific bit=1
External
INTMOD: Interrupt Mode Register (0x00000000)

31 6 5 0
Internal Each bit 0: IRQ, 1: FIQ only one bit is set at most
External
INTMSK: Interrupt Mask Register (0xFFFFFFFF)

31 6 5 0
Internal Each bit 0: interrupt available, 1: interrupt service is masked
External
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SUBSRCPND: Sub Source Pending Register (0x00000000)
31 12 11 10 9 8 6 5 3 2 0
Not Used Each bit 1: if source generates interrupt Should be cleared by writing a data of INT_AC97 specific bit=1 INT_WDT INT_CAM_P INT_CPM_C Each bit 0: IRQ, 1: FIQ only one bit is set at most
UART2 UART1 UART0 UART2 [6]: INT_RXD2 [7]: INT_TXD2 [8]: INT_ERR2 INT_TC INT_ADC
INTSUBMSK: Interrupt Sub Mask Register (0x0000FFFF)

31 14 13 12 11 10 9 8 6 5 3 2 0
Not Used Each bit 0: interrupt available, 1: interrupt service is masked INT_AC97 INT_WDT INT_CAM_P INT_CPM_C
UART2 UART1 UART0 UART2 [6]: INT_RXD2 [7]: INT_TXD2 [8]: INT_ERR2 INT_TC INT_ADC
52
26
S3C2440 S3C2440

PRIORITY: Priority Register (0x0007F)
20 19 8 7 6 0
S6 Arbiter6 priority order set 00: 1-2-3-4 01: 2-3-4-1 10: 3-4-1-2 11: 4-1-2-3 0, 5 is fixed (0:highest, 5:lowest)
S0 M6
M0 Arbiter6 priority rotate enable
53
S3C2440 S3C2440

INTPND: Interrupt Pending Register (0x00000000)
31 6 5 0
Internal Each bit 1: source is asserted as IRQ Only one bit is set Should be cleared by writing a data
External
INTOFEST: Interrupt Offset Register (0x00000000)

31 6 5 0
The value indicates interrupt source number
54
27
S3C2440 S3C2440
LCD Controller
LCD LCD
LCD LCD LCD pixel
Main Memory Image Write Processor Image Buffer Image Read LCD Controller Image Draw LCD Panel Initialize
55
S3C2440 S3C2440
LCD Controller
For STN LCD displays
4-bit dual scan, 4-bit single scan, 8-bit single scan monochrome, 4 gray level, 16 gray level 256 color, 4096 colors for color STN LCD panel multiple screen size physical size: 640x480, 320x240, 160x160, etc virtual size
For TFT LCD displays

1, 2, 4, 8-bpp palettized color displays 16, 24-bpp non-palettized true color displays multiple screen size physical size: 640x480, 320x240, 160x160, etc virtual size: 4Mbytes in 64K color mode: 2048x1024 and others
For common
Dedicated interrupt functions (INT_FrSyn and INT_FiCnt) little/big-endian byte ordering, as well as WinCE data formats
Supports LTS350Q1-PD(E)1/2 TFT LCD panel with touch panel and front light
56
28
S3C2440 S3C2440
LCD Controller
Virtual Screen
LCDBASEU and LCDBASEL in LCDSADDR1/2 register and OFFSIZE and PAGEWIDTH
OFFSIZE PAGEWIDTH OFFSIZE
LINEVAL+1
LCDBASEU Before Scrolling
View Port (LCD panel size)
LCDBASEL
After Scrolling
S3C2440 S3C2440
LCD Controller
REGBANK
17 programmable registers set 256x16 palette memory
System Bus REGBANK TIMEGEN LPC3600 LCC3600 LCDCDMA VIDRPCS VD[23:0]
VIDEO
LCDCDMA
transfer the video data in frame memory to LCD driver can be displayed on the screen without CPU intervention FIFOL(12W) + FIFOH(16W)
MUX
VSYNC HSYNC VCLK VDEN LEND
VIDPRCS
Receives the video data from LCDCDMA Send the video data through the VD[23:0] data port to the LCD driver after changing data format
LPC3600 : LTS350Q1-PD1 or PD2 LCC3600 : LTS350Q1-PE1 or PD2
TIMEGEN
Timing and rates Generates VFRAME, VLINE, VCLK, VM(STN) / VSYNC, HSYNC, VCLK, VDEN(TFT)
58
29
S3C2440 S3C2440
EXTERNAL INTERFACE SIGNAL(1)

STV/VSYNC
Vertical Start Pulse (SEC) Vertical synchronous signal (TFT)
CPV / HSYNC
Vertical Shift Clock (SEC) Horizontal synchronous signal (TFT)
LCD_HCLK / VCLK
Horizontal Sampling Clock (SEC) Pixel clock signal (TFT)
VD[23:0]
LCD pixel data output ports
TP / VDEN
Source Driver Data Load Pulse (SEC) Data enable signal (TFT)
STH / LEND
Horizontal Start Pulse (SEC) Line end signal (TFT)
LCD_PWREN
LCD panel power enable control signal
OE: Gate On Enable, REV: Inversion Signal, REVB: Inversion Signal

59
S3C2440 S3C2440

INT_FrSyn VSYNC HSYNC VDEN
VBPD+1 VSPW+1 1 Frame 1 Line LINEVAL+1 VFPD+1
HSYNC VCLK VD VDEN LEND

HBPD+1 HSPW+1
HOZVAL+1
HFPD+1
60
30
S3C2440 S3C2440

These control signal are highly related with the configuration on the LCD control registers in REGBANK
VSYNC and HSYNC : HOZVAL and LINEVAL field in the LCDCON3/2 registers HOZVAL = (Horizontal display size) 1 LINEVAL = (Vertical display size) - 1 VCLK : CLKVAL field in the LCDCON1 register VCLK=HCLK/[(CLKVAL+1)*2] Frame rate = VSYNC signal frequency Frame Rate = 1/[{(VSPW+1)+(VBPD+1)+(LINEVAL+1)+(VFPD+1)} x {(HSPW+1)+(HBPD+1)+(HOZVAL+1)+(HFPD+1)} x {2x(CLKVAL+1)/(HCLK)}]
HCLK=60MHz
CLKVAL 1 2 ... 1023

60MHz/X 60 MHz/4 60 MHz/6 ... 60 MHz/2048
VCLK 15.0 MHz 10.0 MHz ... 30.0 KHz

61
S3C2440 S3C2440

Register Setting Example
TFT Resolution: 240 x 240 VSPW: 2, VBPD = 14, LINEVAL = 239, VFPD = 4 HSPW = 25, HPBD = 15, HOZVAL = 239, HFPD = 1 HCLK = 60MHz
If target frame rate is 60~70Hz, then CLKVAL should be 5 then, Frame Rate = 67Hz
62
31
S3C2440 S3C2440
LCD PALETTE Usage

256 Color palette for TFT LCD Control From the 64K colors in 5:6:5(R:G:B) and 5:5:5:1(R:G:B:I) formats
ex) 5:6:5 format
Index 15 14 13 12 11 10 00H 01H FFH VD# 9 8 7 6 5 4 3 2 1 0 Address R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0 0x4D000400 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0 0x4D000404 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0 0x4D0007FC 23 22 21 20 19 15 14 13 12 11 10 7 6 5 4 3
0x4D0004000: palette start address VD18, VD10, VD2 have the same output value I when 5:5:5:1 DATA[31:16] is invalid
Read/Write Operation
VSTATUS of LCDCON5 register must be checked No operation for ACTIVE status
S3C2440 S3C2440
: R:G:B = 5:6:5
Using True Color
64B Image Buffer
07e0 001f 07e0 f800 07e0 001f 07e0 f800 001f f800 07e0 001f 001f f800 07e0 001f
07e0 001f ffe0 f800 07e0 001f ffe0 07e0 07e0 001f 001f 07e0 ffe0 f800 f800 f800 001f 001f f800 f800 07e0 07e0 001f 07e0 001f 001f 001f f800 f800 07e0 07e0 001f 07e0 f800 07e0 01 07e0 001f f800 07e0 07e0
64
Using 8-bpp Palettized Color

Palette
0x00 0x01 0x02 0x03 0x04
32B Image Buffer

01 01 03 01 03 02 01 02 01 02 00 02 00 00 02 00 02 02 00 02 00 00 00 00 00 01 01 01 02 01 02
8x4 LCD
07e0 07e0 001f 001f 07e0 ffe0 f800 f800
32
S3C2440 S3C2440
LCD Palette Usage(TFT)

8bpp
Palette : 0x4D000400, 5:6:5=R:G:B static const unsigned short PaletteColors[] ={0xf800, 0x07e0, 0x001f, 0xffff, }; static const unsigned char Pixels[] ={0x01, 0x01, 0x02, 0x02, 0x01, 0x01,};
0x4D000400 0x4D000404 0x07e0 0x01 0x02 0x4D000408 0x001f 0x03 0x4D00040C 0xffff ...
Palette
0x00
0xf800
0x01
0x01 0x01 0x02 0x02
0x02 0x02 0x00 0x00
0x02 0x02 0x00 0x00
0x01 0x01 0x01 0x01
0x01 0x01 0x01 0x01
0x00 0x00 0x01 0x01
0x00 0x00 0x01 0x01
TFT LCD Pixel
0x01 0x02 0x02
65
S3C2440 S3C2440

8bpp: 5:6:5(R:G:B)
BSWP=0, HWSWP=0
D[31:24]D[23:16] D[15:8] D[7:0]
BSWP=1, HWSWP=0
D[31:24]D[23:16] D[15:8] D[7:0]
0x01
0x01 0x01 0x01 0x01
0x02 0x00 0x02 0x00
0x02 0x00 0x02 0x00
0x02 0x00 0x02 0x00
0x02 0x00 0x02 0x00
0x01 0x01 0x01 0x01
0x01 0x01 0x01 0x01
Video 0x01 Memory 0x01

0x01
TFT LCD Pixel
0x01 0x01
0x01 0x01
0x02 0x02
0x02 0x02
0x01 0x01
0x01 0x01
0x00 0x00
0x00 0x00
66
33
S3C2440 S3C2440

for(i=starty; i<endy; i++) //y { for(j=0; j<240; j++)//x { frameBuffer8Bpp[i][j/4]= A B ( frameBuffer8Bpp[i][j/4] & ~(0xff000000>>(j%4)*8) ) | ( ((int)TEMP[j+(i%53)*240])<<((4-1-(j%4))*8) ); } C }
BIT CLEAR BIT MASK
A 10100011110011011011010110111111 & B 00000000111111111111111111111111 00000000110011011011010110111111 | C 10011010000000000000000000000000

S3C2440 S3C2440
LCD Controller Registers

LCDCON1: LCD Control 1 Register (0x00000000)
31 28 27 18 17 8 7 6 5 4 1 0
Not Used
LINECNT(RO)
CLKVAL
BPPMODE
Provide the status of the line counter Down count from LINEVAL to 0 STN: VCLK = HCLK/(CLKVALx2) TFT: VCLK = HCLK/[(CLKVAL+1)x2] MMODE Determine the toggle rate of the VM (STN) 0: Each Frame 1: The rate defined by the MVAL PNRMODE 00, 01, 10: for STN 11: TFT LCD panel BPPMODE 0000~0100: for STN 1000~1101: 1, 2, 4, 8, 16, 24 for TFT ENVID Enable Video output & LCD Control signal
68
34
S3C2440 S3C2440

31 24 23 14 13 8 7 6 5 4 0
VBPD
LINEVAL
VFPD
VSPW
VBPD Vertical Back Porch # of inactive lines at the start of a frame LINEVAL Vertical size of LCD panel VFPD Vertical Front Porch # of inactive lines at the end of a frame VSPW Vertical Sync Pulse Width by counting # of inactive lines
69
S3C2440 S3C2440

31 26 25 19 18 8 7 6 5 4 0
Not Used
HBPD
HOZVAL
HFPD
HBPD Horizontal Back Porch # of VCLK periods after falling edge of HSYNC HOZVAL Horizontal size of LCD panel HFPD Horizontal Front Porch # of VCLK periods at the end of line

31 16 15 8 7 0
Not Used
MVAL STN VM signal rates when MMODE is 1 HSPW Horizontal Sync Pulse Width # of the VCLK
HSPW
70
35
S3C2440 S3C2440

31 20 19 18 17 16 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Not Used VSTATUS 00: VSYNC, 01: BACK Porch 10: ACTIVE, 11: FRONT porch HSTATUS 00: HSYNC, 01: BACK Porch 10: ACTIVE, 11: FRONT porch
SBZ
BPP24BL 0: LSB valid, 1: MSB valid FRM565 0: 5:5:5:1, 1: 5:6:5 INVCLK 0: video data is fetched at VCLK falling edge INVHSYNC INVVSYNC INVVD INVVDEN INVPWREN INVLEND PWREN, ENLEND, BSWP, HWSWP
S3C2440 S3C2440

LCDSADDR1: Frame Buffer Start Address 1 Register (0x00000000)
31 30 29 21 20 0
NU
LCDBANK
LCDBASEU
A[30:22] of the bank location for the video buffer Be aligned 4MB region A[21:1] of the start address of the LCD frame buffer

31 21 20 0
Not Used
LCDBASEL A[21:1] of the end address of the LCD frame buffer = ((the frame end address)>>1)+1 = LCDBASEU+(PAGEWIDTH+OFFSIZE)x(LINEVAL+1)

31 22 21 11 10 0
Not Used
OFFSIZE
PAGEWIDTH
Virtual Screen Offset Size (# of half words) Virtual Screen Page Width (# of half words)
72
36
S3C2440 S3C2440

TPAL: Temporary Palette Register (0x00000000)
31 25 24 23 0
Not Used TPALEN Temporary palette register enable bit TPALVAL Temporary palette value TPALVAL[23:16] : RED TPALVAL[15:8] : GREEN TPALVAL[7:0] : BLUE
TPALVAL
LPCSEL: LPC3600 Control Register (0x00000004)

31 4 3 2 1 0
Not Used CPV_SEL MODE_SEL RES_SEL 0: 320x240, 1: 240x320 LPC_EN LPC3600 Enable
73
S3C2440 S3C2440
LCD CONTROLLER SPECIAL REGISTERS

LCDSRCPND (0x0)
[1]: INT_FrSyn, [0]: INT_FiCnt
LCDINTPND (0x0)
[1]: INT_FrSyn, [0]: INT_FiCnt
LCDINTMSK (0x3)
[2]: FIWSEL determine the trigger level of LCD FIFO 0: 4 words, 1: 8 words [1]: INT_FrSyn, [0]: INT_FiCnt
74
37
S3C2440 S3C2440
ADC & Touch Screen Interface

ADC
Converts an analog input signal into 10-bit binary digital codes 8 channel, maximum 500KSPS with 2.5 MHz
Touch Screen Interface

External transistor control logic ADC interface logic with an interrupt generation logic
Features
Resolution: 10-bit Maximum conversion rate: 500KSPS Analog Input range: 0 ~ 3.3V On-chip Sample-and-hold function Normal conversion mode Separate X/Y position conversion mode Auto X/Y position conversion mode Waiting for interrupt mode
75
S3C2440 S3C2440
ADC & Touch Screen Interface
76
38
S3C2440 S3C2440
Touch Screen Principle

3.3 V
Touch Screen
LCD Panel (1.1/3.3)x1023 1.1 V
3.3 V 0V (341, 620) 2.0 V (2.0/3.3)x1023
Then, what coordinate in LCD Panel?

S3C2440 S3C2440
Touch panel
5
( )
X Y
78
39
Microprocessor-Based System Microprocessor-Based System
Touch Screen

ADC
3.3V

10- : (1023, 1023) : 0 ~ 3.3V X/Y X/Y
XP XM YP YM Touch Panel 0V
nYPON YMON nXPON XMON
External Transistor Control
Interrupt Generator
ADC
X Register Y Register
Controller
4 , ( ) X,Y
Touch Screen

Stylus
XP XM YP YM Touch Panel ADC X Register Y Register 3.3V nYPON YMON nXPON XMON Pull Up Interrupt Generator External Transistor Control
Controller

Stylus down X Y
0V Stylus Up
3.3V
XP
0V 3.3V
YP
0V
40
Touch Screen
X/Y
X Y Touch screen
nYPON YMON nXPON XMON nYPON YMON nXPON XMON
3.3V
3.3V
XP XM YP YM ADC
Interrupt Generator
XP XM
Interrupt Generator
YP YM
ADC
Controller
Controller
0V
0V
81
S3C2440 S3C2440
ADC & TS Control Registers

ADCCON: ADC Control Register (0x3FC4)
15 14 13 6 5 3 2 1 0
PRSCVAL End of conversion (RO) 0: progress, 1: end Prescaler enable 0: disable, 1: enable Prescaler value 1 ~ 255
SEL Enable start 0: disable, 1: ADC start Read start 0: disable, 1: enable start by read Standby mode select 0: normal, 1: standby mode Analog input channel select 000: AIN0, 001: AIN1, 010: AIN2, 011: AIN3, 100: AIN4, 101: AIN5, 110: AIN6, 111: AIN7(XP)
82
41
S3C2440 S3C2440
ADC & TS Control Registers

ADCTSC: ADC Touch Screen Control Register (0x058)
8 7 6 5 4 3 2 1 0
Reserved Should be 0 Output of YMON 0: for Hi-Z, 1: for GND Output of nYPON 0: for External V, 1: for AIN[5] Output of XMON 0: for Hi-Z, 1: for GND
Manual XY_PST 00: No operation, 01: X, 10: Y, 11: Wait for Interrupt Auto_PST 0: normal, 1: auto XY Pull_Up 0: XP pull_up enable, 1: disable Output of nXPON 0: for External V, 1: for AIN7
ADCDLY: ADC Start Delay Register (0x00FF)

15 0
DELAY
ADCDAT0/1: ADC Conversion Data Register

15 10 9 0
XPDATA(YPDATA)
S3C2440 S3C2440
RTC (Real Time Clock)

For clock information while the system power is off
by using backup battery
Features
BCD number: second, minute, hour, date, day, month, year (2 position) Leap year generator Alarm function: alarm interrupt or wake-up from power-down mode Supports millisecond tick time interrupt for RTOS kernel time tick. Round reset function
84
42
S3C2440 S3C2440
RTC Control Registers

RTCCON: RTC Control Register (0x0)
3 2 1 0
CLKRST: Clock Count Reset 0: No-reset, 1: Reset CNTSEL: BCD Count Select 0: Merge BCD Counter 1: reserved
RTCEN: RTC Read/Write Enable 0: disable, 1: enable CLKSEL: BCD Clock Select 0: XTAL 1/2^15 divided clock, 1: reserved
RTCALM: RTC Alarm Control Register (0x00)

7 6 5 4 3 2 1 0
ALMEN: alarm global enable YEAREN: year alarm enable MONEN: month alarm enable
SECEN: second alarm enable MINEN: minute alarm enable HOUREN: hour alarm enable DAYEN: day alarm enable
85
S3C2440 S3C2440

ALMSEC, ALMMIN: Alarm Second(Minute) Data Register (0x00)
7 6 4 3 0
from 0 to 5
from 0 to 9
ALMHOUR(0x00)
7 6 4 3 0
ALMDAY(0x01)
7 6 4 3 0
from 0 to 2
from 0 to 9
from 0 to 3
from 0 to 9
ALMMON(0x01)
7 5 4 3 0
ALMYEAR(0x00)
7 4 3 0
from 0 to 1
from 0 to 9
from 0 to 9
from 0 to 9
RTCRST: RTC Rount Reset Register(0x0)

3 0
SECCR SRSTEN: Round second reset enable

Round Binary for second carry generation 011: over than 30, 100: over than 40, 101: over than 50
86
43
S3C2440 S3C2440

BCDSEC, BCDMIN: BCD Second(Minute) Data Register ()
7 6 4 3 0
from 0 to 5
from 0 to 9
BCDHOUR()
7 6 4 3 0
BCDDAY()
7 6 4 3 0
from 0 to 2
from 0 to 9
from 0 to 3
from 0 to 9
BCDMON()
7 5 4 3 0
BCDYEAR()
7 4 3 0
from 0 to 1
from 0 to 9
from 0 to 9
from 0 to 9
TICNT: Tick Time Count Register (0x00)

7 6 4 3 0
Tick time interrupt enable
Tick time count value (1 ~ 127)
87
S3C2440 S3C2440
IIC(Inter IC)

TV EEPROM, , RTC

2 SDA (Serial Data Line) SCL (Serial Clock Line) IIC , . , SCL . 8 100kbit/s (standard-mode), 400kbit/s (Fastmode), 3.4Mbit/s (High-speed mode) .
APB
Address Register Comparator Control Unit Shift Register Shift Data SDA SCL
88
44
S3C2440 S3C2440
IIC

SCL H SDA H L . H . MSB . ACK L L No Acknowledge . SCL H L H .
SDA
MSB
SCL
S
2 8 bit data
9 A
2 8 bit data
9 A A
ACK from Receiver

ACK or NoACK from Receiver

89
S3C2440 S3C2440
IIC
Write with 7 address
S 7-bit address 0 A 8-bit data A 8-bit data A P A
Read with 7 address

S 7-bit address 1 A 8-bit data A 8-bit data AP
Combined mode Read/Write with 7 address

S 7-bit address R A W 8-bit data A R Sr 7-bit address A A W 8-bit data A P A
Write with 10 address

S 2 bit address 0A 11110xx 8-bit address A 8-bit data A 8-bit data A P A
Read with 10 address

S 2-bit address 0A 11110xx 8-bit address A Sr 2-bit address 1A 11110xx 8-bit data AP
90
45
S3C2440 S3C2440
IIC-BUS Interface
Operation of IIC
Master/Transmitter
Master/Receiver
91
S3C2440 S3C2440
IIC-BUS Interface
Operation of IIC
Slave/Transmitter
Slave/Receiver
92
46
S3C2440 S3C2440
IIC Interface Example

S524C80D80 Serial EEPROM
93
S3C2440 S3C2440

KS24C080C Serial EEPROM
94
47
S3C2440 S3C2440

Byte Write Operation
Slave Address Word Address Data
S 1 0 1 0 X X XWA Page Write Operation

Slave Address Word Address
AE
Data(0)
Data(n)
S 1 0 1 0 X X XWA
AE
Software based Write Protection (Lower 128 bytes

Slave Address Address(Ignored) Data(Ignored)
S 0 1 1 0 X X XWA
AE
95
S3C2440 S3C2440

Current Address Byte Read Operation ( by internal address pointer)
Slave Address Data No ACK
S 1 0 1 0 XXXRA Random Address Byte Read Operation

Slave Address Word Address
1E
Slave Address
Data
No ACK
S 1 0 1 0 X X XWA Sequential Read Operation

Slave Address Data(n)
AS 1 0 1 0 XXXRA
1E
Data(n+1)
No Data(n+x) ACK
S 1 0 1 0 XXXRA
1E
96
48
S3C2440 S3C2440

S524C80D80 Serial EEPROM
97
S3C2440 S3C2440
IIS(Inter IC Sound)
IC 8/16- CODEC IC CODEC
3 SCK: Continuous Serial Clock WS: Word Select Line (Left/Right Channel Select) SD: Serial Data Line SCK WS
APB ADDR DATA CNTL TxFIFO TxFIFO
Control Unit
Signal Control
Shift Register
SD SCK WS
98
49
S3C2440 S3C2440
IIS BUS
SD
8- 16- 2 MSB SCK leading trailing SCK leading
WS
leading
MSB-justified MSB WS .
WS SCK SD
MSB 2 N-1 LSB MSB 2 N-1 LSB MSB LEFT RIGHT LEFT
IIS-bus Format (N=8 or 16) WS SCK SD

MSB 2 N-1 LSB MSB 2 N-1 LSB MSB 2 LEFT RIGHT LEFT
MSB-justified Format (N=8 or 16)

S3C2440 S3C2440
IIS

: Transmitter Transmitter SCK WS SD . : Receiver Receiver SCK WS Transmitter SD . : Controller Controller SCK WS Transmitter SD .
SCK WS SD SCK WS SD
Transmitter
Receiver
Transmitter
Receiver
Master = Transmitter
Master = Receiver
Controller
Transmitter
SCK WS SD
Receiver
Master = Controller
50
S3C2440 S3C2440
SPI(Serial Peripheral Interface)

8-
. : : 0xFF

SCK: Serial Clock MISO: Master-Input Slave-Output MOSI: Master-Output Slave-Input /SS: Slave Select
LSB MSB Tx 8bit Shifter LSB MSB Rx 8bit Shifter Clock Logic
APB ADDR DATA CNTL
MISO MOSI Signal Control SCK /SS
Control Unit
101
S3C2440 S3C2440
SPI
SPI
SCK
Master
SPI
SCK MOSI MISO /SS Slave
SCK MOSI MISO

MSB MSB 6 6 5 5 4 4 3 3 2 2 1 1 LSB LSB MSB
Single-Master Single-Slave
SCK MOSI MISO Master /SS1 /SS2 /SS3 SCK MOSI Slave1 MISO /SS SCK MOSI Slave2 MISO /SS SCK MOSI Slave3 MISO /SS
MSB-maintained method SCK SCK MOSI

MSB 6 6 5 5 4 4 3 3 2 2 1 1 LSB LSB
MISO LSB MSB
LSB-maintained method
Single-Master Multiple-Slave
102
51

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S3C2440

2007. 3. 1 Cho, Sang-Young

SYCHO CSE HUFS

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Smartphones Cellular Printer

S3C2440 RISC Microprocessor Palm PC GPS

Digital STB and NCs PDA / Organizers e-Book

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S3C2440 Block Diagram

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Wake up by EINT[15:0] or RTC alarm interrupt Interrupt Controller 60 Interrupt source

SYCHO CSE HUFS SYCHO CSE HUFS

SYCHO CSE HUFS SYCHO CSE HUFS

Using NAND flash for boot ROM

SYCHO CSE HUFS SYCHO CSE HUFS

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Memory Controller Example

Halfword with Byte

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Memory Controller Example

Halfword with Halfword

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Memory Control Registers

DW4 Bus width 00: 8-bit 01: 16-bit 10: 32-bit

Wait states 0: disable 1: enable

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Memory Control Registers

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Memory Control Registers

Same to the BANKCON0~5

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Memory Control Registers

Refresh Count Refresh count value = 211 + 1 - Ref_period*HCLK

BANKSIZE: Bank Size Register (0x0)

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Memory Control Registers

Res. WL Write burst length 0: burst(Fixed), 1: reserved

BL Burst length 000: 1(Fixed) Others: reserved

Test mode 00: mode register set(Fixed) Others: reserved

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Clock & Power Management(2440)

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Clock When Power-On Reset

SYCHO CSE HUFS SYCHO CSE HUFS

Clock Change When Normal Mode

SYCHO CSE HUFS SYCHO CSE HUFS

Clock & Power Special Registers

PLLCON: MPLL/UPLL Control Register (0x0009_6030/0x0004_d030)

MDIV Main divider control

SDIV Post divider control

Clock & Power Special Registers

CLKSLOW: Clock Slow Control Register (0x0000_0004)

SLOW_VAL Divider value when SB is on

Power Management State

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Clock & Power Special Registers

PDIV PCLK Divider 0: PCLK = HCLK 1: PCLK = HCLK/2

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Clock & Power Special Registers

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Clock & Power Special Registers

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