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Compal Confidential
2

JE50/HM50/SJV50_BZ
P5WE6/P5WH6/P5WS6 Schematics Document
AMD Brazos
Brazos with Zacate / Hudson M1 / Seymour XT
DIS only / UMA only / PX Muxless / PX Muxless with BACO

2010-11-16
LA-7092P REV: 1.0

ZZZ

PCB
Part Number = DAZ0IC00100

2010/08/20

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2011/08/20

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Cover Page
Document Number

Rev
1.0

LA-7092P P5WE6/H6/S6
Tuesday, November 16, 2010

Sheet
E

of

47

Compal Confidential

Model Name : P5WE6/P5WH6/P5WS6


JE50/HM50/SJV50_BZ
PCB PN : DAZ0IC00100

VRAM 512M/1G
64M16/128M16 x 4

Brazos

page 23

DDR3

Memory BUS(DDR3)

ATI Vancuver Seymour


uFCBGA-962
Thermal Sensor

Page 18,19,20,21,22

PCI-Express x 4
Gen2

ADM1032

page 19

DP0
LVDS

204pin DDRIII-SO-DIMM X2

Single Channel

AMD Brazos APU

BANK 0, 1, 2, 3

page 8,9

1.5V DDRIII 800~1066MHz

FT1
BGA 413-Ball
19mm x 19mm

page 10

DP1
2

page 5,6,7
2

CRT
page 12

HDMI
Conn.
page

UMI Gen.1 x4
PCI-Express
2.5GT/s per lane

USB port 0,1,2

USB port 5

USB
Conn x 3

CMOS
Camera

11

page 33

USB port 7

USB port6

Bluetooth
Conn

page 10

page 33

USB port 8

Card
Reader
RT5137

Mini
card
(WL)X1

page 29

page 29

FCH
3.3V 48MHz

Hudson-M1
BGA 605-Ball
23mm x 23mm

S-ATA

page 29

GPP3

HDA Codec
CX20584
page 27

page 26

GPP2

RTC CKT.

LPC BUS

RJ45

page 13

page 26

Power On/Off CKT.

Power sequence
DC/DC

DC/DC Interface CKT.

SATA ODD
Sub/B page

port 0

port 1

MIC Jack x 1
HP Jack x 1
Int MIC x 1
Int SPK x 1

page 32

page 32

EC I/O Buffer

page 34

page 28

Int.KBD

Touch Pad
Fan Control

30

page 31

page 24,25

SATA HDD
Conn. page 30

ENE KB930

page 34

VGA

Gen2

Atheros
AR8151

WLAN

page 32

HD Audio

page 13,14,15,16,17

LAN(GbE)

MINI Card

LED
3

USB

3.3V 24.576MHz/48Mhz

BIOS

page 32

page 32

page 35

Power Circuit
page 36,37,38,39,40,41
42,43,44,45

Extend Card/B
1. USB X2
2. ODD X1

2010/08/20

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2011/08/20

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Block Diagrams
Document Number

Rev
1.0

LA-7092P P5WE6/H6/S6
Monday, November 15, 2010

Sheet
E

of

47

Voltage Rails

Power Plane

Description

S1

S3

S5

VIN

Adapter power supply (19V)

N/A

N/A

N/A

B+

AC or battery power rail for power circuit.

N/A

N/A

N/A

+VSB

VSB always on power rail

ON

ON

ON*

+3VALW

3.3V always on power rail

ON

ON

ON*

+5VALW

5V always on power rail

ON

ON

ON*

+1.1VALW

1.1V always on power rail

ON

ON

ON*

+APU_CORE

Core voltage for CPU (0.7-1.2V)

ON

OFF

OFF

+APU_CORE_NB

1.0V switched power rail

ON

OFF

OFF

ON

ON

ON

ON

S1(Power On Suspend)

LOW

HIGH

HIGH

HIGH

ON

ON

ON

LOW

S3 (Suspend to RAM)

LOW

LOW

HIGH

HIGH

ON

ON

OFF

OFF

S4 (Suspend to Disk)

LOW

LOW

LOW

HIGH

ON

OFF

OFF

OFF

S5 (Soft OFF)

LOW

LOW

LOW

LOW

ON

OFF

OFF

OFF

Board ID / SKU ID Table for AD channel

ON

ON

OFF

OFF

OFF

+1.05VS

1.05V switched power rail for APU VDD10

ON

OFF

OFF

Vcc
Ra/Rc/Re

+1.1VS

1.1VS switched power rail

ON

OFF

OFF

Board ID

+1.8VS

1.8V switched power rail

ON

OFF

OFF

+3VS

3.3V switched power rail

ON

OFF

OFF

0
1
2
3
4
5
6
7

ON

OFF

OFF

OFF

OFF

+3VSG

3.3V switched power rail for GPU

ON

OFF

OFF

+1.8VSG

1.8V switched power rail for GPU

ON

OFF

OFF

+1.5VSG

1.5V switched power rail for GPU

ON

OFF

OFF

+1.0VSG

1.0V switched power rail for GPU

ON

OFF

OFF

+3V_LAN

3.3V power rail for LAN

ON

ON

ON

+RTCVCC

RTC power

ON

ON

ON

Clock

HIGH

ON

ON

+VS

HIGH

1.5V power rail for CPU VDDIO and DDRIII

5V switched power rail

+V

HIGH

0.75VS switched power rail for DDR terminator

Core voltage for GPU

+VALW

HIGH

+0.75VS

+5VS

BOARD ID Table
SLP_S1# SLP_S3# SLP_S4# SLP_S5#

Full ON

+1.5V

+VGA_CORE

SIGNAL

STATE

3.3V +/- 5%
100K +/- 5%
Rb / Rd / Rf
0
8.2K +/- 5%
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%
NC

Board ID
0
1
2
3
4
5
6
7

PCB Revision

Project ID Table
V AD_BID min
0 V
0.216 V
0.436 V
0.712 V
1.036 V
1.453 V
1.935 V
2.500 V

V AD_BID typ
0 V
0.250 V
0.503 V
0.819 V
1.185 V
1.650 V
2.200 V
3.300 V

V AD_BID max
0 V
0.289 V
0.538 V
0.875 V
1.264 V
1.759 V
2.341 V
3.300 V

Board ID
0
1
2
3
4
5
6
7

PCB Revision

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

BOARD ID Table
EC SM Bus1 address
Device

Address

EC SM Bus2 address
HEX

Device
ADM1032 (GPU)

SM Bus Controller 0
Device
3

Address

HEX

1001-101xb

9AH

(FCH_SMB1 ~ FCH_SMB4, SMB_ALERT#)

Address

BTO Option Table


PCB Revision
BTO Item
BOM Structure
Display from APU
UMA@
Display from VGA
DISO@
Use VGA
VGA@
Muxless w/BACO
BACO@
Muxless wo/BACO
WOBACO@
Muxless
PX@
w/Vancouver Serise
VAN@
w/Manhttan Serise
MAN@
Bluetooth
BT@
AR8151
8151@
Seymour
Seymour@
wo/Muxless
WOPX@
wo/VGA
WOVGA@
APU 1.5G
15G@
APU 1.6G
16G@

w/ X'tal X1
wo/ X'tal X1

HEX

APU SIC/SID (FCH_SMB3)

Project ID Table

H_THERMTRIP# (FCH_ALERT#)

SM Bus Controller 1
Device

Board ID
0
1
2
3
4
5
6
7

Board ID
0
1
2
3
4
5
6
7

(FCH_SMB0)

Address

HEX

DDR DIMM1 (FCH_SMB0)

1001-000xb

90

DDR DIMM2 (FCH_SMB0)

1001-001xb

92

WLAN (FCH_SMB0)

PCB Revision

*UMA only : UMA@ BT@ 8151@ WOVGA@ WOPX@


VGA Chip SEL:
1. Seymour@ + Van@
2. Robson@ + Man@

APU Chip SEL:


1. 16G@
2. 15G@

*DIS only : VGA@ DISO@ WOBACO@ BT@ 8151@ WOPX@


*Muxless w/BACO : UMA@ VGA@ PX@ BACO@ BT@ 8151@
Muxless wo/BACO : UMA@ VGA@ PX@ WOBACO@ BT@ 8151@

2010/08/20

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2011/08/20

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Notes List
Document Number

Rev
1.0

LA-7092P P5WE6/H6/S6
Tuesday, November 16, 2010

Sheet
E

of

47

Power-Up/Down Sequence

BACO option :

2. VDDR3 should ramp-up before or simultaneously with VDDC.

PE_GPIO0 : High ->Normal operation (dGPU is not reseton BACO mode)


PE_GPIO1 : Low -> dGPU Power OFF ; High -> dGPU Power ON (always High)

3. For LVDS, DPx_VDD10 should ramp-up before DPx_VDD18 and the PCIe Reference clock should begin before
DPx_VDD18. For power-down, DPx_VDD18 should ramp-down before DPx_VDD10.
4. The external pull-ups on the DDC/AUX signals (if applicable) should ramp-up before or after both VDDC and
VDD_CT have ramped up.
5.VDDC and VDD_CT should not ramp-up simultaneously. (e.g., VDDC should reach 90% before VDD_CT starts to
ramp-up (or vice versa).)

VDDR3(3.3VSG)

Note: Do not drive any IOs before VDDR3 is ramped up.

PCIE_VDDC(1.0V)
C

PE_GPIO0 : Low -> Reset dGPU ; High ->Normal operation


PE_GPIO1 : Low -> dGPU Power OFF ; High -> dGPU Power ON

1. All the ASIC supplies must fully reach their respective nominal voltages within 20 ms of the start of the ramp-up
sequence, though a shorter ramp-up duration is preferred.

Without BACO option :

VDDR1(1.5VSG)

dGPU Power Pins

Voltage

PX 3.0

BACO Mode Max current

PCIE_PVDD, PCIE_VDDR, TSVDD, VDDR4, VDD_CT,


DPE_PVDD, DP[F:E]_VDD18, DP[D:A]_PVDD,
DP[D:A]_VDD18, AVDD, VDD1DI, A2VDDQ, VDD2DI,
DPLL_PVDD, MPV18, and SPV18

1.8V

OFF

ON

1679mA

DP[F:E]_VDD10, DP[D:A]_VDD10, DPLL_VDDC, and


SPV10

1.0V

OFF

ON

575mA

PCIE_VDDC

1.0V

OFF

ON

2A

VDDR3 , and A2VDD

3.3V

OFF

ON

190mA

BIF_VDDC (current consumption = 55mA@1.0V, in


BACO mode)

Same as
VDDC

OFF

ON
Same as
PCIE_VDDC

70mA

VDDR1

1.5V

OFF

OFF

2.8A

VDDC/VDDCI

1.12V

OFF

OFF

12.9A

VDDC/VDDCI(1.12V)
VDD_CT(1.8V)

iGPU

PE_GPIO0

PE_EN

dGPU

PERSTb

BACO Switch

BIF_VDDC
PE_GPIO1

REFCLK

PX_mode

+3.3VALW

Straps Reset

+1.0V

Straps Valid

MOS

Regulator

+3.3VSG

1
+1.0VSG

+1.5V

+1.5VSG

SI4800

Regulator

Global ASIC Reset


+1.8V
T4+16clock

SI4800

+B

+1.8VSG

+VGA_CORE

PWRGOOD

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2010/08/20

Deciphered Date

2011/08/20

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

dGPU Block Diagram


Document Number

Rev
1.0

LA-7092P P5WE6/H6/S6
Monday, November 15, 2010

Sheet
1

of

47

+1.8VS

D10
C10

TDP1_TXP2
TDP1_TXN2

<11> APU_HDMI_CLKP
<11> APU_HDMI_CLKN

A10
B10

TDP1_TXP3
TDP1_TXN3

<10> APU_TXOUT2+
<10> APU_TXOUT2-

B5
A5

LTDP0_TXP0
LTDP0_TXN0

<10> APU_TXOUT1+
<10> APU_TXOUT1-

D6
C6

LTDP0_TXP1
LTDP0_TXN1

APU_PROCHOT#

2 1K_0402_5%

R109 1 UMA@ 2 4.7K_0402_5%

APU_CRT_DDC_SCL

R155 1 UMA@ 2 4.7K_0402_5%

APU_CRT_DDC_SDA

R411 1

2 1K_0402_5%

APU_ALERT#_R

R143 1

2 1K_0402_5%

APU_SIC

R414 1

2 1K_0402_5%

APU_SID

A6
B6

<10> APU_TXCLK+
<10> APU_TXCLK-

D8
C8
V2
V1

<13> APU_CLKP
<13> APU_CLKN

For DVT 1011

<44> APU_SVC
<44> APU_SVD

J1
J2

SVC
SVD

P3
P4

SIC
SID

T3
T4

RESET_L
PWROK

<13> APU_RST#
<13> APU_PWRGD
R169 1
R168 1

APU_PROCHOT#
U1
APU_THERMTRIP# U2
APU_ALERT#_R
T2

2 0_0402_5%
2 0_0402_5%

APU_TDI
APU_TDO
APU_TCK
APU_TMS
APU_TRST#
APU_DBRDY
APU_DBREQ#

T93PAD
T94PAD
Close to APU
<44> APU_VDDNB_RUN_FB_H
<44> APU_VDD0_RUN_FB_H
T77PAD

F4
G1
F3

VDDCR_NB_SENSE
VDDCR_CPU_SENSE
VDDIO_MEM_S_SENSE

A3
B3

LTDP0_HPD

D3

DAC_RED
DAC_REDB
DAC_GREEN
DAC_GREENB
DAC_BLUE
DAC_BLUEB
DAC_HSYNC
DAC_VSYNC

C12
D13
A12
B12
A13
B13

F2
D4

DAC_ZVSS

D12

TEST4
TEST5
TEST6
TEST14
TEST15
TEST16
TEST17
TEST18
TEST19
TEST25_H
TEST25_L
TEST28_H
TEST28_L
TEST31
TEST33_H
TEST33_L
TEST34_H
TEST34_L
TEST35
TEST36
TEST37

R1
R2
R6
T5
E4
K4
L1
L2
M2
K1
K2
L5
M5
M21
J18
J19
U15
T15
H4
N5
R5

APU_HDMI_HPD <11>
APU_LCD_CLK
APU_LCD_DATA
R406 1

2 150_0402_1%

R408 1

2 150_0402_1%

R409 1

2 150_0402_1%

APU_CRT_B <12>

APU_CRT_DDC_SCL <12>
APU_CRT_DDC_SDA <12>
R144 1

2 499_0402_1%
PAD T66
PAD T67
PAD T68

TEST15

R415 1

TEST18
TEST19
TEST25_H
TEST_25_L

R416 1
R417 1
R418 1

2 1K_0402_5%

2 1K_0402_5%
2 1K_0402_5%
2 510_0402_1%

TEST31
PAD T73
TEST33_H
C5161
R420 1
2 0.1U_0402_16V4Z
TEST33_L
C5171
R421 1
2 0.1U_0402_16V4Z
Delete Test point for layout limitation
20100917
TEST35
R422 1
@
2 1K_0402_5%
TEST36
TEST37
R958 1
2 1K_0402_5%
PAD T76
+1.8VS

K3
T1

2 51_0402_1%
2 51_0402_1%

ALLOW_STOP# <13>
R423 1

2 1K_0402_5%

+1.8VS

Zacate FT1 B0

+1.8VS

+1.8VS
JHDT1

2
0_0402_5%
2
R842
1

APU_TRST#

FDV301N, the Vgs is:


min = 0.65V
Typ = 0.85V
Max = 1.5V

BSH111, the Vgs is:


min = 0.4V
Typ = 1.0V
Max = 1.3V

APU_TCK

R843 2

1 1K_0402_5%

APU_TMS

R840 2

1 1K_0402_5%

APU_TDI

R798 2

1 1K_0402_5%

APU_TDO

10

10

APU_PWRGD

11

12

12

APU_RST#

14

APU_DBRDY

16

APU_DBREQ#

R178 1

2 300_0402_5%

18

J108_PLLTST0

R799 1

2 0_0402_5%

TEST19

20

J108_PLLTST1

R863 1

2 0_0402_5%

TEST18

7
0_0402_5%
R846 1
2

APU_TRST#_R

R847 2

1 10K_0402_5%

11

R176 2

1 10K_0402_5%

13

R177 2

1 10K_0402_5%

15

30K_0402_1%

17

1.607V for Gate


EC_SMB_DA

1
@
Q22
BSH111 1N_SOT23-3

APU_CRT_G <12>

APU_CRT_HSYNC <12>
APU_CRT_VSYNC <12>

2
C

H_THERMTRIP# <14>

1
R431

APU_CRT_R <12>

AMD Debug

Q79
1

2 0.1U_0402_10V7K

APU_SID 3

2 100K_0402_5%

R407 1

APU : SA000046G80 (S IC ZACATE 2M161232B2240 1.6G BGA )

@
@
1 R160

APU_LCD_CLK <10>
APU_LCD_DATA <10>

U22 16G@

CPU TSI interface level shift

C236 1

APU_HDMI_CLK <11>
APU_HDMI_DATA <11>

E1
E2

DAC_SCL
DAC_SDA

TEST38
DMAACTIVE_L

RSVD_1
RSVD_2
RSVD_3

If FCH internal pull-up disabled, level-shifter could be deleted.


Need BIOS to disable internal pull-up!!

LTDP0_AUXP
LTDP0_AUXN

APU_HDMI_CLK
APU_HDMI_DATA

APU : SA00004DO60 (S IC ZACATE 2M151132B1240 1.5G BGA)

1
2
1

1
R427 @

31.6K_0402_1%

C1

VSS_SENSE

MMBT3904_NL_SOT23-3

TDP1_HPD

2 150_0402_1%
APU_ENBKL <10>
APU_ENVDD <10>
APU_BLPWM <10>

APU_THERMTRIP#

@
1 R428

TDP1_AUXP
TDP1_AUXN

B2
C2

R398 1

ONTARIO-2M161000-1.6G_BGA413
15G@

R424
10K_0402_5%

1K_0402_5%

PROCHOT_L
THERMTRIP_L
ALERT_L
TDI
TDO
TCK
TMS
TRST_L
DBRDY
DBREQ_L

B4
W11
V5
+3VS

DISP_CLKIN_H
DISP_CLKIN_L

N2
N1
P1
P2
M4
M3
M1

F1

<44> APU_VDD0_RUN_FB_L

R425

CLKIN_H
CLKIN_L

D2
D1

LTDP0_TXP3
LTDP0_TXN3

<13> APU_DISP_CLKP
<13> APU_DISP_CLKN

APU_SIC
APU_SID

<31> EC_THERM#
<13> FCH_PROCHOT#

LTDP0_TXP2
LTDP0_TXN2

G2
H2
H1

SER

R410 1

<10> APU_TXOUT0+
<10> APU_TXOUT0-

H3

TEST

+3VS

CLK

C237
0.01U_0402_25V7K
APU_RST#
1 @ 2
C238
0.01U_0402_25V7K
APU_PWRGD
1 @ 2

DP_ZVSS
DP_BLON
DP_DIGON
DP_VARY_BL

DP MISC

<11> APU_HDMI_TX0P
<11> APU_HDMI_TX0N

VGA DAC

TDP1_TXP1
TDP1_TXN1

DISPLAYPORT 1

B9
A9

DISPLAYPORT 0

<11> APU_HDMI_TX1P
<11> APU_HDMI_TX1N

CTRL

2
2
1
1
2
2

TDP1_TXP0
TDP1_TXN0

JTAG

1
1
2
2
1
1

APU_SVC
APU_SVD
APU_RST#
APU_PWRGD
TEST_25_L
TEST36

1K_0402_5%
1K_0402_5%
300_0402_5%
300_0402_5%
510_0402_1%
1K_0402_5%

1K_0402_5%

R399
R400
R142
R401
R402
R141

+3VS

U22B
A8
B8

<11> APU_HDMI_TX2P
<11> APU_HDMI_TX2N

1
R429
1
R430

If use level shift, EC_SMB need pull up


(pop R747 & R748)

FCH_SID

2
0_0402_5%
EC_SMB_DA2
2
0_0402_5%

FCH_SID <14>

19

14

15

16

17

18

19

20

Please be noted about TEST_18 and TEST_19

T0 FCH

EC_SMB_DA2 <19,31>

13

+1.8VS

SAMTE_ASP-136446-07-B
CONN@

TO EC

2
0_0402_5%

APU_SIC 3

EC_SMB_CK
1
@
Q23
BSH111 1N_SOT23-3
1
R434

@
1
R432
1
R433

FCH_SIC
2
0_0402_5%
EC_SMB_CK2
2
0_0402_5%

FCH_SIC <14>

T0 FCH

EC_SMB_CK2 <19,31> TO EC

Compal Secret Data

Security Classification
2010/08/20

Issued Date

2011/08/20

Deciphered Date

Title

FT1 CTRL/DP/CRT

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2
0_0402_5%

Rev
1.0

LA-7092P P5WE6/H6/S6

Date:

Compal Electronics, Inc.

Wednesday, November 24, 2010

Sheet
1

of

47

U22E

<8,9> DDR_A_DQS0
<8,9> DDR_A_DQS#0
<8,9> DDR_A_DQS1
<8,9> DDR_A_DQS#1
<8,9> DDR_A_DQS2
<8,9> DDR_A_DQS#2
<8,9> DDR_A_DQS3
<8,9> DDR_A_DQS#3
<8,9> DDR_A_DQS4
<8,9> DDR_A_DQS#4
<8,9> DDR_A_DQS5
<8,9> DDR_A_DQS#5
<8,9> DDR_A_DQS6
<8,9> DDR_A_DQS#6
<8,9> DDR_A_DQS7
<8,9> DDR_A_DQS#7

<8>
<8>
<8>
<8>
<9>
<9>
<9>
<9>

DDR_A_CLK0
DDR_A_CLK#0
DDR_A_CLK1
DDR_A_CLK#1
DDR_B_CLK2
DDR_B_CLK#2
DDR_B_CLK3
DDR_B_CLK#3

<8>
<8>
<9>
<9>

DDR_A_DQS0
DDR_A_DQS#0
DDR_A_DQS1
DDR_A_DQS#1
DDR_A_DQS2
DDR_A_DQS#2
DDR_A_DQS3
DDR_A_DQS#3
DDR_A_DQS4
DDR_A_DQS#4
DDR_A_DQS5
DDR_A_DQS#5
DDR_A_DQS6
DDR_A_DQS#6
DDR_A_DQS7
DDR_A_DQS#7

A16
B16
B20
A20
E23
E22
J22
J23
R22
P22
W22
V22
AC20
AC21
AB16
AC16

DDR_A_CLK0
DDR_A_CLK#0
DDR_A_CLK1
DDR_A_CLK#1
DDR_B_CLK2
DDR_B_CLK#2
DDR_B_CLK3
DDR_B_CLK#3

M17
M16
M19
M18
N18
N19
L18
L17

DDR_CKE0
DDR_CKE1

<8,9> DDR_CKE0
<8,9> DDR_CKE1

D15
B19
D21
H22
P23
V23
AB20
AA16

DDR_RST#
DDR_EVENT#

<8,9> DDR_RST#
<8,9> DDR_EVENT#

<8>
<8>
<9>
<9>

DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7

DDR_A_ODT0
DDR_A_ODT1
DDR_B_ODT0
DDR_B_ODT1

DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
DDR_CS0_DIMMB#
DDR_CS1_DIMMB#

F15
E15

DDR_A_ODT0
DDR_A_ODT1
DDR_B_ODT0
DDR_B_ODT1

W19
V15
U19
W15

DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
DDR_CS0_DIMMB#
DDR_CS1_DIMMB#

T17
W16
U17
V16

DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#

<8,9> DDR_A_RAS#
<8,9> DDR_A_CAS#
<8,9> DDR_A_WE#

L23
N17

U18
V19
V17

M_DATA0
M_DATA1
M_DATA2
M_DATA3
M_DATA4
M_DATA5
M_DATA6
M_DATA7
M_DATA8
M_DATA9
M_DATA10
M_DATA11
M_DATA12
M_DATA13
M_DATA14
M_DATA15

DDR SYSTEM MEMORY

R18
T18
F16

<8,9> DDR_A_BS0
<8,9> DDR_A_BS1
<8,9> DDR_A_BS2

M_ADD0
M_ADD1
M_ADD2
M_ADD3
M_ADD4
M_ADD5
M_ADD6
M_ADD7
M_ADD8
M_ADD9
M_ADD10
M_ADD11
M_ADD12
M_ADD13
M_ADD14
M_ADD15
M_BANK0
M_BANK1
M_BANK2
M_DM0
M_DM1
M_DM2
M_DM3
M_DM4
M_DM5
M_DM6
M_DM7
M_DQS_H0
M_DQS_L0
M_DQS_H1
M_DQS_L1
M_DQS_H2
M_DQS_L2
M_DQS_H3
M_DQS_L3
M_DQS_H4
M_DQS_L4
M_DQS_H5
M_DQS_L5
M_DQS_H6
M_DQS_L6
M_DQS_H7
M_DQS_L7

M_DATA16
M_DATA17
M_DATA18
M_DATA19
M_DATA20
M_DATA21
M_DATA22
M_DATA23
M_DATA24
M_DATA25
M_DATA26
M_DATA27
M_DATA28
M_DATA29
M_DATA30
M_DATA31
M_DATA32
M_DATA33
M_DATA34
M_DATA35
M_DATA36
M_DATA37
M_DATA38
M_DATA39
M_DATA40
M_DATA41
M_DATA42
M_DATA43
M_DATA44
M_DATA45
M_DATA46
M_DATA47

M_CLK_H0
M_CLK_L0
M_CLK_H1
M_CLK_L1
M_CLK_H2
M_CLK_L2
M_CLK_H3
M_CLK_L3

M_DATA48
M_DATA49
M_DATA50
M_DATA51
M_DATA52
M_DATA53
M_DATA54
M_DATA55

M_RESET_L
M_EVENT_L
M_CKE0
M_CKE1

M_DATA56
M_DATA57
M_DATA58
M_DATA59
M_DATA60
M_DATA61
M_DATA62
M_DATA63

M0_ODT0
M0_ODT1
M1_ODT0
M1_ODT1
M0_CS_L0
M0_CS_L1
M1_CS_L0
M1_CS_L1

B14
A15
A17
D18
A14
C14
C16
D16

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7

C18
A19
B21
D20
A18
B18
A21
C20

DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15

C23
D23
F23
F22
C22
D22
F20
F21

DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23

H21
H23
K22
K21
G23
H20
K20
K23

DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31

N23
P21
T20
T23
M20
P20
R23
T22

DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39

V20
V21
Y23
Y22
T21
U23
W23
Y21

DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47

Y20
AB22
AC19
AA18
AA23
AA20
AB19
Y18

DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55

AC17
Y16
AB14
AC14
AC18
AB18
AB15
AC15

DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

M23

+MEM_VREF

M22

R437

DDR_A_D[0..63]
DDR_A_MA[0..15]
DDR_A_DM[0..7]

DDR_A_D[0..63]

<8,9>

DDR_A_MA[0..15]
DDR_A_DM[0..7]

<8,9>
<8,9>

U22A
<18> PCIE_GTX_C_FRX_P0
<18> PCIE_GTX_C_FRX_N0

PCIE_GTX_C_FRX_P0
PCIE_GTX_C_FRX_N0

AA6
Y6

<18> PCIE_GTX_C_FRX_P1
<18> PCIE_GTX_C_FRX_N1

PCIE_GTX_C_FRX_P1
PCIE_GTX_C_FRX_N1

AB4
AC4

<18> PCIE_GTX_C_FRX_P2
<18> PCIE_GTX_C_FRX_N2

PCIE_GTX_C_FRX_P2
PCIE_GTX_C_FRX_N2

AA1
AA2

<18> PCIE_GTX_C_FRX_P3
<18> PCIE_GTX_C_FRX_N3

PCIE_GTX_C_FRX_P3
PCIE_GTX_C_FRX_N3

Y4
Y3

+1.05VS

1
2
R435 2K_0402_1%

P_ZVDD_10

Y14

P_GPP_RXP0
P_GPP_RXN0
P_GPP_RXP1
P_GPP_RXN1
P_GPP_RXP2
P_GPP_RXN2
P_GPP_RXP3
P_GPP_RXN3

P_GPP_TXP0
P_GPP_TXN0

PCIE I/F

R17
H19
J17
H18
H17
G17
H15
G18
F19
E19
T19
F17
E18
W17
E16
G15

P_GPP_TXP1
P_GPP_TXN1
P_GPP_TXP2
P_GPP_TXN2
P_GPP_TXP3
P_GPP_TXN3

P_ZVDD_10

P_ZVSS

AB6 PCIE_FTX_GRX_P0
AC6 PCIE_FTX_GRX_N0

C518 1VGA@2 0.1U_0402_16V7K


C519 1VGA@2 0.1U_0402_16V7K

PCIE_FTX_C_GRX_P0 <18>
PCIE_FTX_C_GRX_N0 <18>

AB3 PCIE_FTX_GRX_P1
AC3 PCIE_FTX_GRX_N1

C520 1VGA@2 0.1U_0402_16V7K


C521 1VGA@2 0.1U_0402_16V7K

PCIE_FTX_C_GRX_P1 <18>
PCIE_FTX_C_GRX_N1 <18>

Y1
Y2

PCIE_FTX_GRX_P2
PCIE_FTX_GRX_N2

C522 1VGA@2 0.1U_0402_16V7K


C523 1VGA@2 0.1U_0402_16V7K

PCIE_FTX_C_GRX_P2 <18>
PCIE_FTX_C_GRX_N2 <18>

V3
V4

PCIE_FTX_GRX_P3
PCIE_FTX_GRX_N3

C524 1VGA@2 0.1U_0402_16V7K


C525 1VGA@2 0.1U_0402_16V7K

PCIE_FTX_C_GRX_P3 <18>
PCIE_FTX_C_GRX_N3 <18>

AA14 P_ZVSS

R436 1

1.27K_0402_1%

Less than 1"


Less than 1"
<13> UMI_RX0P
<13> UMI_RX0N

AA12
Y12

<13> UMI_RX1P
<13> UMI_RX1N

AA10
Y10

<13> UMI_RX2P
<13> UMI_RX2N

AB10
AC10

<13> UMI_RX3P
<13> UMI_RX3N

AC7
AB7

P_UMI_RXP0
P_UMI_RXN0
P_UMI_RXP1
P_UMI_RXN1
P_UMI_RXP2
P_UMI_RXN2
P_UMI_RXP3
P_UMI_RXN3

P_UMI_TXP0
P_UMI_TXN0

UMI I/F

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15

P_UMI_TXP1
P_UMI_TXN1
P_UMI_TXP2
P_UMI_TXN2
P_UMI_TXP3
P_UMI_TXN3

AB12
AC12

UMI_TX0P_C
UMI_TX0N_C

C526 1
C527 1

2
2

0.1U_0402_16V7K
0.1U_0402_16V7K

AC11
AB11

UMI_TX1P_C
UMI_TX1N_C

C528 1
C529 1

2
2

0.1U_0402_16V7K
0.1U_0402_16V7K

AA8
Y8

UMI_TX2P_C
UMI_TX2N_C

C530 1
C531 1

2
2

0.1U_0402_16V7K
0.1U_0402_16V7K

AB8
AC8

UMI_TX3P_C
UMI_TX3N_C

C532 1
C533 1

2
2

0.1U_0402_16V7K
0.1U_0402_16V7K

UMI_TX0P <13>
UMI_TX0N <13>
UMI_TX1P <13>
UMI_TX1N <13>
UMI_TX2P <13>
UMI_TX2N <13>
UMI_TX3P <13>
UMI_TX3N <13>

ONTARIO-2M161000-1.6G_BGA413
15G@

M_VREF

M_RAS_L
M_CAS_L
M_WE_L
M_ZVDDIO_MEM_S
ONTARIO-2M161000-1.6G_BGA413
15G@

15 mils

+1.5V

39.2_0402_1%

+1.5V

+1.5V

R438
1K_0402_1%
DDR_EVENT#

2
1K_0402_5%

+MEM_VREF

R149 1

R439
1K_0402_1%

C535

1
1

C534

1000P_0402_50V7K

0.1U_0402_16V4Z

Place within 1000 mils to APU


20100526

Compal Secret Data

Security Classification
Issued Date

2010/08/20

2011/08/20

Deciphered Date

Title

Compal Electronics, Inc.


FT1 DDRIII/UMI/PCIE

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
1.0

LA-7092P P5WE6/H6/S6

Date:

Wednesday, November 24, 2010


E

Sheet

of

47

+APU_CORE
+1.8VS

10U_0603_6.3V6M
2

C577

10U_0603_6.3V6M
2

C578

10U_0603_6.3V6M
2

C579

10U_0603_6.3V6M
2

10U_0603_6.3V6M

1U_0402_6.3V6K
2

C583

C584

1U_0402_6.3V6K
2

C585

1U_0402_6.3V6K
2

1U_0402_6.3V6K
2

C586

1U_0402_6.3V6K
2

C587

180P_0402_50V8J
2

C588

1
@
2

10U_0603_6.3V6M

1U_0402_6.3V6K
C548

1U_0402_6.3V6K
C547

1U_0402_6.3V6K
C538

0.1U_0402_16V7K
C546

1U_0402_6.3V6K
C549

FBMA-L11-201209-221LMA30T_0805
Change from SM010014520 to SD002000080
20100816
+1.05VS

VDDPL_10

L31
+VDDL_10

U11

2
1

VDDIO_MEM_S_1
VDDIO_MEM_S_2
VDDIO_MEM_S_3
VDDIO_MEM_S_4
VDDIO_MEM_S_5
VDDIO_MEM_S_6
VDDIO_MEM_S_7
VDDIO_MEM_S_8
VDDIO_MEM_S_9
VDDIO_MEM_S_10
VDDIO_MEM_S_11

0.2A

5.5A
VDD_10_1
VDD_10_2
VDD_10_3
VDD_10_4

U13
W13
V12
T12

FBMA-L11-201209-221LMA30T_0805

L32
2

0.5A
VDD_33

+VDD_10
1

1
FBMA-L11-201209-221LMA30T_0805
Change from SM010014520 to SD002000080
20100816

VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49

VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSSBG_DAC

C580

180P_0402_50V8J
2

S POLY C 330U 2.5V M D2E TPE LESR9M H1.8 --->+APU_CORE(Qty : 3) Unpop:2

+APU_CORE

+APU_CORE_NB

S_A-P_CAP 390U 2.5V M 6.3X5.7 LESR10M VU--->+APU_CORE_NB(Qty : 1)

C591

0.1U_0402_16V7K
2

C592

C593

0.1U_0402_16V7K
2

C594

0.1U_0402_16V7K
2

10U_0603_6.3V6M
2

0.1U_0402_16V7K
2

C595

POWER

1
C590

10U_0603_6.3V6M
2

Power Cap. Summary


APU

S POLY C 330U 2.5V Y D2 LESR9M EEFS H1.9 --->+APU_CORE_NB(Qty : 1)


C589

ONTARIO-2M161000-1.6G_BGA413
15G@

S_A-P_CAP 390U 2.5V M 6.3X5.7 LESR10M VU --->+APU_CORE(Qty : 2)

+1.5V

N13
N20
N22
P10
P14
R4
R7
R20
T6
T9
T11
T13
U4
U5
U7
U12
U20
U22
V8
V9
V11
V13
W1
W2
W4
W5
W7
W12
W20
Y5
Y7
Y9
Y11
Y13
Y15
Y17
Y19
AA4
AA22
AB2
AB5
AB9
AB13
AB17
AB21
AC5
AC9
AC13
A11

+3VS

A4

ONTARIO-2M161000-1.6G_BGA413
15G@
C582

180P_0402_50V8J
C537

C545

POWER

10U_0603_6.3V6M

VDD_18_DAC

10U_0603_6.3V6M
C684

VDDCR_NB_1
VDDCR_NB_2
VDDCR_NB_3
VDDCR_NB_4
VDDCR_NB_5
VDDCR_NB_6
VDDCR_NB_7
VDDCR_NB_8
VDDCR_NB_9
VDDCR_NB_10
VDDCR_NB_11
VDDCR_NB_12
VDDCR_NB_13
VDDCR_NB_14
VDDCR_NB_15
VDDCR_NB_16
VDDCR_NB_17
VDDCR_NB_18
VDDCR_NB_19
VDDCR_NB_20
VDDCR_NB_21
VDDCR_NB_22

DP Phy/IO

G16
G19
E17
J16
L16
L19
N16
R16
R19
W18
U16

Change from SM010014520 to SD002000080


20100816

10U_0603_6.3V6M

C576

U22D
A7
B7
B11
B17
B22
C4
D5
D7
D9
D11
D14
B15
D17
D19
E7
E9
E12
E20
F8
F11
F13
G4
G5
G7
G9
G12
G20
G22
H6
H11
H13
J4
J5
J7
J20
K10
K14
L4
L6
L8
L11
L13
L20
L22
M7
N4
N6
N8
N11

L30

add Cap. for CRT DVT

+VDD_18_DAC

W9

DDR3

C575

2A

+1.8VS

0.15A

PCIE/IO/DDR3 Phy

+1.5V

10U_0603_6.3V6M
C574

+APU_CORE_NB

1U_0402_6.3V6K
C573

0.1U_0402_16V7K
2

10U_0603_6.3V6M

0.1U_0402_16V7K
2
2
0.1U_0402_16V7K

E8
E11
E13
F9
F12
G11
G13
H9
H12
K11
K13
L10
L12
L14
M11
M12
M13
N10
N12
N14
P11
P13

1U_0402_6.3V6K
C572

C563

10A

10U_0603_6.3V6M
C604

+APU_CORE_NB

1U_0402_6.3V6K
C567

C562

0.1U_0402_16V7K
C571

C555

180P_0402_50V8J
2

1U_0402_6.3V6K
C558

1
C554
180P_0402_50V8J
2

0.1U_0402_16V7K
C566

U8
W8
U6
U9
W6
T7
V7

0.1U_0402_16V7K
C570

C553

1U_0402_6.3V6K
2

VDD_18_1
VDD_18_2
VDD_18_3
VDD_18_4
VDD_18_5
VDD_18_6
VDD_18_7

1U_0402_6.3V6K

10U_0603_6.3V6M
2

VDDCR_CPU_1
VDDCR_CPU_2
VDDCR_CPU_3
VDDCR_CPU_4
VDDCR_CPU_5
VDDCR_CPU_6
VDDCR_CPU_7
VDDCR_CPU_8
VDDCR_CPU_9
VDDCR_CPU_10
VDDCR_CPU_11
VDDCR_CPU_12
VDDCR_CPU_13
VDDCR_CPU_14
VDDCR_CPU_15

DIS PLL

0.1U_0402_16V7K
2

10U_0603_6.3V6M
2
2
2
10U_0603_6.3V6M
10U_0603_6.3V6M

E5
E6
F5
F7
G6
G8
H5
H7
J6
J8
L7
M6
M8
N7
R8

L29
2
1
FBMA-L11-201209-221LMA30T_0805

GND

C561

C540

GPU AND NB CORE

1
C544

DAC

C560

C556

C552

1U_0402_6.3V6K
2

2
1U_0402_6.3V6K

1
C559
0.1U_0402_16V7K
2

C543

180P_0402_50V8J
C557

C551

1U_0402_6.3V6K
2

10U_0603_6.3V6M
2

C564

1
C550

C542

CPU CORE

10U_0603_6.3V6M
2
2
10U_0603_6.3V6M

180P_0402_50V8J
C565

C541

C568

180P_0402_50V8J
C569

C536

+VDD_18

0.1U_0402_16V7K
C581

1
C539

2A
TSense/PLL/DP/PCIE/IO

U22C

11A

+APU_CORE

1
C596

1U_0402_6.3V6K
2

C597

1U_0402_6.3V6K
2

C598

1U_0402_6.3V6K
2

S_A-P_CAP 390U 2.5V M 6.3X5.7 LESR10M VU --->+1.5V(Qty : 1)

+1.5V

S_A-P_CAP 390U 2.5V M 6.3X5.7 LESR10M VU --->1.05VS(Qty : 1)

+1.05VS

S_A-P_CAP 390U 2.5V M 6.3X5.7 LESR10M VU --->+1.8VS(Qty : 1)

+1.8VS

DDR3 Socket

1U_0402_6.3V6K
2

S POLY C 330U 2V M X LESR6M SX H1.9 --->1.5V(Qty : 1)

+1.5V

+1.05VS

FCH
S POLY C 330U 2.5V Y D2 LESR9M EEFS H1.9 --->1.1VS(Qty : 1) UMA unpop
1
C621 +
@
390U_2.5V_10M
2

C599

1
C600

0.1U_0402_16V7K
2

C601

0.1U_0402_16V7K
2

C602

0.1U_0402_16V7K
2

C603

180P_0402_50V8J
2

+1.1VS

GPU

180P_0402_50V8J
2

S POLY C 330U 2V M X LESR6M SX H1.9 --->VGA_CORE(Qty : 2) Unpop:1

+GPU_CORE

S_A-P_CAP 390U 2.5V M 6.3X5.7 LESR10M VU --->+VGA_CORE(Qty : 1)


S_A-P_CAP 390U 2.5V M 6.3X5.7 LESR10M VU --->+1.5VSG(Qty : 1)

+1.5V

POWER

10U_0603_6.3V6M
1
1
1
1
1
330U_D2E_2.5VM_R9M
390U_2.5V_10M
1
C605 +
C606 +
C607 +
C1104+
C1105+
C616
@
@
@
330U_D2E_2.5VM_R9M
330U_D2E_2.5VM_R9M
390U_2.5V_10M
2
2
2
2
2
2

C101
0.1U_0402_16V7K

C102
0.1U_0402_16V7K

USB

C103
180P_0402_50V8J

By case (Along split)

C617 +
390U_2.5V_10M
2

C622 +

C618 +

C619

330U_D2_2.5VY_R9M
2

10U_0603_6.3V6M
2
2
390U_2.5V_10M
2
10U_0603_6.3V6M

390U_2.5V_10M
2

C625
@
10U_0603_6.3V6M
2

C615

C614

C613

10U_0603_6.3V6M
2

Near CPU Socket

Near CPU Socket

Compal Secret Data

Security Classification

Near CPU Socket

Issued Date

2010/08/20

Deciphered Date

2011/08/20

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

(390uF_2.5V_6.3x5.7_ESR10m)*1=(SF000002O00)

Title

Compal Electronics, Inc.


P07-FT1 PWR/VSS

Size
C
Date:

C612

C611

C610

180P_0402_50V8J

C624 +

180P_0402_50V8J

C685

180P_0402_50V8J

C623

0.1U_0402_16V7K

1
1

C609

0.1U_0402_16V7K

POWER
C608

+1.8VS

change 0603 for DVT

0.1U_0402_16V7K

POWER

+1.5V

Near CPU Socket


1

+USB_VCCA

C104
180P_0402_50V8J

+1.5V

+APU_CORE_NB

+1.5VSG

S_A-P_CAP 220U 6.3V M C45 R17M SVPE H4.4 --->+USB_VCCA(Qty : 1)


2

0.1U_0402_16V7K

+APU_CORE

180PF Qt'y follow the distance between


CPU socket and DIMM0. <2.5inch>

180P_0402_50V8J

1
C620
@
10U_0603_6.3V6M
2

Document Number

Rev
1.0

LA-7092P P5WE6/H6/S6
Monday, November 15, 2010

Sheet
1

of

47

+1.5V

+1.5V
JDIMM1

DDR_A_D8
DDR_A_D9
<6,9> DDR_A_DQS#1
<6,9> DDR_A_DQS1
DDR_A_D10
DDR_A_D11
DDR_A_D16
DDR_A_D17
<6,9> DDR_A_DQS#2
<6,9> DDR_A_DQS2
DDR_A_D18
DDR_A_D19
DDR_A_D24
DDR_A_D25
DDR_A_DM3
DDR_A_D26
DDR_A_D27

DDR_A_D[0..63]

DDR_A_MA[0..15]

DDR_A_DQS#0 <6,9>
DDR_A_DQS0 <6,9>

+1.5V

<6,9>
2

DDR_A_D[0..63]

DDR_A_MA[0..15] <6,9>

DDR_A_DM[0..7]

R145
1K_0402_1%

DDR_A_DM[0..7] <6,9>

DDR_A_D6
DDR_A_D7

R146
1K_0402_1%

15mil

15mil
1

DDR_A_D2
DDR_A_D3

+1.5V

DDR_A_D4
DDR_A_D5

+VREF_DQ

DDR_A_D12
DDR_A_D13

+VREF_CA

1000P_0402_50V7K
2

VSS1
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
RESET#
VSS12
DQ14
DQ15
VSS14
DQ20
DQ21
VSS16
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS#3
DQS3
VSS24
DQ30
DQ31
VSS26

DDR_A_DM1

R147
1K_0402_1%

DDR_RST# <6,9>
DDR_A_D14
DDR_A_D15

R148
1K_0402_1%
1

DDR_A_DM0
0.1U_0402_16V4Z
2

VREF_DQ
VSS2
DQ0
DQ1
VSS4
DM0
VSS5
DQ2
DQ3
VSS7
DQ8
DQ9
VSS9
DQS#1
DQS1
VSS11
DQ10
DQ11
VSS13
DQ16
DQ17
VSS15
DQS#2
DQS2
VSS18
DQ18
DQ19
VSS20
DQ24
DQ25
VSS22
DM3
VSS23
DQ26
DQ27
VSS25

DDR_A_D0
DDR_A_D1

1
C627

1
C626

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

+VREF_DQ

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71

DDR_A_D20
DDR_A_D21
DDR_A_DM2
DDR_A_D22
DDR_A_D23
DDR_A_D28
DDR_A_D29
DDR_A_DQS#3 <6,9>
DDR_A_DQS3 <6,9>
DDR_A_D30
DDR_A_D31

+1.5V
<6,9> DDR_CKE0

<6,9> DDR_A_BS2
DDR_A_MA12
DDR_A_MA9
DDR_A_MA8
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1
<6> DDR_A_CLK0
<6> DDR_A_CLK#0
DDR_A_MA10
<6,9> DDR_A_BS0
<6,9> DDR_A_WE#
<6,9> DDR_A_CAS#
DDR_A_MA13
<6> DDR_CS1_DIMMA#

DDR_A_D32
DDR_A_D33
B

<6,9> DDR_A_DQS#4
<6,9> DDR_A_DQS4
DDR_A_D34
DDR_A_D35
DDR_A_D40
DDR_A_D41
DDR_A_DM5
DDR_A_D42
DDR_A_D43
DDR_A_D48
DDR_A_D49
<6,9> DDR_A_DQS#6
<6,9> DDR_A_DQS6
DDR_A_D50
DDR_A_D51
DDR_A_D56
DDR_A_D57
DDR_A_DM7
DDR_A_D58
DDR_A_D59

+3VS
1
C646

1
C647

1
2
R150 10K_0402_5%

R151
0.1U_0402_16V4Z
2

10K_0402_5%
2

2.2U_0603_6.3V4Z
2

73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203

CKE0
VDD1
NC1
BA2
VDD3
A12/BC#
A9
VDD5
A8
A5
VDD7
A3
A1
VDD9
CK0
CK0#
VDD11
A10/AP
BA0
VDD13
WE#
CAS#
VDD15
A13
S1#
VDD17
NCTEST
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
VDDSPD
SA1
VTT1

205

G1

CKE1
VDD2
A15
A14
VDD4
A11
A7
VDD6
A6
A4
VDD8
A2
A0
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
S0#
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

G2

206

FOX_AS0A626-U8SN-7F
CONN@

DDR_CKE1 <6,9>
DDR_A_MA15
DDR_A_MA14

0.1U_0402_16V4Z
2
C628

DDR_A_MA11
DDR_A_MA7

1
0.1U_0402_16V4Z

C629
1

0.1U_0402_16V4Z
2
C630

C631

1
0.1U_0402_16V4Z

0.1U_0402_16V4Z
2

C632

1
0.1U_0402_16V4Z

C633
1

0.1U_0402_16V4Z
2

C634

1
0.1U_0402_16V4Z

C635
1

C636

C637

1
0.1U_0402_16V4Z

0.1U_0402_16V4Z
2
C638

1
0.1U_0402_16V4Z

C110
1

DDR_A_MA6
DDR_A_MA4
DDR_A_MA2
DDR_A_MA0
DDR_A_CLK1 <6>
DDR_A_CLK#1 <6>
DDR_A_BS1 <6,9>
DDR_A_RAS# <6,9>

CRB 0.1u X1

DDR_CS0_DIMMA# <6>
DDR_A_ODT0 <6>
DDR_A_ODT1 <6>

4.7u X1

CRB

DDR_A_D36
DDR_A_D37

1
C645

X2

+1.5V
2
2
C640
C641
@
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1

1
C644

DDR_A_DM4
DDR_A_D38
DDR_A_D39

100U

+0.75VS
+VREF_CA

1000P_0402_50V7K 0.1U_0402_16V4Z
2
2

1
C642

1
+

4.7U_0603_6.3V6K
2

C1102
330U_D2E_2.5VM_R9M

DDR_A_D44
DDR_A_D45
DDR_A_DQS#5 <6,9>
DDR_A_DQS5 <6,9>

330U ESR:9m H:2


P/N:SGA20331E10

Place near JDIMM1

DDR_A_D46
DDR_A_D47
DDR_A_D52
DDR_A_D53
DDR_A_DM6
DDR_A_D54
DDR_A_D55

EMI For DVT 10/20

DDR_A_D60
DDR_A_D61

+1.5V
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
2
2
2

DDR_A_DQS#7 <6,9>
DDR_A_DQS7 <6,9>
DDR_A_D62
DDR_A_D63

C643
1

C675
1

C676
1

C678
1

DDR_EVENT# <6,9>
FCH_SMDAT0 <9,14,29>
FCH_SMCLK0 <9,14,29>
+0.75VS

DDR3 SO-DIMM A H:8mm


Standard Type
P/N:SP07000HA00
F/P:FOX_AS0A626-U8SN-7F_204P

Compal Secret Data

Security Classification
Issued Date

2010/08/20

2011/08/20

Deciphered Date

Title

Compal Electronics, Inc.


DDR3 SODIMM-I Socket

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
1.0

LA-7092P P5WE6/H6/S6

Date:

0.1U_0402_16V4Z
2

Wednesday, November 24, 2010


1

Sheet

of

47

+1.5V

+1.5V
JDIMM2
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71

+VREF_DQ
1
C680

DDR_A_D0
DDR_A_D1

1
C681

DDR_A_DM0
1000P_0402_50V7K
2
DDR_A_D2
DDR_A_D3

0.1U_0402_16V4Z
2
D

DDR_A_D8
DDR_A_D9
<6,8> DDR_A_DQS#1
<6,8> DDR_A_DQS1
DDR_A_D10
DDR_A_D11
DDR_A_D16
DDR_A_D17
<6,8> DDR_A_DQS#2
<6,8> DDR_A_DQS2
DDR_A_D18
DDR_A_D19
DDR_A_D24
DDR_A_D25
DDR_A_DM3
DDR_A_D26
DDR_A_D27

VREF_DQ
VSS2
DQ0
DQ1
VSS4
DM0
VSS5
DQ2
DQ3
VSS7
DQ8
DQ9
VSS9
DQS#1
DQS1
VSS11
DQ10
DQ11
VSS13
DQ16
DQ17
VSS15
DQS#2
DQS2
VSS18
DQ18
DQ19
VSS20
DQ24
DQ25
VSS22
DM3
VSS23
DQ26
DQ27
VSS25

VSS1
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
RESET#
VSS12
DQ14
DQ15
VSS14
DQ20
DQ21
VSS16
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS#3
DQS3
VSS24
DQ30
DQ31
VSS26

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

DDR_A_D4
DDR_A_D5
DDR_A_DQS#0 <6,8>
DDR_A_DQS0 <6,8>

DDR_A_D[0..63]

73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203

<6,8> DDR_CKE0
<6,8> DDR_A_BS2
DDR_A_MA12
DDR_A_MA9
DDR_A_MA8
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1
<6> DDR_B_CLK2
<6> DDR_B_CLK#2
DDR_A_MA10
<6,8> DDR_A_BS0
<6,8> DDR_A_WE#
<6,8> DDR_A_CAS#
DDR_A_MA13
<6> DDR_CS1_DIMMB#

DDR_A_D32
DDR_A_D33
<6,8> DDR_A_DQS#4
<6,8> DDR_A_DQS4

DDR_A_D34
DDR_A_D35
DDR_A_D40
DDR_A_D41
DDR_A_DM5
DDR_A_D42
DDR_A_D43
DDR_A_D48
DDR_A_D49
<6,8> DDR_A_DQS#6
<6,8> DDR_A_DQS6
DDR_A_D50
DDR_A_D51
DDR_A_D56
DDR_A_D57
DDR_A_DM7
For DRAM strap pin reservation
20100817
R961 1
R153 1

DDR_A_D58
DDR_A_D59

2 10K_0402_5%
2 10K_0402_5%

+3VS
A

1
1
C667
2

R154
10K_0402_5%

0.1U_0402_16V4Z
2
2

2.2U_0603_6.3V4Z

1
C668

DDR_A_DM[0..7]

only one 4.7k

G1

CKE1
VDD2
A15
A14
VDD4
A11
A7
VDD6
A6
A4
VDD8
A2
A0
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
S0#
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2
G2

DDR_A_DM[0..7] <6,8>

DDR_A_DM1
DDR_RST# <6,8>
DDR_A_D14
DDR_A_D15
DDR_A_D20
DDR_A_D21
DDR_A_DM2
DDR_A_D22
DDR_A_D23
DDR_A_D28
DDR_A_D29
DDR_A_DQS#3 <6,8>
DDR_A_DQS3 <6,8>

+1.5V

DDR_A_D30
DDR_A_D31
2

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

0.1U_0402_16V4Z
2

1
0.1U_0402_16V4Z

DDR_CKE1 <6,8>

C45
1

0.1U_0402_16V4Z
2
2

2
C652

C653

1
1
0.1U_0402_16V4Z

0.1U_0402_16V4Z
2
2
C654

C655

1
0.1U_0402_16V4Z

0.1U_0402_16V4Z
2
2
C682

1
1
0.1U_0402_16V4Z

C46

C683

C47

1
0.1U_0402_16V4Z

2
C48

1
0.1U_0402_16V4Z

C49
0.1U_0402_16V4Z
C

DDR_A_MA11
DDR_A_MA7
DDR_A_MA6
DDR_A_MA4

CRB 0.1u X1

4,7uX1

DDR_A_MA2
DDR_A_MA0
+0.75VS
DDR_B_CLK3 <6>
DDR_B_CLK#3 <6>

2
C50
@
0.1U_0402_16V4Z
1

DDR_A_BS1 <6,8>
DDR_A_RAS# <6,8>
DDR_CS0_DIMMB# <6>
DDR_B_ODT0 <6>

C51

1
C664

0.1U_0402_16V4Z 4.7U_0603_6.3V6K
1
2

DDR_B_ODT1 <6>
+VREF_CA
DDR_A_D36
DDR_A_D37

1
C665

Place near JDIMM2

1
C666

DDR_A_DM4
DDR_A_D38
DDR_A_D39

0.1U_0402_16V4Z
2

1000P_0402_50V7K
2

DDR_A_D44
DDR_A_D45
DDR_A_DQS#5 <6,8>
DDR_A_DQS5 <6,8>
DDR_A_D46
DDR_A_D47
DDR_A_D52
DDR_A_D53
DDR_A_DM6
DDR_A_D54
DDR_A_D55
DDR_A_D60
DDR_A_D61
DDR_A_DQS#7 <6,8>
DDR_A_DQS7 <6,8>
DDR_A_D62
DDR_A_D63
DDR_EVENT# <6,8>
FCH_SMDAT0 <8,14,29>
FCH_SMCLK0 <8,14,29>

+0.75VS

206

FOX_AS0A626-U4SN-7F
CONN@

R962
10K_0402_5%

Compal Secret Data

Security Classification

DDR3 SO-DIMM B H:4mm


Standard Type
P/N:SP07000H800
F/P:FOX_AS0A626-U4SN-7F_204P

For DRAM strap pin reservation


20100817

2010/08/20

Issued Date

2011/08/20

Deciphered Date

Title

Compal Electronics, Inc.


DDR3 SODIMM-II Socket

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
1.0

LA-7092P P5WE6/H6/S6

Date:

0.1U_0402_16V4Z
2
2

DDR_A_MA15
DDR_A_MA14

CRB

205

CKE0
VDD1
NC1
BA2
VDD3
A12/BC#
A9
VDD5
A8
A5
VDD7
A3
A1
VDD9
CK0
CK0#
VDD11
A10/AP
BA0
VDD13
WE#
CAS#
VDD15
A13
S1#
VDD17
NCTEST
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
VDDSPD
SA1
VTT1

<6,8>

DDR_A_MA[0..15] <6,8>

DDR_A_D12
DDR_A_D13

C44
C

DDR_A_D[0..63]

DDR_A_MA[0..15]

DDR_A_D6
DDR_A_D7

Wednesday, November 24, 2010

Sheet
1

of

47

LCD/LED PANEL Conn.

LCD POWER CIRCUIT

JLVDS1
41
42
43
44
45
46

+LCDVDD
+3VS

+3VALW
1

For LCD flash


Change as 10k ohm

R396
300_0603_5%

W=60mils
1

R393
10K_0402_5%

C669
4.7U_0603_6.3V6K

Change 0603 size


For DVT

Q81
SSM3K7002F_SC59-3

2
G

R397
1K_0402_5%
2
1

1 UMA@ 2 LCDVDD_ON
R963 0_0402_5%

W=60mils

C1005
4.7U_0603_6.3V6K

R395

<NCQD0 use>

C1006
0.1U_0402_16V4Z

Change 0603 size


For DVT

100K_0402_5%

+LCDVDD

Q83
SSM3K7002F_SC59-3

1 DISO@ 2
R964 0_0402_5%

<18> VGA_ENVDD

2
G
3

<5> APU_ENVDD

C670
0.047U_0402_16V7K

AO3413L_SOT23-3
Q82
1

2
D

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

G1
G2
G3
G4
G5
G6

SM010014520 3000ma
220ohm@100mhz
DCR 0.04

W=60mils

<5> APU_ENBKL

R156 1 UMA@ 2

0_0402_5%

B+
2
L113
1.2UH_1127AS-1R2N_2.4A_30%
R419 1
@
2 0_0805_5%

ENBKL <31>

R426 1

1
R157

2
100K_0402_1%
+3VS

2 0_0805_5%

C674
68P_0402_50V8J

EMI request for MP

1
R484
C1007 2

1 220P_0402_50V7K INVT_PWM

C679 2

1 220P_0402_50V7K DISPOFF#

2
1
10K_0402_5% R485

INVT_PWM
DISPOFF#
I2CC_SCL
I2CC_SDA

@
2
+LCDVDD R841

1
0_0603_5%

+LCDVDD
D

W=60mils

+3VS

DAC_BRIG <31>

TXOUT0TXOUT0+
TXOUT1TXOUT1+
TXOUT2TXOUT2+
TXCLKTXCLK+

R862 2

1 0_0402_5%

LOCAL_DIM <31>

R860 2

1 0_0402_5%

COLOY_ENG_EN <31>

+3VS
USB20_N5 <14>
USB20_P5 <14>

D15 @
6
+LCDVDD

Place closed to JLVDS1

2
0_0402_5%

<31> BKOFF#

+LCDVDD_L

@
R483
10K_0402_5%

+3VS

1 220P_0402_50V7K DAC_BRIG

C677 2

+INVPWR_B+

IPEX_20143-040E-20F
CONN@

C673
680P_0402_50V7K

+INVPWR_B+
L2
FBMA-L11-201209-221LMA30T_0805
2
1
L1
FBMA-L11-201209-221LMA30T_0805
2
1

0_0402_5%

<19> VGA_ENBKL

R1097 1 DISO@ 2

W=60mils

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

DISPOFF#

C671

10U_0603_6.3V6M

CH2

Vp

Vn

USB20_N5

C672
USB20_P5

RB751V_SOD323
D4 @

CH3

0.1U_0402_16V4Z

CH4

CH1

CM1293-04SO_SOT23-6

Change P/N as SC300000B00

Change 0603 size


For DVT

VGA ONLY
2
1

3
4

2
1

3
4

2
1

3
4

2
1

3
4

VGA_TXCLK+
VGA_TXCLK0_0404_4P2R_5%
VGA_TXOUT2+
VGA_TXOUT20_0404_4P2R_5%
VGA_TXOUT1+
VGA_TXOUT10_0404_4P2R_5%
VGA_TXOUT0+
VGA_TXOUT00_0404_4P2R_5%

DISO@RP2
DISO@
RP2
TXOUT2+
TXOUT2DISO@RP4
DISO@
RP4
TXOUT1+
TXOUT1DISO@RP6
DISO@
RP6
TXOUT0+
TXOUT0DISO@RP8
DISO@
RP8
I2CC_SCL
I2CC_SDA

0_0402_5% 2 DISO@ 1 R270


0_0402_5% 2
1 R272
DISO@

VGA_LCD_CLK
VGA_LCD_DAT

VGA_TXCLK+ <18>
VGA_TXCLK- <18>
VGA_TXOUT2+ <18>
VGA_TXOUT2- <18>

<5> APU_BLPWM

VGA_TXOUT1+ <18>
VGA_TXOUT1- <18>

<31> EC_INVT_PWM
<18> VGA_INVT_PWM

VGA_TXOUT0+ <18>
VGA_TXOUT0- <18>

INVT_PWM

1
2
R1098 UMA@ 0_0402_5%
1
2
R158 DISO@ 0_0402_5%
1
2
R1099
@
0_0402_5%

TXCLK+
TXCLK-

R1100
100K_0402_5%
2

VGA_LCD_CLK <19>
VGA_LCD_DAT <19>

UMA ONLY
TXCLK+
TXCLK-

1
2

4
3

1
2

4
3

1
2

4
3

1
2

4
3

UMA@RP1
UMA@
RP1
TXOUT2+
TXOUT2UMA@RP3
UMA@
RP3
TXOUT1+
TXOUT1UMA@RP5
UMA@
RP5
TXOUT0+
TXOUT0UMA@RP7
UMA@
RP7

I2CC_SCL
I2CC_SDA

APU_TXCLK+
APU_TXCLK0_0404_4P2R_5%
APU_TXOUT2+
APU_TXOUT20_0404_4P2R_5%
APU_TXOUT1+
APU_TXOUT10_0404_4P2R_5%
APU_TXOUT0+
APU_TXOUT00_0404_4P2R_5%

0_0402_5% 2 UMA@ 1 R269


0_0402_5% 2
1 R271
UMA@

APU_LCD_CLK
APU_LCD_DATA

APU_TXCLK+ <5>
APU_TXCLK- <5>
APU_TXOUT2+ <5>
APU_TXOUT2- <5>
APU_TXOUT1+ <5>
APU_TXOUT1- <5>
APU_TXOUT0+ <5>
APU_TXOUT0- <5>
A

APU_LCD_CLK <5>
APU_LCD_DATA <5>

Compal Secret Data

Security Classification
2010/08/20

Issued Date

2011/08/20

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Compal Electronics, Inc.


LVDS/CAMERA
Document Number

Rev
1.0

LA-7092P P5WE6/H6/S6
Wednesday, November 24, 2010

Sheet
1

10

of

47

@ R521
0_0603_5%
1
2

+3VS

W=40mils

HDMI connector

+HDMI_5V_OUT
1

C690
0.1U_0402_16V4Z

HDMI_SCLK
HDMI_R_D0+
HDMI_R_D1-

HDMI_R_D1+
HDMI_R_D2-

HDMI_SDATA

HDMI_R_D2+

Q128
BSH111 1N_SOT23-3
@

1
0_0402_5%

@
2
R816

1
0_0402_5%

2
R172

HDMI_SDATA
HDMI_SCLK

HDMI_R_CK+
HDMI_R_D0-

Q86
BSH111 1N_SOT23-3

19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

+HDMI_5V_OUT

HDMI_R_CK-

JHDMI1
HDMI_HPD

1.1A_6V_SMD1812P110TF

Change P/N SCS00002000

R161
2K_0402_5%

1 +HDMI_5V

R973 2 DISO@ 1 0_0402_5%

<19> VGA_HDMI_SDATA

R522

R972 2

<5> APU_HDMI_DATA

F2

CH491DPT_SOT23-3
2K_0402_5%

0_0402_5%
1

UMA@
1 0_0402_5%

+5VS

R965

R971 2 DISO@ 1 0_0402_5%

<19> VGA_HDMI_SCLK

UMA@
1 0_0402_5%

D7

+HDMI_5V_OUT

R970 2

<5> APU_HDMI_CLK

R968

4.7K_0402_5%

R966

4.7K_0402_5%

+3VS

SM070001310 400ma 90ohm@100mhz DCR 0.3


R514 1

1
L68
WCM-2012-900T_0805
@
4
C

HDMI_C_TX0-

R516 1

2
1 1
1
1
1
1
1
1
1
1

UMA@2
UMA@2
UMA@2
UMA@2
UMA@2
UMA@2
UMA@2
UMA@2

0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%

HDMI_C_TX2-_R
HDMI_C_TX2+_R
HDMI_C_TX1-_R
HDMI_C_TX1+_R
HDMI_C_TX0-_R
HDMI_C_TX0+_R
HDMI_C_CLK-_R
HDMI_C_CLK+_R

2 DISO@ 1
R977
0_0402_5%

<5> APU_HDMI_HPD

2 UMA@ 1
R981
0_0402_5%

2
150K_0402_5%

HDMI_C_TX1-

R518 1

E
Q34
MMBT3904_NL_SOT23-3

0_0402_5%

HDMI_R_D0-

2
3
0_0402_5%

HDMI_R_D0+

0_0402_5%

HDMI_R_D1-

2
3

R517 1

0_0402_5%

HDMI_R_D1+

HDMI_C_TX2-

R520 1

0_0402_5%

HDMI_R_D2-

1
L70
WCM-2012-900T_0805
@
4

R528
365K_0402_1%
@

HDMI_C_TX1+

HDMI_HPD

R984
R985
R986
R987
R988
R989
R990
R991

<19> VGA_HDMI_DET

3
2

HDMI_R_CK+

HDMI_C_TX2+

R519 1

2
3
HDMI_R_D2+

0_0402_5%

APU_HDMI_TX2N
APU_HDMI_TX2P
APU_HDMI_TX1N
APU_HDMI_TX1P
APU_HDMI_TX0N
APU_HDMI_TX0P
APU_HDMI_CLKN
APU_HDMI_CLKP

HDMI_C_TX2-_R
HDMI_C_TX2+_R
HDMI_C_TX1-_R
HDMI_C_TX1+_R
HDMI_C_TX0-_R
HDMI_C_TX0+_R
HDMI_C_CLK-_R
HDMI_C_CLK+_R

From APU

<5>
<5>
<5>
<5>
<5>
<5>
<5>
<5>

0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%

From VGA

DISO@2
DISO@2
DISO@2
DISO@2
DISO@2
DISO@2
DISO@2
DISO@2

3
0_0402_5%

R530
10K_0402_5%
2

1
1
1
1
1
1
1
1

1
R525

R515 1

2
B

HDMI_C_TX0+

1
L54
WCM-2012-900T_0805
@
4
R527
0_0402_5%

Use common via on related pair

0_0402_5%
@

+3VS

4
2

L69
WCM-2012-900T_0805
@
4
R524

R513 1

HDMI_R_CK-

0_0402_5%

HDMI_C_CLK+

R974
R975
R976
R978
R979
R980
R982
R983

<NAV70 use>

HDMI_C_CLK-

VGA_HDMI_TXD2VGA_HDMI_TXD2+
VGA_HDMI_TXD1VGA_HDMI_TXD1+
VGA_HDMI_TXD0VGA_HDMI_TXD0+
VGA_HDMI_TXCVGA_HDMI_TXC+

20
21
22
23

SUYIN_100042MR019S153ZL
CONN@

Place closed to JHDMI1

<19>
<19>
<19>
<19>
<19>
<19>
<19>
<19>

HP_DET
+5V
DDC/CEC_GND
SDA
SCL
Reserved
CEC
CKGND
CK_shield GND
CK+
GND
D0GND
D0_shield
D0+
D1D1_shield
D1+
D2D2_shield
D2+

1 0.1U_0402_16V7K HDMI_C_TX2- R509 1


1 0.1U_0402_16V7K HDMI_C_TX2+ R508 1

2
2

499_0402_1%
499_0402_1%

HDMI_C_TX1-_R
HDMI_C_TX1+_R

C510
C511

2
2

1 0.1U_0402_16V7K HDMI_C_TX1- R506 1


1 0.1U_0402_16V7K HDMI_C_TX1+ R505 1

2
2

499_0402_1%
499_0402_1%

HDMI_C_TX0-_R
HDMI_C_TX0+_R

C512
C513

2
2

1 0.1U_0402_16V7K HDMI_C_TX0- R503 1


1 0.1U_0402_16V7K HDMI_C_TX0+ R502 1

2
2

499_0402_1%
499_0402_1%

HDMI_C_CLK-_R
HDMI_C_CLK+_R

C514
C515

2
2

1 0.1U_0402_16V7K HDMI_C_CLK- R501 1


1 0.1U_0402_16V7K HDMI_C_CLK+ R500 1

2
2

499_0402_1%
499_0402_1%

2
G

+HDMI_5V_OUT
R512

2
2

C508
C509

2N7002_SOT23
Q87

2010/08/20

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

100K_0402_5%

2011/08/20

Deciphered Date

Title

HDMI_C_TX2-_R
HDMI_C_TX2+_R

Place closed to JHDMI1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

HDMI Connector
Rev
1.0

LA-7092P P5WE6/H6/S6

Date:

Sheet

Wednesday, November 24, 2010


1

11

of

47

W=40mils
D14

D33
PJDLC05C_SOT23-3
@

CRT_R

L57 1

2 FCM2012CF-800T06_2P

CRT_B

L59 1

2 FCM2012CF-800T06_2P

CRT_B_1

C694

10P_0402_50V8J

10P_0402_50V8J

C693

10P_0402_50V8J

C692

150_0402_1%

R533

150_0402_1%

R532

R531

150_0402_1%

CRT_G_1

2 FCM2012CF-800T06_2P

L58 1

C697

C695

2
10P_0402_50V8J

CH491DPT_SOT23-3 1.1A_6VDC_FUSE
1

Change P/N SCS00002000

C691
0.1U_0402_16V4Z

CRT_R_1

CRT_G

W=40mils

D32
PJDLC05C_SOT23-3
@

+CRT_VCC

F1

+R_CRT_VCC

CRT Connector

+5VS

C696

JCRT1

6
11
1
7
12
2
8
13
3
9
14
4
10
15
5

T95PAD

2
10P_0402_50V8J
10P_0402_50V8J

T97PAD

C698

G
G

C-H_13-12201513CP
CONN@

100P_0402_50V8J

+CRT_VCC
C699 1

2 0.1U_0402_16V4Z

R537 2

L60 1
2
FCM2012CF-800T06_2P

1 10K_0402_5%

16
17

P/N : DC060003V00
F/P : SUYIN_070546HR015M21MZR_15P-T

CRT_HSYNC_2
DSUB_12

CRT_HSYNC_1

C700
10P_0402_50V8J

CRT_HSYNC

L81 1
2
FCM2012CF-800T06_2P

U23

OE#

CRT_VSYNC_2
1

C702
10P_0402_50V8J

C703 2
68P_0402_50V8J

74AHCT1G125GW _SOT353-5

DSUB_15

1
C704
68P_0402_50V8J

+CRT_VCC

P
2

U19

CRT_VSYNC_1

CRT_VSYNC

2 0.1U_0402_16V4Z

OE#

C701 1

74AHCT1G125GW _SOT353-5

Close to Conn side


+CRT_VCC
3

<5> APU_CRT_DDC_SCL

<19> VGA_CRT_R
<19> VGA_CRT_G
4

From VGA

<19> VGA_CRT_B
<19> VGA_CRT_HSYNC
<19> VGA_CRT_VSYNC
<19> VGA_CRT_DATA
<19> VGA_CRT_CLK

R998 2 UMA@ 1 0_0402_5% CRT_HSYNC

APU_CRT_VSYNC

R999 2 UMA@ 1 0_0402_5% CRT_VSYNC

APU_CRT_DDC_SDA

R1000 2 UMA@ 1 0_0402_5%

CRT_DATA

APU_CRT_DDC_SCL

R1001 2 UMA@ 1 0_0402_5%

CRT_CLK

DSUB_12

VGA_CRT_R

R1002 2 DISO@ 1 0_0402_5%

CRT_R

VGA_CRT_G

R1003 2 DISO@ 1 0_0402_5%

CRT_G

VGA_CRT_B

R1004 2 DISO@ 1 0_0402_5%

CRT_B

VGA_CRT_HSYNC

R1005 2 DISO@ 1 0_0402_5% CRT_HSYNC

VGA_CRT_VSYNC

R1006 2 DISO@ 1 0_0402_5% CRT_VSYNC

VGA_CRT_DATA

R1007 2 DISO@ 1 0_0402_5%

CRT_DATA

VGA_CRT_CLK

R1008 2 DISO@ 1 0_0402_5%

CRT_CLK

DSUB_15

CRT_CLK

Q129
BSH111 1N_SOT23-3
@
2
R1009

1
0_0402_5%

@
2
R1010

1
0_0402_5%
4

Compal Secret Data

Security Classification
2010/08/20

Issued Date

Deciphered Date

2011/08/20

Title

Compal Electronics, Inc.


CRT Connector

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

CRT_DATA

Q89
BSH111 1N_SOT23-3

2
G

CRT_B

APU_CRT_HSYNC

2
G

CRT_G

R997 2 UMA@ 1 0_0402_5%

<5> APU_CRT_VSYNC
<5> APU_CRT_DDC_SDA

R996 2 UMA@ 1 0_0402_5%

APU_CRT_B

R548
4.7K_0402_5%

<5> APU_CRT_HSYNC

APU_CRT_G

R549
4.7K_0402_5%

From APU

CRT_R

<5> APU_CRT_B

R995 2 UMA@ 1 0_0402_5%

<5> APU_CRT_G

APU_CRT_R

<5> APU_CRT_R

Use common via on related pair

+3VS

Size
Document Number
Custom

Rev
1.0

LA-7092P P5WE6/H6/S6

Date:

W ednesday, November 24, 2010

Sheet
E

12

of

47

For PCIE device reset on FS1 (GFX,GLAN,WLAN,LVDS Travis)

For DVT 1011

U31E

APU_CLKP_R
APU_CLKN_R

V21
T21

<18> CLK_PCIE_VGA
<18> CLK_PCIE_VGA#

R569 1
R570 1

2 0_0402_5%
2 0_0402_5%

CLK_PCIE_VGA_R
CLK_PCIE_VGA#_R

V23
T23

<26> CLK_PCIE_LAN
<26> CLK_PCIE_LAN#

R571 1
R572 1

2 0_0402_5%
2 0_0402_5%

CLK_PCIE_LAN_R
CLK_PCIE_LAN#_R

L29
L28

R573 1
R574 1

2 0_0402_5%
2 0_0402_5%

CLK_PCIE_MINI1_R
CLK_PCIE_MINI1#_R

T26
T27
<5> APU_CLKP
<5> APU_CLKN

LAN

<29> CLK_PCIE_MINI1
<29> CLK_PCIE_MINI1#

WLAN

N29
N28
M29
M28

L24
L23

RTC_32KHI

22P_0402_50V8J

GPP_CLK5P
GPP_CLK5N
GPP_CLK6P
GPP_CLK6N

N26
N27

GPP_CLK7P
GPP_CLK7N

25M_CLK_X1

L26

25M_CLK_X2

L27

R563
20M_0603_5%
2

C65

OSC

NC

OSC

NC

5
G

1
2

<17>
<17>
<17>
<17>
<17>

PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27

APU_PWRGD

H_PWRGD_L <44>

FDV301N_NL_SOT23-3
Q90

+3VALW

@
U33
2 B

VGA_PWRGD

<24,43> VGA_PWRGD

@
C1199
1
2
0.1U_0402_16V4Z
@
1
R830

Y
A

GPP_CLK8P
GPP_CLK8N

ALLOW_LDTSTP/DMA_ACTIVE_L
PROCHOT_L
LDT_PG
LDT_STP_L
LDT_RST_L

PE_GPIO0 <18>
PE_GPIO1 <24,35>
1
R99

@
1
2
R838
100K_0402_5%
1
R839

2
0_0402_5%

For DVT 1011

2
10K_0402_5%
VGA_PWRGD_R

RTC BATT Conn.


R853 1
R575 1

2 0_0402_5%
2 22_0402_5%

LPC_CLK0 <17>
LPC_CLK0_EC <31>

CONN@
JBATT2

SERIRQ <31>

SUYIN_060003HA002G202ZL

P/N: SP07000OU00
F/P: SUYIN_060003HA002G202ZL_2P

ALLOW_STOP# <5>
FCH_PROCHOT# <5>
APU_PWRGD <5>

+RTCBATT

APU_RST# <5>

25M_X1

25M_X2

32K_X1

C1

RTC_32KHI

32K_X2

C2

RTC_32KHO

RTCCLK
INTRUDER_ALERT_L
VDDBT_RTC_G

R179
1K_0402_5%
+RTCVCC

D2
B2
B1

2
1
R864

C1272 1

W=20mils

1 C1271

2
510_0402_5%

R865

C1270

for Clear CMOS

0_0603_5%

Compal Secret Data

Security Classification
2010/08/20

Issued Date

D23

RTC_CLK <17,31>

Deciphered Date

2011/08/20

Title

+CHGRTC

DAN202UT106_SC70-3
4

Compal Electronics, Inc.


FCH PCIE/PCI/ACPI/LPC/RTC

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
1.0

LA-7092P P5WE6/H6/S6

Date:

LPC_CLK1 <17>
LPC_AD0 <31>
LPC_AD1 <31>
LPC_AD2 <31>
LPC_AD3 <31>
LPC_FRAME# <31>

14M_25M_48M_OSC

22P_0402_50V8J

VGA_PWRGD_R

2
0_0402_5%

NC7SZ08P5X_NL_SC70-5

G21
H21
K19
G22
J24

FCH : SA000046H70 (S IC 218-0792006 A13 HUDSON-M1 FCBGA 605P)

RTC_32KHO

+3VS

R164
10K_0402_5%

H24
H25
J27
J26
H29
H28
G28
J25
AA18
AB19

FCH : SA000046H60 (S IC 218-0792001 A12 HUDSON-M1 FCBGA 605P)

PLT_RST# <18,26,29>
2 PCIE_RST#
0_0402_5%

+RTCBATT

21807-A11-HUDSON-M1_FCBGA605

32.768KHZ_12.5PF_Q13MC14610050_10PPM

@
2

+1.8VS

AJ6
AG6
AG4
AJ4

FCH : SA000046HA0 R1

Y4

GPP_CLK4P
GPP_CLK4N

LPCCLK0
LPCCLK1
LAD0
LAD1
LAD2
LAD3
LFRAME_L
LDRQ0_L
LDRQ1_L/CLK_REQ6_L/GPIO49
SERIRQ/GPIO48

Close to FCH
C64

GPP_CLK3P
GPP_CLK3N

Y3

1M_0603_5%
R576

25MHZ_20PF_7A25000012

GPP_CLK2P
GPP_CLK2N

INTE_L/GPIO32
INTF_L/GPIO33
INTG_L/GPIO34
INTH_L/GPIO35

RTC

C67
27P_0402_50V8J
1
2

GPP_CLK1P
GPP_CLK1N

P29
P28

L25

<29> CLK_SD_48M

C66
27P_0402_50V8J

GPP_CLK0P
GPP_CLK0N

CPU

SLT_GFX_CLKP
SLT_GFX_CLKN

P25
M25

T29
T28

Follow result by vender 10/11

CPU_HT_CLKP
CPU_HT_CLKN

LPC

T25
V25

NB_HT_CLKP
NB_HT_CLKN

C1233
150P_0402_50V8J

Y 4
1 A
@
1
R174
R582
8.2K_0402_5% U28
NC7SZ08P5X_NL_SC70-5

2 0_0402_5%
2 0_0402_5%

R162 1
R163 1

NB_DISP_CLKP
NB_DISP_CLKN

2 33_0402_5%

U29
U28

<5> APU_DISP_CLKP
<5> APU_DISP_CLKN

PCIE_RCLKP/NB_LNK_CLKP
PCIE_RCLKN/NB_LNK_CLKN

CLOCK GENERATOR

APU_DISP_CLKP_R
APU_DISP_CLKN_R

R175 1

M23
P23

2 0_0402_5%
2 0_0402_5%

0.1U_0402_16V4Z

close to FCH within 1"


R564 1
R565 1

A_RST#

PCIE_FRX_DTX_P2
PCIE_FRX_DTX_N2
PCIE_FRX_DTX_P3
PCIE_FRX_DTX_N3

GPP_RX0P
GPP_RX0N
GPP_RX1P
GPP_RX1N
GPP_RX2P
GPP_RX2N
GPP_RX3P
GPP_RX3N

AA22
Y21
AA25
AA24
W23
V24
W24
W25

GPP_TX0P
GPP_TX0N
GPP_TX1P
GPP_TX1N
GPP_TX2P
GPP_TX2N
GPP_TX3P
GPP_TX3N

C1234
1
2

0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K

PCIE_FTX_DRX_P2
PCIE_FTX_DRX_N2
PCIE_FTX_DRX_P3
PCIE_FTX_DRX_N3

PCIE_CALRP
PCIE_CALRN

+3VALW

PAD T92
AA1
AA4
AA3
AB1
AA5
AB2
AB6
AB5
AA6
AC2
AC3
AC4
AC1
AD1
AD2
AC6
AE2
AE1
AF8
AE3
AF1
AG1
AF2
AE9
AD9
AC11
AF6
AF4
AF3
AH2
AG2
AH3
AA8
AD5
AD8
AA10
AE8
AB9
AJ3
AE7
AC5
AF5
AE6
AE4
AE11
AH5
AH4
AC12
AD12
AJ5
AH6
AB12
AB11
AD7

2
2
2
2

AA28
AA29
Y29
Y28
Y26
Y27
W28
W29

V2

1
1
1
1

AD29
AD28

PCI I/F

<26>
<26>
<29>
<29>

C61
C62
C717
C63

PCIE_FTX_C_DRX_P2
PCIE_FTX_C_DRX_N2
PCIE_FTX_C_DRX_P3
PCIE_FTX_C_DRX_N3

590_0402_1%
2K_0402_1%

<17>
<17>
<17>
<17>

LAN
WLAN

1
1

AD0/GPIO0
AD1/GPIO1
AD2/GPIO2
AD3/GPIO3
AD4/GPIO4
AD5/GPIO5
AD6/GPIO6
AD7/GPIO7
AD8/GPIO8
AD9/GPIO9
AD10/GPIO10
AD11/GPIO11
AD12/GPIO12
AD13/GPIO13
AD14/GPIO14
AD15/GPIO15
AD16/GPIO16
AD17/GPIO17
AD18/GPIO18
AD19/GPIO19
AD20/GPIO20
AD21/GPIO21
AD22/GPIO22
AD23/GPIO23
AD24/GPIO24
AD25/GPIO25
AD26/GPIO26
AD27/GPIO27
AD28/GPIO28
AD29/GPIO29
AD30/GPIO30
AD31/GPIO31
CBE0_L
CBE1_L
CBE2_L
CBE3_L
FRAME_L
DEVSEL_L
IRDY_L
TRDY_L
PAR
STOP_L
PERR_L
SERR_L
REQ0_L
REQ1_L/GPIO40
REQ2_L/CLK_REQ8_L/GPIO41
REQ3_L/CLK_REQ5_L/GPIO42
GNT0_L
GNT1_L/GPO44
GNT2_L/GPO45
GNT3_L/CLK_REQ7_L/GPIO46
CLKRUN_L
LOCK_L

PCI_CLK1
PCI_CLK2
PCI_CLK3
PCI_CLK4

<26>
<26>
<29>
<29>

2
2

UMI_RX0P
UMI_RX0N
UMI_RX1P
UMI_RX1N
UMI_RX2P
UMI_RX2N
UMI_RX3P
UMI_RX3N

PCIRST_L

PAD T96

W2
W1
W3
W4
Y1

R560
R561

+PCIE_VDDAN

UMI_TX0P
UMI_TX0N
UMI_TX1P
UMI_TX1N
UMI_TX2P
UMI_TX2N
UMI_TX3P
UMI_TX3N

PCICLK0
PCICLK1/GPO36
PCICLK2/GPO37
PCICLK3/GPO38
PCICLK4/14M_OSC/GPO39

0.1U_0402_16V4Z

AE24
AE23
AD25
AD24
AC24
AC25
AB25
AB24

PCIE_RST_L
A_RST_L

AD26
AD27
AC28
AC29
AB29
AB28
AB26
AB27

UMI_RX0P_C
UMI_RX0N_C
UMI_RX1P_C
UMI_RX1N_C
UMI_RX2P_C
UMI_RX2N_C
UMI_RX3P_C
UMI_RX3N_C

UMI_TX0P
UMI_TX0N
UMI_TX1P
UMI_TX1N
UMI_TX2P
UMI_TX2N
UMI_TX3P
UMI_TX3N

0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K

<6>
<6>
<6>
<6>
<6>
<6>
<6>
<6>

2
2
2
2
2
2
2
2

1U_0402_6.3V4Z

UMI_RX0P
UMI_RX0N
UMI_RX1P
UMI_RX1N
UMI_RX2P
UMI_RX2N
UMI_RX3P
UMI_RX3N

1
1
1
1
1
1
1
1

0.1U_0402_16V4Z

<6>
<6>
<6>
<6>
<6>
<6>
<6>
<6>

C53
C54
C55
C56
C57
C58
C59
C60

PCI CLKS

P1
L1

PCI EXPRESS I/F

PCIE_RST#
A_RST#

<31> A_RST#

Wednesday, November 24, 2010

Sheet
E

13

of

47

+3VALW

USB_OC7#
2
10K_0402_5%
EC_LID_OUT#
2
10K_0402_5%
USB_OC5#
2
10K_0402_5%
ODD_DA#_FCH
2
10K_0402_5%
ODD_DETECT#
2
10K_0402_5%

U31A

<31> SLP_S3#
<31> SLP_S5#
<31> PBTN_OUT#

+3VS

<31> EC_GA20
<31> EC_KBRST#
<31> EC_SCI#
<31> EC_SMI#

LAN_CLKREQ#
2
10K_0402_5%
MINI1_CLKREQ#
2
10K_0402_5%
NB_PWRGD
2
4.7K_0402_5%
FCH_SMCLK0
2
2.2K_0402_5%
FCH_SMDAT0
2
2.2K_0402_5%

1
R817
1
R818
1
R597
1
R598
1
R599

R580 2

+3VALW

R579 1

2 10K_0402_5%
<26,29> FCH_PCIE_WAKE#
<5> H_THERMTRIP#

R581 2

1 0_0402_5%
<26> LAN_CLKREQ#

5
P
4

@
@

VGATE <31,44>
<29> MINI1_CLKREQ#

NC7SZ08P5X_NL_SC70-5
U30 @

VRAM_SEL
2
2.2K_0402_5%
2
100K_0402_5%

VRAM_Freq : 1->900Hz
0-> 800Hz*

USB_OC7#
<31> EC_LID_OUT#

USB_OC5#
ODD_DA#_FCH
ODD_DETECT#
USB_OC2#
USB_OC1#

<30> ODD_DA#_FCH
<30> ODD_DETECT#
<33> USB_OC2#
<33> USB_OC1#
<33> USB_OC0#

VGA_CLKREQ#_R
2
10K_0402_5%
FCH_SMCLK1
2
10K_0402_5%
FCH_SMDAT1
2
10K_0402_5%
EC_RSMRST#
2
2.2K_0402_5%
HDA_BITCLK
2
10K_0402_5%
HDA_SDIN0
2
10K_0402_5%
HDA_SDOUT
2
10K_0402_5%

R583 1
R165 1

<27> HDA_BITCLK_AUDIO
<27> HDA_SDOUT_AUDIO
<27> HDA_SDIN0

+3VALW

R593

2 10K_0402_5%
2 10K_0402_5%
2 10K_0402_5%

R596

2 10K_0402_5%

R600

+3VALW +3VALW +3VALW

PX@
VGA@
R912
R911
R910
10K_0402_5%
10K_0402_5%
10K_0402_5%

GPIO189
GPIO190
GPIO191

T85
T86

2 10K_0402_5%

+3VALW
BACO@
WOPX@ WOVGA@
R915
R914
R913
10K_0402_5%
10K_0402_5%
10K_0402_5%

PAD
PAD

T1
T4
L6
L5
T9
U1
U3
T2
U2
T5
V5
P5
M5
P9
T7
P7
M7
P4
M9
V7

GPIO187 E23
GPIO188 E24
F21
G29
GPIO189
GPIO190
GPIO191

D27
F28
F29
E27

AZ_BITCLK
AZ_SDOUT
AZ_SDIN0/GPIO167
AZ_SDIN1/GPIO168
AZ_SDIN2/GPIO169
AZ_SDIN3/GPIO170
AZ_SYNC
AZ_RST_L
GBE_COL
GBE_CRS
GBE_MDCK
GBE_MDIO
GBE_RXCLK
GBE_RXD3
GBE_RXD2
GBE_RXD1
GBE_RXD0
GBE_RXCTL/RXDV
GBE_RXERR
GBE_TXCLK
GBE_TXD3
GBE_TXD2
GBE_TXD1
GBE_TXD0
GBE_TXCTL/TXEN
GBE_PHY_PD
GBE_PHY_RST_L
GBE_PHY_INTR

GBE LAN

M3
N1
L2
M2
M1
M4
N2
P2

USB_FSD0P/GPIO185
USB_FSD0N

H9
J8

USB_HSD13P
USB_HSD13N

B12
A12

USB_HSD12P
USB_HSD12N

F11
E11

USB_HSD11P
USB_HSD11N

E14
E12

PS2_DAT/SDA4/GPIO187
PS2_CLK/SCL4/GPIO188
SPI_CS2_L/GBE_STAT2/GPIO166
FC_RST_L/GPO160

USB_RCOMP 1

2
11.8K_0402_1%

USB_HSD[13:0]P/N:
USB P/N pairs with trace lengths up to
10" and have a decoupling 5.6-pF capacitor
footprint placed near the USB connector or device.

Root

J12
J14
A13
B13
D13
C13

USB20_P8 <29>
USB20_N8 <29>

MINI1-WLAN

G12
G14

USB20_P7 <33>
USB20_N7 <33>

BT

Root

G16
G18

USB20_P6 <29>
USB20_N6 <29>

CardReader

EHCI CTL
DEV 19, Fn 2

USB_HSD5P
USB_HSD5N

D16
C16

USB20_P5 <10>
USB20_N5 <10>

Camera

USB_HSD4P
USB_HSD4N

B14
A14

USB_HSD3P
USB_HSD3N

E18
E16

USB_HSD2P
USB_HSD2N

J16
J18

USB20_P2 <33>
USB20_N2 <33>

USB/B (Right)

Root

USB_HSD1P
USB_HSD1N

B17
A17

USB20_P1 <33>
USB20_N1 <33>

USB/B (Right)

EHCI CTL
DEV 18, Fn 2

A16
B16

USB20_P0 <33>
USB20_N0 <33>

USB Conn (Left)

USB_HSD8P
USB_HSD8N

BLINK/USB_OC7_L/GEVENT18_L
USB_OC6_L/IR_TX1/GEVENT6_L
USB_OC5_L/IR_TX0/GEVENT17_L
USB_OC4_L/IR_RX0/GEVENT16_L
USB_OC3_L/AC_PRES/TDO/GEVENT15_L
USB_OC2_L/TCK/GEVENT14_L
USB_OC1_L/TDI/GEVENT13_L
USB_OC0_L/TRST_L/GEVENT12_L

R578
G19

J10
H11

USB_HSD9P
USB_HSD9N

USB_HSD7P
USB_HSD7N
USB_HSD6P
USB_HSD6N

USB_HSD0P
USB_HSD0N

SCL2/GPIO193
SDA2/GPIO194
SCL3_LV/GPIO195
SDA3_LV/GPIO196
EC_PWM0/EC_TIMER0/GPIO197
EC_PWM1/EC_TIMER1/GPIO198
EC_PWM2/EC_TIMER2/GPIO199
EC_PWM3/EC_TIMER3/GPIO200

EMBEDDED CTRL

R5911
R5921

HDA_BITCLK
HDA_SDOUT
HDA_SDIN0

2 33_0402_5% HDA_SYNC
2 33_0402_5% HDA_RST#

R589 1
R590 1

<27> HDA_SYNC_AUDIO
<27> HDA_RST_AUDIO#

Pull-down for enable high performance mode


20100527 (required for M1)

2 33_0402_5%
2 33_0402_5%

H3
D1
E4
D4
E8
F7
E7
F8

A10

USB_FSD1P/GPIO186
USB_FSD1N

USB_HSD10P
USB_HSD10N

CLK_REQ4_L/SATA_IS0_L/GPIO64
CLK_REQ3_L/SATA_IS1_L/GPIO63
SMARTVOLT1/SATA_IS2_L/GPIO50
CLK_REQ0_L/SATA_IS3_L/GPIO60
SATA_IS4_L/FANOUT3/GPIO55
SATA_IS5_L/FANIN3/GPIO59
SPKR_GPIO66
SCL0_GPIO43
SDA0_GPIO47
SCL1_GPIO227
SDA1_GPIO228
CLK_REQ2_L/FANIN4_GPIO62
CLK_REQ1_L/FANOUT4_GPIO61
IR_LED_L/LLB_L/GPIO184
SMARTVOLT2/SHUTDOWN_L/GPIO51
DDR3_RST_L/GEVENT7_L
GBE_LED0/GPIO183
GBE_LED1/GEVENT9_L
GBE_LED2/GEVENT10_L
GBE_STAT0/GEVENT11_L
CLK_REQG_L/GPIO65_OSCIN

HD AUDIO

1
R173
1
R587
1
R588
1
R606
1
R607
1
R608
1
R609

RSMRST_L

USB OC

1
R626
1
R404

+3VS

EC_PWROK <31>

@
C112
0.1U_0402_16V7K

USB_RCOMP

USB 2.0

<27> FCH_SPKR
<8,9,29> FCH_SMCLK0
<8,9,29> FCH_SMDAT0

AD19
AA16
AB21
AC18
AF20
AE19
AF19
AD22
AE22
FCH_SMCLK1
F5
FCH_SMDAT1
F4
AH21
AB18
E1
AJ21
H4
VRAM_SEL
D5
D7
G5
K3
VGA_CLKREQ#_R AA20

USBCLK/14M_25M_48M_OSC

10mils and <1"

GPIO

+3VS @
C111 0.1U_0402_16V7K
1
2

<44> FCH_PWRGD

G1

<31> EC_RSMRST#

1 0_0402_5%

PCI_PME_L/GEVENT4_L
RI_L/GEVENT22_L
SPI_CS3_L/GBE_STAT1/GEVENT21_L
SLP_S3_L
SLP_S5_L
PWR_BTN_L
PWR_GOOD
SUS_STAT_L
TEST0
TEST1/TMS
TEST2
GA20IN/GEVENT0_L
KBRST_L/GEVENT1_L
LPC_PME_L/GEVENT3_L
LPC_SMI_L/GEVENT23_L
GEVENT5_L
SYS_RESET_L/GEVENT19_L
WAKE_L/GEVENT8_L
IR_RX1/GEVENT20_L
THRMTRIP_L/SMBALERT_L/GEVENT2_L
NB_PWRGD

USB 1.1

J2
K1
D3
F1
H1
F2
FCH_PWRGD H5
G6
B3
T82PAD
C4
T83PAD
F6
T84PAD
AD21
AE21
K2
J29
H2
J1
H6
F3
J6
NB_PWRGD
AC19

<31> EC_SWI#

USB MISC

1
R929
1
R930
1
R931
1
R932
1
R933

ACPI/WAKE UP EVENTS

USB_OC2#
2
10K_0402_5%
USB_OC1#
2
10K_0402_5%
USB_OC0#
2
10K_0402_5%
FCH_SIC
2
10K_0402_5%
FCH_SID
2
10K_0402_5%
FCH_PCIE_WAKE#
2
10K_0402_5%

1
R870
1
R871
1
R872
1
R603
1
R604
1
R605

KSI_0/GPIO201
KSI_1/GPIO202
KSI_2/GPIO203
KSI_3/GPIO204
KSI_4/GPIO205
KSI_5/GPIO206
KSI_6/GPIO207
KSI_7/GPIO208
KSO_0/GPIO209
KSO_1/GPIO210
KSO_2/GPIO211
KSO_3/GPIO212
KSO_4/GPIO213
KSO_5/GPIO214
KSO_6/GPIO215
KSO_7/GPIO216
KSO_8/GPIO217
KSO_9/GPIO218
KSO_10/GPIO219
KSO_11/GPIO220
KSO_12/GPIO221
KSO_13/GPIO222
KSO_14/GPIO223
KSO_15/GPIO224
KSO_16/GPIO225
KSO_17/GPIO226

D25
F23
B26
E26
F25
E22
F22
E21

GPIO193
GPIO194

R584 2
R586 2

<Support Wakeup>

1 10K_0402_5%
1 10K_0402_5%
FCH_SIC <5>
FCH_SID <5>

EC_PWM2
EC_PWM3

EC_PWM2 <17>
EC_PWM3 <17>

G24
G25
E28
E29
D29
D28
C29
C28

B28
A27
B27
D26
A26
C26
A24
B25
A25
D24
B24
C24
B23
A23
D22
C22
A22
B22

PS2KB_DAT/GPIO189
PS2KB_CLK/GPIO190
PS2M_DAT/GPIO191
PS2M_CLK/GPIO192
21807-A11-HUDSON-M1_FCBGA605

SKU_ID
(GPIO189)

SKU_ID : 1->VGA*
0->UMA

PX_FN
(GPIO190)

PX_Function : 1->PX Enable*


0->PX Disable

PX_SEL
(GPIO191)

PX_SEL : 1->PX 3.0*


0->PX 4.0

GPIO

189

190

191

UMA
DISO
PX3.0
PX4.0

0
1
1
1

0
0
1
1

1
1
1
0

2010/08/20

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2011/08/20

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

FCH HDA/USB/ACPI
Rev
1.0

LA-7092P P5WE6/H6/S6

Date:

Wednesday, November 24, 2010

Sheet
E

14

of

47

U31B

HDD

C656
C658

<30> SATA_ITX_DRX_P0
<30> SATA_ITX_DRX_N0

2 0.01U_0402_16V7K
2 0.01U_0402_16V7K

1
1

SATA_ITX_C_DRX_P0 AH9
SATA_ITX_C_DRX_N0 AJ9

<30> SATA_DTX_C_IRX_N0
<30> SATA_DTX_C_IRX_P0

ODD

SATA_TX0P
SATA_TX0N

AJ8
AH8
C648
C649

<30> SATA_ITX_DRX_P1
<30> SATA_ITX_DRX_N1

2 0.01U_0402_16V7K
2 0.01U_0402_16V7K

1
1

SATA_RX0N
SATA_RX0P

SATA_ITX_C_DRX_P1 AH10
SATA_ITX_C_DRX_N1 AJ10
AG10
AF10

SATA_RX1N
SATA_RX1P

AG12
AF12

SATA_TX2P
SATA_TX2N

AJ12
AH12

SATA_RX2N
SATA_RX2P

AH14
AJ14

SATA_TX3P
SATA_TX3N

AG14
AF14

SATA_RX3N
SATA_RX3P

AG17
AF17

SATA_TX4P
SATA_TX4N

AJ17
AH17

SATA_RX5N
SATA_RX5P

10 mils and < 1"


2 1K_0402_1%
2 931_0402_1%

1
1

SATA_CALRP
SATA_CALRN

AB14
AA14

SATA_CALRP
SATA_CALRN

AD11

<32> SATA_LED#
R616 1
1
3

@ C107

25M_SATA_X1 AD16

22P_0402_50V8J
2

@ C106
22P_0402_50V8J
1
2

1M_0603_5%
R861

25M_SATA_X2 AC16

SATA_X2

T78PAD

J5
E2
K4
K9
G2

SPI_DI/GPIO164
SPI_DO/GPIO163
SPI_CLK/GPIO162
SPI_CS1_L/GPIO165
ROM_RST_L/GPIO161

SPI ROM

25MHZ_20PF_7A25000012
FCH_SI_SPI_SO
FCH_SO_SPI_SI
FCH_SPICLK
FCH_SPICS#/FSEL#

FANIN0/GPIO56
FANIN1/GPIO57
FANIN2/GPIO58

VIN0/GPIO175
VIN1/GPIO176
VIN2/GPIO177
VIN3/GPIO178
VIN4/GPIO179
VIN5/GPIO180
VIN6/GBE_STAT3/GPIO181
VIN7/GBE_LED3/GPIO182

SATA_X1

@
Y7

FANOUT0/GPIO52
FANOUT1/GPIO53
FANOUT2/GPIO54

TEMPIN0/GPIO171
TEMPIN1/GPIO172
TEMPIN2/GPIO173
TEMPIN3/TALERT_L/GPIO174
TEMP_COMM

SATA_ACT_L/GPIO67

2 10K_0402_5%
2
1

+3VS

HW MONITOR

SATA_TX5P
SATA_TX5N

AH19
AJ19
R610
R611

FC_ADQ0/GPIOD128
FC_ADQ1/GPIOD129
FC_ADQ2/GPIOD130
FC_ADQ3/GPIOD131
FC_ADQ4/GPIOD132
FC_ADQ5/GPIOD133
FC_ADQ6/GPIOD134
FC_ADQ7/GPIOD135
FC_ADQ8/GPIOD136
FC_ADQ9/GPIOD137
FC_ADQ10/GPIOD138
FC_ADQ11/GPIOD139
FC_ADQ12/GPIOD140
FC_ADQ13/GPIOD141
FC_ADQ14/GPIOD142
FC_ADQ15/GPIOD143

SATA_RX4N
SATA_RX4P

AJ18
AH18

+AVDD_SATA

SERIAL ATA

FC_OE_L/GPIOD145
FC_AVD_L/GPIOD146
FC_WE_L/GPIOD148
FC_CE1_L/GPIOD149
FC_CE2_L/GPIOD150
FC_INT1/GPIOD144
FC_INT2/GPIOD147

SATA_TX1P
SATA_TX1N

GPIOD

<30> SATA_DTX_C_IRX_N1
<30> SATA_DTX_C_IRX_P1

FC_CLK
FC_FBCLKOUT
FC_FBCLKIN

NC1
NC2

AH28
AG28
AF26
AF28
AG29
AG26
AF27
AE29
AF29
AH27
AJ27
AJ26
AH25
AH24
AG23
AH23
AJ22
AG21
AF21
AH22
AJ23
AF23
AJ24
AJ25
AG25
AH26

W5
W6
Y9

ODD_PWR

ODD_PWR <30>

W7
V9
W8
B6
A6
A5
B5
C7

TEMPIN0 R612 2
TEMPIN1 R613 2
TEMPIN2 R614 2
R615 2

1
1
1
1

10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%

A3
B4
A4
C5
A7
B7
B8
A8

GPIO175
GPIO176
GPIO177
GPIO178
GPIO179
GPIO180
GPIO181
GPIO182

1
1
1
1
1
1
1
1

10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%

R617
R618
R619
R620
R621
R622
R623
R624

2
2
2
2
2
2
2
2

VIN6/GBE_STAT3/GPIO181
Enable integrated pull-down/up and leave unconnected

G27
Y2

21807-A11-HUDSON-M1_FCBGA605

@
+3VS

@
1
R504

2
0_0603_5%

C784 1

2 0.1U_0402_16V4Z

FCH_+SPI_VCC
U32

+3VS

R507 1
R491 1

@
@

FCH_SPICS#/FSEL#
FCH_SPI_WP#
2 4.7K_0402_5%
FCH_SPI_HOLD#
2 4.7K_0402_5%

1
3
7
4

CS#
WP#
HOLD#
GND

VCC
SCLK
SI
SO

8
6
5
2

FCH_SPICLK_R
FCH_SO_SPI_SI
FCH_SI_SPI_SO

R510 1

2 0_0402_5% FCH_SPICLK
4

MX25L1605DM2I-12G SOP 8P
SA00002TO00
@

2010/08/20

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2011/08/20

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

FCH-SATA/SPI
Rev
1.0

LA-7092P P5WE6/H6/S6

Date:

Wednesday, November 24, 2010

Sheet
E

15

of

47

M6
P8

PLL

0.1U_0402_16V7K

C93

C94

FBMA-L11-160808-221LMT_2P

2.2U_0603_6.3V6K

L48
2

+1.1VALW

+VDDAN_11_USB C11
D11

88.6mA

VDDCR_11_S_1
VDDCR_11_S_2

F26
G26

VDDPL_33_USB_S

VDDAN_11_USB_S_1
VDDAN_11_USB_S_2

VDDAN_33_HWM_S
VDDXL_33_S

C99

Change 0603 size


For DVT

+3VALW

C776

C775

C778

C68

10U_0603_6.3V6M

10U_0603_6.3V6M

C109

10U_0603_6.3V6M

C743

C75

1U_0402_6.3V6K

C74

1U_0402_6.3V6K

0.1U_0402_16V7K

330U_D2_2.5VY_R9M

10U_0603_6.3V6M

C71

C118

1U_0402_6.3V6K

C117

1U_0402_6.3V6K

C119

+VDDIO_AZ

58mA

Add VGA@
For DVT

+VDDCR_11_USB @
L107
2
1
5
FBMA-L11-160808-221LMT 0603

F19

C989
@

Reserve
+1.1VALW

+VDDAN33_HWM
+VDDXL_33_S

L20

FB

1U_0402_6.3V6K
2
1
2

L47
2
1
FBMA-L11-201209-221LMA30T_0805

+1.1VALW

+AVDD_USB

11.4mA

D6

GND

+VDDPL11

16.1mA

VIN
VOUT

APL5317

+VDDPL33

65.3mA

L22

@
U85

EN

46.5mA

M21

+3VALW

+VDDCR_11_USB

5mA

0.1U_0402_16V7K

0.1U_0402_16V7K

1U_0402_6.3V6K

C97

1U_0402_6.3V6K

C96

L49
2

+3VS

FBMA-L11-160808-221LMT_2P

+VDDIO_AZ

+3VALW
@
1
R634
1
R635

2
0_0603_5%
2
0_0603_5%

+3VS

For DVT 1011

C98
2.2U_0603_6.3V6K

For 3V AZ device

+VDDAN33_HWM

L53
2
1
FBMA-L11-160808-221LMT_2P

2 2.2U_0603_6.3V6K
C100

2
+VDDPL33

C782

L52
2
1
FBMA-L11-160808-221LMT_2P

10U_0603_6.3V6M

+VDDPL11
+1.1VALW

+1.1VS

0.1U_0402_16V7K

2 2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

C777 1

L50
2
1
FBMA-L11-201209-221LMA30T_0805
C108

2
1
FBMA-L11-160808-221LMT_2P

C73

15.3mA

A11
B11

10U_0603_6.3V6M

+3VS

+1.1VS

C70

C738

165.2mA

M8

21807-A11-HUDSON-M1_FCBGA605

+AVDD_SATA
+VDDPL_33_SATA

0.1U_0402_16V7K

0.1U_0402_16V7K

49.5mA

L51

FBMA-L11-201209-221LMA30T_0805

+3VALW

A21
D21
B21
K10
L10
J9
T6
T8

VDDPL_33_SYS

L43 2

+
2

Change 0603 size


For DVT

VDDIO_33_S_1
VDDIO_33_S_2
VDDIO_33_S_3
VDDIO_33_S_4
VDDIO_33_S_5
VDDIO_33_S_6
VDDIO_33_S_7
VDDIO_33_S_8

VDDPL_11_SYS_S

C92

VDDIO_GBE_S_1
VDDIO_GBE_S_2

VDDIO_AZ_S

M10

L7
L9

VDDCR_11_USB_S_1
VDDCR_11_USB_S_2

10U_0603_6.3V6M

VDDAN_33_USB_S_1
VDDAN_33_USB_S_2
VDDAN_33_USB_S_3
VDDAN_33_USB_S_4
VDDAN_33_USB_S_5
VDDAN_33_USB_S_6
VDDAN_33_USB_S_7
VDDAN_33_USB_S_8
VDDAN_33_USB_S_9
VDDAN_33_USB_S_10
VDDAN_33_USB_S_11
VDDAN_33_USB_S_12

+1.1VS

VGA@

C91

C89

C88

0.1U_0402_16V7K

1U_0402_6.3V6K

C87

1U_0402_6.3V6K

10U_0603_6.3V6M

C86

10U_0603_6.3V6M

C85

A18
A19
A20
B18
B19
B20
C18
C20
D18
D19
D20
E19

USB I/O

534.5mA

+1.1VS

0.1U_0402_16V7K

+AVDD_USB

0.1U_0402_16V7K

CORE S5

C90

VDDAN_11_SATA_1
VDDAN_11_SATA_4
VDDAN_11_SATA_2
VDDAN_11_SATA_3
VDDAN_11_SATA_5
VDDAN_11_SATA_6
VDDAN_11_SATA_7

L46
FBMA-L11-201209-221LMA30T_0805

C82

AJ20
AF18
AH20
AG19
AE18
AD18
AE16

VDDPL_33_SATA

V1

VDDCR_11_GBE_S_1
VDDCR_11_GBE_S_2

3.3V_S5 I/O

+AVDD_SATA

1345.2mA

+3VALW

15.5mA
+VDDPL_33_SATA AD14

2.2U_0603_6.3V6K

VDDAN_11_PCIE_1
VDDAN_11_PCIE_2
VDDAN_11_PCIE_3
VDDAN_11_PCIE_4
VDDAN_11_PCIE_5
VDDAN_11_PCIE_6
VDDAN_11_PCIE_7
VDDAN_11_PCIE_8

SERIAL ATA

Change 0603 size


For DVT
2

U26
V22
V26
V27
V28
V29
W22
W26

C84

+PCIE_VDDAN

1U_0402_6.3V6K

1115.6mA

VDDIO_33_GBE_S
VDDPL_33_PCIE

382.9mA

+VDDAN_11_CLK

K28
K29
J28
K26
J21
J20
K21
J22

C81

C80

AE28

2.2U_0603_6.3V6K

22.5mA
+VDDPL33_PCIE

C83

C76
C79

VDDRF_GBE_S

979.4mA

1U_0402_6.3V6K

VDDAN_11_CLK_1
VDDAN_11_CLK_2
VDDAN_11_CLK_3
VDDAN_11_CLK_4
VDDAN_11_CLK_5
VDDAN_11_CLK_6
VDDAN_11_CLK_7
VDDAN_11_CLK_8

N13
R15
N17
U13
U17
V12
V18
W12
W18

2.2U_0603_6.3V6K

0.1U_0402_16V7K

1U_0402_6.3V6K

C105

C78

2
1
FBMA-L11-201209-221LMA30T_0805

10U_0603_6.3V6M

L45

C77

+1.1VS

10U_0603_6.3V6M

VDDIO_18_FC_1
VDDIO_18_FC_2
VDDIO_18_FC_3
VDDIO_18_FC_4

GBE LAN

AF22
AE25
AF24
AC22

PCI EXPRESS

L44
2
1
FBMA-L11-160808-221LMT_2P

+3VS

0.1U_0402_16V7K

C69

C746

0.16mA

2.2U_0603_6.3V6K

0.1U_0402_16V7K

For DVT 1011

0.1U_0402_16V7K

4.7U_0603_6.3V6K

C744

R633
2

FLASH I/O

+VDDIO_18_FC

VDDCR_11_1
VDDCR_11_2
VDDCR_11_3
VDDCR_11_4
VDDCR_11_5
VDDCR_11_6
VDDCR_11_7
VDDCR_11_8
VDDCR_11_9

C72

R632
@
2
0_0603_5%

VDDIO_33_PCIGP_1
VDDIO_33_PCIGP_2
VDDIO_33_PCIGP_3
VDDIO_33_PCIGP_4
VDDIO_33_PCIGP_5
VDDIO_33_PCIGP_6
VDDIO_33_PCIGP_7
VDDIO_33_PCIGP_8
VDDIO_33_PCIGP_9
VDDIO_33_PCIGP_10
VDDIO_33_PCIGP_11
VDDIO_33_PCIGP_12

C95

AH1
V6
Y19
AE5
AC21
AA2
AB4
AC8
AA7
AA9
AF7
AA19

0.1U_0402_16V7K

C116

0.1U_0402_16V7K

C115

C114

C113

0.1U_0402_16V7K

CLKGEN I/O

GPIO I/F implemented: tied to +1.8V_S0


GPIO I/F not implemented: tied to
+1.8V_S0 or 0 ohm to ground

+1.8VS

10U_0603_6.3V6M

POWER

U31C

42mA

0_0402_5%

CORE S0

PCI/GPIO I/O

C121

Change 0603 size


For DVT
10U_0603_6.3V6M

+3VS

0.1U_0402_16V7K

L55
+3VS

2
1
FBMA-L11-160808-221LMT_2P
C120 1

2010/08/20

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2 2.2U_0603_6.3V6K

2011/08/20

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

FCH PWR
Rev
1.0

LA-7092P P5WE6/H6/S6

Date:

Tuesday, November 16, 2010

Sheet
E

16

of

47

U31D

VSSXL

P21
P20
M22
M24
M26
P22
P24
P26
T20
T22
T24
V20
J23

VSSIO_PCIECLK_1
VSSIO_PCIECLK_2
VSSIO_PCIECLK_3
VSSIO_PCIECLK_4
VSSIO_PCIECLK_5
VSSIO_PCIECLK_6
VSSIO_PCIECLK_7
VSSIO_PCIECLK_8
VSSIO_PCIECLK_9
VSSIO_PCIECLK_10
VSSIO_PCIECLK_11
VSSIO_PCIECLK_12
VSSIO_PCIECLK_13

PCI_CLK3

PCI_CLK4

LPC_CLK0 LPC_CLK1

WATCHDOG
TIMER
ENABLE

ALLOW PCIE
GEN2

USE
DEBUG
STRAP

NON Fusion
CLOCK
Mode

internal EC
ENABLE

VSSPL_SYS

RTC_CLK

Internal
CLKGEN
Mode

EC_PWM2 EC_PWM3
LPC ROM (H.L)

S5 PLUS
MODE
DISABLED

DEFAULT

DEFAULT

DEFAULT
DEFAULT

WATCHDOG
TIMER
DISABLE

PULL
LOW

FORCE PCIE
GEN1

IGNORE
DEBUG
STRAP

Fusion
CLOCK
Mode

internal EC
DISABLE

DEFAULT

DEFAULT

DEFAULT

External
CLKGEN
Mode

S5 PLUS
MODE
ENABLED

SPI ROM(L,H)

DEFAULT

+3VALW

+3VALW

+3VALW

+3VALW

+3VALW

+3VS

+3VS

+3VS

+3VS

PCI_CLK2
PCI_CLK1
PCI_CLK3
PCI_CLK4
LPC_CLK0
LPC_CLK1
EC_PWM2
EC_PWM3
RTC_CLK

<13>
<13>
<13>
<13>
<13>
<13>
<14>
<14>
<13,31>

R649
R636
R637
R638
R639
R166
R594
R550
R551
@
@
@
@
@
@
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%

R640
R641
R642
R643
R167
R601
R602
R625
@
@
@
@
10K_0402_5%
10K_0402_5%
10K_0402_5%
2.2K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
2.2K_0402_5%
2.2K_0402_5%
2

R650

VSSAN_HWM

PCI_CLK1

D8
M19

Check Internal PU/PD

EFUSE

PULL
HIGH

PCI_CLK2

Y4

REQUIRED STRAPS

AJ2
A28
A2
E5
D23
E25
E6
F24
N15
R13
R17
T10
P10
V11
U15
M18
V19
M11
L12
L18
J7
P3
V4
AD6
AD4
AB7
AC9
V8
W9
W10
AJ28
B29
U4
Y18
Y10
Y12
Y11
AA11
AA12
G4
J4
G8
G9
M12
AF25
H7
AH29
V10
P6
N4
L4
L8

VSSIO_USB_1
VSSIO_USB_2
VSSIO_USB_3
VSSIO_USB_4
VSSIO_USB_5
VSSIO_USB_6
VSSIO_USB_7
VSSIO_USB_8
VSSIO_USB_9
VSSIO_USB_10
VSSIO_USB_11
VSSIO_USB_12
VSSIO_USB_13
VSSIO_USB_14
VSSIO_USB_15
VSSIO_USB_16
VSSIO_USB_17
VSSIO_USB_18
VSSIO_USB_19
VSSIO_USB_20
VSSIO_USB_21
VSSIO_USB_22
VSSIO_USB_23
VSSIO_USB_24
VSSIO_USB_25
VSSIO_USB_26
VSSIO_USB_27
VSSIO_USB_28

VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52

GND

A9
B10
K11
B9
D10
D12
D14
D17
E9
F9
F12
F14
F16
C9
G11
F18
D9
H12
H14
H16
H18
J11
J19
K12
K14
K16
K18
H19

VSSIO_SATA_1
VSSIO_SATA_2
VSSIO_SATA_3
VSSIO_SATA_4
VSSIO_SATA_5
VSSIO_SATA_6
VSSIO_SATA_7
VSSIO_SATA_8
VSSIO_SATA_9
VSSIO_SATA_10
VSSIO_SATA_11
VSSIO_SATA_12
VSSIO_SATA_13
VSSIO_SATA_14
VSSIO_SATA_15
VSSIO_SATA_16
VSSIO_SATA_17
VSSIO_SATA_18
VSSIO_SATA_19

Y14
Y16
AB16
AC14
AE12
AE14
AF9
AF11
AF13
AF16
AG8
AH7
AH11
AH13
AH16
AJ7
AJ11
AJ13
AJ16

M20

H23
H26
AA21
AA23
AB23
AD23
AA26
AC26
Y20
W21
W20
AE26
L21
K20

DEBUG STRAPS
FCH M1 HAS 15K INTERNAL PU FOR PCI_AD[27:23]

DEFAULT

PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23

21807-A11-HUDSON-M1_FCBGA605

BYPASS
PCI PLL

ILA
AUTORUN
Enabled

Check AD29,AD28 strap function

Getting Value
from I2C EPROM

R644
R645
R646
R647
R648
@
@
@
@
@
2.2K_0402_5%
2.2K_0402_5%
2.2K_0402_5%
2.2K_0402_5%
2.2K_0402_5%

Reserved

check default

Compal Electronics, Inc.

Compal Secret Data

Security Classification
Issued Date

FC PLL
bypassed

PULL
LOW

2010/08/20

Deciphered Date

2011/08/20

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

DEFAULT

DEFAULT

<13>
<13>
<13>
<13>
<13>

DEFAULT

Required Setting

Disable I2C
ROM

ILA AUTORUN Selects


Disabled
FC PLL

DEFAULT

PCI_AD23
Enable ROM Straps

PCI_AD24

USE internal
PLL generated
PLL CLK

PCI_AD25

PULL
HIGH

PCI_AD26

PCI_AD27

VSSIO_PCIECLK_14
VSSIO_PCIECLK_15
VSSIO_PCIECLK_16
VSSIO_PCIECLK_17
VSSIO_PCIECLK_18
VSSIO_PCIECLK_19
VSSIO_PCIECLK_20
VSSIO_PCIECLK_21
VSSIO_PCIECLK_22
VSSIO_PCIECLK_23
VSSIO_PCIECLK_24
VSSIO_PCIECLK_25
VSSIO_PCIECLK_26
VSSIO_PCIECLK_27

FCH-VSS/Strap
Document Number

Rev
1.0

LA-7092P P5WE6/H6/S6
Wednesday, November 24, 2010

Sheet
1

17

of

47

GFX PCIE LANE REVERSAL

add for VB support.


U2G

<6> PCIE_FTX_C_GRX_P[0..3]
<6> PCIE_FTX_C_GRX_N[0..3]

PCIE_FTX_C_GRX_P[0..3]

PCIE_GTX_C_FRX_P[0..3]

PCIE_FTX_C_GRX_N[0..3]

PCIE_GTX_C_FRX_N[0..3]

PCIE_FTX_C_GRX_P0
PCIE_FTX_C_GRX_N0

AA38
Y37

PCIE_FTX_C_GRX_P1
PCIE_FTX_C_GRX_N1

Y35
W36

PCIE_FTX_C_GRX_P2
PCIE_FTX_C_GRX_N2

W38
V37

PCIE_FTX_C_GRX_P3
PCIE_FTX_C_GRX_N3

V35
U36

PCIE_RX0P
PCIE_RX0N

PCIE_TX0P
PCIE_TX0N

Y33
Y32

PCIE_GTX_FRX_P0 C1
PCIE_GTX_FRX_N0 C2

PCIE_GTX_C_FRX_P[0..3] <6>

W33
W32

PCIE_GTX_FRX_P1 C3
PCIE_GTX_FRX_N1 C4

2
1
VGA@

PCIE_RX2P
PCIE_RX2N

PCIE_TX2P
PCIE_TX2N

U33
U32

PCIE_GTX_FRX_P2 C5
PCIE_GTX_FRX_N2 C6

2
1
VGA@

PCIE_RX3P
PCIE_RX3N

PCIE_TX3P
PCIE_TX3N

U30
U29

PCIE_GTX_FRX_P3 C7
PCIE_GTX_FRX_N3 C8

U38
T37

PCIE_RX4P
PCIE_RX4N

PCIE_TX4P
PCIE_TX4N

T33
T32

T35
R36

PCIE_RX5P
PCIE_RX5N

PCIE_TX5P
PCIE_TX5N

T30
T29

2
VGA@
2
VGA@

2
1
VGA@

TXCLK_UP_DPF3P
TXCLK_UN_DPF3N

0.1U_0402_16V7K PCIE_GTX_C_FRX_P1
0.1U_0402_16V7K PCIE_GTX_C_FRX_N1

TXOUT_U0P_DPF2P
TXOUT_U0N_DPF2N

0.1U_0402_16V7K PCIE_GTX_C_FRX_P2
0.1U_0402_16V7K PCIE_GTX_C_FRX_N2

TXOUT_U1P_DPF1P
TXOUT_U1N_DPF1N
TXOUT_U2P_DPF0P
TXOUT_U2N_DPF0N

0.1U_0402_16V7K PCIE_GTX_C_FRX_P3
0.1U_0402_16V7K PCIE_GTX_C_FRX_N3

P35
N36

PCIE_RX7P
PCIE_RX7N

N38
M37

PCIE_RX8P
PCIE_RX8N

M35
L36

PCIE_RX9P
PCIE_RX9N

L38
K37
K35
J36
J38
H37
H35
G36
B

PCIE_RX6P
PCIE_RX6N

G38
F37
F35
E37

PCIE_RX10P
PCIE_RX10N
PCIE_RX11P
PCIE_RX11N
PCIE_RX12P
PCIE_RX12N

PCI EXPRESS INTERFACE

R38
P37

PCIE_TX6P
PCIE_TX6N

P30
P29

PCIE_TX8P
PCIE_TX8N

N33
N32

PCIE_TX9P
PCIE_TX9N

N30
N29

PCIE_TX10P
PCIE_TX10N
PCIE_TX11P
PCIE_TX11N
PCIE_TX12P
PCIE_TX12N

PCIE_RX13P
PCIE_RX13N

PCIE_TX13P
PCIE_TX13N

PCIE_RX14P
PCIE_RX14N

PCIE_TX14P
PCIE_TX14N

PCIE_RX15P
PCIE_RX15N

PCIE_TX15P
PCIE_TX15N

VGA_INVT_PWM <10>
VGA_ENVDD <10>

R2
1
2
10K_0402_5%
VGA@
AK35
AL36
AJ38
AK37
AH35
AJ36
AG38
AH37
AF35
AG36

TXCLK_LP_DPE3P
TXCLK_LN_DPE3N

AP34
AR34

VGA_TXCLK+
VGA_TXCLK-

TXOUT_L0P_DPE2P
TXOUT_L0N_DPE2N

AW37
AU35

VGA_TXOUT0+
VGA_TXOUT0-

TXOUT_L1P_DPE1P
TXOUT_L1N_DPE1N

AR37
AU39

VGA_TXOUT1+
VGA_TXOUT1-

TXOUT_L2P_DPE0P
TXOUT_L2N_DPE0N

AP35
AR35

VGA_TXOUT2+
VGA_TXOUT2-

LVTMDP

P33
P32

PCIE_TX7P
PCIE_TX7N

AK27
AJ27

TXOUT_U3P
TXOUT_U3N

VGA@

VARY_BL
DIGON

0.1U_0402_16V7K PCIE_GTX_C_FRX_P0
0.1U_0402_16V7K PCIE_GTX_C_FRX_N0

2
VGA@

PCIE_TX1P
PCIE_TX1N

PCIE_RX1P
PCIE_RX1N

LVDS CONTROL

PCIE_GTX_C_FRX_N[0..3] <6>

2
1
VGA@

R1
10K_0402_5%
1
2
VGA@

U2A

TXOUT_L3P
TXOUT_L3N

VGA_TXCLK+ <10>
VGA_TXCLK- <10>
VGA_TXOUT0+ <10>
VGA_TXOUT0- <10>

VGA_TXOUT1+ <10>
VGA_TXOUT1- <10>
VGA_TXOUT2+ <10>
VGA_TXOUT2- <10>

AN36
AP37

2160809000A11SEYMOU_FCBGA962

L33
L32

Seymour@

L30
L29
K33
K32
J33
J32
B

K30
K29
H33
H32
+3VSG

CLOCK
PCIE_REFCLKP
PCIE_REFCLKN

<13> PE_GPIO0

<13,26,29> PLT_RST#

U16
PX@
Y

4 VGA_RST#

PERSTB
3

AA30

PCIE_CALRN

Y30
1 VGA@ 2
R3
1.27K_0402_1%
Y29
1 VGA@ 2
+1.0VSG
R6
2K_0402_1%

PCIE_CALRP

2 VGA@ 1
AH16
R5
10K_0402_5% PWRGOOD
VGA_RST#

R394
2.2K_0402_5%
@

CALIBRATION

AB35
AA36

<13> CLK_PCIE_VGA
<13> CLK_PCIE_VGA#

AH16
Accessiable for "Test Purposes"
Connect to GND for "Normal Operation"

2160809000A11SEYMOU_FCBGA962

NC7SZ08P5X_NL_SC70-5

1 DISO@ 2
R159
0_0402_5%

Seymour@

Seymour XT P/N: SA000047H10 (S IC 216-0809000 A11 SEYMOUR XT M2)


Robson XT P/N: SA00004DR20 (S IC 216-0774211 A11 Robson XT M2 )
A

U2 Robson@

Robson A11 (SA00004DR20)

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Robson XT-M2 A11

2010/08/20

2011/08/20

Deciphered Date

Title

Vancouver_ PCIE / LVDS

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
1.0

LA-7092P P5WE6/H6/S6

Date:

Wednesday, November 24, 2010

Sheet
1

18

of

47

U2B

Setting

TX_DEEMPH_EN

PCI Express Transmitter De-emphasis Enable


0: Tx de-emphasis diabled for mobile mode
1: Tx de-emphasis enabled (Defailt setting for desktop)

GPIO1

CONFIG[2]
CONFIG[1]
CONFIG[0]

GPIO13,12,11 (config 2,1,0) :


a) If BIOS_ROM_EN = 1, then Config[2:0] defines
the ROM type.

GPIO13
GPIO12
GPIO11

BIOS_ROM_EN

b) If BIOS_ROM_EN = 0, then Config[2:0] defines


the primary memory aperture size.

GPIO22

AUD[1]
AUD(0)

RESERVED

memory apertures
CONFIG[3:0]
128 MB 000
256 MB 001 *
64 MB 010

NC on Park and Robson


VRAM_ID0
VRAM_ID1
VRAM_ID2
VRAM_ID3

001

Enable external BIOS ROM device


0: Diable, 1: Enable

GPIO2

NC on Park,
Robson and Seymour

00: No audio function;


10: Audio for DisplayPort only;
01: Audio for DisplayPort and HDMI if adapter is detected;
11: Audio for both DisplayPort and HDMI
0= Advertises the PCI-E device as 2.5 GT/s capable at power-on
1= Advertises the PCI-E device as 5.0 GT/s capable at power-on
5.0 GT/s capability will be controlled by software

HSYNC
VSYNC

BIF_GEN2_EN

11

H2SYNC
Internal use only. THIS PAD HAS AN INTERNAL
(GENLK_CLK) PULL-DOWN AND MUST BE 0 V AT RESET. The
pad may be left unconnected
GPIO8
GPIO21
GENERICC
GPIO5

NC on Park,
Robson and Seymour

DNI

+3VSG

AJ21
AK21

+3VSG
VGA@ R11
VGA@ R13
@ R15
@ R16
@ R17
VGA@ R18
@ R19
@ R20
DISO@R21
DISO@
R21
DISO@R22
DISO@
R22
@ R23
@ R24
@ R25
@ R26
@ R27
@ R28

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2

VGA_GPIO0
VGA_GPIO1
VGA_GPIO2
SOUT_GPIO8
SIN_GPIO9
VGA_GPIO11
VGA_GPIO12
VGA_GPIO13
VGA_CRT_VSYNC
VGA_CRT_HSYNC
GENERICC
V2SYNC
H2SYNC
BB_EN_GPIO21
ROMSE_GPIO22
VGA_GPIO5

10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%

R12
R14

1 VGA@
1 VGA@

GPU_VID1
BB_EN_GPIO21
ROMSE_GPIO22

<43> GPU_VID1
T2
T3
T4
T5
T6
T7

<4 pcs>

GENERICC

<4 pcs>

SOUT_GPIO8

2
1

2
1

2
1

1
2
1
2

470ohm/1A

TYPE 1

HOLD

2
VGA@

W
VCC

2
VGA@

GPIO_0
GPIO_1
GPIO_2
GPIO_3_SMBDATA
GPIO_4_SMBCLK
GPIO_5_AC_BATT
GPIO_6
GPIO_7_BLON
GPIO_8_ROMSO
GPIO_9_ROMSI
GPIO_10_ROMSCK
GPIO_11
GPIO_12
GPIO_13
GPIO_14_HPD2
GPIO_15_PWRCNTL_0
GPIO_16
GPIO_17_THERMAL_INT
GPIO_18_HPD3
GPIO_19_CTF
GPIO_20_PWRCNTL_1
GPIO_21_BB_EN
GPIO_22_ROMCSB
GPIO_23_CLKREQB
JTAG_TRSTB
JTAG_TDI
JTAG_TCK
JTAG_TMS
JTAG_TDO
GENERICA
GENERICB
GENERICC
GENERICD
GENERICE_HPD4
NC_GENERICF_HPD5
NC_GENERICG_HPD6

27MCLK
R53

27MCLK
XTALOUT

+DPLL_VDDC
1

2
VGA@

1
R49
1
R50

B
BB

DAC1

HSYNC
VSYNC
RSET

70mA
45mA

AVDD
AVSSQ
VDD1DI
VSS1DI
R2/NC
R2B/NC
G2/NC
G2B/NC
B2/NC
B2B/NC

C/NC
Y/NC
COMP/NC

@
@

AV33
AU34

H2SYNC/GENLK_CLK
V2SYNC/GENLK_VSYNC

AK32
AL31

C36
VGA@
18P_0402_50V8J

2
VGA@

2
VGA@

C34
0.1U_0402_16V4Z

2
VGA@

27MHZ_16PF_X5H027000FG1H

C33
1U_0402_6.3V4Z

VGA@
1

10mil

+TSVDD

C32
10U_0603_6.3V6M

L5
BLM18AG121SN1D_0603
2
1
VGA@
1

AJ32
AJ33

THERM#

GND

VGA_SMB_DA2

R7
0_0402_5%

VGA_SMB_DA2

2
4.7K_0402_5%

+3VSG

EC_SMB_CK2

EC_SMB_CK2

<5,31>

EC_SMB_DA2

<5,31>

Q1B VGA@
DMN66D0LDW-7_SOT363-6

AT21
AR20

Q1A

EC_SMB_DA2
6
VGA@
DMN66D0LDW-7_SOT363-6

NC on Park,
Robson and Seymour

AU22
AV21
AT23
AR22

<12>

VGA_CRT_G

<12>

AF37
AE38

VGA_CRT_B

<12>

AC36
AC38

VGA_CRT_HSYNC
VGA_CRT_VSYNC

AB34

R30

AD34
AE34

+AVDD

AC33
AC34

+VDD1DI

1 VGA@

10mil

AD30
AD31

AF30
AF31

AC32
AD32
AF32

2
VGA@

AD29
AC29

H2SYNC
V2SYNC

2mAA2VDDQ/NC

AD33

+A2VDDQ

XTALIN
XTALOUT

10mil

2
VGA@

10mil

AA29

R48
715_0402_1%
1
2
VGA@

DDC1CLK
DDC1DATA

DDC2CLK
DDC2DATA
AUX2P
AUX2N

NC_DDCCLK_AUX4P
NC_DDCDATA_AUX4N
DDCCLK_AUX5P
DDCDATA_AUX5N

TS_FDO
DDC6CLK
DDC6DATA

TS_A/NC

NC_DDCCLK_AUX7P
NC_DDCDATA_AUX7N

2160809000A11SEYMOU_FCBGA962

AM26
AN26

VGA_HDMI_SCLK
VGA_HDMI_SDATA

L78
BLM18AG121SN1D_0603
1
+1.8VSG
VGA@

120ohm/0.3A

+3VSG

VGA_CRT_CLK
VGA_CRT_DATA

VGA@ R33
VGA@ R34

1
1

2 10K_0402_5%
2 10K_0402_5%

VGA_CRT_R
VGA_CRT_G
VGA_CRT_B

VGA@ R35
VGA@ R36
VGA@ R37

1
1
1

2 150_0402_1%
2 150_0402_1%
2 150_0402_1%

Change 0603 size


For DVT

2
VGA@
L79
BLM18AG121SN1D_0603
2
1
+1.8VSG
VGA@

120ohm/0.3A

NC on Whistler and Seymour

2
VGA@

2
VGA@

VGA@
1

VGA@
1

VGA_HDMI_SCLK <11>
VGA_HDMI_SDATA <11>

+3VSG

In Whistler and Seymour, change to


GENLK_CLK, GENLK_VSYNC for
Global Swap Lock on multiple GPUs

+1.8VSG

Except A2VSSQ change to TSVSSQ,


others are NC on Whistler and Seymour

HDMI

AM27
AL27
AM19
AL19
AN20
AM20
AL30
AM30

NC on Park,
Robson and Seymour

AL29
AM29
AN21
AM21

VGA_CRT_CLK
VGA_CRT_DATA

VGA_CRT_CLK <12>
VGA_CRT_DATA <12>

CRT

AJ30
AJ31
AK30
AK29

Issued Date

2
VGA@

VGA@
1

NC on Park,
Robson and Seymour

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Seymour@

2
VGA@

2
VGA@

2
VGA@

AF33

XO_IN
XO_IN2

10mil

+A2VDD

AUX1P
AUX1N

20mA

<12>
<12>

499_0402_1%

2
VGA@

AC30
AC31

75mA

THERMAL

10mil

AG33

PLL/CLOCK
DPLL_VDDC

DPLUS
DMINUS

VGA_CRT_R

AE36
AD35

130mAA2VDD/NC

R2SET/NC
DPLL_PVDD
DPLL_PVSS

AD39
AD37

2010/08/20

Deciphered Date

2011/08/20

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

1
R8
VGA@

Title

Vancouver_Strape/DP/HDMI//CRT
Size
Document Number
Custom

Rev
1.0

LA-7092P P5WE6/H6/S6

Date:
5

THM_ALERT#

VGA@

R10
4.7K_0402_5%
VGA@

AU20
AT19

+VDD1DI

VREFG

TSVDD
TSVSS

VGA_SMB_CK2

AT17
AR16

AG31
AG32

100mAVDD2DI/NC

DDCCLK_AUX3P
DDCDATA_AUX3N
AF29
AG29

AU16
AV15

DAC2

DDC/AUX
AN31

2
AW34
0_0402_5%
2
AW35
0_0402_5%

GPU_THERM_D+
GPU_THERM_D-

120ohm/0.3A

C35
VGA@
18P_0402_50V8J

HPD1

G
GB

125mA

AL31 Manhattan/Vancouver is NC, Boardway is


ADC input(0-1V) use measure regulator current or temperature

VGA@

10mil

+1.8VSG

XTALOUT

Y1

2
VGA@

VSS

M25P10-AVMN6P
C31
@
0.1U_0402_16V4Z

1M_0603_5%

2
VGA@

ALERT#

C23
10U_0603_6.3V6M

+1.0VSG
L4
BLM18AG121SN1D_0603
2
1
VGA@

2
VGA@

R9
4.7K_0402_5%
VGA@

C20
10U_0603_6.3V6M

470ohm/1A

AM32
AN32

D-

Not share via for other GND


R
RB

10mil
+DPLL_PVDD

SDATA

VGA_SMB_CK2

SCLK

D+

+3VSG

AT15
AR14

C24
0.1U_0402_16V4Z

NC_TX4P_DPD1P
NC_TX4M_DPD1N

A2VSSQ/TSVSSQ

+1.8VSG

L3
BLM18AG121SN1D_0603
2
1
VGA@
1

AH13

VDD

+3VSG

AU14
AV13

C19
0.1U_0402_16V4Z

@
A

AK24

Address 1001 101X b

AT33
AU32

C22
1U_0402_6.3V4Z

@
2
1
R52
0_0402_5% 2

+VGA_VREF

C27
1U_0402_6.3V4Z

7
R51
0_0402_5%
@
2
1

DPD

NC_TX5P_DPD0P
NC_TX5M_DPD0N

15mil

2 VGA@
0.1U_0402_16V4Z

C30
1U_0402_6.3V4Z

+3VSG

2 249_0402_1%

C29
0.1U_0402_16V4Z

ROMSE_GPIO22

2 499_0402_1%

1 VGA@
C21

1 VGA@

R43

PD-Reset

C28
10U_0603_6.3V6M

R42

C26
0.1U_0402_16V4Z

+1.8VSG

Internal PD

C25
10U_0603_6.3V6M

NC_TX3P_DPD2P
NC_TX3M_DPD2N

VSS2DI/NC
VRAM_ID0
VRAM_ID1
VRAM_ID2
VRAM_ID3

U5
CLK_GPIO10

NC_TXCDP_DPD3P
NC_TXCDM_DPD3N

FLASH ROM
SIN_GPIO9

VGA_HDMI_DET

<11> VGA_HDMI_DET

R47
10K_0402_5%

R46
10K_0402_5%

R45
10K_0402_5%

R44
10K_0402_5%

R41
10K_0402_5%

R40
10K_0402_5%

R39
10K_0402_5%

R38
10K_0402_5%
@

TX2P_DPC0P
TX2M_DPC0N

U4 VGA@
1

ADM1032ARMZ-2REEL_MSOP8

AR32
AT31

C18
1U_0402_6.3V4Z

NC on Park

+1.8VSG

TX1P_DPC1P
TX1M_DPC1N

SCL
SDA

DPC

AV31
AU30

C17
10U_0603_6.3V6M

Hynix
SA000041S40 Vega-die
H5TQ1G63DFR-11C

TX0P_DPC2P
TX0M_DPC2N

AR30
AT29

C52
10U_0603_6.3V6M

T1

<4 pcs>

TXCCP_DPC3P
TXCCM_DPC3N

GPU_THERM_D+
2200P_0402_50V7K
VGA@ 1
2
C11
GPU_THERM_D-

C14
10U_0603_6.3V6M

<size>

TX5P_DPB0P
TX5M_DPB0N

VGA_HDMI_TXD2+ <11>
VGA_HDMI_TXD2- <11>

C16
0.1U_0402_16V4Z

Hynix
SA000032420 Orion-die
H5TQ1G63BFR-12C

<vendor2>

TX4P_DPB1P
TX4M_DPB1N

AT27
AR26

1
C10
VGA@

HDMI

C13
0.1U_0402_16V4Z

GPU_VID0
THM_ALERT#

<pcs> 64MX16

DPB

VGA_HDMI_TXD1+ <11>
VGA_HDMI_TXD1- <11>

C15
1U_0402_6.3V4Z

VGA_ENBKL
SOUT_GPIO8
SIN_GPIO9
CLK_GPIO10
VGA_GPIO11
VGA_GPIO12
VGA_GPIO13

Location VRAM_ID3 VRAM_ID2 VRAM_ID1 VRAM_ID0


<vendor1>

TX3P_DPB2P
TX3M_DPB2N

VGA_HDMI_TXD0+ <11>
VGA_HDMI_TXD0- <11>

AU26
AV25

C12
1U_0402_6.3V4Z

AH20
AH18
AN16
AH23
AJ23
AH17
AJ17
AK17
AJ13
AH15
AJ16
AK16
AL16
AM16
AM14
AM13
AK14
AG30
AN14
AM17
AL13
AJ14
AK13
AN13
AM23
AN23
AK23
AL24
AM24
AJ19
AK19
AJ20
AK20
AJ24
AH26
AH24

VGA_GPIO5
<10> VGA_ENBKL
1
R29
VGA@
10K_0402_5%

Samsung
SA00004GS10 G-die
K4W1G1646G-BC11

TXCBP_DPB3P
TXCBM_DPB3N

I2C
AK26
AJ26

VGA_GPIO0
VGA_GPIO1
VGA_GPIO2

change VGA@ as DISO@


For PVT

<43> GPU_VID0

SWAPLOCKA
SWAPLOCKB

TX2P_DPA0P
TX2M_DPA0N

GENERAL PURPOSE I/O

GPIO_0 will use to control


PSI in the future product

VRAM

NC_DVPCNTL_MVP_0
NC_DVPCNTL_MVP_1
NC_DVPCNTL_0
NC_DVPCNTL_1
NC_DVPCNTL_2
NC_DVPCLK
DVPDATA_0
DVPDATA_1
DVPDATA_2
DVPDATA_3
DVPDATA_4
DVPDATA_5
DVPDATA_6
DVPDATA_7
DVPDATA_8
DVPDATA_9
DVPDATA_10
DVPDATA_11
DVPDATA_12
DVPDATA_13
DVPDATA_14
DVPDATA_15
DVPDATA_16
NC_DVPDATA_17
NC_DVPDATA_18
NC_DVPDATA_19
NC_DVPDATA_20
NC_DVPDATA_21
NC_DVPDATA_22
NC_DVPDATA_23

2 4.7K_0402_5%
2 4.7K_0402_5%

VGA_LCD_CLK
VGA_LCD_DAT

<10> VGA_LCD_CLK
<10> VGA_LCD_DAT

Robson (XT)/Seymour(XT)

TX1P_DPA1P
TX1M_DPA1N
AR8
AU8
AP8
AW8
AR3
AR1
AU1
AU3
AW3
AP6
AW5
AU5
AR6
AW6
AU6
AT7
AV7
AN7
AV9
AT9
AR10
AW10
AU10
AP10
AV11
AT11
AR12
AW12
AU12
AP12

AT25
AR24

+3VSG

Transmitter Power Saving Enable


0: 50% Tx output swing for mobile mode
1: full Tx output swing (Default setting for Desktop)

GPIO0

DPA

VGA_HDMI_TXC+ <11>
VGA_HDMI_TXC- <11>

TX_PWRS_ENB

TX0P_DPA2P
TX0M_DPA2N

MUTI GFX

AU24
AV23

VGA Disable determines


0: VGA Controller capacity enabled
1: The device will not be recognized as the systems VGA controller

GPIO9

TXCAP_DPA3P
TXCAM_DPA3N

0.1U_0402_16V4Z

VGA_DIS

External VGA Thermal Sensor


Don't have this strap on
Whistler and Seymour

VIP Device Strap Enable indicates to the software driver


V2SYNC
0: Driver would ignore the value sampled on VHAD_0 during reset
VIP_DEVICE_EN
(GENLK_VSYNC) 1: VHAD_0 to determine whether or not a VIP slave device

Pin Straps description <all internal PD>

Strap Name

Wednesday, November 24, 2010


1

Sheet

19

of

47

Robson,Seymour only support single channel


memory (channel B only)
D

D
U2D

DDR2
GDDR3/GDDR5
DDR3

K23
K19

NC_CASA0B
NC_CASA1B

K20
K17

NC_CSA0B_0
NC_CSA0B_1

K24
K27

NC_CSA1B_0
NC_CSA1B_1

M13
K16

NC_CKEA0
NC_CKEA1

K21
J20

NC_RASA0B
NC_RASA1B

NC_MVREFDA
NC_MVREFSA

J14
H14

L18
L20

NC_CLKA1
NC_CLKA1B

VGA@

+1.5VSG

R60
VGA@
40.2_0402_1%
MVREFSB

R61
VGA@
100_0402_1%

C40
VGA@

NC_WEA0B
NC_WEA1B

K26
L15

R66
R67
R69

2 VGA@
2 VGA@
2 VGA@

1 243_0402_1% M12
1 243_0402_1% M27
1 243_0402_1% AH12

MEM_CALRP1
NC_MEM_CALRP0
NC_MEM_CALRP2

NC_MAA0_8
NC_MAA1_8

H23
J19

TESTEN
2 VGA@ 1
R65
5.11K_0402_1%
TEST_MCLK
TEST_YCLK
C41
VGA@
0.1U_0402_16V4Z

GDDR5

NC_MEM_CALRN0
MEM_CALRN1
NC_MEM_CALRN2

2160809000A11SEYMOU_FCBGA962

MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
B_BA2
B_BA0
B_BA1

WCKB0_0/DQMB_0
WCKB0B_0/DQMB_1
WCKB0_1/DQMB_2
WCKB0B_1/DQMB_3
WCKB1_0/DQMB_4
WCKB1B_0/DQMB_5
WCKB1_1/DQMB_6
WCKB1B_1/DQMB_7
GDDR5/DDR2/GDDR3
EDCB0_0/QSB_0/RDQSB_0
EDCB0_1/QSB_1/RDQSB_1
EDCB0_2/QSB_2/RDQSB_2
EDCB0_3/QSB_3/RDQSB_3
EDCB1_0/QSB_4/RDQSB_4
EDCB1_1/QSB_5/RDQSB_5
EDCB1_2/QSB_6/RDQSB_6
EDCB1_3/QSB_7/RDQSB_7

H3
H1
T3
T5
AE4
AF5
AK6
AK5

DQMB#0
DQMB#1
DQMB#2
DQMB#3
DQMB#4
DQMB#5
DQMB#6
DQMB#7

F6
K3
P3
V5
AB5
AH1
AJ9
AM5

QSB0
QSB1
QSB2
QSB3
QSB4
QSB5
QSB6
QSB7

DDBIB0_0/QSB_0B/WDQSB_0
DDBIB0_1/QSB_1B/WDQSB_1
DDBIB0_2/QSB_2B/WDQSB_2
DDBIB0_3/QSB_3B/WDQSB_3
DDBIB1_0/QSB_4B/WDQSB_4
DDBIB1_1/QSB_5B/WDQSB_5
DDBIB1_2/QSB_6B/WDQSB_6
DDBIB1_3/QSB_7B/WDQSB_7

G7
K1
P1
W4
AC4
AH3
AJ8
AM3

QSB#0
QSB#1
QSB#2
QSB#3
QSB#4
QSB#5
QSB#6
QSB#7

T7
W7

ODTB0
ODTB1

ADBIB0/ODTB0
ADBIB1/ODTB1

AD28

TESTEN

AK10
AL10

CLKTESTA
CLKTESTB

DQMB#[0..7]

QSB[0..7]

L9
L8

CLKB0
CLKB0#

CLKB1
CLKB1B

AD8
AD7

CLKB1
CLKB1#

RASB0B
RASB1B

T10
Y10

RASB0#
RASB1#

CASB0B
CASB1B

W10
AA10

CASB0#
CASB1#

CSB0B_0
CSB0B_1

P10
L10

CSB0#_0

CSB1B_0
CSB1B_1

AD10
AC10

CSB1#_0

CKEB0
CKEB1

U10
AA11

CKEB0
CKEB1

WEB0B
WEB1B

N10
AB11

WEB0#
WEB1#

MAB0_8
MAB1_8

T8
W8

DRAM_RST

2160809000A11SEYMOU_FCBGA962

DQMB#[0..7]

<23>

<23>

<23>

ODTB0 <23>
ODTB1 <23>
CLKB0 <23>
CLKB0# <23>
CLKB1 <23>
CLKB1# <23>
RASB0# <23>
RASB1# <23>
CASB0# <23>
CASB1# <23>

CSB0#_0 <23>
CSB1#_0 <23>
CKEB0 <23>
CKEB1 <23>
WEB0# <23>
WEB1# <23>

VGA@
1

<23>

QSB#[0..7]

MAB13 <23>
R68

AH11

<23>

B_BA[0..2]

QSB[0..7]

QSB#[0..7]

CLKB0
CLKB0B

MVREFDB
MVREFSB

MAB[0..12]

B_BA[0..2]

VGA@
2

10_0402_5%
1

C43
120P_0402_50V8

1 243_0402_1%
L27
1 243_0402_1%
N12
1 243_0402_1% AG12

P8
T9
P9
N7
N8
N9
U9
U8
Y9
W9
AC8
AC9
AA7
AA8
Y8
AA9

R71
VGA@
5.11K_0402_1%

2 VGA@
2 VGA@
2 VGA@

MVREFDB
Y12
MVREFSB AA12

C42
VGA@
0.1U_0402_16V4Z

R62
R63
R64

MAB[0..12]

MAB0_0/MAB_0
MAB0_1/MAB_1
MAB0_2/MAB_2
MAB0_3/MAB_3
MAB0_4/MAB_4
MAB0_5/MAB_5
MAB0_6/MAB_6
MAB0_7/MAB_7
MAB1_0/MAB_8
MAB1_1/MAB_9
MAB1_2/MAB_10
MAB1_3/MAB_11
MAB1_4/MAB_12
MAB1_5/BA2
MAB1_6/BA0
MAB1_7/BA1

MVREFDA
MVREFSA

+1.5VSG

H27
G27

C38

0.1U_0402_16V4Z

NC_CLKA0
NC_CLKA0B

MVREFDB

DQB0_0/DQB_0
DQB0_1/DQB_1
DQB0_2/DQB_2
DQB0_3/DQB_3
DQB0_4/DQB_4
DQB0_5/DQB_5
DQB0_6/DQB_6
DQB0_7/DQB_7
DQB0_8/DQB_8
DQB0_9/DQB_9
DQB0_10/DQB_10
DQB0_11/DQB_11
DQB0_12/DQB_12
DQB0_13/DQB_13
DQB0_14/DQB_14
DQB0_15/DQB_15
DQB0_16/DQB_16
DQB0_17/DQB_17
DQB0_18/DQB_18
DQB0_19/DQB_19
DQB0_20/DQB_20
DQB0_21/DQB_21
DQB0_22/DQB_22
DQB0_23/DQB_23
DQB0_24/DQB_24
DQB0_25/DQB_25
DQB0_26/DQB_26
DQB0_27/DQB_27
DQB0_28/DQB_28
DQB0_29/DQB_29
DQB0_30/DQB_30
DQB0_31/DQB_31
DQB1_0/DQB_32
DQB1_1/DQB_33
DQB1_2/DQB_34
DQB1_3/DQB_35
DQB1_4/DQB_36
DQB1_5/DQB_37
DQB1_6/DQB_38
DQB1_7/DQB_39
DQB1_8/DQB_40
DQB1_9/DQB_41
DQB1_10/DQB_42
DQB1_11/DQB_43
DQB1_12/DQB_44
DQB1_13/DQB_45
DQB1_14/DQB_46
DQB1_15/DQB_47
DQB1_16/DQB_48
DQB1_17/DQB_49
DQB1_18/DQB_50
DQB1_19/DQB_51
DQB1_20/DQB_52
DQB1_21/DQB_53
DQB1_22/DQB_54
DQB1_23/DQB_55
DQB1_24/DQB_56
DQB1_25/DQB_57
DQB1_26/DQB_58
DQB1_27/DQB_59
DQB1_28/DQB_60
DQB1_29/DQB_61
DQB1_30/DQB_62
DQB1_31/DQB_63

VGA@

J21
G19

R57
VGA@
100_0402_1%

C5
C3
E3
E1
F1
F3
F5
G4
H5
H6
J4
K6
K5
L4
M6
M1
M3
M5
N4
P6
P5
R4
T6
T1
U4
V6
V1
V3
Y6
Y1
Y3
Y5
AA4
AB6
AB1
AB3
AD6
AD1
AD3
AD5
AF1
AF3
AF6
AG4
AH5
AH6
AJ4
AK3
AF8
AF9
AG8
AG7
AK9
AL7
AM8
AM7
AK1
AL4
AM6
AM1
AN4
AP3
AP1
AP5

GDDR5

C39
0.1U_0402_16V4Z

R59
VGA@
100_0402_1%

NC_ADBIA0/ODTA0
NC_ADBIA1/ODTA1

R56
VGA@
40.2_0402_1%

MVREFSA

R58
VGA@
40.2_0402_1%

NC_DDBIA0_0/QSA_0B/WDQSA_0
NC_DDBIA0_1/QSA_1B/WDQSA_1
NC_DDBIA0_2/QSA_2B/WDQSA_2
NC_DDBIA0_3/QSA_3B/WDQSA_3
NC_DDBIA1_0/QSA_4B/WDQSA_4
NC_DDBIA1_1/QSA_5B/WDQSA_5
NC_DDBIA1_2/QSA_6B/WDQSA_6
NC_DDBIA1_3/QSA_7B/WDQSA_7

C34
D29
D25
E20
E16
E12
J10
D7

0.1U_0402_16V4Z

+1.5VSG

A34
E30
E26
C20
C16
C12
J11
F8

+1.5VSG

VGA@

NC_WCKA0_0/DQMA_0
NC_WCKA0B_0/DQMA_1
NC_WCKA0_1/DQMA_2
NC_WCKA0B_1/DQMA_3
NC_WCKA1_0/DQMA_4
NC_WCKA1B_0/DQMA_5
NC_WCKA1_1/DQMA_6
NC_WCKA1B_1/DQMA_7
GDDR5/DDR2/GDDR3
NC_EDCA0_0/QSA_0/RDQSA_0
NC_EDCA0_1/QSA_1/RDQSA_1
NC_EDCA0_2/QSA_2/RDQSA_2
NC_EDCA0_3/QSA_3/RDQSA_3
NC_EDCA1_0/QSA_4/RDQSA_4
NC_EDCA1_1/QSA_5/RDQSA_5
NC_EDCA1_2/QSA_6/RDQSA_6
NC_EDCA1_3/QSA_7/RDQSA_7

A32
C32
D23
E22
C14
A14
E10
D9

C37

G24
J23
H24
J24
H26
J26
H21
G21
H19
H20
L13
G16
J16
H16
J17
H17

NC_MAA0_0/MAA_0
NC_MAA0_1/MAA_1
NC_MAA0_2/MAA_2
NC_MAA0_3/MAA_3
NC_MAA0_4/MAA_4
NC_MAA0_5/MAA_5
NC_MAA0_6/MAA_6
NC_MAA0_7/MAA_7
NC_MAA1_0/MAA_8
NC_MAA1_1/MAA_9
NC_MAA1_2/MAA_10
NC_MAA1_3/MAA_11
NC_MAA1_4/MAA_12
NC_MAA1_5/MAA_13_BA2
NC_MAA1_6/MAA_14_BA0
NC_MAA1_7/MAA_A15_BA1

MDB0
MDB1
MDB2
MDB3
MDB4
MDB5
MDB6
MDB7
MDB8
MDB9
MDB10
MDB11
MDB12
MDB13
MDB14
MDB15
MDB16
MDB17
MDB18
MDB19
MDB20
MDB21
MDB22
MDB23
MDB24
MDB25
MDB26
MDB27
MDB28
MDB29
MDB30
MDB31
MDB32
MDB33
MDB34
MDB35
MDB36
MDB37
MDB38
MDB39
MDB40
MDB41
MDB42
MDB43
MDB44
MDB45
MDB46
MDB47
MDB48
MDB49
MDB50
MDB51
MDB52
MDB53
MDB54
MDB55
MDB56
MDB57
MDB58
MDB59
MDB60
MDB61
MDB62
MDB63

0.1U_0402_16V4Z

R55
VGA@
100_0402_1%

MDB[0..63]

<23> MDB[0..63]

MVREFDA

R54
VGA@
40.2_0402_1%
C

NC_DQA0_0/DQA_0
NC_DQA0_1/DQA_1
NC_DQA0_2/DQA_2
NC_DQA0_3/DQA_3
NC_DQA0_4/DQA_4
NC_DQA0_5/DQA_5
NC_DQA0_6/DQA_6
NC_DQA0_7/DQA_7
NC_DQA0_8/DQA_8
NC_DQA0_9/DQA_9
NC_DQA0_10/DQA_10
NC_DQA0_11/DQA_11
NC_DQA0_12/DQA_12
NC_DQA0_13/DQA_13
NC_DQA0_14/DQA_14
NC_DQA0_15/DQA_15
NC_DQA0_16/DQA_16
NC_DQA0_17/DQA_17
NC_DQA0_18/DQA_18
NC_DQA0_19/DQA_19
NC_DQA0_20/DQA_20
NC_DQA0_21/DQA_21
NC_DQA0_22/DQA_22
NC_DQA0_23/DQA_23
NC_DQA0_24/DQA_24
NC_DQA0_25/DQA_25
NC_DQA0_26/DQA_26
NC_DQA0_27/DQA_27
NC_DQA0_28/DQA_28
NC_DQA0_29/DQA_29
NC_DQA0_30/DQA_30
NC_DQA0_31/DQA_31
NC_DQA1_0/DQA_32
NC_DQA1_1/DQA_33
NC_DQA1_2/DQA_34
NC_DQA1_3/DQA_35
NC_DQA1_4/DQA_36
NC_DQA1_5/DQA_37
NC_DQA1_6/DQA_38
NC_DQA1_7/DQA_39
NC_DQA1_8/DQA_40
NC_DQA1_9/DQA_41
NC_DQA1_10/DQA_42
NC_DQA1_11/DQA_43
NC_DQA1_12/DQA_44
NC_DQA1_13/DQA_45
NC_DQA1_14/DQA_46
NC_DQA1_15/DQA_47
NC_DQA1_16/DQA_48
NC_DQA1_17/DQA_49
NC_DQA1_18/DQA_50
NC_DQA1_19/DQA_51
NC_DQA1_20/DQA_52
NC_DQA1_21/DQA_53
NC_DQA1_22/DQA_54
NC_DQA1_23/DQA_55
NC_DQA1_24/DQA_56
NC_DQA1_25/DQA_57
NC_DQA1_26/DQA_58
NC_DQA1_27/DQA_59
NC_DQA1_28/DQA_60
NC_DQA1_29/DQA_61
NC_DQA1_30/DQA_62
NC_DQA1_31/DQA_63

MEMORY INTERFACE A

+1.5VSG

C37
C35
A35
E34
G32
D33
F32
E32
D31
F30
C30
A30
F28
C28
A28
E28
D27
F26
C26
A26
F24
C24
A24
E24
C22
A22
F22
D21
A20
F20
D19
E18
C18
A18
F18
D17
A16
F16
D15
E14
F14
D13
F12
A12
D11
F10
A10
C10
G13
H13
J13
H11
G10
G8
K9
K10
G9
A8
C8
E8
A6
C6
E6
A5

DDR2
GDDR5/GDDR3
DDR3

DDR2
GDDR3/GDDR5
DDR3

MEMORY INTERFACE B

U2C

DDR2
GDDR5/GDDR3
DDR3

R70
2

MAB13 is for 128M*16 VRAM


VRAM_RST# <23>

51.1_0402_1%

VGA@

R72
VGA@
51.1_0402_1%

Seymour@

Seymour@

R73
VGA@
51.1_0402_1%

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2010/08/20

Deciphered Date

2011/08/20

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Vancouver_Memory
Size Document Number
Custom

Rev
1.0

LA-7092P P5WE6/H6/S6

Date:

Wednesday, November 24, 2010


1

Sheet

20

of

47

U2E

MEM I/O

2800mA
+1.5VSG

C347 VGA@
10U_0603_6.3V6M

C346 VGA@
1U_0402_6.3V4Z

C345 VGA@
1U_0402_6.3V4Z

+ C395
C394
VGA@
VGA@
390U_2.5V_10M 330U_D2_2V_Y
2
2

L39 VGA@
2
1
FBMA-L11-201209-121LMA50T_0805

+VDDCI

Issued Date

J7
2
@

Change 0603 size


For DVT
Compal Secret Data
2010/08/20

+VGA_CORE

2
1
FBMA-L11-201209-121LMA50T_0805

Deciphered Date

Compal Electronics, Inc.


2011/08/20

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

JUMP_43X118

L41 VGA@

C428 VGA@
10U_0603_6.3V6M

C427 VGA@
10U_0603_6.3V6M

C420 VGA@
1U_0402_6.3V4Z

Security Classification

Seymour@

C421 VGA@
10U_0603_6.3V6M

2160809000A11SEYMOU_FCBGA962

+BIF_VDDC

C426 VGA@
1U_0402_6.3V4Z

FB_GND

330U ESR:10m H:5.7


P/N:SF000002O00

C425 VGA@
1U_0402_6.3V4Z

FB_VDDCI

55mA

C424 VGA@
1U_0402_6.3V4Z

FB_VDDC

AG28

+VGA_CORE

C383 VGA@
1U_0402_6.3V4Z

C373 VGA@
1U_0402_6.3V4Z

C382 VGA@
1U_0402_6.3V4Z

C372 VGA@
1U_0402_6.3V4Z

C381 VGA@
1U_0402_6.3V4Z

C371 VGA@
1U_0402_6.3V4Z

Change 0603 size


For DVT

C423 VGA@
1U_0402_6.3V4Z

AF28

VGA@
390U_2.5V_10M
2

C393 VGA@
10U_0603_6.3V6M

C419 VGA@
1U_0402_6.3V4Z

SPVSS

C380 VGA@
1U_0402_6.3V4Z

C418 VGA@
1U_0402_6.3V4Z

AN10

C686 +

C370 VGA@
1U_0402_6.3V4Z

C392 VGA@
10U_0603_6.3V6M

C379 VGA@
1U_0402_6.3V4Z

C391 VGA@
10U_0603_6.3V6M

C390 VGA@
10U_0603_6.3V6M

C369 VGA@
1U_0402_6.3V4Z

C378 VGA@
1U_0402_6.3V4Z

C368 VGA@
1U_0402_6.3V4Z

C377 VGA@
1U_0402_6.3V4Z

SPV10

Change 0603 size


For DVT

C357 VGA@
10U_0603_6.3V6M

C356 VGA@
1U_0402_6.3V4Z

C355 VGA@
1U_0402_6.3V4Z

C367 VGA@
1U_0402_6.3V4Z

SPV18

AN9

FB_GND AH29
2
0_0402_5%

C422 VGA@
1U_0402_6.3V4Z

VGA@

1 R375

4A

AM10

VOLTAGE
SENESE
GCORE_SEN

C334 VGA@
1U_0402_6.3V4Z

AA13
AB13
AC12
AC15
AD13
AD16
M15
M16
M18
M23
N13
N15
N17
N20
N22
R12
R13
R16
T12
T15
V15
Y13

C417 VGA@
1U_0402_6.3V4Z

VDDCI#1
VDDCI#2
VDDCI#3
VDDCI#4
VDDCI#5
VDDCI#6
VDDCI#7
VDDCI#8
VDDCI#9
VDDCI#10
VDDCI#11
VDDCI#12
VDDCI#13
VDDCI#14
ISOLATED VDDCI#15
CORE I/O VDDCI#16
VDDCI#17
VDDCI#18
VDDCI#19
VDDCI#20
VDDCI#21
VDDCI#22

FBMA-L11-201209-221LMA30T_0805
2
1
+1.8VSG
L34 VGA@
1
1
220ohm/2A

FOR XT DDR3 13 A (RMS)/14.2 A(Peak)

C416 VGA@
1U_0402_6.3V4Z

120mA

MPV18#1
MPV18#2

Change 0603 size


For DVT

C415 VGA@
1U_0402_6.3V4Z

75mA

H7
H8

C344 VGA@
1U_0402_6.3V4Z

NC_VDDRHB
NC_VSSRHB

C389 VGA@
10U_0603_6.3V6M

V12
U12

C376 VGA@
1U_0402_6.3V4Z

NC_VDDRHA
NC_VSSRHA

C366 VGA@
1U_0402_6.3V4Z

M20
M21

C333 VGA@
1U_0402_6.3V4Z

VDDR4#1
VDDR4#2
VDDR4#3
VDDR4#6

C414 VGA@
0.1U_0402_16V4Z

+SPV10

75mA

C413 VGA@
0.1U_0402_16V4Z

2
1
L40
VGA@
BLM18AG121SN1D_0603

<43> GCORE_SEN

AD12
AF11
AF12
AG11

C328 VGA@
1U_0402_6.3V4Z

+MPV_18

470ohm/1A

VDDR4#4
VDDR4#5
VDDR4#7
VDDR4#8

C354 VGA@
1U_0402_6.3V4Z

C412 VGA@
1U_0402_6.3V4Z

+1.0VSG

AF13
AF15
AG13
AG15

PLL

C408 VGA@
10U_0603_6.3V6M

C411 VGA@
0.1U_0402_16V4Z

VDDR3#1
VDDR3#2
VDDR3#3
VDDR3#4

+1.0VSG
1

C388 VGA@
10U_0603_6.3V6M

C402 VGA@
0.1U_0402_16V4Z

C407 VGA@
0.1U_0402_16V4Z

C401 VGA@
1U_0402_6.3V4Z

C400 VGA@
10U_0603_6.3V6M

C406 VGA@
1U_0402_6.3V4Z

C405 VGA@
0.1U_0402_16V4Z

C404 VGA@
1U_0402_6.3V4Z

I/O
AF23
AF24
AG23
AG24

+VDDR4

+SPV_18
C410 VGA@
1U_0402_6.3V4Z

C409 VGA@
10U_0603_6.3V6M

BLM18AG121SN1D_0603
2
1
+1.8VSG
L38
VGA@
1
120ohm/0.3A

C403 VGA@
10U_0603_6.3V6M

C399 VGA@
0.1U_0402_16V4Z

170mA

120ohm/0.3A

+1.8VSG

VGA@

BLM18AG601SN1D_2P

C398 VGA@
1U_0402_6.3V4Z

L36
2

+1.8VSG

C397 VGA@
10U_0603_6.3V6M

BLM18AG121SN1D_0603
2
1
L37
VGA@
1
470ohm/1A

60mA

+VDDR3

+3VSG

Removed bead on ref137-12

VDD_CT#1
VDD_CT#2
VDD_CT#3
VDD_CT#4

2A

C387 VGA@
10U_0603_6.3V6M

AF26
AF27
AG26
AG27

C327 VGA@
1U_0402_6.3V4Z

219mA

C375 VGA@
1U_0402_6.3V4Z

C365 VGA@
1U_0402_6.3V4Z

LEVEL
TRANSLATION

AA15
AA17
AA20
AA22
AA24
AA27
AB16
AB18
AB21
AB23
AB26
AB28
AC17
AC20
AC22
AC24
AC27
AD18
AD21
AD23
AD26
AF17
AF20
AF22
AG16
AG18
AG21
AH22
AH27
AH28
M26
N24
N27
R18
R21
R23
R26
T17
T20
T22
T24
T27
U16
U18
U21
U23
U26
V17
V20
V22
V24
V27
Y16
Y18
Y21
Y23
Y26
Y28

POWER

C386 VGA@
0.1U_0402_16V4Z

120ohm/0.3A

C385 VGA@
1U_0402_6.3V4Z

C384 VGA@
10U_0603_6.3V6M

+VDD_CT

2
1
L35
VGA@
BLM18AG121SN1D_0603

VDDC#1
VDDC#2
VDDC#3
VDDC#4
VDDC#5
VDDC#6
VDDC#7
VDDC#8
VDDC#9
VDDC#10
VDDC#11
VDDC#12
VDDC#13
VDDC#14
VDDC#15
VDDC#16
VDDC#17
VDDC#18
VDDC#19
VDDC#20
VDDC#21
VDDC#22
VDDC#23
VDDC#24
VDDC#25
VDDC#26
VDDC#27
VDDC#28
VDDC#29
VDDC#30
VDDC#31
VDDC#32
VDDC/BIF_VDDC#33
VDDC#34
VDDC#35
VDDC#36
VDDC#37
VDDC#38
VDDC#39
VDDC#40
VDDC#41
VDDC/BIF_VDDC#42
VDDC#43
VDDC#44
VDDC#45
VDDC#46
VDDC#47
VDDC#48
VDDC#49
VDDC#50
VDDC#51
VDDC#52
VDDC#53
VDDC#54
VDDC#55
VDDC#56
VDDC#57
VDDC#58
CORE

+PCIE_VDDR
1

C374 VGA@
1U_0402_6.3V4Z

+1.8VSG

G30
G31
H29
H30
J29
J30
L28
M28
N28
R28
T28
U28

504mA

C364 VGA@
1U_0402_6.3V4Z

Change 0603 size


For DVT

PCIE_VDDC#1
PCIE_VDDC#2
PCIE_VDDC#3
PCIE_VDDC#4
PCIE_VDDC#5
PCIE_VDDC#6
PCIE_VDDC#7
PCIE_VDDC#8
PCIE_VDDC#9
PCIE_VDDC#10
PCIE_VDDC#11
PCIE_VDDC#12

AA31
AA32
AA33
AA34
V28
W29
W30
Y31
AB37

C332 VGA@
1U_0402_6.3V4Z

C363 VGA@
1U_0402_6.3V4Z

PCIE_VDDR#1
PCIE_VDDR#2
PCIE_VDDR#3
PCIE_VDDR#4
PCIE_VDDR#5
PCIE_VDDR#6
PCIE_VDDR#7
PCIE_VDDR#8
PCIE_VDDR/PCIE_PVDD

C343 VGA@
0.1U_0402_16V4Z

VDDR1#1
VDDR1#2
VDDR1#3
VDDR1#4
VDDR1#5
VDDR1#6
VDDR1#7
VDDR1#8
VDDR1#9
VDDR1#10
VDDR1#11
VDDR1#12
VDDR1#13
VDDR1#14
VDDR1#15
VDDR1#16
VDDR1#17
VDDR1#18
VDDR1#19
VDDR1#20
VDDR1#21
VDDR1#22
VDDR1#23
VDDR1#24
VDDR1#25
VDDR1#26
VDDR1#27
VDDR1#28
VDDR1#29
VDDR1#30
VDDR1#31
VDDR1#32
VDDR1#33
VDDR1#34

C353 VGA@
1U_0402_6.3V4Z

PCIE
AC7
AD11
AF7
AG10
AJ7
AK8
AL9
G11
G14
G17
G20
G23
G26
G29
H10
J7
J9
K11
K13
K8
L12
L16
L21
L23
L26
L7
M11
N11
P7
R11
U11
U7
Y11
Y7

C326 VGA@
0.1U_0402_16V4Z

C352VGA@
1U_0402_6.3V4Z

C362 VGA@
1U_0402_6.3V4Z

C342 VGA@
1U_0402_6.3V4Z

C351VGA@
1U_0402_6.3V4Z

C341 VGA@
1U_0402_6.3V4Z

C337 VGA@
1U_0402_6.3V4Z

C350VGA@
1U_0402_6.3V4Z

C325 VGA@
1U_0402_6.3V4Z

C361 VGA@
1U_0402_6.3V4Z

C331VGA@
1U_0402_6.3V4Z

C360 VGA@
10U_0603_6.3V6M

C330VGA@
1U_0402_6.3V4Z

C359 VGA@
10U_0603_6.3V6M

C336 VGA@
10U_0603_6.3V6M

C358 VGA@
10U_0603_6.3V6M

C335 MAN@
10U_0603_6.3V6M

C329VGA@
1U_0402_6.3V4Z

C349VGA@
1U_0402_6.3V4Z

C348VGA@
1U_0402_6.3V4Z

390U ESR:10m H:5.7


P/N:SF000002O00

C340 VGA@
1U_0402_6.3V4Z

C324 VGA@
1U_0402_6.3V4Z

C339 VGA@
1U_0402_6.3V4Z

C322
VGA@
390U_2.5V_10M

C338 VGA@
1U_0402_6.3V4Z

C323 VGA@
1U_0402_6.3V4Z

Title

Vancouver_Power/GND
Size Document Number
Custom

Rev
1.0

LA-7092P P5WE6/H6/S6

Date:

Wednesday, November 24, 2010


1

Sheet

21

of

47

U2F

U2H

DP C/D POWER

+1.8VSG

L42
VGA@
BLM18AG121SN1D_0603
2
1

470ohm/1A

150mA

+1.0VSG

110mA

+DPCD_VDD10

+DPCD_VDD10

+1.8VSG

AN19
AP18
AP19
AW20
AW22

PX_EN <24>

C443
VGA@
1U_0402_6.3V4Z

2
BACO@ 0_0402_5%

C442
VGA@
0.1U_0402_16V4Z

2
R378

AW18

+DPEF_VDD18

AH34
AJ34

+DPEF_VDD10

AL33
AM33

470ohm/1A
1

440mA

DP/DPA_VSSR#1
DP/DPA_VSSR#2
DP/DPA_VSSR#3
DP/DPA_VSSR#4
DP/DPA_VSSR#5

DPCD/DPD_VDD18#1
DPCD/DPD_VDD18#2

DPAB/DPB_VDD18#1
DPAB/DPB_VDD18#2

DPCD/DPD_VDD10#1
DPCD/DPD_VDD10#2

DPAB/DPB_VDD10#1
DPAB/DPB_VDD10#2

AN34
AP39
AR39
AU37

DP/DPD_VSSR#1
DP/DPD_VSSR#2
DP/DPD_VSSR#3
DP/DPD_VSSR#4
DP/DPD_VSSR#5

DPCD_CALR

DP/DPB_VSSR#1
DP/DPB_VSSR#2
DP/DPB_VSSR#3
DP/DPB_VSSR#4
DP/DPB_VSSR#5

DPAB_CALR

DP E/F POWER
DPEF/DPE_VDD18#1
DPEF/DPE_VDD18#2

DP PLL POWER
DPAB_VDD18/DPA_PVDD
DP_VSSR/DPA_PVSS

DPEF/DPE_VDD10#1
DPEF/DPE_VDD10#2

DPAB_VDD18/DPB_PVDD
DP_VSSR/DPB_PVSS

DP/DPE_VSSR#1
DP/DPE_VSSR#2
DP/DPE_VSSR#3
DP/DPE_VSSR#4

DPCD_VDD18/DPC_PVDD
DP_VSSR/DPC_PVSS

DPCD_VDD18/DPD_PVDD
DP_VSSR/DPD_PVSS
+DPEF_VDD18

+1.0VSG

L80
VGA@
BLM18AG121SN1D_0603
2
1

470ohm/1A

AF34
AG34

DPEF/DPF_VDD18#1
DPEF/DPF_VDD18#2
DPEF_VDD18/DPE_PVDD
DP_VSSR/DPE_PVSS

+DPEF_VDD10

AK33
AK34

+DPAB_VDD10

AN27
AP27
AP28
AW24
AW26

AP25
AP26

AF39
AH39
AK39
AL34
AM34
R379
2 VGA@ 1 AM39

+1.8VSG

+DPAB_VDD18

+DPAB_VDD10

AN33
AP33

220mA

AN29
AP29
AP30
AW30
AW32

L66
VGA@
BLM18AG121SN1D_0603
1
+1.0VSG

470ohm/1A

R377
150_0402_1%
1 VGA@ 2

AW28

AU28
AV27

+DPAB_VDD18

AV29
AR28

+DPAB_VDD18

AU18
AV17

+DPCD_VDD18

AV19
AR18

+DPCD_VDD18

AM37
AN38

+DPEF_VDD18

AL38
AM35

+DPEF_VDD18

DP/DPF_VSSR#1
DP/DPF_VSSR#2
DP/DPF_VSSR#3
DP/DPF_VSSR#4
DP/DPF_VSSR#5

DPEF_CALR

150_0402_1%
2160809000A11SEYMOU_FCBGA962

Seymour@

VSS_MECH#1
VSS_MECH#2
VSS_MECH#3

A39
AW1
AW39

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2010/08/20

2011/08/20

Deciphered Date

Title

Vancouver_Power/GND

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2160809000A11SEYMOU_FCBGA962

Rev
1.0

LA-7092P P5WE6/H6/S6

Seymour@

Date:

470ohm/1A

DPEF/DPF_VDD10#1
DPEF/DPF_VDD10#2
DPEF_VDD18/DPF_PVDD
DP_VSSR/DPF_PVSS

C446 VGA@
1U_0402_6.3V4Z

C445 VGA@
0.1U_0402_16V4Z

C444 VGA@
10U_0603_6.3V6M

240mA

AP31
AP32

R376
150_0402_1%
2 VGA@ 1
L67
VGA@
BLM18AG121SN1D_0603
2
1

AP14
AP15

DP/DPC_VSSR#1
DP/DPC_VSSR#2
DP/DPC_VSSR#3
DP/DPC_VSSR#4
DP/DPC_VSSR#5

DPAB/DPA_VDD10#1
DPAB/DPA_VDD10#2

C440
VGA@
10U_0603_6.3V6M

AP22
AP23

DPCD/DPC_VDD10#1
DPCD/DPC_VDD10#2

C439
VGA@
1U_0402_6.3V4Z

AP13
AT13
AN17
AP16
AP17
AW14
AW16

C437 VGA@
1U_0402_6.3V4Z

C436 VGA@
0.1U_0402_16V4Z

+DPAB_VDD18

C438
VGA@
0.1U_0402_16V4Z

470ohm/1A

DPAB/DPA_VDD18#1
DPAB/DPA_VDD18#2

L63
VGA@
BLM18AG121SN1D_0603
2
1

300mA
1

+DPCD_VDD18
L64
VGA@
BLM18AG121SN1D_0603
2
1

DPCD/DPC_VDD18#1
DPCD/DPC_VDD18#2

AN24
AP24

C434 VGA@
1U_0402_6.3V4Z

+DPCD_VDD18

DP A/B POWER

C433 VGA@
0.1U_0402_16V4Z

AP20
AP21

C432 VGA@
10U_0603_6.3V6M

C431 VGA@
1U_0402_6.3V4Z

C430 VGA@
0.1U_0402_16V4Z

GND
GND#100
GND#101
GND#102
GND#103
GND#104
GND#105
GND#106
GND#107
GND#108
GND#109
GND#110
GND#111
GND#112
GND#113
GND#114
GND#115
GND#116
GND#117
GND#118
GND#119
GND#120
GND#121
GND#122
GND#123
GND#124
GND#125
GND#126
GND#127
GND#128
GND#129
GND#130
GND#131
GND#132
GND#133
GND#134
GND#135
GND#136
GND#137
GND#138
GND#139
GND#140
GND#141
GND#142
GND#143
GND#144
GND#145
GND#146
GND#147
GND#148
GND#149
GND#150
GND#151
GND#153
GND#154
GND#155
GND#156
GND#157
GND#158
GND#159
GND#160
GND#161
GND#163
GND#164
GND#165
GND#166
GND#167
GND#168
GND#169
GND#170
GND#171
GND#172
GND#173
GND#174
GND#175
GND#152
GND#162

A3
A37
AA16
AA18
AA2
AA21
AA23
AA26
AA28
AA6
AB12
AB15
AB17
AB20
AB22
AB24
AB27
AC11
AC13
AC16
AC18
AC2
AC21
AC23
AC26
AC28
AC6
AD15
AD17
AD20
AD22
AD24
AD27
AD9
AE2
AE6
AF10
AF16
AF18
AF21
AG17
AG2
AG20
AG22
AG6
AG9
AH21
AJ10
AJ11
AJ2
AJ28
AJ6
AK11
AK31
AK7
AL11
AL14
AL17
AL2
AL20
AL21
AL23
AL26
AL32
AL6
AL8
AM11
AM31
AM9
AN11
AN2
AN30
AN6
AN8
AP11
AP7
AP9
AR5
B11
B13
B15
B17
B19
B21
B23
B25
B27
B29
B31
B33
B7
B9
C1
C39
E35
E5
F11
F13

C441
VGA@
10U_0603_6.3V6M

GND#1
GND#2
GND#3
GND#4
GND#5
GND#6
GND#7
GND#8
GND#9
GND#10
GND#11
GND#12
GND#13
GND#14
GND#15
GND#16
GND#17
GND#18
GND#19
GND#20
GND#21
GND#22
GND#23
GND#24
GND#25
GND#26
GND#27
GND#28
GND#29
GND#30
GND#31
GND#32
GND#33
GND#34
GND#35
GND#36
GND#37
GND#38
GND#39
GND#40
GND#41
GND#42
GND#43
GND#44
GND#45
GND#46
GND#47
GND#48
GND#49
GND#50
GND#51
GND#52
GND#53
GND#54
GND#55
GND#56
GND#57
GND#58
GND#59
GND#60
GND/PX_EN#61
GND#62
GND#63
GND#64
GND#65
GND#66
GND#67
GND#68
GND#69
GND#70
GND#71
GND#72
GND#73
GND#74
GND#75
GND#76
GND#77
GND#78
GND#79
GND#80
GND#81
GND#82
GND#83
GND#84
GND#85
GND#86
GND#87
GND#88
GND#89
GND#90
GND#91
GND#92
GND#93
GND#94
GND#95
GND#96
GND#97
GND#98

C435 VGA@
10U_0603_6.3V6M

F15
F17
F19
F21
F23
F25
F27
F29
F31
F33
F7
F9
G2
G6
H9
J2
J27
J6
J8
K14
K7
L11
L17
L2
L22
L24
L6
M17
M22
M24
N16
N18
N2
N21
N23
N26
N6
R15
R17
R2
R20
R22
R24
R27
R6
T11
T13
T16
T18
T21
T23
T26
U15
U17
U2
U20
U22
U24
U27
U6
V11
V16
V18
V21
V23
V26
W2
W6
Y15
Y17
Y20
Y22
Y24
Y27
U13
@
1
2
V13
R455 0_0603_5%

PCIE_VSS#1
PCIE_VSS#2
PCIE_VSS#3
PCIE_VSS#4
PCIE_VSS#5
PCIE_VSS#6
PCIE_VSS#7
PCIE_VSS#8
PCIE_VSS#9
PCIE_VSS#10
PCIE_VSS#11
PCIE_VSS#12
PCIE_VSS#13
PCIE_VSS#14
PCIE_VSS#15
PCIE_VSS#16
PCIE_VSS#17
PCIE_VSS#18
PCIE_VSS#19
PCIE_VSS#20
PCIE_VSS#21
PCIE_VSS#22
PCIE_VSS#23
PCIE_VSS#24
PCIE_VSS#25
PCIE_VSS#26
PCIE_VSS#27
PCIE_VSS#28
PCIE_VSS#29
PCIE_VSS#30
PCIE_VSS#31
PCIE_VSS#32
PCIE_VSS#33
PCIE_VSS#34
PCIE_VSS#35

C429 VGA@
10U_0603_6.3V6M

AB39
E39
F34
F39
G33
G34
H31
H34
H39
J31
J34
K31
K34
K39
L31
L34
M34
M39
N31
N34
P31
P34
P39
R34
T31
T34
T39
U31
U34
V34
V39
W31
W34
Y34
Y39

Wednesday, November 24, 2010

Sheet
1

22

of

47

U6
VREFCB_A1 M8
VREFDB_Q1 H1
MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
MAB13

<20> B_BA0
<20> B_BA1
<20> B_BA2

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

E3
F7
F2
F8
H3
H8
G2
H7

MDB26
MDB28
MDB27
MDB31
MDB25
MDB30
MDB24
MDB29

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

D7
C3
C8
C2
A7
A2
B8
A3

MDB15
MDB10
MDB12
MDB11
MDB13
MDB9
MDB14
MDB8

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

B2
D9
G7
K2
K8
N1
N9
R1
R9

VREFCA
VREFDQ

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

M2
N8
M3

BA0
BA1
BA2

CLKB0
CLKB0#
<20> CKEB0
<20> MAB[13..0]

ODTB0_1
<20>
<20>
<20>
<20>

<20> DQMB#[7..0]

CSB0#_0
RASB0#
CASB0#
WEB0#

J7
K7
K9

CK
CK
CKE/CKE0

K1
L2
J3
K3
L3

ODT/ODT0
CS/CS0
RAS
CAS
WE

QSB3
QSB1

F3
C7

DQMB#3
DQMB#1

E7
D3

QSB#3
QSB#1

G3
B7

VREFCB_A2 M8
VREFDB_Q2 H1
MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
MAB13

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

B_BA0
B_BA1
B_BA2

M2
N8
M3

BA0
BA1
BA2

CLKB0
CLKB0#
CKEB0

J7
K7
K9

CK
CK
CKE/CKE0

K1
L2
J3
K3
L3

ODT/ODT0
CS/CS0
RAS
CAS
WE

DQSL
DQSU

ODTB0_1
CSB0#_0
RASB0#
CASB0#
WEB0#

A1
A8
C1
C9
D2
E9
F1
H2
H9

VREFCA
VREFDQ
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

+1.5VSG

QSB2
QSB0

F3
C7

DQMB#2
DQMB#0

E7
D3

QSB#2
QSB#0

G3
B7

U8

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

+1.5VSG

MDB[0..63]

<20> MDB[0..63]

U7
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

E3
F7
F2
F8
H3
H8
G2
H7

MDB22
MDB20
MDB21
MDB18
MDB19
MDB17
MDB23
MDB16

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

D7
C3
C8
C2
A7
A2
B8
A3

MDB1
MDB6
MDB0
MDB4
MDB3
MDB7
MDB2
MDB5

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

B2
D9
G7
K2
K8
N1
N9
R1
R9

VREFCB_A3 M8
VREFDB_Q3 H1
MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
MAB13

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

B_BA0
B_BA1
B_BA2

M2
N8
M3

BA0
BA1
BA2

CLKB1
CLKB1#

J7
K7
K9

CK
CK
CKE/CKE0

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

K1
L2
J3
K3
L3

ODT/ODT0
CS/CS0
RAS
CAS
WE

DQSL
DQSU

<20> CKEB1
ODTB1_1

A1
A8
C1
C9
D2
E9
F1
H2
H9

<20>
<20>
<20>
<20>

CSB1#_0
RASB1#
CASB1#
WEB1#
QSB4
QSB5

F3
C7

DQMB#4
DQMB#5

E7
D3

QSB#4
QSB#5

G3
B7

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

E3
F7
F2
F8
H3
H8
G2
H7

MDB35
MDB37
MDB34
MDB39
MDB33
MDB38
MDB32
MDB36

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

D7
C3
C8
C2
A7
A2
B8
A3

MDB44
MDB43
MDB47
MDB41
MDB45
MDB40
MDB46
MDB42

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

B2
D9
G7
K2
K8
N1
N9
R1
R9

VREFCA
VREFDQ

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

+1.5VSG

+1.5VSG

U9
VREFCB_A4 M8
VREFDB_Q4 H1
MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
MAB13

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

B_BA0
B_BA1
B_BA2

M2
N8
M3

BA0
BA1
BA2

CLKB1
CLKB1#
CKEB1

J7
K7
K9

CK
CK
CKE/CKE0

ODTB1_1
CSB1#_0
RASB1#
CASB1#
WEB1#

K1
L2
J3
K3
L3

ODT/ODT0
CS/CS0
RAS
CAS
WE

+1.5VSG

DQSL
DQSU

+1.5VSG

A1
A8
C1
C9
D2
E9
F1
H2
H9

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VREFCA
VREFDQ

QSB6
QSB7

F3
C7

DQMB#6
DQMB#7

E7
D3

QSB#6
QSB#7

G3
B7

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

E3
F7
F2
F8
H3
H8
G2
H7

MDB55
MDB49
MDB52
MDB50
MDB53
MDB48
MDB54
MDB51

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

D7
C3
C8
C2
A7
A2
B8
A3

MDB56
MDB59
MDB63
MDB62
MDB57
MDB61
MDB58
MDB60

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

B2
D9
G7
K2
K8
N1
N9
R1
R9

+1.5VSG

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

DQSL
DQSU

+1.5VSG

A1
A8
C1
C9
D2
E9
F1
H2
H9

<20> QSB[7..0]

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

RESET

L8

B1
B9
D1
D8
E2
E8
F9
G1
G9

ZQ/ZQ0

J1
L1
J9
L9

R81
VGA@
243_0402_1%

96-BALL
SDRAM DDR3
K4B1G1646E-HC12_FBGA96
X76@
+1.5VSG

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

R103 VGA@
56_0402_1%
2

R104 VGA@
56_0402_1%
2

VGA@ 2

VREFCB_A3
1

R78
VGA@
4.99K_0402_1%

C173
VGA@ 2

VREFDB_Q3
1

C172

VREFDB_Q2
1

R100
VGA@
4.99K_0402_1%

R89
VGA@
4.99K_0402_1%

C174
VGA@ 2

VGA@ 2

R98
VGA@
4.99K_0402_1%

R88
VGA@
4.99K_0402_1%

C171

VREFCB_A2
1

R97
VGA@
4.99K_0402_1%

1
2

R87
VGA@
4.99K_0402_1%

R90
VGA@
4.99K_0402_1%

VREFCB_A4
1

R101
VGA@
4.99K_0402_1%

C175
VGA@ 2

R102
VGA@
4.99K_0402_1%

VREFDB_Q4
1
C176
VGA@ 2

+1.5VSG
+1.5VSG
+1.5VSG

C197 VGA@
1U_0402_6.3V6K

+1.5VSG

C196 VGA@
1U_0402_6.3V6K

C195 VGA@
1U_0402_6.3V6K

C194 VGA@
1U_0402_6.3V6K

C193 VGA@
1U_0402_6.3V6K

C192 VGA@
1U_0402_6.3V6K

C191 VGA@
1U_0402_6.3V6K

C190 VGA@
1U_0402_6.3V6K

C189 VGA@
1U_0402_6.3V6K

C188 VGA@
1U_0402_6.3V6K

C187 VGA@
1U_0402_6.3V6K

C186 VGA@
1U_0402_6.3V6K

C185 VGA@
1U_0402_6.3V6K

C184 VGA@
1U_0402_6.3V6K

C183 VGA@
1U_0402_6.3V6K

C182 VGA@
1U_0402_6.3V6K

C181 VGA@
1U_0402_6.3V6K

C180 VGA@
1U_0402_6.3V6K

C179 VGA@
1U_0402_6.3V6K

+1.5VSG

Compal Electronics, Inc.

Compal Secret Data

Security Classification
Issued Date

C206 VGA@
10U_0603_6.3V6M

C205 VGA@
10U_0603_6.3V6M

C204 VGA@
10U_0603_6.3V6M

VRAM P/N :
Samsung : SA00004GS10 (S IC D3 64M16 K4W1G1646G-BC11 FBGA) 900MHz
Hynix : SA000032420 (S IC D3 64MX16 H5TQ1G63BFR-12C FBGA 1.5V )800MHz
Hynix : SA000041S40 ( S IC D3 64MX16 H5TQ1G63DFR-11C FBGA )900MHz

C203 VGA@
10U_0603_6.3V6M

C202 VGA@
10U_0603_6.3V6M

C201 VGA@
10U_0603_6.3V6M

C200 VGA@
10U_0603_6.3V6M

C199 VGA@
10U_0603_6.3V6M

<20> CLKB1#

R106 VGA@
56_0402_1%
1
2

C198 VGA@
0.01U_0402_25V7K

<20> CLKB1

R105 VGA@
56_0402_1%
1
2

C178 VGA@
1U_0402_6.3V6K

+1.5VSG

C177 VGA@
0.01U_0402_25V7K

<20> CLKB0#

VGA@ 2

B1
B9
D1
D8
E2
E8
F9
G1
G9

0.1U_0402_16V4Z

<20> CLKB0

VGA@ 2

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

+1.5VSG

0.1U_0402_16V4Z

ODTB1_1

VREFDB_Q1
1
C170

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

+1.5VSG

0.1U_0402_16V4Z

R95
VGA@
4.99K_0402_1%

R96
VGA@
4.99K_0402_1%

ZQ/ZQ0

96-BALL
SDRAM DDR3
K4B1G1646E-HC12_FBGA96
X76@
+1.5VSG

0.1U_0402_16V4Z

<20> ODTB1

VREFCB_A1
1
C169

R86
VGA@
4.99K_0402_1%

0.1U_0402_16V4Z

R94 VGA@
56_0402_1%
2

0_0402_5%
VGA@
ODTB1 R93
0_0402_5%

R82
VGA@
243_0402_1%

RESET

+1.5VSG

0.1U_0402_16V4Z

R83
VGA@
4.99K_0402_1%

0.1U_0402_16V4Z

R92 VGA@
56_0402_1%
2

0.1U_0402_16V4Z

J1
L1
J9
L9

96-BALL
SDRAM DDR3
K4B1G1646E-HC12_FBGA96
X76@

R85
VGA@
4.99K_0402_1%

VGA@
ODTB0 R91

<20> ODTB0

R84
VGA@
4.99K_0402_1%

T2
L8

B1
B9
D1
D8
E2
E8
F9
G1
G9

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

+1.5VSG
ODTB0_1

VRAM_RST#

+1.5VSG

T2

96-BALL
SDRAM DDR3
K4B1G1646E-HC12_FBGA96
X76@
+1.5VSG

+1.5VSG

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

VRAM_RST#

DQSL
DQSU

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

R80
VGA@
243_0402_1%

J1
L1
J9
L9

ZQ/ZQ0

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

B1
B9
D1
D8
E2
E8
F9
G1
G9

RESET

DQSL
DQSU

DML
DMU

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

R79
VGA@
243_0402_1%

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

L8

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

J1
L1
J9
L9

VRAM_RST# T2

DML
DMU

ZQ/ZQ0

DQSL
DQSU

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

RESET

L8

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

T2

DML
DMU

DQSL
DQSU

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

VRAM_RST#

<20> VRAM_RST#

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

<20> QSB#[7..0]

DML
DMU

2010/08/20

2011/08/20

Deciphered Date

Title

VRAM_DDR3 / Channel B

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
1.0

LA-7092P P5WE6/H6/S6

Date:

Wednesday, November 24, 2010

Sheet
1

23

of

47

Power Sequence of Whistler and Seymour

(JUMP form +3VS)

VGA_ON

10ms

VGA_PWR_ON

+3VSG

1.5_VDDC_PWREN

+VGA_CORE

+VGA_CORE

VDDCI

+1.5VSG

+1.5VSG

+1.0VSG

+1.0VSG

+1.8VSG

+1.8VSG

20ms

20ms

For PX sequence, >1mS delay is required between


PE_GPIO1 and VGA_PWR_ON

VGA Muxless with BACO Status Mapping table


Normal mode
BACO mode
PX_EN
0
1
1.5_VDDC_PWREN
1
0
VDDC_EN
1
0
1.0_EN
0
1
+3.3VSG
ON
ON
+1.8VSG
ON
ON
+1.0VSG
ON
ON
+VGA_CORE
ON
OFF
+1.5VSG
ON
OFF
+BIF_VDDC
+VGA_CORE
+1.0VSG

WOBACO@
R107 1
2 0_0402_5%
+3VS

PE_GPIO1
C

+3VS

R108 1

2 10K_0402_5% 1

BACO@

7
1

1
3

1
4

Q2
BACO@
2N7002_SOT23
+5VS

1 VAN@ 2
R170
0_0402_5%

For DVT 1011

30mil

+VGA_CORE
WOBACO@
1
2
R117
0_0805_5%

Change 0603 size


For DVT
2
G

VDDC_EN

C214
0.1U_0402_16V4Z
@

30mil

3
+VGA_CORE

Q9
PX@

1
BACO@

3
BACO@

+BIF_VDDC

Q7
AO3416_SOT23-3

Q8
AO3416_SOT23-3

2011/08/20

Title

AO3416 NMOS
Vgs(th)(Max)= 1V
Rds(on)(Max)= 22m ohm @Vgs=4.5V

2
G
2N7002_SOT23
S
3

VAN@2
1
R122
0_0402_5%
1 MAN@ 2
R123
0_0402_5%

1
1
C212
C239
BACO@
BACO@
10U_0603_6.3V6M
2
2 10U_0603_6.3V6M

2
G

VGA_PWR_ON <25,35>
2

MAN_GPIO1_DELAY

3
BACO@

For VGA Power on control

PX@ 2
1
R120
0_0402_5%

12

VAN_GPIO1_DELAY

2
14

O
G

1
BACO@

1.0_EN

2
G
2N7002_SOT23
S

VGA@
U11F
SN74LVC14APWLE_TSSOP14

14

13

2
C213
VGA@
0.1U_0402_16V4Z
1

10

20mil

1
2
1

Q5
AO3416_SOT23-3

AO3416_SOT23-3

PX@ 2
0_0402_5%

1
R121

C211
VGA@
2 0.1U_0402_16V4Z

VGA@
U11E
SN74LVC14APWLE_TSSOP14

+1.0VSG
R116
0_0402_5%
DISO@

<35> PE_GPIO1#

NC7SZ08P5X_NL_SC70-5

For DVT 1011

+3VALW

11
Q6
PX@

From +VGA_CORE regulator

+3VALW

R118
31.6K_0402_1%
@

1 MAN@ 2
R171
0_0402_5%

Q4

R119 PX@
10K_0402_1%
1
2

Y
A

MAN_GPIO1_DELAY

+3VS

<13,35> PE_GPIO1

14
I

O
7

C210
VGA@
0.1U_0402_16V4Z

1 BACO@ 2
2
R114
0_0402_5%
1

14
P
1 MAN@ 2
R115
0_0402_5%

<13,43> VGA_PWRGD

Q3A
BACO@
DMN66D0LDW-7_SOT363-6

Delay EC_PWROK 50ms

U12
BACO@

Q3B
BACO@
DMN66D0LDW-7_SOT363-6

1.5_VDDC_PWREN
VGA@
U11D
SN74LVC14APWLE_TSSOP14

VDDC_EN
1.0_EN

+3VALW

<31> INT_VGAPWR_ON

R113
BACO@
1K_0402_5%

+3VS

C209 BACO@
0.1U_0402_10V7K
2
1

VGA@
U11C
SN74LVC14APWLE_TSSOP14

+5VS

R112
BACO@
1K_0402_5%

VAN_GPIO1_DELAY

+3VALW

1.5_VDDC_PWREN <35,43>

14
I

C208
VGA@
0.1U_0402_16V4Z

VGA@
U11B
SN74LVC14APWLE_TSSOP14

1 VAN@ 2
R111
0_0402_5%

<31,35> VGA_ON

R110
5.11K_0402_1%
BACO@

1.5_VDDC_PWREN

14

VGA@
U11A
SN74LVC14APWLE_TSSOP14

Delay SUSP# 10ms

+3VALW

1 BACO@ 2
2
R77
0_0402_5% G

<22> PX_EN

NC7SZ08P5X_NL_SC70-5

VGA Power ON Circuit


+3VALW

VGA_PWR_ON

U10
BACO@

>1ms

C207 BACO@
0.1U_0402_10V7K
1
2

VGA_PWR_ON

VGA Power Enable Signal Mapping table


Graville
Whistler and Seymour
VGA_PWR_ON source signal INT_VGAPWR_ON VGA_ON
VGA_PWR_ON
SUSP#
+3.3VSG
VGA_PWR_ON
VGA_PWR_ON
+1.8VSG
VGA_PWR_ON
VGA_PWR_ON
+1.0VSG
+VDDCI
VGA_PWR_ON
Combine with +VGA_CORE
VGA_PWR_ON
1.5_VDDC_PWREN
+VGA_CORE
VGA_PWR_ON
1.5_VDDC_PWREN
+1.5VSG

VGA_PWR_ON

50ms

Ref CLK
INT_VGAPWR_ON
D

VGA_PWR_ON
1.5_VDDC_PWREN
+3.3VSG
+1.8VSG
+1.0VSG
+VGA_CORE
+1.5VSG
+BIF_VDDC

SUSP#
+3VSG

38ms

FCH_PWRGD

VGA Muxless and Dis only Status Mapping table


Muxless Power-saving GPU
Dis only
Muxless High performance GPU
1
1
0
1
1
0
ON
ON
OFF
ON
ON
OFF
ON
OFF
ON
ON
ON
OFF
ON
ON
OFF
+VGA_CORE
+VGA_CORE
OFF

Power Sequence of Granville

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2010/08/20

Deciphered Date

VGA power sequence and BACO

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
1.0

LA-7092P P5WE6/H6/S6

Date:

Wednesday, November 24, 2010

Sheet
1

24

of

47

+3.3VS TO +3.3VSG

1.05VS TO +1.0VSG

Change P/N SB548000210


+1.05VS

S
SSM3K7002FU_SC70-3

ACIN

<31,35,37> ACIN

4
2
D

2 VGA_PW R_ON#
G
Q11 VGA@
2N7002_SOT23

VGA_PW R_ON# 2 VGA@ 1


2
G
R131 100K_0402_5%
Q14
S
1
2N7002_SOT23
C223
VGA@
VGA@
2
0.1U_0603_25V7K

510K_0402_5%

VGA_PW R_ON# <35>

1.0VSG_GATE

@ R132
1

MAN@
2 VGA_PW R_ON#
G
Q12
2N7002_SOT23

R125
VGA@
470_0603_5%

2 VGA@ 1
R129 10K_0402_5%
1

MAN@
Q13

1
1
C215
VGA@
10U_0603_6.3V6M C217
2
2 VGA@
1U_0402_6.3V4Z

Change 0603 size


For DVT
+VSB

C218

VGA@ VGA@
2
2
10U_0603_6.3V6M 10U_0603_6.3V6M

R127
470_0603_5%
MAN@

10U_0603_6.3V6M
2

C222
MAN@
2
0.1U_0603_25V7K

C220

2
G

1
1

1
2
R128 33K_0402_5%
MAN@

MAN@
VGA_PW R_ON 1
2
10K_0402_5% R130

C216

MAN@
3VSG_GATE

R126
MAN@
100K_0402_5%

<24,35> VGA_PW R_ON

Change 0603 size


For DVT

C219 1
MAN@
0.1U_0603_25V7K
2
3VSG_GATE

Change 0603 size


For DVT

1 VAN@ 2
R124
0_0805_5%
Q10
SI2301CDS-T1-GE3_SOT23-3
MAN@
3
1

+1.0VSG
U13
VGA@
SI4800BDY-T1-GE3_SO8
8
1
7
2
6
3
5

+3VSG

+3VS

C221
VGA@
0.1U_0603_25V7K

2N7002_SOT23
VGA@
Q15

2
G

+1.8VS TO +1.8VSG

Change P/N SB548000210

2
1
1
C227
VGA@
10U_0603_6.3V6M C228
2
2 VGA@
1U_0402_6.3V4Z

Change 0603 size


For DVT
1.5_VDDC_PW REN#

<35>

+VSB

1.8VSG_GATE
2 VGA@ 1
R135 100K_0402_5%
D

VGA_PW R_ON# 2 VGA@ 1


2
G
R137 100K_0402_5%
Q18
S
1
2N7002_SOT23
C234
VGA@
VGA@
2
0.1U_0603_25V7K
ACIN 2
G

2 VGA_PW R_ON#
G
Q16 VGA@
2N7002_SOT23

C232
VGA@
0.1U_0603_25V7K

Q20
VGA@
2N7002_SOT23

VGA@
R140
C233
1.5_VDDC_PW REN# 2 VGA@ 1
VGA@
VGA@
2
G
R139 47K_0402_5%
510K_0402_5%
0.1U_0603_25V7K
2
Q19
S
1 2N7002_SOT23
C235
VGA@
D
0.1U_0603_25V7K
Q21
2
ACIN 2
VGA@
G
2N7002_SOT23
S

R134
VGA@
470_0603_5%

2 1.5_VDDC_PW REN#
G
Q17
2N7002_SOT23
VGA@

510K_0402_5%

VGA@ VGA@
2
2
10U_0603_6.3V6M 10U_0603_6.3V6M

@ R138
1

1.5VSG_GATE
1 VGA@ 2
R136
100K_0402_5%

+VSB
B

C229

Change 0603 size


For DVT

2
10U_0603_6.3V6M

C226
R133
VGA@
470_0603_5%

VGA@

C225
VGA@
1U_0402_6.3V4Z
2

10U_0603_6.3V6M

C231

C224
VGA@
10U_0603_6.3V6M
2

Change 0603 size


For DVT
1

+1.8VSG
U15
VGA@
SI4800BDY-T1-GE3_SO8
8
1
7
2
6
3
5

C230
VGA@

U14
VGA@
SI4800BDY-T1-GE3_SO8
8
1
7
2
6
3
5

Change 0603 size


For DVT

+1.5VSG

+1.5V

+1.8VS

Change P/N SB548000210

+1.5V TO +1.5VSG

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2010/08/20

Issued Date

Deciphered Date

2011/08/20

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

VGA DC Interface
Size
Document Number
Custom

Rev
1.0

LA-7092P P5WE6/H6/S6

Date: Monday, November 29, 2010

Sheet
1

25

of

47

U70
C907 1

<13> PCIE_FRX_DTX_P2

C908 1

0.1U_0402_16V4Z

0.1U_0402_16V4Z

PCIE_FRX_C_DTX_N0
PCIE_FRX_C_DTX_P0

<13> PCIE_FTX_C_DRX_N2

CLK_PCIE_LAN#
CLK_PCIE_LAN

<13> CLK_PCIE_LAN#
<13> CLK_PCIE_LAN
R909 1

<13,18,29> PLT_RST#

R1143 1
R1144 1

<14,29> FCH_PCIE_WAKE#
<31> EC_PME#

+3V_LAN
1
R1148
1
R1150
1
R1152

TX_P

36

RX_N

32
33

2 0_0402_5%
@

2 0_0402_5%
2 0_0402_5%

LAN_PME#

1
C1475

1
C1476

1
C1477

1
C1478

REFCLK_N
REFCLK_P

WAKE#

7
8

1
C1479

RX_P

8151@
LAN_CLKREQ#
1 R1155 2 0_0402_5% 1.8V_VDDCT_REG 4
<14> LAN_CLKREQ#
8152@
0.1U_0402_16V4Z 1
2 C1474
13
19
31
34
W=30mils
+1.1_AVDDL
6
1

41
C1480

LAN_X11

Y6
2

close to pin34

LAN_ACTIVITY
LAN_LINK#
LED2_CKR#

TRXN0
TRXP0
TRXN1
TRXP1
TRXN2
TRXP2
TRXN3
TRXP3

12
11
15
14
18
17
21
20

LAN_MDI0LAN_MDI0+
LAN_MDI1LAN_MDI1+
LAN_MDI2LAN_MDI2+
LAN_MDI3LAN_MDI3+

RBIAS

TEST_RST
TESTMODE

VDD33
LX

XTLO
XTLI

Close LAN chip

LAN_CLKREQ#
1
2
R1139 8152@ 0_0402_5%

LAN_MDI0LAN_MDI1+
LAN_MDI1LAN_MDI2+
LAN_MDI2LAN_MDI3+
LAN_MDI3-

1@

2 C1466 1000P_0402_50V7K

2 C1467 0.1U_0402_16V4Z

1@

2 C1468 1000P_0402_50V7K

VDDCT
CLKREQ#
DVDDL
DVDDL_REG
AVDDL
AVDDL
AVDDL
AVDDL
AVDDL_REG

AVDDH
AVDDH
AVDDH_REG

overclocking

0*

Un-overclocking

1*

SWR mod

2 C1469 0.1U_0402_16V4Z

LDO mode

1@

2 C1470 1000P_0402_50V7K

2 C1471 0.1U_0402_16V4Z

1@

2 C1472 1000P_0402_50V7K

2 C1473 0.1U_0402_16V4Z

LAN_LINK#
* default

8151@

8151@

R1146 keep away other singal (25mil)


1

1
LAN_ACTIVITY

R1140 49.9_0402_1%
1
2
R1142 49.9_0402_1%
1
2
R1145 49.9_0402_1%
1
2
R1147 49.9_0402_1%
1
2
R1149 49.9_0402_1%
1 8151@ 2
R1151 49.9_0402_1%
1 8151@ 2
R1153 49.9_0402_1%
1 8151@ 2
R1154 49.9_0402_1%
1 8151@ 2

LAN_MDI0+

R1146 2.37K_0402_1%
2
1

10

+3V_LAN

40

LX

W=40mils

W=40mils

+1.7V_VDDCT

W=40mils
L108

LX

+1.7V_VDDCT

4.7UH_PG031B-4R7MS_1.1A_20%
24
37

+1.1V_DVDDL

1
C1481

W=30mils

1
C1482

0.1U_0402_16V4Z
2
16 R1156 1 8151@ 2 0_0603_5% +2.7V_AVDDH
22
9

close to Lan pin5

1
C1484

C1483

1000P_0402_50V7K0.1U_0402_16V4Z
1
2

+2.7V_AVDDH

+1.1V_DVDDL

C1494
1

AR8152-AL1E

SA00003JW10

C1495

1U_0402_6.3V6K
2
2

close to pin6

close to Lan pin40

W=30mils

W=30mils

8152@

8151@

PN:SA00003LE30
PN:SA00003JW10

10U_0603_6.3V6M
2

W=30mils

U70

GND

AR8151-AL1B
AR8152-AL1E

close to pin31

close to pin19

38
39
23

AR8151-AL1A_QFN40_5X5

2
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1U_0402_6.3V6K
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z

close to pin13

LED_0
LED_1
LED_2

SMCLK
SMDATA

8151@ 2 8151@ 2
2

8151-AL1A

PERST#

28
27
LAN_X2
LAN_X1

Atheros

25
26

PLT_RST#
2
4.7K_0402_5%
LAN_PME#
2
4.7K_0402_5%
LAN_CLKREQ#
2
4.7K_0402_5%

TX_N

30

35

<13> PCIE_FTX_C_DRX_P2

29

Pin23 Function:
1.CLKREQ
2.AR8152L revA PH:

LAN_X2

1
C1496
2

0.1U_0402_16V4Z

<13> PCIE_FRX_DTX_N2

R1138 5.1K_0402_5%
1
2

0.1U_0402_16V4Z

C1487

C1488

C1489

C1497
1U_0402_6.3V6K 0.1U_0402_16V4Z
2
2

8151@
2

0.1U_0402_16V4Z
2

0.1U_0402_16V4Z

W=40mils

2
C1485
33P_0402_50V8K

25MHZ_20PF_7A25000012
C1486
33P_0402_50V8K

close to Lan pin9

close to Lan pin22

close to Lan pin16

close to Lan pin37

close to Lan pin24

+3V_LAN
+3VALW

Change Y6 P/N as SJ100003300

R1157 1

1A

2 0_0603_5%
C1490
1

Follow result by vender 10/11

C1491
1

C1492
1

C1493
1
JRJ45

10

R1159
8152@

close to Pin 1
BOTH_TST1284

SP050001X10

LAN_MDI0+
LAN_MDI0-

10
11
12

24
23
22

RJ45_MDI3+
RJ45_MDI3-

TCT2
TD2+
TD2-

MCT2
MX2+
MX2-

21
20
19

RJ45_MDI2+
RJ45_MDI2-

TCT3
TD3+
TD3-

MCT3
MX3+
MX3-

TCT4
TD4+
TD4-

MCT4
MX4+
MX4-

LAN_ACTIVITY

18
17
16

RJ45_MDI1+
RJ45_MDI1-

15
14
13

RJ45_MDI0+
RJ45_MDI0-

LAN_ACTIVITY
LAN_LINK#

LANGND

RJ45_MDI1+

RJ45_MDI2+

RJ45_MDI2-

RJ45_MDI1-

RJ45_MDI3+

RJ45_MDI3-

D51
PJDLC05C_SOT23-3
@

PR2+

R456
0_0805_5%

PR3+

PR2PR4+
PR4-

11

Yellow LED+

12

Yellow LEDSANTA_130451-K
CONN@

RJ45_GND

LANGND

1
1
@
@
C942
C939
L109
0.1U_0402_16V4Z 4.7U_0603_6.3V6K
2
2

D49
@
B88069X9231T203_4P5X3P2-2

100UH +-20% SSC0301101MCF 0.18A

40mil

40mil

RJ45_GND

C941
1000P_1206_2KV7K
@

Security Classification
@ 1
D48
Issued Date
B88069X9231T203_4P5X3P2-2

8151@

Populate when AR8151-AL1A

8152@

Populate when AR8152-AL1E

EMI Request for MP

Compal Secret Data


2010/08/20

2011/08/20

Deciphered Date

Title

Compal Electronics, Inc.


LAN AR8151 / AR8152

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
1.0

LA-7092P P5WE6/H6/S6

EMI Request for MP


5

PR3-

C940
1000P_1206_2KV7K

Place close to TCT pin

14
13

SHLD1
SHLD2

PR1-

R1161 511_0402_1%

PR1+

@
470P_0402_50V7K
2
D47
PJDLC05C_SOT23-3
@

close to pin7 close to pin10

2
C1499

R819
75_0402_1%
1000P_0402_50V7K 1000P_0402_50V7K 1000P_0402_50V7K 1000P_0402_50V7K
75_0402_1%
R820
8151@
1
1
1
1
1
1
1
1
1
C1503
C1504
C1505 C1506 C1507 C1508 C1509
C1510 C1511
@
@
8151@
@
8151@
@
@
R821
R822
1U_0402_6.3V6K
0.1U_0402_16V4Z 0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
75_0402_1% 75_0402_1%
2
2
2
2
2
2
2
2
2
8151@

close to pin4

RJ45_MDI0-

Green LED-

LAN_MDI1+
LAN_MDI1-

7
8
9

close to pin1

RJ45_MDI0+

EMI Request
for MP

Green LED+

LAN_MDI2+
LAN_MDI2-

4
5
6

MCT1
MX1+
MX1-

TCT1
TD1+
TD1-

1
2
3

350UH_IH-037-2
8151@

C1498
@
470P_0402_50V7K

LAN_MDI3+
LAN_MDI3-

+1.7V_VDDCT

0_0603_5%
1
2
R1160

511_0402_1%

T25

LAN_LINK#

2 0_0402_5%

T25

R1158 1

+3V_LAN

2
2
2
2
10U_0603_6.3V6M
1U_0402_6.3V6K
10U_0603_6.3V6M
0.1U_0402_16V4Z

Date:

Monday, November 29, 2010

Sheet
1

26

of

47

+5VS_AVDD

+3VS

R783
20K_0402_1%

D38

R789
10K_0402_5%

CH751H-40PT_SOD323-2

C936
1
1U_0402_6.3V4Z

R787

1 R786
2
15.4K_0402_1%

C952 1
1U_0402_6.3V4Z

<31> BEEP#

MONO_IN

Dos Beep issue for PVT 10/28

Q72

2
B

HD Audio Codec

560_0402_5%

2SC2411KT146_SOT23-3

R788

560_0402_5%

C946 1
1U_0402_6.3V4Z

<14> FCH_SPKR

D37
CH751H-40PT_SOD323-2

0_0603_5%
2

80mil

+3VS_DVDD
1
1
C1512 0.1U_0402_16V4Z
C1513
C1514
10U_0603_6.3V6M 0.1U_0402_16V4Z
2
2
2

Change 0603 size


For DVT

+3VS_AUX

10mil

2
34
41
42

+3VS_AUX

1
C1524

2
1U_0402_6.3V6K

Change 2.2u
For DVT
MIC1_L
MIC1_R

<28> MIC1_R

1
C1520

22

2.2U_0603_6.3V6K
MIC1_C_L
35

C932 1

MIC1_C_R
36
2.2U_0603_6.3V6K
37

+MIC1_BIASC

SPK_OUT_R+
PORTE_R
SPK_OUT_RPORTF_L
PORTB_L
PORTF_R
PORTB_R
FLY_P

16

SPKL-

19

SPKR+

SPKL+ <28>

SPKR-

39

MIC2_C_L C794 1

40

MIC2_C_R

1
C797

38

RESET#

11

HDA_RST_AUDIO#

HDA_BITCLK_AUDIO

R1168 10K_0402_5%

MONO_IN
1

<31> EC_MUTE#

JUMP_43X39 @
J2
1 1
2 2

JUMP_43X39 @
J5
1 1
2 2

JUMP_43X39 @
J3
1 1
2 2

JUMP_43X39 @
J6
1 1
2 2

JUMP_43X39 @

GND

JUMP_43X39

DMIC_CLK0
DMIC_1/2

C1528

2
0_0402_5%

+AVEE
1
C1529

44
43

SENSE A
SENSE B

47

GPIO0/EAPD#

48

SPDIFO

24
49

GPIO1/SPK_MUTE#
GPIO2/SPDIF2

FILT_1.8

AVEE

FILT_1.65

EP_GND

AVDD_3.3

Change 2.2u & 100ohm


For DVT

HDA_SDOUT_AUDIO <14>
HDA_SYNC_AUDIO

Port
Port
Port
Port
Port
Port
Port
Port
Port

HDA_RST_AUDIO# <14>
HDA_BITCLK_AUDIO <14>

L112 2

2 C948
22P_0402_50V8J

FBMA-10-100505-301T_2P
2

Pop For EMI 10/18

3
4

G1
G2

ACES_88266-02001
CONN@

D27 @
PJDLC05C_SOT23-3

A:
B:
C:
D:
E:
F:
G:
J:
H:

Headphone jack (jack shared with S/PDIF)


Internal MIC (mono or stereo)
Microphone/LI/LO jack
Line Out jack (Optional)
Line In jack (Optional)
Not used.
Internal stereo speakers
Internal stereo digital mic (Optional)
S/PDIF (jack shared with headphone)

46
45

10mil

30

1
C1525

+FILT_1.65V

32

10mil

+3VS_LDO_OUT

10mil
1
C1531

C1532

1
C1527

R1170

0.1U_0402_16V4Z 10U_0603_6.3V6M 10K_0402_5%


2
2
R1170 only needed if supply to VAUX_3.3 is
removed during system re-start.

1
C1530

1U_0603_10V6K
2

+FILT_1.8
1
C1526

0.1U_0402_16V4Z
2

Change 0603 size


For DVT

Change 0603 size


For DVT
Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2010/08/20

2011/08/20

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

GNDA
B

1
2

Port Configuration

<14>

0.1U_0402_16V4Z 10U_0603_6.3V6M
2
2

Change 0603 size


For DVT

1
1
220P_0402_50V7K 220P_0402_50V7K
@
@
C979
C980
2
2

1
2

HDA_SDIN0 <14>

CX20584-11Z_QFN48_7X7

GNDA GND
A

EXT_MUTE#

0.1U_0402_16V4Z
10U_0603_6.3V6M
2
2

J4

J1
2

12

15mil

SENSE_A

1
R796

<31> EAPD

PCBEEP

Mic issue For MP

EC_MUTE# change as Pin12

Sense resistors must be


connected same power
that is used for VAUX_3.3

2
0_0402_5%

R1169

DMIC_3/4

13

R797 2
0_0402_5%

INT_MIC
1
100_0402_1%

+MIC2_BIASC

HDA_SYNC_AUDIO

C_BIAS

C808
220P_0402_50V7K

SPKR- <28>
2 2.2U_0603_6.3V6K
INT_MIC_22
R523
2
2.2U_0603_6.3V6K

10

PORTC_R

SPKR+ <28>

17

R800 2
0_0402_5%

SPKL- <28>

BIT_CLK

MIC_PLUG# <28>

JMIC2
SPKL+

SYNC

SDATA_OUT
PORTC_L

INT_MIC1
14

1
2
R793
33_0402_5%
HDA_SDOUT_AUDIO

SDATA_IN

Close to Conn

INT_MIC

SPK_OUT_LPORTE_L

HP_PLUG# <28>

1
C1523

PORTD_R

FLY_N

1
C1522

Change 0603 size


For DVT

20

18

15

31

29

21

SPK_OUT_L+

B_BIAS
23

C934 1

PORTD_L

1
C1521

0.1U_0402_16V4Z
10U_0603_6.3V6M
2
2
2
2
0.1U_0402_16V4Z
10U_0603_6.3V6M

CLASSDREF

PORTA_R

RPWR5.0

26

LPWR5.0

PORTA_L

HP_RIGHT

AVDD_5V

25

AVDD_HP

HP_LEFT

33

<28> MIC1_L

40mil

28

R1166
5.11K_0402_1%

R585
2.2K_0402_5%

0.1U_0402_16V4Z
2
+CLASSD_REF

+3VS_AUX

27

+5VS

2
C1519

<28> HP_RIGHT

2
0_0603_5%

80mil

1
C1518
0.1U_0402_16V4Z
2

U82

1
R1164

1
C1516
1U_0402_6.3V6K
2

<28> HP_LEFT

SENSE_A

0_0603_5%
2

C1517
10U_0603_6.3V6M

DVDD_3.3

R1167
2
1
39.2K_0402_1%

R1162
1

+MIC2_BIASC

10U_0603_6.3V6M 0.1U_0402_16V4Z
2
2

+CLASSD_5V

VDD_IO

1
C1515
0.1U_0402_16V4Z

Change 0603 size


For DVT

+5VS_AVDD
1
C1210
C1211

0.1_1206_1%

VAUX_3.3

R1163

+3VS_AUX
2
0_0402_5%

1
R1165

+3VS

2
R1093
+3VS

Layout Note: Path from +5V to LPWR_5.0 and


RPWR_5.0 must be very low resistance ( <0.01 ohms).
Place bypass caps very close to device.

Change 0603 size


For DVT
20mil

HD Audio Codec CX20584


Document Number

Date:

Rev
1.0

LA-7092P P5WE6/H6/S6
Wednesday, November 24, 2010
G

Sheet

27
H

of

47

Int. Speaker Conn.


1

R834 1
R833 1

30mil

D39
2

C1533
C1534
@
1000P_0402_50V7K
1
1
1000P_0402_50V7K

1
2

1
2

3
4

G1
G2

Left

ACES_88266-02001
CONN@

JSPK2

SPK_L+
SPK_L-

2 0_0603_5%
2 0_0603_5%
2

SPKL+
SPKL-

<27> SPKL+
<27> SPKL-

PJDLC05C_SOT23-3

JSPK1
R831 1
R832 1

@
@

SPK_R+
SPK_R-

2 0_0603_5%
2 0_0603_5%
3

30mil
2

D41
@

C1535
C1536
@
1000P_0402_50V7K
1
1
1000P_0402_50V7K

1
2

3
4

G1
G2

Right

ACES_88266-02001
CONN@

1
2

SPKR+
SPKR-

<27> SPKR+
<27> SPKR-

PJDLC05C_SOT23-3

C779
330P_0402_50V7K

<27> HP_LEFT

R686
1

<27> HP_RIGHT

R685

HPOUT_L_1

2
39_0603_1%
2
39_0603_1%

HPOUT_R_1

1
L94
1
L93

C774

Headphone Out

330P_0402_50V7K
1

JHP1
1
2

HPOUT_L_2
2
FBMA-L11-160808-700LMT_2P
HPOUT_R_2
2
FBMA-L11-160808-700LMT_2P

3
4

<27> HP_PLUG#

HP_PLUG#

6
SINGA_2SJ-0960-C01
CONN@

MIC_PLUG#

<NAL00 use>

1 1

1 1

JMIC1

MIC1_R_R
1

C780
220P_0402_50V7K

1
2

MIC1_L_R

L89 1
2
FBMA-L11-160808-700LMT_2P
L90 1
2
FBMA-L11-160808-700LMT_2P

3
3

1
R695

MIC1_L_1
2
100_0603_1%
MIC1_R_1
2
100_0603_1%

MIC JACK

R693
3.01K_0402_1%

2
<27> MIC1_R

@
D24
PJDLC05C_SOT23-3

D42
CH751H-40PT_SOD323-2

R692
3.01K_0402_1%

R694

+MIC1_BIASC

D43
CH751H-40PT_SOD323-2

<27> MIC1_L

HP_PLUG#
+MIC1_BIASC

C781
220P_0402_50V7K

@
D29
<27> MIC_PLUG#

4
MIC_PLUG#

PJDLC05C_SOT23-3
6

SINGA_2SJ-A960-C01
CONN@

<NAL00 use>

2010/08/20

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2011/08/20

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Amplifier & Audio Jack


Document Number

Rev
1.0

LA-7092P P5WE6/H6/S6
Wednesday, November 24, 2010

Sheet
E

28

of

47

Mini-Express Card for WLAN


+3VS

+1.5VS

C705
4.7U_0603_6.3V6K

C706
0.1U_0402_16V4Z

C707
0.1U_0402_16V4Z

C708
4.7U_0603_6.3V6K

Change 0603 size


For DVT

C709
0.1U_0402_16V4Z

C710
0.1U_0402_16V4Z

Change 0603 size


For DVT
JMINI1

R440 1

2 0_0402_5%

<14> MINI1_CLKREQ#
<13> CLK_PCIE_MINI1#
<13> CLK_PCIE_MINI1

17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

<13> PCIE_FRX_DTX_N3
<13> PCIE_FRX_DTX_P3
<13> PCIE_FTX_C_DRX_N3
<13> PCIE_FTX_C_DRX_P3
+3VS

R445 1

E51TXD_P80DATA_R
E51RXD_P80CLK

1
3
5
7
9
11
13
15

2
4
6
8
10
12
14
16

17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

+3VS

53
54
55
56

Mini Card Power Rating


Power

WL_OFF#
PLT_RST#
+3V_WLAN

1
R441 1
R442
MINI1_SMBCLK
1
MINI1_SMBDAT
R443
1
R444

@
@
@

WL_OFF# <31>
PLT_RST# <13,18,26>
+3VS
+3VALW

2
2 0_0603_5%
0_0603_5%
2
0_0603_5%
2
0_0603_5%

FCH_SMCLK0
FCH_SMDAT0

USB20_N8
USB20_P8

Auxiliary Power (mA)

Peak

Normal

+3VS

1000

750

+3V

330

250

250 (wake enable)

+1.5VS

500

375

Normal

5 (Not wake enable)

<8,9,14>
<8,9,14>

<14>
<14>

WIMAX_LED#
WLAN_LED#_L

(MINI1_LED#)

+3VS

R835 1

+3VS
ACES_88910-5204
CONN@

WIMAX_LED#
@
1
R836

<NAV70 use>

2
10K_0402_5%

WLAN_LED#_L

0_0402_5%
2

R848
100K_0402_5%

2
1

MINI1_LED#

3
CHP202UPT_SOT323-3
D44 @
1
2
R837
0_0402_5%

Height : 4mm

Primary Power (mA)

2
R492
100K_0402_5%

+1.5VS

G1
G2
G3
G3

<31> E51TXD_P80DATA
<31> E51RXD_P80CLK

0_0402_5%
2

1
3
5
7
9
11
13
15

FCH_PCIE_WAKE#

<14,26> FCH_PCIE_WAKE#

<31>

(9~16mA)
2

Card Reader RTS5138 / RTS5137


(only SD+MMC function)
Card Reader Connector

R854

2 0_0805_5%

2
C981
R855 1

USB20_N6
USB20_P6

30mil
C984

1
0.1U_0402_16V4Z

RREF

+SDPWR_MMCPWR

+3VS_CR
+CARDPWR
VREG

10mil

C985
1U_0402_6.3V6K
XDDRY_SDWP_MSCLK
XDCE#_SDD1
XDCLE_SDD0

U84
1
2
3
4
5
6
7
8
9
10
11
12

5IN1_LED#

REFE
GPIO0
DM
DP

CLK_IN

3V3_IN
CARD_3V3
V18

XD_D7

XD_CD#
SP1
SP2
SP3
SP4
SP5

SP14
SP13
SP12
SP11
SP10
SP9
SP8
SP7
SP6

17

1
R856

24

2
10_0402_5%
CLK_SD_48M_R

5IN1_LED#
C982 1

<32>

2 10P_0402_50V8J

JCR1
XDD4_SDD3_MSD1
XDD2_SDCMD

@
2
R857

1
22_0402_5%

CLK_SD_48M

<13>

1
2
3
4
5
6

23
XDD0_SDCLK_MSD2
22
21
20
19
18
16
15
14
13

XDD5_SDD2_MS_D5
XDD4_SDD3_MSD1
XDD2_SDCMD

+CARDPWR

+SDPWR_MMCPWR

30mil

1
R858

XDD0_SDCLK_MSD2
XDWE#_SDCD#

RTS5138-GR_QFN24_4X4

2
0_0805_5%

XDCLE_SDD0
XDCE#_SDD1
XDD5_SDD2_MS_D5
XDDRY_SDWP_MSCLK
XDWE#_SDCD#

30mil

R859
100K_0402_5%

25

Change 0603 size


For DVT

30mil
10mil

1
100P_0402_50V8J
2
6.2K_0603_1%

<14> USB20_N6
<14> USB20_P6

C983
4.7U_0603_6.3V6K

+3VS_CR

7
8
9
10
11

D3
CMD
VSS1
VDD
CLK
VSS2
D0
D1
D2
WP
CD

+3VS

EPAD

C986
0.1U_0402_16V4Z

C987
0.1U_0402_16V4Z

C988
0.1U_0402_16V4Z

C987, C988 close to connector

Change to RTS5137 (SA000043500)

12
13

GND1
GND2
TAITW_PSDBTC09GLBS1N14N0
CONN@

Compal Secret Data

Security Classification
Issued Date

2010/08/20

Deciphered Date

2011/08/20

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title
Size

Document Number

Rev
1.0

LA-7092P P5WE6/H6/S6
Date:

Compal Electronics, Inc.


MINI CARD / CardReader RTS5137
Wednesday, November 24, 2010
E

Sheet

29

of

47

SATA HDD Conn.


JHDD1

<15> SATA_ITX_DRX_P0
<15> SATA_ITX_DRX_N0

SATA_DTX_C_IRX_N0
SATA_DTX_C_IRX_P0

<15> SATA_DTX_C_IRX_N0
<15> SATA_DTX_C_IRX_P0

1
2
3
4
5
6
7

SATA_ITX_DRX_P0
SATA_ITX_DRX_N0
C657 1
C659 1

2 0.01U_0402_16V7K
2 0.01U_0402_16V7K

SATA_DTX_IRX_N0
SATA_DTX_IRX_P0

GND
A+
AGND
BB+
GND

+3VS
1

R405 1

+5VS

0.1U_0402_16V4Z

+5VS_HDD

2 0_0805_5%
10U_0603_6.3V6M
C660

Change 0603 size


For DVT

C661

8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

+3VS
C639

0.1U_0402_16V4Z
1

C662

C663

1U_0402_6.3V4Z

V33
V33
V33
GND
GND
GND
V5
V5
V5
GND
Reserved
GND
V12
V12
V12

GND
GND

24
23

SANTA_192301-1
CONN@

1000P_0402_50V7K

<NAV70 use>

SATA ODD FFC Conn.


JODD1
<15> SATA_ITX_DRX_P1
<15> SATA_ITX_DRX_N1
SATA_DTX_IRX_N1
SATA_DTX_IRX_P1
ODD_DA#_FCH_R

C650 1
2 0.01U_0402_16V7K
C651 1
2 0.01U_0402_16V7K
R412 1
@
0_0402_5%
2
R403 1
@
0_0402_5%
2

80mils
+5VS

1
R955

+5VS_ODD
2
0_0805_5%

1
2
3
4
5
6
7
8
9
10
11
12

GND
GND

13
14

<15> SATA_DTX_C_IRX_N1
<15> SATA_DTX_C_IRX_P1
<14> ODD_DA#_FCH
<14> ODD_DETECT#

1
2
3
4
5
6
7
8
9
10
11
12

ACES_85201-1205N
CONN@

R413
0_0402_5%

+5VS

+5VS_ODD

R760
470K_0402_5%
@

@
1

D
Q66
SSM3K7002FU_SC70-3

S
1

2
G

1
@

C811
0.1U_0402_25V6K

<15> ODD_PWR

U40 @
SI4800BDY-T1-GE3_SO8
8
1
7
2
6
3
5

R764
1.5M_0402_5%

ODD_EN

C812
1U_0402_6.3V6K

+VSB

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2010/08/20

2011/08/20

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

HDD & ODD CONN


Document Number

Date:

Rev
1.0

LA-7092P P5WE6/H6/S6
Wednesday, November 24, 2010
G

Sheet

30
H

of

47

For EC Tools

+3VALW
L84

0.1U_0402_16V4Z
1 C725
1

0.1U_0402_16V4Z
1
2

C724

C726
KSO[0..17] <32>

KSI[0..7]

KSI[0..7]

2
2
0.1U_0402_16V4Z

2
2
0.1U_0402_16V4Z

C728
1000P_0402_50V7K
1
1

0.1U_0402_16V4Z

E51RXD_P80CLK
E51TXD_P80DATA

ACES_85205-0400
@

67

9
22
33
96
111
125

65W /90W #

AVCC

R458
VR_ON

@
R489
10K_0402_5%

TP_CLK
2
4.7K_0402_5%
TP_DATA
2
4.7K_0402_5%

1
R465
1
R466

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17

+3VALW +3VS

@
R852
0_0402_5%

@
R851
0_0402_5%

1
R467
1
R468

@
@

EC_SMB_CK2
2
2.2K_0402_5%
EC_SMB_DA2
2
2.2K_0402_5%

+3VALW

1
R471
1
R472
1
R473
1
R474
2
R475
1
R476
2
R497

@
@

EC_SMB_CK1
2
2.2K_0402_5%
EC_SMB_DA1
2
2.2K_0402_5%
KSO1
2
47K_0402_5%
KSO2
2
47K_0402_5%
LID_SW #
1
100K_0402_5%
EC_PME#
2
10K_0402_5%
PBTN_OUT#
1
100K_0402_5%

<39>
<39>
<5,19>
<5,19>

<14> SLP_S3#
<14> SLP_S5#
<14> EC_SMI#
<10> LOCAL_DIM
<29> MINI1_LED#

For LED INV_PWM freq to 1K


ENBKL
1
100K_0402_5%
LOCAL_DIM
1
100K_0402_5%
COLOY_ENG_EN
1
100K_0402_5%

2
R488
2
R844
2
R845

EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2

<10> COLOY_ENG_EN
<10> EC_INVT_PW M
<34> FAN_SPEED1
<33> BT_ON#
<34> ON/OFF
<32> PW R_SUSP_LED
<32> W LAN_LED#

55
56
57
58
59
60
61
62
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
81
82

EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2

77
78
79
80

SLP_S3#
SLP_S5#
EC_SMI#
LOCAL_DIM
MINI1_LED#
COLOY_ENG_EN
EC_INVT_PW M
FAN_SPEED1
BT_ON#
E51TXD_P80DATA
E51RXD_P80CLK
ON/OFF
PW R_SUSP_LED
W LAN_LED#

6
14
15
16
17
18
19
25
28
29
30
31
32
34
36

EC_CRY1
EC_CRY2

122
123

DAC_BRIG
EN_DFAN1
IREF
CALIBRATE#

KSI0/GPIO30
KSI1/GPIO31
KSI2/GPIO32
KSI3/GPIO33
KSI4/GPIO34
KSI5/GPIO35
KSI6/GPIO36
KSI7/GPIO37
KSO0/GPIO20
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23
KSO4/GPIO24
KSO5/GPIO25 Int. K/B
KSO6/GPIO26 Matrix
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
KSO10/GPIO2A
KSO11/GPIO2B
KSO12/GPIO2C
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
KSO16/GPIO48
KSO17/GPIO49

PSCLK1/GPIO4A
PSDAT1/GPIO4B
PSCLK2/GPIO4C
PSDAT2/GPIO4D
TP_CLK/PSCLK3/GPIO4E
TP_DATA/PSDAT3/GPIO4F

83
84
85
86
87
88

EC_MUTE#

SDICS#/GPXOA00
SDICLK/GPXOA01
SDIDO/GPXOA02
SDIDI/GPXID0

97
98
99
109

3S/4S#
65W /90W #
VLDT_EN
LID_SW #

SPIDI/RD#
SPIDO/WR#
SPICLK/GPIO58
SPICS#

119
120
126
128

CIR_RX/GPIO40
CIR_RLC_TX/GPIO41
FSTCHG/SELIO#/GPIO50
BATT_CHGI_LED#/GPIO52
CAPS_LED#/GPIO53
BATT_LOW_LED#/GPIO54
SUSP_LED#/GPIO55
SYSON/GPIO56
VR_ON/XCLK32K/GPIO57
AC_IN/GPIO59

73
74
89
90
91
92
93
95
121
127

EC_RSMRST#/GPXO03
EC_LID_OUT#/GPXO04
EC_ON/GPXO05
EC_SWI#/GPXO06
ICH_PWROK/GPXO06
GPO
BKOFF#/GPXO08
WL_OFF#/GPXO09
GPXO10
GPXO11

100
101
102
103
104
105
106
107
108

EC_RSMRST#
EC_LID_OUT#
EC_ON
EC_SW I#
EC_PW ROK_R
BKOFF#
W L_OFF#

PM_SLP_S4#/GPXID1
ENBKL/GPXID2
GPXID3
GPXID4
GPXID5
GPXID6
GPXID7

110
112
114
115
116
117
118

VGATE
ENBKL
EAPD
EC_THERM#
SUSP#
PBTN_OUT#
EC_PME#

V18R

124

PS2 Interface

OSC
NC

SPI Flash ROM

GPIO
SM Bus

PM_SLP_S3#/GPIO04
PM_SLP_S5#/GPIO07
EC_SMI#/GPIO08
LID_SW#/GPIO0A
SUSP#/GPIO0B
PBTN_OUT#/GPIO0C
GPIO
EC_PME#/GPIO0D
EC_THERM#/GPIO11
FAN_SPEED1/FANFB1/GPIO14
FANFB2/GPIO15
EC_TX/GPIO16
EC_RX/GPIO17
ON_OFF/GPIO18
PWR_LED#/GPIO19
NUMLED#/GPIO1A

GPI

69

R889
100K_0402_5%

11
24
35
94
113

@
C740
15P_0402_50V8J

Ra

3S/4S# <37>
65W /90W # <37>
VLDT_EN <35>
LID_SW # <32>

AD_PID0

ECAGND 2

L85

R464

C734
C

0.1U_0402_16V4Z

Analog Board ID definition


+3VALW

EC_SI_SPI_SO <32>
EC_SO_SPI_SI <32>
1

Board_ID : 0-> w / X1
1-> wo / X1

EC_SPICS#/FSEL#

R469

L1112
EC_SPICLK <32>Ra
<32>
FBMA-10-100505-301T_2P
C783
10P_0402_50V8J

FSTCHG <37>
BATT_BLUE_LED# <32>
INT_VGAPW R_ON <24>
BATT_AMB_LED# <32>
PW R_LED <32>
SYSON <35,40,42> Reserve
VR_ON <44>
ACIN <25,35,37>

BATT_BLUE_LED#
INT_VGAPW R_ON
BATT_AMB_LED#
PW R_LED
SYSON
VR_ON
ACIN

100K_0402_5%
AD_BID0

R470

Rb

8.2K_0402_5%

C735
0.1U_0402_16V4Z

for EMI, close to EC


B

EC_RSMRST# <14>
EC_LID_OUT# <14>
EC_ON <34,38>
EC_SW I# <14>
BKOFF# <10>
W L_OFF# <29>
VGA_ON <24,35>

Delay SUSP# 10ms

VGATE <14,44>
ENBKL <10>
EAPD <27>
EC_THERM# <5>
SUSP# <35,40,41>
PBTN_OUT# <14>
EC_PME# <26>

EC_PW ROK_R 1
R254

2
0_0402_5%

EC_PW ROK <14>

C736
4.7U_0603_6.3V6K

Change 0603 size For DVT

20mil

BATT_TEMP

C737
2

100P_0402_50V8J
1

ACIN

C741
2

100P_0402_50V8J
1

BLM18AG601SN1D_2P

Compal Electronics, Inc.

Compal Secret Data


2010/08/20

Issued Date

100K_0402_5%

TP_CLK <32>
TP_DATA <32>

Deciphered Date

2011/08/20

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Rb

EC_MUTE# <27>

TP_CLK
TP_DATA

KB930QF A1 LQFP 128P

Security Classification

32.768KHZ_12.5PF_Q13MC14610002

Project_ID : 0->
1->
2->

8.2K_0402_5%

AGND

XCLK1
XCLK0
GND
GND
GND
GND
GND

OSC

X1
@

NC

C739
@
15P_0402_50V8J

2
0_0402_5%

+3VALW

DAC_BRIG <10>
EN_DFAN1 <34>
IREF <37>
CALIBRATE# <37>

SPI Device Interface

EC_CRY2

2
A

1
R888

Analog Project ID definition

ADP_I <37>

68
70
71
72

EC_CRY1

RTC_CLK

BATT_TEMP <39>

ADP_I
AD_BID0
AD_PID0

DAC_BRIG/DA0/GPIO3C
EN_DFAN1/DA1/GPIO3D
IREF/DA2/GPIO3E
DA3/GPIO3F

For Low PWR panel use


<13,17> RTC_CLK

ECAGND
2
1
C731 0.01U_0402_16V7K

R463

DA Output

SCL1/GPIO44
SDA1/GPIO45
SCL2/GPIO46
SDA2/GPIO47

ACOFF <36,37>

BATT_TEMP

PCICLK
PCIRST#/GPIO05
ECRST#
SCI#/GPIO0E
CLKRUN#/GPIO1D

ACOFF

+5VS

EC_SCI#

<14> EC_SCI#

2
1
R462
47K_0402_5%
2
1
C733
0.1U_0402_16V4Z

+3VALW

AD

BEEP# <27>

<13> A_RST#

12
13
37
20
38

BATT_TEMP/AD0/GPIO38
BATT_OVP/AD1/GPIO39
ADP_I/AD2/GPIO3A
Input
AD3/GPIO3B
AD4/GPIO42
SELIO2#/AD5/GPIO43

63
64
65
66
75
76

BEEP#

LPC_CLK0_EC

<13> LPC_CLK0_EC

PWM Output

21
23
26
27

1
33_0402_5%

INVT_PWM/PWM1/GPIO0F
BEEP#/PWM2/GPIO10
FANPWM1/GPIO12
ACOFF/FANPWM2/GPIO13

2
R461

GA20/GPIO00
KBRST#/GPIO01
SERIRQ#
LFRAME#
LAD3
LAD2
LAD1
LAD0 LPC & MISC

1
2
3
4
5
7
8
10

R460

C732
@ 22P_0402_50V8J
2
1

<14> EC_GA20
<14> EC_KBRST#
<13> SERIRQ
<13> LPC_FRAME#
<13> LPC_AD3
<13> LPC_AD2
<13> LPC_AD1
<13> LPC_AD0

1
100K_0402_5%
1
100K_0402_5%
2
4.7K_0402_5%

R459
3S/4S#

EC_GA20
EC_KBRST#
SERIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

E51RXD_P80CLK <29>
E51TXD_P80DATA <29>

+3VALW

VCC
VCC
VCC
VCC
VCC
VCC

U26

1
2
3
4

1
2
3
4

C730

<32>

Place on MiniCard door

JP7

C729
1000P_0402_50V7K

ECAGND

KSO[0..17]

C727

+3VALW

1
2+EC_VCCA
BLM18AG601SN1D_2P
1

Title

EC ENE KB930
Size
B
Date:

Document Number

Rev
1.0

LA-7092P P5WE6/H6/S6
Monday, November 29, 2010

Sheet
1

31

of

47

To TP/B Conn.
+3VALW

1
R479

C742 1

2
0_0603_5%

2 0.1U_0402_16V4Z

U27

<31> EC_SPICS#/FSEL#
+3VALW

EC_SPICS#/FSEL#
2 4.7K_0402_5% SPI_W P#
2 4.7K_0402_5% SPI_HOLD#

R480 1
R482 1

1
3
7
4

CS#
WP#
HOLD#
GND

VCC
SCLK
SI
SO

8
6
5
2

EC_SPICLK_R

+5VS

JTP1

+SPI_VCC

R481 1

2 0_0402_5%
EC_SO_SPI_SI <31>
EC_SI_SPI_SO <31>

7
8

EC_SPICLK <31>

1
2
3
4
5
6
GND
GND

+5VS

1
2
3
4
5
6

LEFT_BTN#
RIGHT_BTN#

C745
0.1U_0402_16V4Z

1
1
C723 C785
100P_0402_50V8J
100P_0402_50V8J
2
2

RIGHT_BTN#

5
6

TP_DATA

RIGHT_BTN#

TP_CLK

LEFT_BTN#
D11

2
5
6

LEFT_BTN#

SW 2
SMT1-05-A_4P
3
1

SW 1
SMT1-05-A_4P
3
1

EMI request
For MP

ACES_85201-0605N
CONN@

MX25L1605DM2I-12G SOP 8P
SA000041N00

TP_CLK <31>
TP_DATA <31>

D13

PJDLC05C_SOT23-3

JLED1

28
27

<31>

ON/OFFBTN# <34>

+3VS

ACES_85201-08051
CONN@

KSO[0..17] <31>

+3VS

R486

100K_0402_5%

P
G

U29
2

MEDIA_LED#

5IN1_LED# <29>

SATA_LED# <15>

NC7SZ08P5X_NL_SC70-5

PW R_LED#

100P_0402_50V8J

KSO17

C748 1

100P_0402_50V8J

C749 1

100P_0402_50V8J

KSO7

C750 1

100P_0402_50V8J

KSO14

C751 1

100P_0402_50V8J

KSO6

C752 1

100P_0402_50V8J

KSO13

C753 1

100P_0402_50V8J

KSO5

C754 1

100P_0402_50V8J

KSO12

C755 1

100P_0402_50V8J

KSO4

C756 1

100P_0402_50V8J

KSI0

C757 1

100P_0402_50V8J

KSO3

C758 1

100P_0402_50V8J

KSO11

C759 1

100P_0402_50V8J

KSI4

C760 1

100P_0402_50V8J

KSO10

C761 1

100P_0402_50V8J

KSO2

C762 1

100P_0402_50V8J

KSI1

C763 1

100P_0402_50V8J

KSO1

C764 1

100P_0402_50V8J

KSI2

C765 1

100P_0402_50V8J

KSO0

C766 1

100P_0402_50V8J

KSO9

C767 1

100P_0402_50V8J

KSI5

C768 1

100P_0402_50V8J

KSI3

C769 1

100P_0402_50V8J

KSI6

C770 1

100P_0402_50V8J

KSO8

C771 1

100P_0402_50V8J

KSI7

C772 1

100P_0402_50V8J

+3VALW

1
R511

LED1
2
750_0402_1% HT-191NB5_BLUE

+3VS

@
1
R477

2
2
750_0402_1%

PW R_LED#

C747 1

DMN66D0LDW -7_SOT363-6
Q26A

<31> PW R_LED
KSO16

KSO15

R487
100K_0402_5%

LED2
HT-191UD5_AMBER

1
R478

+3VALW

2
2
3.01K_0402_1%

PW R_SUSP_LED#

LED3
HT-191NB5_BLUE
PW R_SUSP_LED#

3
R490
100K_0402_5%

1
R499

+3VALW

2
2
750_0402_1%

DMN66D0LDW -7_SOT363-6
Q26B

<31> PW R_SUSP_LED

2010/08/20

Issued Date

BATT_BLUE_LED#

BATT_BLUE_LED# <31>

BATT_AMB_LED#

BATT_AMB_LED# <31>

LED4
HT-191UD5_AMBER

1
R498

+3VALW

2
2
3.3K_0402_5%

For PEW76/86/96 LED light,


R477, R499 change as 750 ohm
R478 change as 3.01k ohm
R498 change as 3.3k ohm

Deciphered Date

2011/08/20

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

Compal Secret Data

Security Classification

Pop R486 for RTS5137

KSI[0..7]

KSO[0..17]

+3VS

PW R_LED#
ON/OFFBTN#

ACES_88747-2601
CONN@

KSI[0..7]

+3VALW
LID_SW # <31>
W LAN_LED# <31>

LID_SW #
W LAN_LED#
MEDIA_LED#

KSO0
G2
KSO1
G1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7

26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

1
2
3
4
5
6
7
8
9
10

KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7

1
2
3
4
5
6
7
8
GND
GND

INT_KBD Conn.

JKB1

PJDLC05C_SOT23-3

Title

Compal Electronics, Inc.


KB/TP/LED/SPI ROM/PWRb

Size
B
Date:

Document Number

Rev
1.0

LA-7092P P5WE6/H6/S6
W ednesday, November 24, 2010

Sheet
1

32

of

47

+USB_VCCA

+3VALW

SVPE, 4.2m, 18mohm


Change P/N SF000002Y00

+USB_VCCA

8
7
6
5

R447 1

4.7U_0603_6.3V6K
2

VOUT
VOUT
VOUT
FLG

Change 0603 size


For DVT
C713

GND
VIN
VIN
EN

+
R446
100K_0402_5%

80mil

C712

2 10K_0402_5%

C714
0.1U_0402_16V4Z

AP2301MPG-13_MSOP8

C711

2
470P_0402_50V7K

USB_OC0# <14>

R448

<35> SYSON#

220U_6.3V_M

W=80mils

1
2
3
4

EPAD

U24

+5VALW

+USB_VCCA

0_0402_5%

L83
USB20_N0

<14> USB20_N0

JUSB1

USB20_P0

VOUT
VOUT
VOUT
FLG

8
7
6
5

80mil

R450
100K_0402_5%

AP2301MPG-13_MSOP8

WCM2012F2S-900T04_0805
USB_OC2# <14>
R451

1
2
R452
10K_0402_5%

1
2
3
4
GND
GND
GND
GND

<NAL00 use>

SUYIN_020133MB004S580ZL-C
CONN@

0_0402_5%

USB_OC1# <14>

4.7U_0603_6.3V6K
2

GND
VIN
VIN
EN

R449 @
0_0402_5%
1
2

Change 0603 size


For DVT
C715

EPAD

U25

1
2
3
4

<14> USB20_P0
+USB_VCCB

1
2
3
4
5
6
7
8

USB20_N0_R
USB20_P0_R

+3VALW
+5VALW

C716
0.1U_0402_16V4Z

SYSON#

D10
USB20_N0_R

SA00003XM00 S IC AP2301MPG-13 MSOP 8P PWR SW

USB20_P0_R

+USB_VCCA

To USB/B Connector

PJUSB208_SOT23-6

Change P/N SC300000O00 for ESD

+USB_VCCB

USB20_N2
USB20_P2

USB20_N1 <14>
USB20_P1 <14>

BT@ 2
1
R453
10K_0402_5%

<31> BT_ON#
USB20_N2 <14>
USB20_P2 <14>

+BT_VCC
C721

+BT_VCC

Change 0603 size


For DVT

10

GND 8
7
6
5
4
3
2
GND 1

8
7
6
5
4
3
2
1

AO3413L_SOT23-3

W=40mils

BT@
0.1U_0402_16V4Z

JBT1

1U_0402_6.3V4Z
3

C720

<NAL00 use>

G
D

ACES_85201-1205N
CONN@

BT@
Q24

BT@
C719

BT@

C722

BT@

GND
GND

USB20_N1
USB20_P1

BT@
0.1U_0402_16V4Z

BT@
R454
300_0603_5%

4.7U_0603_6.3V6K
2
0.1U_0402_16V4Z

13
14

C718

USB20_P7 <14>
USB20_N7 <14>

+3VS

1
2
3
4
5
6
7
8
9
10
11
12

1
2
3
4
5
6
7
8
9
10
11
12

+3VALW

Bluetooth Conn.

JUSB2

(Port 1,2)

BT@
Q25
2N7002_SOT23

2
G

ACES_87213-0800G
CONN@

<NAL00 use>
4

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2010/08/20

Deciphered Date

2011/08/20

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

USB/BT/USBsub
Rev
1.0

LA-7092P P5WE6/H6/S6

Date:

Monday, November 29, 2010

Sheet
E

33

of

47

FAN1 Conn

Power Button

Change 0603 size


For DVT

+5VS

2
+VCC_FAN1
ON/OFF <31>
51_ON# <36>

C824
1000P_0402_50V7K
1
2

R568
10K_0402_5%

1000P_0402_50V7K
1

40mil
2
1

S 2N7002_SOT23

10K_0402_5%

C825
1000P_0402_50V7K

1
2
3

G1
G2

4
5

CONN@
ACES_85204-03001

H4
H_3P0

1
H12
H_3P0

H3
H_4P0

H19
H_3P0

H24
H_3P0

H11
H_3P0

H2
H_4P0

H1
H_3P0

H18
H_3P4

H14
H_3P0

2010/08/20

Deciphered Date

H7
H_3P0

H8
H_3P0

H20
H_4P2

H21
H_4P2

H17
H_3P0X3P5N

H10
H_3P0

H22
H_4P2

H23
H_4P2

H13
H_3P0N

FD4

FD3

FIDUCIAL_C40M80

FIDUCIAL_C40M80

FIDUCIAL_C40M80

FIDUCIAL_C40M80

Compal Electronics, Inc.

Compal Secret Data

Security Classification
Issued Date

FD2

H5
H_3P0

FD1

R496

Q27

2
G

EC_ON

4
6
5

<31,38> EC_ON

1
2
3

<31> FAN_SPEED1

SMT1-05-A_4P
1
3

JFAN1

+VCC_FAN1

Bottom Side
@ SW 4

C773

+3VS

0.01U_0402_25V4Z

6
5

Change to SC600000B00

Change 0603 size


For DVT

C823
10U_0603_6.3V6M
1
2

APL5607KI-TRG_SO8

DAN202UT106_SC70-3

ON/OFFBTN# <32>

C822

2
0_0402_5% 1

1
R567

@ D26 BAS16_SOT23-3
1
2

<31> EN_DFAN1

8
7
6
5

GND
GND
GND
GND

D12

EN
VIN
VOUT
VSET

ON/OFFBTN#

Bottom Side

@ SW 3
SMT1-05-A_4P
1
3

U37

1
2
3
4

100K_0402_5%

R495

2
@ 10K_0603_5%

D25
1SS355_SOD323-2

@
R566
0_0603_5%
@

2
@ 10K_0603_5%

+5VS

10U_0603_6.3V6M
2

R494

R493

C821
1

+3VALW

TOP Side

ON/OFF switch

2011/08/20

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

Other IO/USB (right)


Size
Document Number
Custom

Rev
1.0

LA-7092P P5WE6/H6/S6

Date: W ednesday, November 24, 2010

Sheet

34

of

47

+3VALW TO +3VS

<25,31,37> ACIN

Change P/N SB548000210

2
2

3
3
3

<24,25> VGA_PWR_ON

S
SSM3K7002FU_SC70-3

Q68
2N7002_SOT23

2
G

R1123
100K_0402_5%
2

VGA_PWR_ON#

<25> VGA_PWR_ON#
SUSP
2
G
Q65
2N7002_SOT23

Q67

2
G

R1119
100K_0402_5%

C1463
0.1U_0603_25V7K

D
3

1
200K_0402_5% 1

1
+5VALW
2

R1120
470_0603_5%

R1134
10K_0402_5%

Change 0603
size For DVT

R1122
2

2
1
1

Q77
2N7002_SOT23

Q62
2N7002_SOT23

R1118
100K_0402_5%

2
G

2
G

<13,24> PE_GPIO1

SUSP#

PE_GPIO1#

<24> PE_GPIO1#

C1461

R1117
100K_0402_5%

R1115
10K_0402_5%

1.5_VDDC_PWREN#

+1.5VS

10U_0603_6.3V6M
2

Q59
2N7002_SOT23

+5VALW

<24,43> 1.5_VDDC_PWREN

2
2

R1121

R1131
100K_0402_5%

100K_0402_5%

1
1
1

0.1U_0603_25V7K

2
G

+5VALW
2 SUSP
G
Q60
2N7002_SOT23

C1456

Q63
SI2301CDS-T1-GE3_SOT23-3

<31,40,41> SUSP#

+1.5VS
3

Q58
2N7002_SOT23

R1113
10K_0402_5%

<25> 1.5_VDDC_PWREN#

+1.5V

2
G

R1110
470_0603_5%

SUSP

<42> SUSP

VGA_ON#

Q57
2N7002_SOT23

R1116
100K_0402_5%

R1114
100K_0402_5%

2
1

Change 0603
size For DVT

SUSP

2
Q61 G
2N7002_SOT23

10U_0603_6.3V6M
C1455
2
2
1U_0402_6.3V4Z

3VS_GATE

1
120K_0402_5%

2
R1112

+VSB

0.1U_0603_25V7K

10U_0603_6.3V6M
2
2
10U_0603_6.3V6M

Audio issue
For DVT

C1452

+5VALW

Q52
2N7002_SOT23

1 1

C1454

+5VALW

C1451

<24,31> VGA_ON

2
G

R1109
100K_0402_5%

R1107
10K_0402_5%

U41
SI4800BDY-T1-GE3_SO8
8
1
7
2
6
3
5
4

C1453

ACIN 2
G

+3VALW

S
2N7002_SOT23

2 VLDT_EN#
G
Q54

<31,40,42> SYSON

+3VS

Change 0603
size For DVT

Q51
2N7002_SOT23

2
G

2
Q56 G
2N7002_SOT23

VLDT_EN#

R1106

0.1U_0603_25V7K

300K_0402_5%

2
Q55 G
2N7002_SOT23

1.1VS_GATE

<31> VLDT_EN

SYSON#

<33> SYSON#
D

2
47K_0402_5%

470_0603_5%

1
R1105

VLDT_EN#

R1102

+VSB

C1450

SUSP

1 2

Change 0603
size For DVT

2
10U_0603_6.3V6M

10U_0603_6.3V6M
C1449
2
2
1U_0402_6.3V4Z

C1447

2 SUSP
G
Q53
2N7002_SOT23

5VS_GATE

2
100K_0402_5%

1
R1103

R1104
C1448
1K_0402_5%

Change 0603
size For DVT
+VSB

R1101
470_0603_5%

R1108
100K_0402_5%

R1111
100K_0402_5%

2
1

10U_0603_6.3V6M
C1444
2
2
1U_0402_6.3V4Z

10U_0603_6.3V6M
2
2
10U_0603_6.3V6M

C1446

C1445

+1.1VS

U39
SI4800BDY-T1-GE3_SO8
8
1
7
2
6
3
5

Change 0603
size For DVT

+5VALW

Change P/N SB548000210

+1.1VALW

+5VS

C1443

+5VALW

+1.1VALW TO +1.1VS

Change P/N SB548000210

U38
SI4800BDY-T1-GE3_SO8
8
1
7
2
6
3
5

Change 0603
size For DVT

+5VALW TO +5VS
+5VALW

2 SUSP
G
Q80
2N7002_SOT23

2 VLDT_EN#
G
Q74
2N7002_SOT23

2 SYSON#
G
Q78
2N7002_SOT23

R1126
470_0603_5%
VGA@

R1128
470_0603_5%

R1137
470_0603_5%

+VGA_CORE

R1135
470_0603_5%
4

+1.1VS

+0.75VS

+1.5V

2 1.5_VDDC_PWREN#
G
Q28
2N7002_SOT23
VGA@

2010/08/20

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2011/08/20

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

DC Interface
Rev
1.0

LA-7092P P5WE6/H6/S6

Date:

Monday, November 29, 2010

Sheet
E

35

of

47

1
PC3
100P_0402_50V8J

PC2
100P_0402_50V8J

1
2

PC1
1000P_0402_50V7K

VIN

PL1
SMB3025500YA_2P
1
2

1
2
3
4
GND
GND

@ PJP1
ACES_50305-00441-001

PC4
1000P_0402_50V7K

VIN

PD2
LL4148_LL34-2
2
1

BATT+

PD1
LL4148_LL34-2

2
1

<34> 51_ON#

VS

1
PJ1
PC6
0.1U_0603_25V7K

+3VALWP

PJ2
2

+3VALW

+1.8VSP

(4.73A,200mils ,Via NO.= 10)

+1.8VS

(3A,120mils ,Via NO.=6)

2
PJ3

PR4
22K_0402_5%

+5VALWP

PJ4
2

+5VALW

+1.1VALWP

PreCHG

(3.15A,140mils ,Via NO.=7)

PJ6
2

+VSB

+0.75VSP

+0.75VS

(3A,120mils ,Via NO.=6)

(120mA,40mils ,Via NO.= 2)

@PJP3
@
PJP3
JUMP_43X118
1
2 2

+VGA_COREP

@PJP4
@
PJP4
JUMP_43X118
1
2 2

+VGA_CORE
B

(13A,520mils ,Via NO.= 26)

12

@ PR13
100K_0402_5%

@ PD4
2

PJ11
1

+1.05VSP

BAS40CW_SOT323-3

@PQ3
@
PQ3
PDTC115EU_SOT323-3

@ PQ4
PDTC115EU_SOT323-3

+1.05VS

JUMP_43X118

PJ7

(6A,240mils ,Via NO.=12)

+1.5VP

<38> +5VALWP

JUMP_43X79

@ PR12
1K_1206_5%
1
2

<31,37> ACOFF

+1.1VALW

(5A,200mils ,Via NO.= 10)

B+

PR9
1
@
2

@ PR11
1K_1206_5%
1
2
B

PR10
1

@ PR8
1K_1206_5%
1
2

100K_0402_5%

@PQ2
@
PQ2
TP0610K-T1-E3_SOT23-3

+3VLP

@PD3
@
PD3
LL4148_LL34-2

100K_0402_5%

PR7
0_1206_5%
1
2

VIN

JUMP_43X118

JUMP_43X39
PR5
0_0603_5%
1
2

JUMP_43X118

PJ5

+VSBP

+CHGRTC

JUMP_43X118

JUMP_43X118

PR2
68_1206_5%

1
PR3
100K_0402_5%

PC5
0.22U_0603_25V7K
2
1

N1

PR1
68_1206_5%
PQ1
TP0610K-T1-E3_SOT23-3

+1.5V

JUMP_43X118
PJ13
1 1
2 2
JUMP_43X118

(7A,280mils ,Via NO.=14)

PJ16

+1.5VSP

+1.5VS1

JUMP_43X118

(1A,40mils ,Via NO.= 2)

Compal Secret Data

Security Classification
Issued Date

2010/07/13

2011/07/13

Deciphered Date

Title

Compal Electronics, Inc.


PWR DCIN / Pre-charge

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
0.1

P5WE0 M/B LA-6901P Schematic

Date:

Wednesday, November 24, 2010

Sheet
1

36

of

47

UGATE

17

DH_CHG

PC23
0.1U_0603_25V7K
BST_CHGA 2
1

12

15

VADJ

LGATE

14

GND

PGND

13

6251VDDP
2

VDDP

ACLIM

PD8
RB751V-40_SOD323-2

DL_CHG

PC28
4.7U_0603_6.3V6M

2
1

1
2
PR44
15.4K_0402_1%

<31> CALIBRATE#

PR45
31.6K_0402_1%
6251VDD

CC=0.6~4.48A

IREF=0.43V~3.24V

PR48
10K_0402_1%
1
2

PR47
10K_0402_1%
2

PR46
47K_0402_5%

ACIN <25,31,35>

PACIN

PR49
14.3K_0402_1%
2

ACPRN

2
PQ19
PDTC115EU_SOT323-3

Kv
Rinternal ic=514K Rec=3K R1=PR379=15.4K R2=PR381=31.6K
R=514K//31.6K//(15.4K+3k)=11.372K
r=514K//514K//31.6K=28.14K
Vcell=0.175*Vadj+3.99v
4.2V=0.175*Vadj+3.99V =>Vadj=1.2V
Vadj=Vref*(R/(R+514K))+CALIBRATE*(r/(r=514K))
1.1483=CALIBRATE*0.6046 =>CALIBRATE=1.899
1.899=(4.2-(Vcell+A*0.175))*Kv=(4.2-(4.2+A*0.175))*Kv
A=Vref*(R/(R+514K))=0.052
Kv=9.451

Compal Secret Data

Security Classification
Issued Date

2010/07/13

Deciphered Date

2011/07/13

Title

Compal Electronics, Inc.


PWR-CHARGER

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

PC253
0.1U_0603_25V7K
2
1

BATT+

4 PR34
0.02_1206_1%
3

Ki
Vchlim=Iref*(PR374/(PR372+PR374))
=Iref*(100K/(80.6K+100K))
=Iref*0.5537
Ichanrge=(165mV/PR369)*(Vchlim/3.3V)
=(165m/20m)*(1/3.3V)*Iref*0.5537
=1.3842*Iref
Iref=0.7224*Ichanrge =>Ki=0.7224

12.60V

PC16
10U_1206_25V6M
2
1

PR41
4.7_0603_5%

12600mV

PQ16
AO4466_SO8
4

26251VDD

11

<40,41>

TCR=50ppm / C
PL2
10UH_PCMB104T-100MS_6A_20%
CHG
1
2

PR37
0_0603_5%
BST_CHG 1

1
PR43
20K_0402_1%

10

@ PC17
2200P_0402_25V7K

@ PQ12
2N7002W -T/R7_SOT323-3

16

BOOT

2
G

CHLIM

VREF

PQ61
2N7002W -T/R7_SOT323-3
2 PACIN
G

PC26
10U_1206_25V6M
2
1

PHASE

ICM

18

19

CSIP

VCOMP

PQ15
AO4466_SO8

5
6
7
8

PC25
10U_1206_25V6M
2
1

ACPRN

3
2
1

CSOP

20

IREF=0.7224*Icharge
Normal 3S LI-ON Cells

PC11
2200P_0402_25V7K
2
1

1
CSIN

CSON

ICOMP

2
1
@ PR21
100K_0402_5%

ACPRN <38>

CV mode

PC10
0.1U_0603_25V7K
2
1

2
1

PC14
1000P_0402_25V8J
2
1

V1

PR28
20_0402_5%
1
2
PC18
0.047U_0402_16V7K
1
2
PR29
20_0402_5%
2
1
PR30
PC21
20_0402_5%
0.1U_0603_25V7K
1
2
PR32
2_0402_5%
LX_CHG

PR31

PC15
DCIN 2
1

Charging Voltage
(0x15)

BATT Type

PQ9
PDTC115EU_SOT323-3

PR35
4.7_1206_5%

PC19 6800P_0402_25V7K
1
2
5

VIN

ISL6251AHAZ-T_QSOP24
3

<31> 65W/90W#

CP mode
Iinput=(1/0.02)(0.05*Vaclm/2.39+0.05)
where Vaclm=1.502V, Iinput=4.07A

PC27
680P_0402_50V7K

21

6251aclim

2
G
PQ18
2N7002W -T/R7_SOT323-3

PR357
200K_0402_1%
1
2

5
6
7
8

CSOP

ACOFF

PD12
1SS355_SOD323-2

3
2
1

CELLS

PQ17
PDTC115EU_SOT323-3

PC9
10U_1206_25V6M
2
1

1
2
4

0.01U_0402_25V7K
10K_0402_1%
1
2
PR33 100_0402_1%
1
2
6251VREF
PC22 .1U_0402_16V7K

12.1K_0402_1%

PR23
14.3K_0402_1%

PR40
6251VREF

PR15
10K_0402_1%

ACSETIN

<31,36> ACOFF

PR22
10_1206_5%
2
1 1
CSON

1 2
1
PR42
2.55K_0402_1%

PR39
100K_0402_1%
ACOFF

VIN

PR26

EN

22

6251_EN

9
PC24
0.01U_0402_25V7K
2
1

<31> IREF

PR36
80.6K_0402_1%
2
1
1

PR38
47K_0402_5%
1
2

PR16
47K_0402_1%
2

PD9
1SS355_SOD323-2

S
<31> ADP_I

23

PC20
1
2

5
G

PACIN

24

DCIN

ACSET ACPRN

PQ14B
DMN66D0LDW -7_SOT363-6

0.1U_0603_25V7K
ACSETIN 2

S
PQ14A
DMN66D0LDW -7_SOT363-6

VDD

<31> 3S/4S#
1

PQ13
PDTC115EU_SOT323-3

6
2
G

PD5
RB751V-40_SOD323-2

PU1
1

PR27
150K_0402_1%
PQ10
PDTC115EU_SOT323-3

PR18
191K_0402_1%

6251VDD

PR24
0_0402_5%
2
1

8
7
6
5

CSIN

VIN PreCHG

<31> FSTCHG

PR25 47K_0402_5%
1
2

6251VDD

1
2
3

CHG_B+

PL22
HCB4532KF-800T90_1812
1
2

CSIP

47K

PQ8
PDTA144EU_SOT323-3

PC13
2.2U_0603_6.3V6K
2
1

PR17
200K_0402_1%

V1

47K
2

PR14 0.02_2512_1%

PC7
5600P_0402_25V7K
1
2

1
3

PR19
200K_0402_1%

PC12
0.1U_0603_25V7K
2

P3

PQ7
SI4459ADY-T1-GE3_SO8
8
7
6
5

1
2
3

1
2
3

8
7
6
5

100K_0402_1%

P2

PQ6
AO4407A_SO8

VIN

PL17
1.2UH_1231AS-H-1R2N=P3_2.9A_30%
1
2

B+

CP = 85%*Iada ; CP = 4.07A

ADP_I = 19.9*Iadapter*Rsense

PQ5
AO4407A_SO8

@ PC30
10U_1206_25V6M
1
2
@ PC56
10U_1206_25V6M
1
2

PC8
10U_1206_25V6M
2
1

Iada=0~4.74A(90W/19V=4.736A)

Rev
0.1
P5WE0 M/B LA-6901P Schematic

W ednesday, November 24, 2010


D

Sheet

37

of

47

PC29
1U_0603_10V6K

2VREF_8205

12

LGATE2

LGATE1

19

LG_5V

PL5
4.7UH_PCMC063T-4R7MN_5.5A_20%
1
2

RT8205EGQW _W QFN24_4X4

NC

5
6
7
8

PC38
0.1U_0603_25V7K
2
1

PC37
2200P_0402_50V7K
2
1

LX_5V

18

VIN

VREG5
17

16

GND

SKIPSEL

EN
13

PC36
4.7U_0805_25V6-K
2
1

UG_5V

20

LG_3V

3
2
1

AO4712_SO8
PQ23

PC46
1U_0603_10V6K
2
1

RT8205_B+

2VREF_8205

PC47
4.7U_0805_10V6K

VL

Typ: 175mA

+5VALWP

1
+

PC43
220U_6.3V_M

TONSEL=VREF (1)SMPS1=300KHZ (+5VALWP)


(2)SMPS2=375KHZ(+3VALWP)

+3.3VALWP
Ipeak=6.768A ; 1.2Ipeak=8.12A; Imax=4.738A
f=375KHz, L=4.7UH,Rentrip=162k ohm
Rdson=15~18m ohm
1/2Delta I = 1/2 *(19-3)*(3/19)/(375KHz*4.7UH)=0.774A
Vlimit=10*10^-6*162Kohm/10=0.162V
Ilimit=0.162/(18m*1.2)~0.162/(15m*1.2)=7.5A~9A
Iocp=8.274A~9.774A

+5VALWP
Ipeak=7A ; 1.2Ipeak=8.4A; Imax=4.9A
f=300KHz, L=4.7UH,Rentrip=154k ohm
Rdson=15~18m ohm
1/2Delta I = 1/2 *(19-5)*(5/19)/(300KHz*4.7UH)=1.306A
Vlimit=10*10^-6*154Kohm/10=0.15V
Ilimit=0.15/(18m*1.2)~0.15/(15m)=7.13~10.26A
Iocp=8.44~9.86A

Compal Secret Data

Security Classification
2010/07/13

Issued Date

21

@ PR60
4.7_1206_5%

PHASE1

@ PC45
680P_0402_50V7K

PHASE2

3
2
1

11

SPOK <39,41>

PC49
2.2U_0603_6.3V6K

PR66
100K_0402_1%

1
3

VS

2
1
PR67
40.2K_0402_1%

PQ24A
DMN66D0LDW -7_SOT363-6

PQ25
PDTC115EU_SOT323-3

PQ27
PDTC115EU_SOT323-3

2
G

<31,34> EC_ON

2
G

22

UGATE1

VFB=2.0V

1
5

2N7002W -T/R7_SOT323-3
PQ26
<37> ACPRN

BOOT1

PR57
PC41
0_0603_5% 0.1U_0603_25V7K
BST_5V 1
2 1
2

PR64
100K_0402_1%
2
1

VL

23

5
6
7
8

LX_3V

PC35
4.7U_0805_25V6-K
2
1

ENTRIP1

UGATE2

2
PC48
0.1U_0603_25V7K

G
S

24

1
2

PR62
100K_0402_1%

ENTRIP2

D
PQ24B
DMN66D0LDW -7_SOT363-6

PR65
200K_0402_5%
2
1

VO1
PGOOD

PQ21
AO4466_SO8
4

B+

ENTRIP1

PR63
0_0402_5%
2
1

BOOT2

10

PR61
499K_0402_1%
1
2

<39> MAINPWON

ENTRIP1

FB1

REF

UG_3V

1
2
3

FB2

BST_3V

PR59 @
0_0402_5%
2
1

MAINPW ON

TONSEL

VREG3

15

PQ22
AO4712_SO8

ENTRIP2

VO2

14

1
2
3

2 1
2
0_0603_5%
PC40
0.1U_0603_25V7K

8
7
6
5

@ PR58
4.7_1206_5%
2
1

P PAD

RT8205_B+

PR55
154K_0402_1%
2

7
PR56

+
@ PC44
680P_0402_50V7K
2
1

PC42
220U_6.3V_M

25

+3VLP

PR53
20K_0402_1%
1
2

PU2

4.7UH_PCMC063T-4R7MN_5.5A_20%
PL4
1
2

+3VALWP

PR52
20K_0402_1%
1
2

PQ20
AO4466_SO8
4

PR51
30K_0402_1%
1
2

PR54
137K_0402_1%
1
2

PC39
4.7U_0805_10V6K

8
7
6
5

PC34
2200P_0402_50V7K
2
1

PC33
4.7U_0805_25V6-K
2
1

Typ: 175mA
PC32
4.7U_0805_25V6-K
2
1

PC31
0.1U_0603_25V7K
2
1

B+

PL3
HCB4532KF-800T90_1812
1
2

PR50
13K_0402_1%
1
2

ENTRIP2

RT8205_B+

Deciphered Date

2011/07/13

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

Title

Compal Electronics, Inc.


3VALWP/5VALWP

Size
Document Number
Custom

Rev
0.1

P5WE0 M/B LA-6901P Schematic

Date:

W ednesday, November 24, 2010

Sheet
1

38

of

47

PJP2
SUYIN_200275GR008G13GZR
D

10
9
8
7
6
5
4
3
2
1

EC_SMDA
EC_SMCA
TH
PI

PR68
100_0402_1%

PH1 under CPU botten side :


CPU thermal protection at 92 degree C
Recovery at 56 degree C

GND
GND
8
7
6
5
4
3
2
1

PR69
100_0402_1%

EC_SMB_DA1 <31>

VL

<40,41>
VMB
<40,41>
BATT+

PC50
0.1U_0603_25V7K

PR72
21K_0402_1%

VCC TMSNS1
GND RHYST1

8
7

PR76
9.53K_0402_1%

2
3

<38> MAINPWON

4
BATT_TEMP <31>

OT1 TMSNS2
OT2 RHYST2

PU3
1

@ PR77
47K_0402_1%
1

G718TM1U_SOT23-8

@ PR74
100K_0402_1%
PR75
1K_0402_1%

PR71
10K_0402_1%

VL

+3VALWP
2

PC52
0.01U_0402_25V7K

1
PR73
6.49K_0402_1%
2
1

1
PC51
1000P_0402_50V7K

EC_SMB_CK1 <31>
PR70
1K_0402_5%

PL6
SMB3025500YA_2P
1
2

PH2 @

PH1

100K_0402_1%_NCP15WF104F03RC
2

100K_0402_1%_NCP15WF104F03RC
PQ28
TP0610K-T1-E3_SOT23-3

+VSBP

PC54
0.1U_0603_25V7K

1
2

VL

PC53
0.22U_0603_25V7K

PR79
22K_0402_1%
1
2

2
1
PR78
100K_0402_1%

B+

PR80
100K_0402_1%
1

1
2

PQ29
2N7002W-T/R7_SOT323-3

2
G
PC55
1U_0402_6.3V6K

<38,41> SPOK

PR81
1K_0402_5%
1
2

Compal Secret Data

Security Classification
Issued Date

2010/07/13

2011/07/13

Deciphered Date

Title

Compal Electronics, Inc.


PWR-BATTERY CONN/OTP

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
0.1

P5WE0 M/B LA-6901P Schematic

Date:

Wednesday, November 24, 2010

Sheet
1

39

of

47

FB

0.22U_0402_10V6K

FB_1.8VS

PR85
10K_0402_1%

1M_0402_5%

PR83
20K_0402_1%

1
1
PC120

PR86

PC119

LX_1.8VS

200K_0402_5%
@

NC

NC

TP

2 EN_1.8VS

11

PR84

PR82

1
2
1

<31,35,41> SUSP#

FB=0.6Volt

PC118
22U_0805_6.3VAM

EN

PC115
22U_0805_6.3VAM

+1.8VSP

SVIN

PC117
22U_0805_6.3VAM

LX

LX_1.8VS

PC116
68P_0402_50V8J
2
1

PVIN

JUMP_43X39

LX

PVIN

10

4.7_1206_5%

680P_0603_50V7K

+5VALW

PL7
2.2UH_MSCDRI-74A-2R2M-E_6.5A_20%
1
2

PU4
SY8033BDBC_DFN10_3X3
@ PJ14

PG

G5603

RT8209B

Temperature
Compensated

TPS51117

-1180ppm/

RT8209M

1600ppm/

4500ppm/

4800ppm/

50mV

30mV

50mV

PR87
255K_0402_1%
1
2
2
1

FB

PGOOD

15
NC

14
UGATE

13

DH_1.5V

PHASE

12

LX_1.5V

CS

11

VDDP

10

LGATE

VFB=0.75V

3
2
1

PL9
1.0UH_PCMC104T-1R0MN_20A_20%
2

+1.5VP

0.1U_0603_25V7K

PR92
1
2
7.68K_0402_1%

@ PR93
4.7_1206_5%

+5VALW

DL_1.5V

+ PC128
330U_6.3V_M

PGND

RT8209MGQW _W QFN14_3P5X3P5

PC131
4.7U_0805_10V6K

PQ31
AO4726L_SO8

@ PC130
680P_0603_50V7K

GND

PC129
4.7U_0603_6.3V6K

PQ30
AO4466_SO8

PC127
1
2

5
6
7
8

VDD

BST_1.5V-1

BOOT

VOUT

0_0603_5%

100_0603_5%

PR91

TON

PR89

+5VALW

PU5

EN/DEM

PC126 @
.1U_0402_16V7K

PR90
30K_0402_5%

3
2
1

0_0402_5%

BST_1.5V

PR88

<31,35,42> SYSON

B+

PC125
2200P_0402_50V7K
2
1

200mV

PC124
0.1U_0603_25V7K
2
1

200mV

PC123
4.7U_0805_25V6-K
2
1

200mV

PC121
4.7U_0805_25V6-K
2
1

200mV

PL8
HCB2012KF-121T50_0805
1
2

5
6
7
8

Vtrip_max (SPEC)

30mV

Vtrip_min (SPEC)

Rtrip: 5K~15K
Rds(on) = 5.3m ohm (typ)
7m ohm (max)
1

PR94

5.1K_0402_1%

PR95
5.1K_0402_1%

<Vo=1.5V> VFB=0.75V
Vo=0.75*(1+10K/10K)=1.5V
Fsw=280KHz

Cout ESR=17 mohm Rdson(max)=7 mohm Rdson(typ)=5.3 mohm


Ipeak=9.45A, Imax=6.615A
Delta I=((19-1.5)*(1.5/19))/(L*Fsw)=4.93A
=>1/2Delta I=2.467A
Vtrip=Rtrip*10uA=0.0768
Iocpmin=Vtrip/(Rds(on)(max)*1.2)+Delta I/2=11.61A
Iocpmax=Vtrip/(Rds(on)(typ)*1.2)+Delta I/2=14.54A
Iocp=11.61A~14.54A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2010/01/25

Deciphered Date

2009/04/28

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

1.8VSP/1.5VP
Rev
0.1

W ednesday, November 24, 2010


D

Sheet

40

of

47

PL10
HCB2012KF-121T50_0805

PR96
255K_0402_1%
1
2

PR97
0_0402_5%
1
2

PC208
0.1U_0603_25V7K

PC207
0.1U_0603_25V7K
2
1

PC135
2200P_0402_50V7K
2
1

PC134
0.1U_0603_25V7K
2
1

1
2

PR98
0_0603_5%
1
2

PQ32
AO4466_SO8

LGATE

DL_1.1VALW

PQ33
AO4712_SO8

4
1

PGND
8

GND
7

PC139
4.7U_0603_6.3V6K

+5VALW

RT8209MGQW _W QFN14_3P5X3P5

PC140
4.7U_0805_10V6K

Rtrip: 5K~15K

PR103
4.7K_0402_1%
1
2

PC138
330U_6.3V_M

10

VDDP

2
PR102
10.7K_0402_1%

LX_1.1VALW
1

@ PR100
4.7_1206_5%

11

PGOOD

12

CS

PHASE

@ PC141
680P_0603_50V7K

FB

13

5
6
7
8

DH_1.1VALW
0.1U_0603_25V7K

UGATE

3
2
1

VDD

BOOT

VOUT

14

15

PR101
100_0603_1%
1
2

TON

PL11
2.2UH_FDVE0630-H-2R2M=P3_8.3A_20%
1
2

PC137
1

+5VALW

NC

PU6

EN/DEM

PC136
.1U_0402_16V7K
@

PR99
30K_0402_5%
@

BST_1.1V ALW

B+

<Vo=1.1V> VFB=0.75V
V=0.75*(1+4.7K/10K)=1.1V
Fsw=280KHz

Cout ESR=17 mohm Rdson(max)=18 mohm Rdson(typ)=15 mohm


Ipeak=4.5A, Imax=3.15A
Delta I=((19-1.1)*(1.1/19))/(L*Fsw)=1.68A
=>1/2Delta I=0.84A
Vtrip=Rtrip*10uA=0.107
Iocpmin=Vtrip/(Rds(on)(max)*1.2)+Delta I/2=5.79A
Iocpmax=Vtrip/(Rds(on)(typ)*1.2)+Delta I/2=6.78A
Iocp=5.79A~6.78A

<38,39> SPOK

3
2
1

PC133
4.7U_0805_25V6-K

5
6
7
8

PC132
4.7U_0805_25V6-K

1.1VALW _B+

+1.1VALW P

1
+
2

PR104
10K_0402_1%
2

PL12
HCB2012KF-121T50_0805

3
2
1

CS

11

VDDP

10

PR111
8.25K_0402_1%

DL_1.05VALW

LX_1.05VALW

LGATE

RT8209MGQW _W QFN14_3P5X3P5

PC150
4.7U_0805_10V6K

Rtrip: 5K~15K

PR112
4.02K_0402_1%
1
2
1

RT8209B

Vtrip_min (SPEC)

-1180ppm/

30mV

TPS51117

RT8209M

1600ppm/

4500ppm/

4800ppm/

50mV

30mV

50mV

200mV

200mV

200mV

200mV

2010/01/25

Deciphered Date

PC206
0.1U_0603_25V7K

2009/04/28

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Compal Electronics, Inc.

Compal Secret Data

Security Classification
Issued Date

Vtrip_max (SPEC)

PC205
0.1U_0603_25V7K
2
1

PC145
2200P_0402_50V7K
2
1

PC144
0.1U_0603_25V7K
2
1

1
2

PC143
4.7U_0805_25V6-K
2
1

G5603

+
2

Cout ESR=17 mohm Rdson(max)=7 mohm Rdson(typ)=5.3 mohm


Ipeak=8.7A, Imax=6.09A
Delta I=((19-1.05)*(1.05/19))/(L*Fsw)=1.61A
=>1/2Delta I=0.81A
Vtrip=Rtrip*10uA=0.0825
Iocpmin=Vtrip/(Rds(on)(max)*1.2)+Delta I/2=10.63A
Iocpmax=Vtrip/(Rds(on)(typ)*1.2)+Delta I/2=13.78A
Iocp=10.63A~13.78A

Temperature
Compensated

<Vo=1.05V> VFB=0.75V
V=0.75*(1+4.02K/10K)=1.05V
Fsw=280KHz

Rds(on) = 5.3m ohm (typ)


7m ohm (max)

PR113
10K_0402_1%

+1.05VSP

PQ35
AO4726L_SO8

PGND
8

PGOOD

GND

6
2

PC149
4.7U_0603_6.3V6K

+5VALW

PC148
330U_6.3V_M

12

PHASE

PR109
4.7_1206_5%

14

13

PC151
680P_0603_50V7K

FB

PL13
2.2UH_FDVE0630-H-2R2M=P3_8.3A_20%
1
2

DH_1.05VALW
0.1U_0603_25V7K

UGATE

VDD

5
6
7
8

VOUT

BST_1.05V ALW
PC147

BOOT

B+

PQ34
AO4466_SO8

3
2
1

PR110
100_0603_1%
1
2

+5VALW

TON

4
PR107
0_0603_5%
1
2

NC

PU7

EN/DEM

PC146
.1U_0402_16V7K

PR108
30K_0402_5%
@

<31,35,40> SUSP#

PR106
200K_0402_5%
1
2

15

PR105
255K_0402_1%
1
2

PC142
4.7U_0805_25V6-K

5
6
7
8

1.05VALW _B+ 2

1.1VALWP/1.05VSP
Rev
0.1

W ednesday, November 24, 2010


D

Sheet

41

of

47

14

PGOOD

10

3
2
1

@ PR182
4.7_1206_5%

+5VALW

DL_1.5V-2

+1.5VSP

1
+

@ PC202
330U_6.3V_M

RT8209MGQW_WQFN14_3P5X3P5

@ PQ39
AO4726L_SO8

@ PC200
4.7U_0805_10V6K

@ PC195
680P_0603_50V7K

LGATE

11

VDDP

LX_1.5V-2
@
PR185
1
2
7.68K_0402_1%

12

5
6
7
8

15

BOOT

CS

VFB=0.75V

FB

PHASE

VDD

0.1U_0603_25V7K

DH_1.5V-2

3
2
1

100_0603_5%

VOUT

@ PL21
1.0UH_PCMC104T-1R0MN_20A_20%

13

@ PQ46
AO4466_SO8

@ PC199
1
2

BST_1.5V-2

@ PR178
1
2

@ PC196
4.7U_0603_6.3V6K

0_0603_5%

UGATE

PGND

+5VALW

TON

NC

PU11

EN/DEM

@ PC203
.1U_0402_16V7K

@ PR183
30K_0402_5%

@ PR181
BST_1.5V-2 1
2

0_0402_5%

B+

@ PR186
1
2

GND

<31,35,40> SYSON

@ PL20
HCB2012KF-121T50_0805
1
2

PC197
2200P_0402_50V7K
2
1

@
@ PR180
255K_0402_1%
1
2

PC201
0.1U_0603_25V7K
2
1

PC204
4.7U_0805_25V6-K
2
1

PC198
4.7U_0805_25V6-K
2
1

5
6
7
8

Rtrip: 5K~15K

PR184
2

5.1K_0402_1%

<Vo=1.5V> VFB=0.75V
Vo=0.75*(1+10K/10K)=1.5V
Fsw=280KHz

@ PR179
5.1K_0402_1%

RT8209B

TPS51117

RT8209M

G5603
Temperature
Compensated

-1180ppm/

1600ppm/

4500ppm/

4800ppm/

Vtrip_min (SPEC)

30mV

50mV

30mV

50mV

Vtrip_max (SPEC)

200mV

200mV

200mV

200mV

Cout ESR=17 mohm Rdson(max)=7 mohm Rdson(typ)=5.3 mohm


Ipeak=9.45A, Imax=6.615A
Delta I=((19-1.5)*(1.5/19))/(L*Fsw)=4.93A
=>1/2Delta I=2.467A
Vtrip=Rtrip*10uA=0.0768
Iocpmin=Vtrip/(Rds(on)(max)*1.2)+Delta I/2=11.61A
Iocpmax=Vtrip/(Rds(on)(typ)*1.2)+Delta I/2=14.54A
Iocp=11.61A~14.54A

PJ15
JUMP_43X39

+1.5V

PU8
VIN

NC

GND

NC

VREF VCNTL

PC153
1U_0603_10V6K

PR114
1K_0402_1%

+3VALW
1

VOUT

PC152
4.7U_0805_6.3V6K

NC
TP

5
9

+0.75VSP

S PQ36
2N7002W-T/R7_SOT323-3

PC154
.1U_0402_16V7K
2
1

1
PR116
1K_0402_1%

PC155
10U_0603_6.3V6M

PC156
.1U_0402_16V7K

2
G
3

PR115
300K_0402_5%
1
2
1

<35> SUSP

APL5336KAI-TRL_SOP8P8

For shortage changed

Compal Secret Data

Security Classification
2009/10/02

Issued Date

2010/10/02

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Compal Electronics, Inc.


0.75VSP
Document Number

Rev
0.3

Wednesday, November 24, 2010

Sheet
1

42

of

47

VGA@ PL14
HCB2012KF-121T50_0805

B+

B+_CORE

<13,24> VGA_PWRGD

TRIP

DRVH

DH_VCORE

EN

SW

SW_VCORE

VFB

V5IN

RF

DRVL

VGA@
PC162
1U_0603_6.3V6M

@ PR122
4.7_1206_5%

2
4

VGA@ PC163
390U_2.5V_M

VGA@ PR124
0_0402_5%

@ PC164
680P_0603_50V7K

VGA@ PR125
10_0402_5%
2
1 GCORE_SEN

GCORE_SEN <21>
C

3
2
1

VGA@ PQ38
TPCA8057-H_PPAK56-8-5

VGA@ PR126
2.87K_0402_1%

Rds=2.6m/3.2mOHM
1

VGA@ PC165
.1U_0402_16V7K

ESR=10mohm

DL_VCORE

11

Switch Freq. (RF pin setting)


47K =>450KHz
100K =>390KHz
200K =>350KHz
470K =>290KHz

+VGA_COREP

TP

VFB=0.7V

1
2

VGA@ PL15
0.36UH_PCMC104T-R36MN1R17_30A_20%
1
2
+5VALW

TPS51218DSCR_SON10_3X3

<24,35> 1.5_VDDC_PWREN

VGA@ PQ37
TPCA8065-H_PPAK56-8-5

VGA@ PR120
200K_0402_1%

10

1
@ PR121
10K_0402_5%

VBST

VGA@ PR118 VGA@ PC161


0_0603_5% 0.1U_0603_25V7K
BST_VCORE 1
2
1
2

+3VS

VGA@ PU9
1 PGOOD

3
2
1

VGA@ PR119
44.2K_0402_1%
1
2

VGA@ PR123
20K_0402_1%
1
2

VGA@

VGA@

@ PR117
10K_0402_5%

VGA@

PC160
10U_0805_25V6K
2
1

VGA@

PC159
10U_0805_25V6K
2
1

PC158
0.1U_0603_25V7K
2
1

PC157
2200P_0402_25V7K
2
1

+3VS

+3VSG

VGA@ PC167
4700P_0402_25V7K

@ PR132
10K_0402_5%

DMN66D0LDW-7_SOT363-6
VGA@ PQ40A

2
1

VGA@ PR133
10K_0402_5%
VGA@ PR134
10K_0402_5%
1
2

VGA@ PR130
40.2K_0402_1%
1
2

+3VSG

2
VGA@ PR129
10K_0402_5%

VGA@ PR128
9.31K_0402_1%

VGA@ PC166
2200P_0402_25V7K

Ipeak=18.2A Imax=12.74A, 1.2*Ipeak=21.84A


Delta I= ((19-0.9)*(0.9/19))/(L*Fsw)=6.8A
Iocpmax=(66.5K*11uA)/(8*1.2*0.0026) +3.4=32.71A
Iocpmin=(66.5K*9uA)/(8*1.2*0.0032)+3.4=22.88A
Iocp=22.88~32.71A

VGA@ PR127
15.4K_0402_1%

VGA@ PR131
30.1K_0402_1%

VGA_CORE
Vtrip= 0.7V
Vo=0.7*(1+Rtop/Rdown)
Fsw=350KHz

VGA@ PC168
4700P_0402_25V7K

@ PR135
10K_0402_5%

+3VSG

GPIO 15

GPIO 20

GPU_VID0

GPU_VID1 Core Voltage Level

Seymour

VGA@ PQ41B
DMN66D0LDW-7_SOT363-6

VGA@ PR140
10K_0402_5%
5 2
1

@ PR139
10K_0402_5%

+3VSG

GPU_VID0 <19>

11

VGA@ PQ40B
DMN66D0LDW-7_SOT363-6

VGA@ PR141
10K_0402_5%

@ PR136
10K_0402_5%

0.9V

D
AP

1.00V
1.05V

1.10V

GPU_VID1 <19>
VGA@ PR138
10K_0402_5%

VGA@ PR137
10K_0402_5%
2
1

VGA@PQ41A
DMN66D0LDW-7_SOT363-6

Compal Secret Data

Security Classification
Issued Date

2010/07/13

2011/07/13

Deciphered Date

Title

Compal Electronics, Inc.


+VGA_COREP

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Rev
0.1

P5WE6/S6/H6

Wednesday, November 24, 2010

Sheet
1

43

of

47

PL16
HCB2012KF-121T50_0805

CPU_B+

7
8

ENABLE

LGATE0

ISL6265CHRTZ-T_TQFN48_6X6

RBIAS

PVCC

OCSET

LGATE1

VDIFF0

PGND1

PHASE0

32

+5VALW

28

<5> APU_VDD0_RUN_FB_L
2

PR170
10_0402_1%
1

PC57
10U_1206_25V6M
2
1

PC175
220U_25V_M

PC173
0.1U_0603_25V7K
2
1 2
1

PC212
0.1U_0603_25V7K
2
1

PC211
0.1U_0603_25V7K
2
1

PC210
0.1U_0603_25V7K
2
1

PC209
0.1U_0603_25V7K
2
1

PC214
0.1U_0603_25V7K
2
1

PC185
0.1U_0603_25V7K
2
1

PC184
4.7U_0805_25V6-K
2
1

PC183
4.7U_0805_25V6-K
2
1

PQ45
TPCA8057-H 1N PPAK56-8

PR162
12.7K_0402_1%

PC188
680P_0603_50V7K

PC189
2
1
0.1U_0603_16V7K

PC190
1U_0603_16V6K

2
LGATE0

27

PR166
4.53K_0402_1%

26

TP

25

49

ISN1
24

ISP1
23

VW1
22

COMP1
21

FB1
20

VDIFF1
19

VSEN1
18

RTN1
17

16

+APU_CORE

ISN0

VSEN0

0_0402_5%
PR171
1 RTN0

+1.5V

DIFF_0

PR169
0_0402_5%
2
1

<5> APU_VDD0_RUN_FB_H

14

PR168
0_0402_5%

10_0402_1%

ISP0

+APU_CORE

BOOT1

30
29

ISP0
ISN0

VSEN1

PR167

13

VSEN1
2

RTN0

UGATE1

VW0

VSEN0

COMP0

ISP0

12

PHASE1

15

11

FB0

ISN0

10

3
2
1

PR161
4.7_1206_5%

LGATE0

31

PGND0

UGATE0

33

PQ44, PQ45 need to link


1

SVC

34

PC187
0.22U_0603_10V7K

38

39

40

41

37
UGATE_NB

PHASE_NB

LGATE_NB

PGND_NB

43

44

45

42
RTN_NB

VSEN_NB

FSET_NB

46
FB_NB

PHASE0

BOOT0

UGATE0

SVD

35

ISN0

PWROK

36

PL19

PR163
0_0402_5%

PR165
95.3K_0402_1%
2
1

BOOT0

DCR = 1.1m ohm +-7%

0.36UH_PCMC104T-R36MN1R17_30A_20%

ISP0

BOOT_NB

PGOOD

BOOT_NB

PR158
2.2_0603_1%
BOOT0 1
2 1

PQ44
TPCA8065-H_PPAK56-8-5

1 2

ESR = 15 m ohm

PC179
220U_6.3V_M

<31> VR_ON
PR164
21.5K_0402_1%
2
1

1
PR160
0_0402_5%2

PHASE0

3
2
1

ISL6265_PWROK

<5> APU_SVD
<5> APU_SVC

OFS/VFIXEN

OCSET_NB

COMP_NB

VCC

47

VIN

48

1
2

PU10

<13> H_PWRGD_L

CPU_B+

PR190
0_0603_5%
1
2 UGATE0-1 4

UGATE0
@ PR156
105K_0402_1%

2
@ PR159 100K_0402_5%
2
PR157 100K_0402_5%

Rds(on) max =18 m ohm


typ = 15 m ohm

UGATE_NB

2
1

PC180
680P_0603_50V7K

PC182
4.7U_0805_25V6-K
2
1

1
2
1

LGATE_NB

@ PR153
105K_0402_1%

<14,31> VGATE
<14> FCH_PWRGD

PR146
4.7_1206_5%

PC213
0.1U_0603_25V7K
2
1

1
2
PR187
1 10_0402_5%PHASE_NB

@ PR155
10K_0402_1%

+APU_CORE_NB

<5>

1 2

PQ43
AO4712_SO8

PHASE_NB

PR154
105K_0402_1%

PC174
2200P_0402_50V7K
2
1

5
6
7
8
2

PC186
2200P_0402_50V7K
2
1

PR152
0_0402_5%

PL18
2.2UH_FDVE0630-H-2R2M=P3_8.3A_20%
1
2

PC178
0.22U_0603_10V7K
4

APU_VDDNB_RUN_FB_H

+
2

B+

APU_VDD0_RUN_FB_L

PR151
23.7K_0402_1%
2

PC181
0.1U_0603_25V7K

LGATE_NB

PR148
2_0603_5%

+3VS

PQ42
AO4466_SO8

+5VS

PHASE_NB
PR145
2.2_0603_1%
BOOT_NB
1
2 1

PR149
0_0402_5%
2
1
PR150
0_0402_5%
2
1

+3VS

UGATE_NB1 4

PC170
1000P_0402_50V7K

PR147
10_0402_5%
1
2 +APU_CORE_NB

PR189
0_0603_5%
1
2

PR188
220_0402_1%

3
2
1

UGATE_NB

PR144
22K_0402_1%
2
1

PC177
0.1U_0603_16V7K

CPU_B+

PC176
1000P_0402_50V7K
2
1
1

+5VALW

3
2
1

PR142
44.2K_0402_1%
PR143
2_0603_5%
1
2

PC171
4.7U_0805_25V6-K
2
1

5
6
7
8

PC172
4.7U_0805_25V6-K
2
1

2
PC169
47P_0402_50V8J
2
1

PC58
10U_1206_25V6M
2
1

1K_0402_5%
PR172
1

VW0

PR173
PC191
255_0402_1% 2200P_0402_25V7K
2
1 2
1

COMP0

PC192
220P_0402_50V8J

PR174
1K_0402_5%
2
1

PR175
2

PC194
2
1

PC193
1000P_0402_50V7K

PR176
6.81K_0402_1%
2
1

54.9K_0402_1% 1200P_0402_50V7K

Compal Secret Data

Security Classification
PR177
36.5K_0402_1%

2009/10/02

Issued Date

2010/10/02

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Compal Electronics, Inc.


CPU_CORE
Document Number

Rev
0.3

Wednesday, November 24, 2010

Sheet
E

44

of

47

Version change list (P.I.R. List)


Item

Fixed Issue

Page 1 of 1
for PWR
Reason for change

Rev.

PG#

Modify List

Date

Change PR115 from SD028000080 to SD028300380(S RES 1/16W 300K +-5% 0402)
Add PC156 SE076104K80(S CER CAP .1U 16V K X7R 0402)

Phase

2010/09/24

DVT

0.75VSP EN RC value

HW adjust timing

0.1

42

1.8VSP EN RC value

HW adjust timing

0.1

40

Change PR84 from SD028000080 to SD028200380(S RES 1/16W 200K +-5% 0402)
Add PC120 SE095224K00(S CER CAP 0.22U 10V K X5R 0402)

2010/09/24

DVT

1.05VSP EN RC value

HW adjust timing

0.1

41

Change PR106 from SD028000080 to SD028200380(S RES 1/16W 200K +-5% 0402)
Add PC146 SE076104K80(S CER CAP .1U 16V K X7R 0402)

2010/09/24

DVT

HW adjust timing

0.1

43

Change PR123 from SD034100280 to SD034200280(S RES 1/16W 20K +-1% 0402)

2010/09/24

DVT

42

Change PU11, PL21, PQ39, PQ46, PR178, PR179, PR180, PR181, PR184, PR185,
PR186, PC196, PC197, PC198, PC199, PC200, PC201, PC202, PC204 BOM structure
to VGA@
del PL20 SM01000C000(S SUPPRE_ TAI-TECH HCB2012KF-121T50 0805)

2010/10/05

DVT

3
4
5

VGA_COREP EN RC value

change BOM structure

1.5VSP change BOM structure to VGA@ for cost down of UMA

0.1

Adjust APU_CORE_NB OCP to 15A

0.1

44

Add input choke in charger circuit.

Add input choke for EMI ISN test in charger circuit.

0.1

37

Add snubber

Add snubber in APU_COREP and APU_CORE_NB circuit.

0.1

44

Add PR146, PR161 SD001470B80(S RES 1/4W 4.7 +-5% 1206)


Add PC180, PC188 SE025681K80(S CER CAP 680P 50V K X7R 0603)
Add PR188 SD034220080(S RES 1/16W 220 +-1% 0402)

Add snubber and input Cup.

0.1

41

10

Add input Cup.

0.1

Adjust APU_CORE_NB OCP

Add snubber and input Cup. in 1.05VSP circuit.

Add input Cup. in 1.1VALWP circuit for EMI test.

2010/10/07

DVT

2010/10/18

DVT

2010/10/18

DVT

Add PR161 SD001470B80(S RES 1/4W 4.7 +-5% 1206)


Add PC188 SE025681K80(S CER CAP 680P 50V K X7R 0603)
Add PC205, PC206 SE042104K80(S CER CAP .1U 25V K X7R 0603)

2010/10/18

DVT

41

Add PC207, PC208 SE042104K80(S CER CAP .1U 25V K X7R 0603)

2010/10/18

DVT

Add PC209, PC210, PC211, PC212 SE042104K80(S CER CAP .1U 25V K X7R 0603)
Add PC57, PC58 SE142106M80(S CER CAP 10U 25V M X5R 1206 H1.7)
Add PR189, PR190 SD013000080(S RES 1/10W 0 +-5% 0603)

Change PR151 from SD034110280 to SD034237280(S RES 1/16W 23.7K +-1% 0402)

Change PL17 from SM010018710 to SH00000IY00(S COIL


1.2UH +-30% 1231AS-H-1R2N=P3 2.9A)

11

Add input Cup.

Add input Cup. and H/S gate resistance in CPU_COREP


circuit for EMI ISN test.

0.1

44

2010/10/19

DVT

12

Adjust VGA_COREP VID value

Adjust VGA_COREP VID value

0.1

43

Change PR128 from SD034100280 to SD034931180(S RES 1/16W 9.31K +-1% 0402)
Change PR127 from SD034200280 to SD034154280(S RES 1/16W 15.4K +-1% 0402)
Change PR131 from SD000009K00 to SD034301280(S RES 1/16W 30.1K +-1% 0402)

2010/10/21

DVT

13

change BOM structure

1.5VSP change BOM structure to @ for cost down

0.1

42

Change PU11, PL21, PQ39, PQ46, PR178, PR179, PR180, PR181, PR184, PR185,
PR186, PC196, PC197, PC198, PC199, PC200, PC201, PC202, PC204 BOM structure
to @
del PL20 SM01000C000(S SUPPRE_ TAI-TECH HCB2012KF-121T50 0805)

2010/10/21

DVT

14

change main source

change main source for reduce source

0.1

42

2010/10/26

DVT

Adjust VGA_COREP VID timing to avoid OVP.

0.1

43

2010/11/01

DVT

2010/11/01

DVT

15

Adjust VGA_COREP VID timing

16

Delete precharge circuit

Change PQ36 from SB000009610 to SB000006800(S TR 2N7002W T/R7 1N SOT-323)

Change PR130 from SD028100280 to SD034402280(S RES 1/16W 40.2K +-1% 0402)

Delete precharge circuit to avoid adapter UVP.

0.1

36

del PR8, PR11, PR12 SD001100180(S RES 1/4W 1K +-5% 1206)


del PD3 SC100001Y80(S DIO LL4148 LL-34 PANJIT)
del PR9, PR10, PR13 SD028100380(S RES 1/16W 100K +-5% 0402)
change PR7 SD001100180 to SD011000080(S RES 1/4W 0 +-5% 1206)

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2010/04/12

Issued Date

Deciphered Date

2010/10/12

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

PIR (PWR)
Rev
0.1

PEW96 LA-6552P

Monday, November 15, 2010

Sheet
1

45

of

47

Version change list (P.I.R. List)


Item

Fixed Issue

Page 1 of 1
for PWR
Reason for change

Rev.

PG#

Delete precharge circuit

Delete precharge

circuit

Delete precharge

circuit

Delete precharge

circuit to avoid adapter UVP.

0.1

37

Delete precharge

circuit

Delete precharge

circuit to avoid adapter UVP.

0.1

37

Delete precharge

circuit

Delete precharge

circuit to avoid adapter UVP.

0.1

37

0.1

44

Delete precharge circuit to avoid adapter UVP.

Delete precharge

0.1

circuit to avoid adapter UVP.

36

0.1

37

Modify List

Date

del PQ2 SB906100210(S TR TP0610K-T1-E3 1P SOT23)


del PQ3, PQ4 SB301150200(S TR PDTC115EU NPN SOT323)
del PD4 SCS00001200(S SCH DIO BAS40CW SOT-323)

change PQ7 SB00000DL00 to SB00000I600(S TR


SI4459ADY-T1-GE3 1P SO8)

del PR21 SD034100380(S RES 1/16W 100K +-1% 0402)


del PC17 SE075222K80(S CER CAP 2200P 25V K X7R 0402)
del PQ12 SB000006800(S TR 2N7002W T/R7 1N SOT-323)

Phase

2010/11/01

DVT

2010/11/01

DVT

2010/11/01

DVT

Add PR357 SD034200380(S RES 1/16W 200K +-1% 0402)


add PC253 SE042104K80(S CER CAP .1U 25V K X7R 0603)
add PQ61 SB000006800(S TR 2N7002W T/R7 1N SOT-323)

2010/11/01

DVT

Add PD9, PD12 SC100001K00(S DIO 1SS355 SOD323 T/R-5K)

2010/11/01

DVT

Add PC213, PC214 SE042104K80(S CER CAP .1U 25V K X7R 0603)

Add input Cup.

Add input Cup.

in CPU_COREP circuit for EMI ISN test.

PVT

2010/11/12

8
9
10
B

11
12
13
14
15
A

16

2010/04/12

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Deciphered Date

2010/10/12

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

PIR (PWR)
Rev
0.1

PEW96 LA-6552P

Monday, November 15, 2010

Sheet
1

46

of

47

PHASE

PAGE

0.1

P08

0.2
0.2
D

0.2

P-P--

Modification list

PURPOSE

First release

Base on PEW96, change platform (NB,CPU-->APU,SB820-->FCH)

C220, C336, C347, C357, C359, C360, C387, C388, C389, C390, C391, C392, C393, C421,

Follow Standard Part 0805-->0603

C427, C428, C1461 change 0603 size


C721 C669, C1005, C705, C708, C713, C715, C736, C794, C797, C932, C934, C983

Follow Standard Part 0805-->0603

change 0603 size


C215, C216, C218, C224, C226, C227, C229, C230, C231, C660, C671, C821, C823,

P--

C1210, C1517, C1522, C1526, C1529, C1532, C1512, C1523, C1443, C1445, C1446, C1447,

Follow Standard Part 0805-->0603

C1448, C1452, C1453, C1454 change 0603 size

0.2

P35

R1122 change as 200k ohm, C1463 change as 0.1UF

Adjust sequence

0.2

P5

Add R109, R155

Pull up 4.7k ohm for CRT EDIE

0.2

P16

Unpop R632, C744, C69, C746; Pop R633

+VDDIO_18_FC Tie to GND for Nun-share ROM

0.2

P16

Add R635; Unpop R634

AMD suggestion for +VDDIO_AZ

0.2

P24

Add R170, R171

For DISO BOM option

0.2

P13

Add U33, C1199, R830, R838, R839

For VGA_PWRGD

0.2

P13

Remove C52, R557

For A_RST#

0.2

P27

EC_MUTE# change as 12 PIN form 46 PIN in Codec

For External Mute Fail issue

0.2

P16

C113, C77, C743, C96 change 0603 size and add C121, C105, C108, C109

22uF cap. change two 10uF cap. 0603 size

0.2

P19

C14 change 0603 size and add C52

22uF cap. change two 10uF cap. 0603 size

0.2

P13

C66, C67 change 27pF

Follow suggestion by TXC result

0.2

P26

C1485, C1486 change 33pF

Follow suggestion by TXC result

0.2

P33

C711 Change as SF000003I00

Material shortage

0.2

P9

Add C643, C675, C676, C678

For DDR3 moat issue

0.2

P26

Remove C939 ; Reserve C941, D48, D49, D51, L109

For LAN

0.2

P7

Add C604, C684

For CRT Moniter issue

0.3

P--

C212, C623 change 0603 size ; add C628, C685

Follow Standard Part 0805-->0603

0.3

P27

R786 change as 15k ohm

Dos Beep issue

0.3

P19

change R21, R22 as DISO@

Device Menage Audio issue

1.0

P27

Add R797, R800

Mic noise issue

1.0

P26,10

1.0

P32

Reverse C939, C942, R456, R419, R426

for EMI ISN solution

Add C753, C785

for EMI request

Compal Secret Data

Security Classification
2010/08/20

Issued Date

Change footprint
20100812
5

Deciphered Date

2011/08/20

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

: For cost down purpose to change parts


4

Title

Compal Electronics, Inc.


HW-PIR

Size
B
Date:

Document Number

Rev
1.0

LA-7092P P5WE6/H6/S6
Tuesday, November 16, 2010

Sheet
1

47

of

47

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