Thc hnh Cu trc my tnh

Trang 1

BI 1 : HNG DN S DNG QUARTUS II

1/- To project : 1. Sau khi ci t xong phn mm QuartusII, bt u chy chng trnh bng cch double-click vo biu tng trn desktop.

Giao din QuartusII s xut hin :

2. u tin, cn to mt project mi : File New Project Wizard. ca s u tin in vo thng tin v th mc cha project, tn project v tn top-module (tn topmodule thng trng tn project). Click Next 2 ln.

GV: TS. Hunh Hu Thun ThS. Cao Trn Bo Thng

Thc hnh Cu trc my tnh

Trang 2

3. Ca s Family & Device Settings dng chn h v tn linh kin FPGA cu hnh. Chn h linh kin CycloneII, tn EP2C70F896C6 (board DE2-70). Chn Finish.

4. Vo File New Block Diagram/Schematic File. 5. Click chut phi vo trong thit k, chn Insert Symbol.

Chn cng AND bng cch g vo and2. Bm OK. Gn vo trong thit k. GV: TS. Hunh Hu Thun ThS. Cao Trn Bo Thng

Thc hnh Cu trc my tnh

Trang 3

6. Lm tng t bc 5 gn input (ng vo) v output (ng ra) cho thit k (c th dng phm Ctrl copy). a chut vo chn ca linh kin v thc hin ni dy.

7. t tn cho input v output (input : in1, in2; output : out) bng cch doubleclick vo symbol.

8. Cui cng ta c hnh cng AND vi input v output, chn File Save, tn file : congand.

9. Bin dch thit k chn Processing Start Compilation GV: TS. Hunh Hu Thun ThS. Cao Trn Bo Thng

Thc hnh Cu trc my tnh

Trang 4

10. Nu khng c li, s xut hin ca s bo successful. Bm OK.

* M phng thit k 11. Vo File New Vector Waveform File. 12. Click chut phi vo ca s Name. Chn InsertInsert Node or Bus.

GV: TS. Hunh Hu Thun ThS. Cao Trn Bo Thng

Thc hnh Cu trc my tnh

Trang 5

13. Chn Node Finder. Ca s Node Finder chn Pins: all v bm List. Chn tt c cc chn. Bm OK 2 ln.

14. V dng sng cho cc ng input bng hp cng c bn tri

15. Zoom out, dng cc biu tng ln 1 v xung 0 v cc ng tn hiu ng vo. Lu li vi tn file : congand.vwf.

GV: TS. Hunh Hu Thun ThS. Cao Trn Bo Thng

Thc hnh Cu trc my tnh

16. Vo Processing Start Simulation m phng.

Trang 6

17. Kt qu dng sng thu c.

* Cu hnh cho FPGA trn DE2-70 18. Thc hin map chn cho FPGA : vo Assignments Assignment Editor

19. Map chn cho 2 ng vo ca cng AND vi nt gt SW[0] v SW[1], ng ra ni vi led LEDR[0].

GV: TS. Hunh Hu Thun ThS. Cao Trn Bo Thng

Thc hnh Cu trc my tnh

Trang 7

20. Sau khi map chn xong, Save v Compile li mt ln na. cu hnh cho FPGA: chn Tools Programmer

21. Bm Start. Sau khi chy 100%, FPGA c cu hnh xong. Kim tra li hot ng ca thit k trn kit DE2-70.

Bi tp : Thay i cc cng logic OR, XOR, NAND, NOR, XNOR v kim tra bng chn tr ca chng trn DE2-70.

* Tham kho : www.altera.com www.terasic.com

GV: TS. Hunh Hu Thun ThS. Cao Trn Bo Thng