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CHNG I : GII THIU V VK 89C51

I. GII THIU CU TRC PHN CNG H MSC-51 (8951) : c im v chc nng hot ng ca cc IC h MSC-51 hon ton tng t nh nhau. y gii thiu IC8951 l mt h IC vi iu khin do hng Intel ca M sn xut. Chng c cc c im chung nh sau: Cc c im ca 8951 c tm tt nh sau : 8 KB EPROM bn trong. 128 Byte RAM ni. 4 Port xut /nhp I/O 8 bit. Giao tip ni tip. 64 KB vng nh m ngoi 64 KB vng nh d liu ngoi. X l Boolean (hot ng trn bit n). 210 v tr nh c th nh v bit. 4 s cho hot ng nhn hoc chia.

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S khi ca 8951:
INT1\ INT0\ SERIAL PORT TIMER 0 TIMER 1 TIME 2

128 byte RAM 8051\8052

INTERRUPT CONTROL

OTHER REGISTER

128 byte RAM

ROM 4K: 8031 4K: 8051 EPROM 4K: 8951

TIMER 2 TIMER1 TIMER1

CPU

BUS CONTROL OSCILATOR

I/O PORT

SERIAL PORT

EA\ RST

ALE\ PSEN\

P0 P1 P2 P3 Address\Data

TXD RXD

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II. KHO ST S CHN 8951, CHC NNG TNG CHN: 1.S chn 8951:
5v 5v

+ C3 10MF

1 2 3 4 5 6 7 8 9

40

U4 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 RST

P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7

39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21

R3 10K

12M C4 30P Y2

10 11 12 13 14 15 16 17 18 19

EA/VPP P3.0/RXD ALE/PROG PSEN P3.1/TXD P3.2/INT0 P3.3/INT1 P2.7/A15 P3.4/T0 P2.6/A14 P3.5/T1 P2.5/A13 P3.6/WR P2.4/A12 P3.7/RD P2.3/A11 P2.2/A10 XTAL2 P2.1/A9 XTAL1 P2.0/A8 AT89C51 20 GND

C4 30P

S chn IC 8951 2. Chc nng cc chn ca 8951: - 8951 c tt c 40 chn c chc nng nh cc ng xut nhp. Trong c 24 chn c tc dng kp (c ngha 1 chn c 2 chc nng), mi ng c th hot ng nh ng xut nhp hoc nh ng iu khin hoc l thnh phn ca cc bus d liu v bus a ch. a.Cc Port: Port 0 : - Port 0 l port c 2 chc nng cc chn 32 39 ca 8951. Trong cc thit k c nh khng dng b nh m rng n c chc nng nh cc ng IO. i vi cc thit k c ln c b nh m rng, n c kt hp gia bus a ch v bus d liu. Port 1:

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- Port 1 l port IO trn cc chn 1-8. Cc chn c k hiu P1.0, P1.1, P1.2, c th dng cho giao tip vi cc thit b ngoi nu cn. Port 1 khng c chc nng khc, v vy chng ch c dng cho giao tip vi cc thit b bn ngoi. Port 2 : - Port 2 l 1 port c tc dng kp trn cc chn 21 - 28 c dng nh cc ng xut nhp hoc l byte cao ca bus a ch i vi cc thit b dng b nh m rng. Port 3: - Port 3 l port c tc dng kp trn cc chn 10 - 17. Cc chn ca port ny c nhiu chc nng, cc cng dng chuyn i c lin h vi cc c tnh c bit ca 8951 nh bng sau: Bit Tn Chc nng chuyn i P3.0 RXT Ng vo d liu ni tip. P3.1 TXD Ng xut d liu ni tip. P3.2 INT0\ Ng vo ngt cng th 0. P3.3 INT1\ Ng vo ngt cng th 1. P3.4 T0 Ng vo ca TIMER/COUNTER th 0. P3.5 T1 Ng vo ca TIMER/COUNTER th 1. P3.6 WR\ Tn hiu ghi d liu ln b nh ngoi. P3.7 RD\ Tn hiu c b nh d liu ngoi.

Cc ng tn hiu iu khin :
Ng tn hiu PSEN (Program store enable): - PSEN l tn hiu ng ra chn 29 c tc dng cho php c b nh chng trnh m rng thng c ni n chn 0E\ (output enable) ca Eprom cho php c cc byte m lnh. - PSEN mc thp trong thi gian Microcontroller 8951 ly lnh. Cc m lnh ca chng trnh c c t Eprom qua bus d liu v c cht vo thanh ghi lnh bn trong 8951 gii m lnh. Khi 8951 thi hnh chng trnh trong ROM ni PSEN s mc logic 1. Ng tn hiu iu khin ALE (Address Latch Enable ) : - Khi 8951 truy xut b nh bn ngoi, port 0 c chc nng l bus a ch v bus d liu do phi tch cc ng d liu v a ch. Tn hiu ra ALE chn th 30 dng lm tn hiu iu khin gii a hp cc ng a ch v d liu khi kt ni chng vi IC cht. - Tn hiu ra chn ALE l mt xung trong khong thi gian port 0 ng vai tr l a ch thp nn cht a ch hon ton t ng. Cc xung tn hiu ALE c tc bng 1/6 ln tn s dao ng trn chip v c th c dng lm tn hiu clock cho cc phn khc ca h thng. Chn ALE c dng lm ng vo xung lp trnh cho Eprom trong 8951. Ng tn hiu EA\(External Access): - Tn hiu vo EA\ chn 31 thng c mc ln mc 1 hoc mc 0. Nu mc 1, 8951 thi hnh chng trnh t ROM ni trong khong a ch thp 8 Kbyte. Nu mc 0, 8951 s thi hnh chng trnh t b nh m rng. Chn EA\ c ly lm chn cp ngun 21V khi lp trnh cho Eprom trong 8951. Ng tn hiu RST (Reset) :

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-Ng vo RST chn 9 l ng vo Reset ca 8951. Khi ng vo tn hiu ny a ln cao t nht l 2 chu k my, cc thanh ghi bn trong c np nhng gi tr thch hp khi ng h thng. Khi cp in mch t ng Reset. Cc ng vo b dao ng X1, X2: - B dao ng c tch hp bn trong 8951, khi s dng 8951 ngi thit k ch cn kt ni thm thch anh v cc t nh hnh v trong s . Tn s thch anh thng s dng cho 8951 l 12Mhz. Chn 40 (Vcc) c ni ln ngun 5V. III. CU TRC BN TRONG VI IU KHIN 1. T chc b nh:

FFFF FF 00 On - Chip Memory 0000 CODE Memory

FFFF DATA Memory

Enable via PSEN

0000

Enable via RD & WR

External Memory

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Bng tm tt cc vng nh 8951. Bn b nh Data trn Chip nh sau : a ch a ch byte a ch bit byte
7F RAM a dng E0 E7 E6 E5 E4 E3 E2 E1 E0 ACC

a ch bit
B

FF F0 F7 F6 F5 F4 F3 F2 F1 F0

D0 D7 D6 D5 D4 D3 D2 D1 D0 PSW 30 2F 2E 2D 2C 2B 2A 29 28 27 26 25 24 23 22 21 20 1F 18 17 10 0F 08 07 00 B8 7F 7E 77 76 6F 6E 67 66 5F 5E 57 56 4F 4E 47 46 3F 3E 37 36 2F 2E 27 26 1F 1E 17 16 0F 0E 07 06 Bank 3 Bank 2 Bank 1 Bank thanh ghi 0 (mc nh cho R0 -R7)
RAM

BC BB BA B9 B8 IP

7D 75 6D 65 5D 55 4D 45 3D 35 2D 25 1D 15 0D 05

7C 74 6C 64 5C 54 4C 44 3C 34 2C 24 1C 14 0C 04

7B 73 6B 63 5B 53 4B 43 3B 33 2B 23 1B 13 0B 03

7A 72 6A 62 5A 52 4A 42 3A 32 2A 22 1A 12 0A 02

79 71 69 61 59 51 49 41 39 31 29 21 19 11 09 01

78 70 68 60 58 50 48 40 38 30 28 20 18 10 08 00

B0 B7 B6 B5 B4 B3 B2 B1 B0 P.3 A8 AF AC AB AA A9 A8 IE

A0 A7 A6 A5 A4 A3 A2 A1 A0 P2 99 khng c a ch ho bit 98 9F 9E 9D 9C 9B 9A 99 98 90 97 96 95 94 93 92 91 90 8D 8C 8B 8A 89 khng c a ch ho bit khng c a ch ho bit khng c a ch ho bit khng c a ch ho bit khng c a ch ho bit SBUF SCON P1 TH1 TH0 TL1 TL0 TMOD TCON PCON DPH DPL SP P0

88 8F 8E 8D 8C 8B 8A 89 88 87 khng c a ch ho bit 83 82 81 80 khng c a ch ho bit khng c a ch ho bit khng c a ch ho bit 87 86 85 84 83 82 81 80

CC THANH GHI CHC NNG C BIT

- B nh trong 8951 bao gm ROM v RAM. RAM trong 8951 bao gm nhiu thnh phn: phn lu tr a dng, phn lu tr a ch ha tng bit, cc bank thanh ghi v cc thanh ghi chc nng c bit. - 8951 c b nh theo cu trc Harvard: c nhng vng b nh ring bit cho chng trnh v d liu. Chng trnh v d liu c th cha bn trong 8951 nhng 8951 vn c th kt ni vi 64K byte b nh chng trnh v 64K byte d liu. Hai c tnh cn ch la :

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Cc thanh ghi v cc port xut nhp c nh v (xc nh) trong b nh v c th truy xut trc tip ging nh cc a ch b nh khc. Ngn xp bn trong Ram ni nh hn so vi Ram ngoi nh trong cc b Microcontroller khc. RAM bn trong 8951 c Phn chia nh sau: Cc bank thanh ghi c a ch t 00H n 1FH. RAM a ch ha tng bit c a ch t 20H n 2FH. RAM a dng t 30H n 7FH. Cc thanh ghi chc nng c bit t 80H n FFH. RAM a dng: - Mc d trn hnh v cho thy 80 byte a dng chim cc a ch t 30H n 7FH, 32 byte di t 00H n 1FH cng c th dng vi mc ch tng t (mc d cc a ch ny c mc ch khc). - Mi a ch trong vng RAM a dng u c th truy xut t do dng kiu a ch trc tip hoc gin tip. RAM c th truy xut tng bit: - 8951 cha 210 bit c a ch ha, trong c 128 bit c cha cc byte c cha cc a ch t 20F n 2FH v cc bit cn li cha trong nhm thanh ghi c chc nng c bit. - tng truy xut tng bit bng phn mm l cc c tnh mnh ca microcontroller x l chung. Cc bit c th c t, xa, AND, OR, . . . , vi 1 lnh n. a s cc microcontroller x l i hi mt chui lnh c sa - ghi t c mc ch tng t. Ngoi ra cc port cng c th truy xut c tng bit. - 128 bit truy xut tng bit ny cng c th truy xut nh cc byte hoc nh cc bit ph thuc vo lnh c dng. Cc bank thanh ghi: - 32 byte thp ca b nh ni c dnh cho cc bank thanh ghi. B lnh 8951 h tr 8 thanh ghi c tn l R0 n R7 v theo mc nh sau khi reset h thng, cc thanh ghi ny c cc a ch t 00H n 07H. - Cc lnh dng cc thanh ghi RO n R7 s ngn hn v nhanh hn so vi cc lnh c chc nng tng ng dng kiu a ch trc tip. Cc d liu c dng thng xuyn nn dng mt trong cc thanh ghi ny. - Do c 4 bank thanh ghi nn ti mt thi im ch c mt bank thanh ghi c truy xut bi cc thanh ghi RO n R7 chuyn i vic truy xut cc bank thanh ghi ta phi thay i cc bit chn bank trong thanh ghi trng thi. 2. Cc thanh ghi c chc nng c bit: - Cc thanh ghi ni ca 8951 c truy xut ngm nh bi b lnh. - Cc thanh ghi trong 8951 c nh dng nh mt phn ca RAM trn chip v vy mi thanh ghi s c mt a ch (ngoi tr thanh ghi b m chng trnh v thanh ghi lnh v cc thanh ghi ny him khi b tc ng trc tip). Cng nh R0 n R7, 8951 c 21 thanh ghi c chc nng c bit (SFR: Special Function Register) vng trn ca RAM ni t a ch 80H n FFH. Ch : tt c 128 a ch t 80H n FFH khng c nh ngha, ch c 21 thanh ghi c chc nng c bit c nh ngha sn cc a ch. - Ngoi tr thanh ghi A c th c truy xut ngm nh ni, a s cc thanh ghi c chc nng c bit SFR c th a ch ha tng bit hoc byte.

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Thanh ghi trng thi chng trnh (PSW: Program Status Word): T trng thi chng trnh a ch D0H c tm tt nh sau:
BIT PSW.7 PSW.6 PSW.5 PSW4 PSW.3 SYMBOL ADDRESS CY AC F0 RS1 RS0 D7H D6H D5H D4H D3H DESCRIPTION Cary Flag Auxiliary Cary Flag Flag 0 Register Bank Select 1 Register Bank Select 0 00=Bank 0; address 00H07H 01=Bank 1; address 08H0FH 10=Bank 2; address 10H17H 11=Bank 3; address 18H1FH PSW.2 PSW.1 PSW.0 OV P D2H D1H DOH Overlow Flag Reserved Even Parity Flag

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Chc nng tng bit trng thi chng trnh

C Carry CY (Carry Flag): - C nh c tc dng kp. Thng thng n c dng cho cc lnh ton hc: C=1 nu php ton cng c s trn hoc php tr c mn v ngc li C= 0 nu php ton cng khng trn v php tr khng c mn. C Carry ph AC (Auxiliary Carry Flag): Khi cng nhng gi tr BCD (Binary Code Decimal), c nh ph AC c set nu kt qu 4 bit thp nm trong phm vi iu khin 0AH 0FH. Ngc li AC= 0. C 0 (Flag 0): C 0 (F0) l 1 bit c a dng dng cho cc ng dng ca ngi dng. Nhng bit chn bank thanh ghi truy xut: - RS1 v RS0 quyt nh dy thanh ghi tch cc. Chng c xa sau khi reset h thng v c thay i bi phn mm khi cn thit. - Ty theo RS1, RS0 = 00, 01, 10, 11 s c chn Bank tch cc tng ng l Bank 0, Bank1, Bank2, Bank3. RS1 0 0 1 1 C trn OV (Over Flag) : - C trn c set sau mt hot ng cng hoc tr nu c s trn ton hc. Khi cc s c du c cng hoc tr vi nhau, phn mm c th kim tra bit ny xc nh xem kt qu c nm trong tm xc nh khng. Khi cc s khng c du c cng bit OV c b qua. Cc kt qu ln hn +127 hoc nh hn 128 th bit OV = 1. Bit Parity (P): - Bit t ng c set hay Clear mi chu k my lp Parity chn vi thanh ghi A. S m cc bit 1 trong thanh ghi A cng vi bit Parity lun lun chn. V d A cha 10101101B th bit P set ln mt tng s bit 1 trong A v P to thnh s chn. - Bit Parity thng c dng trong s kt hp vi nhng th tc ca Port ni tip to ra bit Parity trc khi pht i hoc kim tra bit Parity sau khi thu. Thanh ghi B: RS0 0 1 0 1 BANK 0 1 2 3

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- Thanh ghi B a ch F0H c dng cng vi thanh ghi A cho cc php ton nhn chia. Lnh MUL AB s nhn nhng gi tr khng du 8 bit trong hai thanh ghi A v B, ri tr v kt qu 16 bit trong A (byte cao) v B(byte thp). Lnh DIV AB ly A chia B, kt qu nguyn t vo A, s d t vo B. - Thanh ghi B c th c dng nh mt thanh ghi m trung gian a mc ch. N l nhng bit nh v thng qua nhng a ch t F0HF7H. Con tr Ngn xp SP (Stack Pointer) : - Con tr ngn xp l mt thanh ghi 8 bit a ch 81H. N cha a ch ca byte d liu hin hnh trn nh ngn xp. Cc lnh trn ngn xp bao gm cc lnh ct d liu vo ngn xp (PUSH) v ly d liu ra khi Ngn xp (POP). Lnh ct d liu vo ngn xp s lm tng SP trc khi ghi d liu v lnh ly ra khi ngn xp s lm gim SP. Ngn xp ca 8031/8051 c gi trong RAM ni v gii hn cc a ch c th truy xut bng a ch gin tip, chng l 128 byte u ca 8951. - khi ng SP vi ngn xp bt u ti a ch 60H, cc lnh sau y c dng: MOV SP , #5F - Vi lnh trn th ngn xp ca 8951 ch c 32 byte v a ch cao nht ca RAM trn chip l 7FH. S d gi tr 5FH c np vo SP v SP tng ln 60H trc khi ct byte d liu. - Khi Reset 8951, SP s mang gi tr mc nh l 07H v d liu u tin s c ct vo nh ngn xp c a ch 08H. Nu phn mm ng dng khng khi ng SP mt gi tr mi th bank thanh ghi1 c th c 2 v 3 s khng dng c v vng RAM ny c dng lm ngn xp. Ngn xp c truy xut trc tip bng cc lnh PUSH v POP lu tr tm thi v ly li d liu, hoc truy xut ngm bng lnh gi chng trnh con ( ACALL, LCALL) v cc lnh tr v (RET, RETI) lu tr gi tr ca b m chng trnh khi bt u thc hin chng trnh con v ly li khi kt thc chng trnh con

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Con tr d liu DPTR (Data Pointer): -Con tr d liu (DPTR) c dng truy xut b nh ngoi l mt thanh ghi 16 bit a ch 82H (DPL: byte thp) v 83H (DPH: byte cao). Ba lnh sau s ghi 55H vo RAM ngoi a ch 1000H: MOV A , #55H MOV DPTR, #1000H MOV @DPTR, A - Lnh u tin dng np 55H vo thanh ghi A. Lnh th hai dng np a ch ca nh cn lu gi tr 55H vo con tr d liu DPTR. Lnh th ba s di chuyn ni dung thanh ghi A (l 55H) vo nh RAM bn ngoi c a ch cha trong DPTR (l 1000H). Cc thanh ghi Port (Port Register): - Cc Port ca 8951 bao gm Port0 a ch 80H, Port1 a ch 90H, Port2 a ch A0H, v Port3 a ch B0H. Tt c cc Port ny u c th truy xut tng bit nn rt thun tin trong kh nng giao tip. Cc thanh ghi Timer (Timer Register): - 8951 c cha hai b nh thi/ b m 16 bit c dng cho vic nh thi c m s kin. Timer0 a ch 8AH (TLO: byte thp ) v 8CH (THO: byte cao). Timer1 a ch 8BH (TL1: byte thp) v 8DH (TH1: byte cao). Vic khi ng timer c SET bi Timer Mode (TMOD) a ch 89H v thanh ghi iu khin Timer (TCON) a ch 88H. Ch c TCON c a ch ha tng bit . Cc thanh ghi Port ni tip (Serial Port Register) : - 8951 cha mt Port ni tip cho vic trao i thng tin vi cc thit b ni tip nh my tnh, modem hoc giao tip ni tip vi cc IC khc. Mt thanh ghi m d liu ni tip (SBUF) a ch 99H s gi c hai d liu truyn v d liu nhp. Khi truyn d liu ghi ln SBUF, khi nhn d liu th c SBUF. Cc mode vn khc nhau c lp trnh qua thanh ghi iu khin Port ni tip (SCON) c a ch ha tng bit a ch 98H. Cc thanh ghi ngt (Interrupt Register): - 8951 c cu trc 5 ngun ngt, 2 mc u tin. Cc ngt b cm sau khi b reset h thng v s c cho php bng vic ghi thanh ghi cho php ngt (IE) a ch A8H. C hai c a ch ha tng bit.

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Thanh ghi iu khin ngun PCON (Power Control Register): - Thanh ghi PCON khng c bit nh v. N a ch 87H cha nhiu bit iu khin. Thanh ghi PCON c tm tt nh sau: Bit 7 (SMOD) : Bit c tc Baud mode 1, 2, 3 Port ni tip khi set. Bit 6, 5, 4 : Khng c a ch. Bit 3 (GF1) : Bit c a nng 1. Bit 2 (GF0) : Bit c a nng 2 . Bit 1 (PD) : Set khi ng mode Power Down v thot reset. Bit 0 (IDL) : Set khi ng mode Idle v thot khi ngt mch hoc reset. Cc bit iu khin Power Down v Idle c tc dng chnh trong tt c cc IC h MSC-51 nhng ch c thi hnh trong s bin dch ca CMOS. 3. B nh ngoi (external memory) : - 8951 c kh nng m rng b nh ln n 64K byte b nh chng trnh v 64k byte b nh d liu ngoi. Do c th dng thm RAM v ROM nu cn. - Khi dng b nh ngoi, Port0 khng cn chc nng I/O na. N c kt hp gia bus a ch (A0-A7) v bus d liu (D0-D7) vi tn hiu ALE cht byte ca bus a ch khi bt u mi chu k b nh. Port c cho l byte cao ca bus a ch. Truy xut b nh m ngoi (Accessing External Code Memory) : - B nh chng trnh bn ngoi l b nh ROM c cho php ca tn hiu PSEN\. S kt ni phn cng ca b nh EPROM nh sau:
Port 0 EA
74HC373

D0 D7 A0 A7

8951

ALE Port 2 PSEN

O G

EPROM
A8 A15 OE

- Trong mt chu k my tiu biu, tn hiu ALE tch 2 ln. Ln th nht cho php 74HC373 m cng cht a ch byte thp, khi ALE xung 0 th byte thp v byte cao ca b m chng trnh u c nhng EPROM cha xut v PSEN\ cha tch cc, khi tn hiu ln mt tr li th Port 0 c d liu l Opcode. ALE tch cc ln th hai c gii thch tng t v byte 2 c c t b nh chng trnh. Nu lnh ang hin hnh l lnh 1 byte th CPU ch c Opcode, cn byte th hai b i. Truy xut b nh d liu ngoi (Accessing External Data Memory): - B nh d liu ngoi l mt b nh RAM c c hoc ghi khi c cho php ca tn hiu RD\ v WR. Hai tn hiu ny nm chn P3.7 (RD) v P3.6 (WR).

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Lnh MOVX c dng truy xut b nh d liu ngoi v dng mt b m d liu 16 bit (DPTR), R0 hoc R1 nh l mt thanh ghi a ch. - Cc RAM c th giao tip vi 8951 tng t cch thc nh EPROM ngoi tr chn RD\ ca 8951 ni vi chn OE\ (Output Enable) ca RAM v chn WR\ ca 8951 ni vi chn WE\ ca RAM. S ni cc bus a ch v d liu tng t nh cch ni ca EPROM.

Port 0
74HC373

D0 D7 RAM
O G D

8951

EA\

A0 A7

ALE A8 A15 OE\

Port 2

S gii m a ch (Address Decoding): - S gii m a ch l mt yu cu tt yu chn EPROM, RAM, 8279, S gii m a ch i vi 8951 chn cc vng nh ngoi nh cc vi iu khin. Nu cc con EPROM hoc RAM 8K c dng th cc bus a ch phi c gii m chn cc IC nh nm trong phm vi gii hn 8K: 0000H1FFFH, 2000H3FFFH, . . - Mt cch c th, IC gii m 74HC138 c dng vi nhng ng ra ca n c ni vi nhng ng vo chn Chip CS (Chip Select) trn nhng IC nh EPROM, RAM, Hnh sau y cho php kt ni nhiu EPROM v RAM.

RD\

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Address Bus (A0 Data Bus (D0 D7)

PSEN \

D0 - D7 OE EPROM A0 A12 8K Bytes CS

RD\ WR\

OE D0 - D7 W RAM A0 A12 8K Bytes CS

74HC138

CS CS

CS CS

C B A E E0 Address E1

0 1 2 3 4 5 6 Decoding 7

Select other EPROM/RAM

(Gii m a ch)

S ln nhau ca cc vng nh d liu ngoi: - V b nh chng trnh l ROM, nn ny sinh mt vn bt tin khi pht trin phn mm cho vi iu khin. Mt nhc im chung ca 8951 l cc vng nh d liu ngoi nm ln nhau, v tn hiu PSEN\ c dng c b nh m ngoi v tn hiu RD\ c dng c b nh d liu, nn mt b nh RAM c th cha c chng trnh v d liu bng cch ni ng OE\ ca RAM n ng ra mt cng AND c hai ng vo PSEN\ v RD\. S mch nh hnh sau cho php cho php b nh RAM c hai chc nng va l b nh chng trnh va l b nh d liu: RAM WR\ RD\ WR\

OE\ PSEN\ Overlapping the External code and data space -Vy mt chng trnh c th c ti vo RAM bng cch xem n nh b nh d liu v thi hnh chng trnh bng cch xem n nh b nh chng trnh. Hot ng Reset:

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- 8951 c ng vo reset RST tc ng mc cao trong khong thi gian 2 chu k xung my, sau xung mc thp 8951 bt u lm vic. RST c th kch bng tay bng mt phm nhn thng h, s mch reset nh sau: +5V
100

Reset

10 F RST 8.2 K

Manual Reset

Reset bng tay.

Trng thi ca tt c cc thanh ghi trong 8951 sau khi reset h thng c tm tt nh sau: Thanh ghi Ni dung m chng trnh PC Thanh ghi tch ly A Thanh ghi B Thanh ghi thi PSW SP DPRT Port 0 n port 3 IP IE Cc thanh ghi nh thi SCON SBUF PCON (MHOS) PCON (CMOS) 0000H 00H 00H 00H 07H 0000H FFH XXX0 0000 B 0X0X 0000 B 00H 00H 00H 0XXX XXXXH 0XXX 0000 B

-Thanh ghi quan trng nht l thanh ghi b m chng trnh PC c reset tai a ch 0000H. Khi ng vo RST xung mc thp, chng trnh lun bt u ti a ch 0000H ca b nh chng trnh. Ni dung ca RAM trn chip khng b thay i bi tc ng ca ng vo reset. VI. HOT NG TIMER CA 8951: 1. GII THIU: - B nh thi ca Timer l mt chui cc Flip Flop c chia lm 2, n nhn tn hiu vo l mt ngun xung clock, xung clock c a vo Flip Flop th nht l xung clock ca Flip Flop th hai m n cng chia tn s clock ny cho 2 v c tip tc.

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- V mi tng k tip chia cho 2, nn Timer n tng phi chia tn s clock ng vo cho 2n. Ng ra ca tng cui cng l clock ca Flip Flop trn Timer hoc c m n kim tra bi phn mm hoc sinh ra ngt. Gi tr nh phn trong cc FF ca b Timer c th c ngh nh m xung clock hoc cc s kin quan trng bi v Timer c khi ng. V d Timer 16 bit c th m n t FFFFH sang 0000H. - Hot ng ca Timer n gin 3 bit c minh ha nh sau: Flag FF
D Q Q0 D Q Q1 D Q Q2 D Q Q3

LSB Timer Flip Flops. Clock Q0 (LSB) Q1 Q2 Count Flag 0 1 2 3

MSB

Flag

- Trong hnh trn mi tng l mt FF loi D ph nh tc ng cnh xung c hot ng mode chia cho 2 (ng ra Q\ c ni vo D). FF c l mt b cht n gin loi D c set bi tng cui cng trong Timer. Trong biu thi gian, tng u i trng thi tn s clock, tng th hai i trng thi tn s tn s clock . . . S m c bit dng thp phn v c kim tra li d dng bi vic kim tra cc tng ca 3 FF. V d s m 4 xut hin khi Q2=1, Q1=0, Q0=0 (410=1002). - Cc Timer c ng dng thc t cho cc hot ng nh hng. 8951 c 2 b Timer 16 bit, mi Timer c 4 mode hot ng. Cc Timer dng m gi, m cc s kin cn thit v s sinh ra tc ca tc Baud bi s gn lin Port ni tip. - Mi s nh thi l mt Timer 16 bit, do tng cui cng l tng th 16 s chia tn s clock vo cho 216 = 65.536. - Trong cc ng dng nh thi, 1 Timer c lp trnh trn mt khong thi gian u n v c set c trn Timer. C c dng ng b chng trnh thc hin mt hot ng nh vic a ti 1 tng cc ng vo hoc gi d liu m ng ra. Cc ng dng khc c s dng vic ghi gi u u ca Timer o thi gian

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tri qua hai trng thi (v d o rng xung).Vic m mt s kin c dng xc nh s ln xut hin ca s kin , tc thi gian tri qua gia cc s kin. - Cc Timer ca 8951 c truy xut bi vic dng 6 thanh ghi chc nng c bit nh sau : Timer SFR TCON TMOD TL0 TL1 TH0 TH1 Purpose Control Mode Timer 0 low-byte Timer 1 low-byte Timer 0 high-byte Timer 1 high-byte Address 88H 89H 8AH 8BH 8CH 8DH Bit-Addressable YES NO NO NO NO NO

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2. CC THANH GHI IU KHIN TIMER 2.1. Thanh ghi iu khin ch timer TMOD (timer mode register) : - Thanh ghi mode gm hai nhm 4 bit l: 4 bit thp t mode hot ng cho Timer 0 v 4 bit cao t mode hot ng cho Timer 1. 8 bit ca thanh ghi TMOD c tm tt nh sau: Bit 7 6 Name GATE C/T Timer 1 1 Description Khi GATE = 1, Timer ch lm vic khi INT1=1 Bit cho m s kin hay ghi gi C/T = 1 : m s kin C/T = 0 : Ghi gi u n 5 4 3 2 1 0 M1 M0 GATE C/T M1 M0 1 1 0 0 0 0 Bit chn mode ca Timer 1 Bit chn mode ca Timer 1 Bit cng ca Timer 0 Bit chn Counter/Timer ca Timer 0 Bit chn mode ca Timer 0 Bit chn mode ca Timer 0

Hai bit M0 v M1 ca TMOD chn mode cho Timer 0 hoc Timer 1. M1 0 0 1 1 M0 0 1 0 1 MODE 0 1 2 3 DESCRIPTION Mode Timer 13 bit (mode 8048) Mode Timer 16 bit Mode t ng np 8 bit Mode Timer tch ra : Timer 0 : TL0 l Timer 8 bit c iu khin bi cc bit ca Timer 0. TH0 tng t nhng c iu khin bi cc bit ca mode Timer 1. Timer 1 : c ngng li. - TMOD khng c bit nh v, n thng c LOAD mt ln bi phn mm u chng trnh khi ng mode Timer. Sau s nh gi c th dng li, c khi ng li nh th bi s truy xut cc thanh ghi chc nng c bit ca Timer khc.

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2.2. Thanh ghi iu khin timer TCON (timer control register): - Thanh ghi iu khin bao gm cc bit trng thi v cc bit iu khin bi Timer 0 v Timer 1. Thanh ghi TCON c bit nh v. Hot ng ca tng bit c tm tt nh sau : Bit TCON.7 Symbol TF1 Bit Address 8FH Description C trn Timer 1 c set bi phn cng s trn, c xa bi phn mm hoc bi phn cng khi cc vect x l n th tc phc v ngt ISR Bit iu khin chy Timer 1 c set hoc xa bi phn mm chy hoc ngng chy Timer. C trn Timer 0(hot ng tng t TF1) Bit iu khin chy Timer 0 (ging TR1) C kiu ngt 1 ngoi. Khi cnh xung xut hin trn INT1 th IE1 c xa bi phn mm hoc phn cng khi CPU nh hng n th tc phc v ngt ngoi. C kiu ngt 1 ngoi c set hoc xa bng phn mm bi cnh kch hot bi s ngt ngoi. C cnh ngt 0 ngoi C kiu ngt 0 ngoi.

TCON.6

TR1

8EH

TCON.5 TCON.4 TCON.3

TF0 TR0 IE1

8DH 8CH 8BH

TCON.2

IT1

8AH

TCON.1 TCON

IE0 IT0

89H 88H

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2.3. Cc ngun xung nhp cho timer (clock sources): - C hai ngun xung clock c th m gi l s nh gi bn trong v s m s kin bn ngoi. Bit C/T trong TMOD cho php chn 1 trong 2 khi Timer c khi ng. Crystal

On Chip Oscillator

12

Timer Clock

T0 or T1 pin C/T

0 = Up (internal Timing) 1 = Down (Event Counting) S bm gi bn trong (Interval Timing): - Nu bit C/T = 0 th hot ng ca Timer lin tc c chn vo b Timer c ghi gi t dao ng trn Chip. Mt b chia 12 c thm vo gim tn s clock n 1 gi tr ph hp vi cc ng dng. Cc thanh ghi TLx v THx tng tc 1/12 ln tn s dao ng trn Chip. Nu dng thch anh 12MHz th s a n tc clock 1MHz. - Cc s trn Timer sinh ra sau mt con s c nh ca nhng xung clock, n ph thuc vo gi tr khi to c LOAD vo cc thanh ghi THx v TLx.

S m cc s kin (Event Counting) :

- Nu bit C/T = 1 th b Timer c ghi gi t ngun bn ngoi trong nhiu ng dng, ngun bn ngoi ny cung cp 1 s nh gi vi 1 xung trn s xy ra ca s kin. S nh gi l s m s kin. Con s s kin c xc nh trong phn mm bi vic c cc thanh ghi Timer. Tlx/THx, bi v gi tr 16 bit trong cc thanh ny tng ln cho mi s kin. - Ngun xung clock bn ngoi a vo chn P3.4 l ng nhp ca xung clock bi Timer 0 (T0) v P3.5 l ng nhp ca xung clock bi Timer 1 (T1). - Trong cc ng dng m cc thanh ghi Timer c tng trong p ng ca s chuyn trng thi t 1 sang 0 ng nhp Tx. Ng nhp bn ngoi c th trong sut S5P2 ca mi chu k my: Do khi ng nhp a ti mc cao trong mt chu k v mc thp trong mt chu k k tip th b m tng ln mt. Gi tr mi xut hin trong cc thanh ghi Timer trong sut S5P1 ca chu k theo sau mt s chuyn i. Bi v n chim 2 chu k my (2s) nhn ra s chuyn i t 1 sang 0, nn tn s bn ngoi ln nht l 500KHz nu dao ng thch anh 12 MHz.

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2.4. s bt u, kt thc v s iu khin cc timer (starting, stopping and controlling the timer) : - Bit TRx trong thanh ghi c bit nh v TCON c iu khin bi phn mm bt u hoc kt thc cc Timer. bt u cc Timer ta set bit TRx v kt thc Timer ta Clear TRx. V d Timer 0 c bt u bi lnh SETB TR0 v c kt thc bi lnh CLR TR0 (bit Gate= 0). Bit TRx b xa sau s reset h thng, do cc Timer b cm bng s mc nh. - Thm phng php na iu khin cc Timer l dng bit GATE trong thanh ghi TMOD v ng nhp bn ngoi INTx. iu ny c dng o cc rng xung. Gi s xung a vo chn INT0 ta khi ng Timer 0 cho mode 1 l mode Timer 16 bit vi TL0/TH0 = 0000H, GATE = 1, TR0 = 1. Nh vy khi INT0 = 1 th Timer c m cng v ghi gi vi tc ca tn s 1MHz. Khi INT0 xung thp th Timer ng cng v khong thi gian ca xung tnh bng s l s m c trong thanh ghi TL0/TH0. On Chip Oscillator
12 MHz T0 (P3.4)

12

TL0 TH0

TF0

C/T TR0

GATE

INTO (P3.2) Timer Operating Mode 1.

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2.5. S khi ng v truy xut cc thanh ghi timer: - Cc Timer c khi ng 1 ln u chng trnh t mode hot ng cho chng. Sau trong chng trnh cc Timer c bt u, c xa, cc thanh ghi Timer c c v cp nht theo yu cu ca tng ng dng c th. - Mode Timer TMOD l thanh ghi u tin c khi gn, bi v t mode hot ng cho cc Timer. V d khi ng cho Timer 1 hot ng mode 1 (mode Timer 16bit) v c ghi gi bng dao ng trn Chip ta dng lnh : MOV TMOD, # 00001000B. Trong lnh ny M1 = 0, M0 = 1 vo mode 1 v C/T = 0, GATE = 0 cho php ghi gi bn trong ng thi xa cc bit mode ca Timer 0. Sau lnh trn Timer vn cha m gi, n ch bt u m gi khi set bit iu khin chy TR1 ca n. - Nu ta khng khi gn gi tr u cho cc thanh ghi TLx/THx th Timer s bt u m t 0000Hln v khi trn t FFFFH sang 0000H n s bt u trn TFx ri tip tc m t 0000H ln tip . . . - Nu ta khi gn gi tr u cho TLx/THx, th Timer s bt u m t gi tr khi gn ln nhng khi trn t FFFFH sang 0000H li m t 0000H ln. - Ch rng c trn TFx t ng c set bi phn cng sau mi s trn v s c xa bi phn mm. Chnh v vy ta c th lp trnh ch sau mi ln trn ta s xa c TFx v quay vng lp khi gn cho TLx/THx Timer lun lun bt u m t gi tr khi gn ln theo ta mong mun. c bit nhng s khi gn nh hn 256 s, ta s gi mode Timer t ng np 8 bit ca mode 2. Sau khi khi gn gi tr u vo THx, khi set bit TRx th Timer s bt u m gi tr khi gn v khi trn t FFH sang 00H trong TLx, c TFx t ng c set ng thi gi tr khi gn m ta khi gn cho Thx c np t ng vo TLx v Timer li c m t gi tr khi gn ny ln. Ni cch khc, sau mi trn ta khng cn khi gn li cho cc thanh ghi Timer m chng vn m c li t gi tr ban u. 3. CC CH TIMER V C TRN (TIMER MODES AND OVERFLOW): - 8951 c 2 Timer l Timer 0 v timer 1. Ta dng k hiu TLx v Thx ch 2 thanh ghi byte thp v byte cao ca Timer 0 hoc Timer 1. 3.1. Mode Timer 13 bit (MODE 0) :
Timer Clock

Overflow

TLx (5 bit) THx (8 bit)

TFx

- Mode 0 l mode Timer 13 bit, trong byte cao ca Timer (Thx) c t thp v 5 bit trng s thp nht ca byte thp Timer (TLx) t cao hp thnh Timer 13 bit. 3 bit cao ca TLx khng dng. 3.2. Mode Timer 16 bit (MODE 1) : Timer Clock TLx (8 bit) THx (8 bit) TFx

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- Mode 1 l mode Timer 16 bit, tng t nh mode 0 ngoi tr Timer ny hot ng nh mt Timer y 16 bit, xung clock c dng vi s kt hp cc thanh ghi cao v thp (TLx, THx). Khi xung clock c nhn vo, b m Timer tng ln 0000H, 0001H, 0002H, , v mt s trn s xut hin khi c s chuyn trn b m Timer t FFFH sang 0000H v s set c trn Time, sau Timer m tip. - C trn l bit TFx trong thanh ghi TCON m n s c c hoc ghi bi phn mm. - Bit c trng s ln nht (MSB) ca gi tr trong thanh ghi Timer l bit 7 ca THx v bit c trng s thp nht (LSB) l bit 0 ca TLx. Bit LSB i trng thi tn s clock vo c chia 216 = 65.536. - Cc thanh ghi Timer TLx v Thx c th c c hoc ghi ti bt k thi im no bi phn mm. 3.3. Mode t ng np 8 bit (MODE 2) : Timer Clock TL x (8 bit) Reload TH x (8 bit) -Mode 2 l mode t ng np 8 bit, byte thp TLx ca Timer hot ng nh mt Timer 8 bit trong khi byte cao THx ca Timer gi gi tr Reload. Khi b m trn t FFH sang 00H, khng ch c trn c set m gi tr trong THx cng c np vo TLx : B m c tip tc t gi tr ny ln n s chuyn trng thi t FFH sang 00H k tip v c th tip tc. Mode ny th ph hp bi v cc s trn xut hin c th m mi lc ngh thanh ghi TMOD v THx c khi ng. TFx Overflow

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3.4 Mode Timer tch ra (MODE 3) : Timer Clock TL1 (8 bit) TH1 (8 bit) Overflow

Timer Clock

TL1 (8 bit)

TF0

Timer Clock TH0 (8 bit) TF1 - Mode 3 l mode Timer tch ra v l s khc bit cho mi Timer. - Timer 0 mode 3 c chia l 2 timer 8 bit. TL0 v TH0 hot ng nh nhng Timer ring l vi s trn s set cc bit TL0 v TF1 tng ng. - Timer 1 b dng li mode 3, nhng c th c khi ng bi vic ngt n vo mt trong cc mode khc. Ch c nhc im l c trn TF1 ca Timer 1 khng b nh hng bi cc s trn ca Timer 1 bi v TF1 c ni vi TH0. - Mode 3 cung cp 1 Timer ngoi 8 bit l Timer th ba ca 8951. Khi vo Timer 0 mode 3, Timer c th hot ng hoc tt bi s ngt n ra ngoi v vo trong mode ca chnh n hoc c th c dng bi Port ni tip nh l mt my pht tc Baud, hoc n c th dng trong hng no m khng s dng Interrupt. V. HOT NG PORT NI TIP 1. Gii thiu 8951 c mt port ni tip trong chip c th hot ng nhiu ch trn mt dy tn s rng. Chc nng ch yu l thc hin chuyn i song song sang ni tip vi d liu xut v chuyn i ni tip sang song song vi d liu nhp. Port ni tip cho hot ng song cng (full duplex: thu v pht ng thi) v m thu (receiver buffering) cho php mt k t s c thu v c gi trong khi k t th hai c nhn. Nu CPU c k t th nht trc khi k t th hai c thu y th d liu s khng b mt. Hai thanh ghi chc nng c bit cho php phn mm truy xut n port ni tip l: SBUF v SCON. B m port ni tip (SBUF) i ch 99H nhn d liu thu hoc pht. Thanh ghi iu khin port ni tip (SCON) i ch 98H l thanh ghi c i ch bit cha cc bit trng thi v cc bit iu khin. Cc bit iu khin t ch hot ng cho port ni tip, v cc bit trng thi Bo co kt thc vic pht hoc thu k t . Cc bit trng thi c th c kim tra bng phn mm hoc c th lp trnh to ngt.

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SUBF

(Ch ghi)

Thanh ghi dch

SBUF

(ch c)
SBUF

(ch c) BUS ni 8051/8031 2. Cc thanh ghi v cc ch hot ng ca port ni tip: 2.1. Thanh ghi iu khin port ni tip: Ch hot ng ca port ni tip c t bng cch ghi vo thanh ghi ch port ni tip (SCON) a ch 98H .Sau y cc bn tm tt thanh ghi SCON v cc ch ca port ni tip: Bit SCON.7 SCON.6 SCON.5 K hiu SM0 SM1 SM3 a ch 9FH 9EH 9DH M t Bit 0 ca ch port ni tip Bit 1 ca ch port ni tip Bit 2 ca ch port ni tip . Cho php truyn thng x l trong cc ch 2 v 3, RI s khng b tc ng nu bit th 9 thu c l 0 Cho php b thu phi c t ln 1 thu cc k t Bit 8 pht, bit th 9 c pht trong ch 2 v 3, c t v xa bng phn mm. B it 8 thu, bit th 9 thu c C ngt pht. t ln 1 khi kt thc pht k t, c xa bng phn mm C ngt thu. t ln 1 khi kt thc thu k t, c xa bng phn mm

SCON.4 SCON.3 SCON.2 SCON.1 SCON.0

REN TB8 RB8 TI RI

9CH 9BH 9AH 99H 98H

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Tm tt thanh ghi ch port ni tip SM0 0 0 1 1 SM1 0 1 0 1 Ch 0 1 2 3 M t Thanh ghi dch UART 8 bit UART 9 bit UART 9 bit Tc baud C nh (Fosc /12 ) Thay i ( t bng timer ) C nh (Fosc /12 hoc Fosc/64 ) Thay i ( t bng timer )

Cc ch port ni tip Trc khi s dng port ni tip, phi khi ng SCON cho ng ch . V d, lnh sau: MOV SCON, #01010010B Khi ng port ni tip cho ch 1 (SM0/SM1=0/1), cho php b thu (REN=1) v c ngt pht (TP=1) b pht sn sng hot ng. 2.2. Ch 0 (Thanh ghi dch n 8 bit) : Ch 0 c chn bng cc thanh ghi cc bit 0 vo SM1 v SM2 ca SCON, a port ni tip vo ch thanh ghi dch 8bit. D liu ni tip vo v ra qua RXD v TXD xut xung nhp dch, 8 bit c pht hoc thu vi bit u tin l LSB. Tc baud c nh 1/12 tn s dao ng trn chip. Vic pht i c khi ng bng bt c lnh no ghi d liu vo SBUF. D liu dch ra ngoi trn ng RXD (P3.0) vi cc xung nhp c gi ra ng TXD (P3.1). Mi bit pht i hp l (trn RXD) trong mt chu k my, tn hiu xung nhp xung thp S3P1 v tr v cao S6P1.

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Mt chu k my

S1 S5 S6

S2

S3

S4

OSC
ALE
Data Out Shift Clock WRITE to SBUF

P1

P2 P1

P2 P1

P2

P1 P2

P1 P2

P1

Bit Data Hp L S3P1

S6P1

Phng to

ALE Data Out RXD Shift Clock (TXD)

Gin thi gian Port ni tip pht ch 0

Vic thu c khi ng khi cho php b thu (REN) l 1 v bit ngt thu (RI) l 0. Quy tc tng qut l t REN khi bt u chng trnh khi ng port ni tip, ri xo RI bt u nhn d liu. Khi RI b xo, cc xung nhp c a ra ng TXD, bt u chu k my k tip v d liu theo xung nhp ng RXD. Ly xung nhp cho d liu vo port ni tip xy ra cnh ng ca TXD.

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Mt chu k my

Data out Shift clock

D0

D1

D2

D3

D4

D5

D6

D7

Gin thi gian pht ni tip ch 0

2.3. Ch 1 (UART 8 bit vi tc baud thay i c): ch 1, port ni tip ca 8951 lm vic nh mt UART 8 bit vi tc baud thay i c. Mt UART (B thu pht ng b vn nng) l mt dng c thu pht d liu ni tip vi mi k t d liu i trc l bit start mc thp v theo sau bit stop mc cao. i khi xen thm bit kim tra chn l gia bit d liu cui cng v bit stop. Hot ng ch yu ca UART l chuyn i song song sang ni tip vi d liu nhp. ch 1, 10 bit c pht trn TXD hoc thu trn RXD. Nhng bit l: 1 bit start (lun lun l 0), 8 bit d liu (LSB u tin) v 1 bit stop (lun lun l 1). Vi hot ng thu, bit stop c a vo RB8 trong SCON. Trong 8951 ch baud c t bng tc bo trn ca timer 1. To xung nhp v ng b ha cc thanh ghi dch ca port ni tip trong cc ch 1,2 v 3 c thit lp bng b m 4 bit chia cho 16, ng ra l xung nhp tc baud. Ng vo ca b m ny c chn qua phn mm Tc baud

16

Xung nhp tc baud Thanh ghi dch port ni tip 2.4. UART 9 bit vi tc baud c nh (ch 2): Khi SM1=1 v SM0=0, cng ni tip lm vic ch 2, nh mt UART 9bit c tc baud c nh, 11 bit s c pht hoc thu:1bit start, 8 bit data, 1 bit data th 9 c th c lp trnh v 1 bit stop. Khi pht bit th 9 l bt c g c a vo TB8 trong SCON (c th l bit Parity) .Khi thu bit th 9 thu c s trong RB8. Tc baud ch 2 l 1/32 hoc 1/16 tn s dao ng trn chip. 2.5. UART 9 bit vi tc baud thay i c (ch 3): Ch ny ging nh ch 2 ngoi tr tc baud c th lp trnh c v c cung cp bi Timer.Tht ra cc ch 1, 2, 3 rt ging nhau. Ci khc bit l

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tc baud (c nh trong ch 2, thay i trong ch 1 v 3) v s bit data (8 bit trong ch 1,9 trong ch 2 v 3). 2.6. Khi ng v truy xut cc thanh ghi cng ni tip: Cho Php Thu Bit cho php b thu (REN=Receiver Enable) Trong SCON phi c t ln 1bng phn mm cho php thu cc k t thng thng thc hin vic ny u chng trnh khi khi ng cng ni tip, timer C th thc hin vic ny theo hai cch. Lnh: SETB REN ; t REN ln 1 Hoc lnh MOV SCON,#XXX1XXXXB ; t REN ln 1 hoc xo cc bit khc trn SCON khi cn (cc X phi l 0 hoc 1 t ch lm vic) Bit d liu th 9: Bit d liu th 9 cn pht trong cc ch 2 v 3 phi c np vo trong TB8 bng phn mm. Bit d liu th 9 thu c t RB8. Phn mm c th cn hoc khng cn bit d liu th 9, ph thuc vo c tnh k thut ca thit b ni tip s dng (bit d liu th 9 cng ng vai tr quan trng trong truyn thng a x l ) Thm 1 bit parity: Thng s dng bit d liu th 9 thm parity vo k t. Nh nhn xt chng trc, bit P trong t trng thi chng trnh (PSW) c t ln 1 hoc b xo bi chu k my thit lp kim tra chn vi 8 bit trong thanh tch ly. Cc c ngt: Hai c ngt thu v pht (RI v TI) trong SCON ng mt vai tr quan trng trong truyn thng ni tip dng 8951/8051. C hai bit c t ln 1 bng phn cng, nhng phi c xo bng phn mm. 2.7. Tc baud port ni tip Nh ni, tc baud c nh cc ch 0 v 2. Trong ch 0 n lun lun l tn s dao ng trn chip c chia cho 12. Thng thng thch anh n nh tn s dao ng trn chip nhng cng c th s dng ngun xung nhp khc.

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Dao ng trn chip baud

Xung nhp

12
tc

a. Ch 0

64
SMOD=0 Dao ng trn chip SMOD=1 Xung nhp tc baud

32
b. Ch 2

Dao ng trn chip

32

SMOD=0 SMOD=1

Xung nhp tc baud

c. Ch 1 v 3 Cc ngun to xung nhp cho port ni tip Mc nhin sau khi reset h thng, tc baud ch 2 l tn s b dao ng chia cho 64, tc baud cng b nh hng bi 1 bit trong thanh ghi iu khin ngun cung cp (PCON) bit 7 ca PCON l bit SMOD. t bit SMOD ln 1 lm gp i tc baud trong cc ch 1, 2 v 3. Trong ch 2, tc baud c th b gp i t gi tr mc nhin ca 1/64 tn s dao ng (SMOD=0) n 1/32 tn s dao ng (SMOD=1) V PCON khng c nh a ch theo bit, nn t bit SMOD ln 1 cn phi theo cc lnh sau: MOV A,PCON ; ly gi tr hin thi ca PCON SETB ACC.7 ; t bit SMOD ln 1 MOV PCON,A ; ghi gi tr ngc v PCON Cc tc baud trong cc ch 1 v 3 c xc nh bng tc trn ca timer 1. V timer hot ng tn s tng i cao, trn timer c chia thm cho 32 (hoc 16 nu SMOD =1 ) trc khi cung cp tc xung nhp cho port ni tip. 3. T chc ngt trong 8051 Vi iu Khin c 5 ngun ngt:2 ngun ngt ngoi,2 ngt timer v 1 ngt Port ni tip, tt c cc ngun ngt b cm sau khi reset h thng v cho php bi phn mm 3.1.Cho Php v Khng Cho Php Ngt Mi ngun ngt c cho php hoc khng cho php thng qua thanh ghi chc nng c bit c cc bit c a ch ha IE (Interrupt Enable) ti a ch 0A8H. BIT SYMBOL BIT ADDRESS DESCRIPTION (1:ENABLE,0:DISABLE)

16

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IE.7 IE.6 IE.5 IE.4 IE.3 IE.2 IE.1 IE.0

EA EA ET2 ES ET1 EX1 ET0 EX0

AFH AEH ADH ACH ABH AAH A9H A8H

Global Enable/Disable Undefined Enable Timer 2 Interrupt (8052) Enable Serial Port Interrupt Enable Timer 1 Interrupt Enable External 1 Interrupt Enable Timer 0 Interrupt Enable External 0 Interrupt

a. u tin ngt. Mi ngun ngt uc lp trnh ring vo mt trong hai mc u tin qua thanh ghi chc nng c bit c a ch bit Ip (Interrupt priority : u tin ngt) a ch B8H. Bit IP.7 IP.6 IP.5 IP.4 IP.3 IP.2 IP.1 IP.0 K hiu a ch bit M t (1=mc cao hn,0=mc thp) Khng c nh ngha Khng c nh ngha u tin cho ngt t timer 2 (8052) u tin cho ngt Port ni tip u tin cho ngt t timer 1 u tin cho ngt ngoi u tin cho ngt t timer 0 u tin cho ngt ngoi 0

PT2 PS PT1 PX1 PT0 PX0

BDH BCH BBH BAH B9H B8H

Tm tt thanh ghi IP. Cc ngt u tin c xa sau khi reset h thng ttt c cc ngt mc u tin thp hn. 3.2 X l ngt. Khi c mt ngn xy ra v c CPU chp nhn, chng trnh chnh b ngt qung. Nhng hot ng sau xy ra: - Thi hnh hon chnh lnh ang hin hnh. - Cc DC vo ngt xp. - Trng thi ngt hin hnh c ct bn trong. - Cc ngt c chn ti mc ca ngt. - Nap vp DC a ch Vector ca ISR. - ISR thc thi. ISR thc thi v p ng ngt. ISR hon tt bng lnh RET1. iu ny lm ly li gi tr c ca PC t ngn xp v ly li trng thi ngt c. Chng trnh li tip tc thi hnh ti ni m n dng. 3.3 VcT Ngt Khi ngt c chp nhn gi tr c a vo PC (Program Counter) gi l vector ngt (Interrupt Vector) INTERRUPT FLAG VECTOR ADDRESS

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System Reset External 0 Timer 0 External 1 Timer 1 Serial Port Timer 2 3.4

RST IE0 TF0 IE1 TF1 RI OR TI TF2 OR EXF2

0000 H 0003 H 000B H 0013 H 001B H 0023 H 002B H

Ngt Port ni Tip Ngt Port ni tip xy ra khi c 2 c ngt truyn (TI) hoc c ngt nhn (RI) c t. Ngt truyn xy ra khi bit cui cng trong SBUF truyn xong tc l lc ny thanh ghi SBUF rng .Ngt nhn xy ra khi SBUF hon thnh vic nhn v ang i c tc l lc ny thanh ghi SBUF y. C hai c ngt ny c t bi phn cng v xa bng phn mm. Cc ngt ca 8051. a. Cc ngt timer. Cc ngt timer c a ch Vector ngt l 000BH (timer 0) v 001BH (timer 1). Ngt timer xy ra khi cc thanh ghi timer (TLx ITHx) trn v set c bo trn (TFx) ln 1. Cc c timer (TFx) khng b xa bng phn mm. Khi cho php cc ngt, TFx t ng b xa bng phn cng khi CPU chuyn n ngt. b. Cc ngt cng ni tip. Ngt cng ni tip xy ra khi hoc c pht (TI) hoc c ngt thu (KI) c t ln 1. Ngt pht xy ra khi mt k t c nhn xong v ang i trong SBUP c c. Cc ngt cng ni tip khc vi cc ngt timer. C gy ra ngt cng ni tip khng b xa bng phn cng khi CPU chuyn ti ngt. Do c hai ngun ngt cng ni tip Ti v RI. Ngun ngt phi c xc nh trong ISR v c to ngt s c xa bng phn mm. Cc ngt timer c ngt c ngt c xa bng phn cng khi CPU hng ti ISR. c. Cc ngt ngoi. - Cc ngt ngoi xy ra khi c mt mc thp hoc cnh xung trn chn INT0 hoc INT1 ca vi iu khin. y l chc nng chuyn i ca cc bit Port 3.(Port 3.2 v Port 3.3). Cc c to ngt ny l cc bit IE0 v IE1 trong TCON. Khi quyn iu khin chuyn n ISR, c to ra ngt ch c xa nu ngt c tch cc bng cnh xung. Nu ngt c tch cc theo mc, th ngun yu cu ngt bn ngoi s iu khin mc ca c thay cho phn cng. S la chn ngt tch cc mc thp hay tch cc cnh xung c lp trnh qua cc bit IT0 v IT1 trong TCON. Nu IT1 = 0, ngt ngoi 1 c tc ng bng mc thp chn IT1. Nu IT1 = 1 ngt ngoi 1 s c tc ng bng cnh xung. trong ch ny, nu cc mu lin tip trn chn INT1 ch mc cao trong mt chu k v ch mc thp trong chu k k, c yu cu ngt IE1 trong TCON c t ln 1, ri bit I yu cu ngt. Nu ngt ngoi c tc ng bng cnh xung th ngun bn ngoi phi gi chn tc ng mc cao ti thiu mt chu k v gi n mc thp thm mt chu k na m bo pht hin c cnh xung. Nu ngt ngoi c tc ng theo mc

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th ngun bn ngoi phi gi tn hiu yu cu tc ng cho n khi ngt c yu cu c tht s to ra v khng tc ng yu cu ngt trc khi ISR c hon tt . Nu khng mt ngt khc s c lp li.
VI. CC CH NH A CH: TRONG TP LNH C 8 CH NH A CH:

a. Thanh ghi a ghi: 8051/8031 c 4 bank thanh ghi, mi bank c 8 thanh ghi 1nh s t R0 n R7. Ti mi thi im ch c mt bank thanh ghi c tch cc. Mun chn bank thanh ghi no ta ch cn gn cc bit nh phn thch hp vo RSI (PSW.4) v RS0(PSW.3) trong thanh ghi trng thi chng trnh (PSW).
Ma len h n n n

a ch thanh ghi. Ngoi ra, mt s thanh ghi c bit nh thanh ghi tch ly, con tr d liu.. cng c xc nh trong cc lnh nn khng cn cc bit a ch. Trong cc lnh ny thanh ghi tch ly c xc nh l A, con tr d liu l DPTR, thanh ghi m chng trnh l PC, c nh l C, cp thanh ghi tch ly B l AB. b.

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c. a ch trc tip.
Trong ch ny, cc thanh ghi bn trong 8051/8031 c nh a ch trc tip bng 8 bit a ch nm trong byte th hai ca m lnh.

Ma lenh

a ch trc tiep

a ch trc tip. D vy, trnh hp dch cho php gi tn cc thanh ghi chc nng c bit (c a ch trc tip t 80H n FFH) v d :P0 cho port 0, TMOD cho thanh ghi ch timer... d. a ch gin tip. R0 v R1 c dng cha a ch nh m lnh tc ng n. ngi ta quy c dng du @ trc R0 hoc R1.
Ma lenh i a ch gin tip.

e. a ch tc thi: Ngi ta dng # trc cc ton hng tc thi. Cc ton hng c th l mt hng s, mt k s hay mt biu thc ton hc... Trng hp dch s t ng tnh ton v thay th d liu trc tip vo m lnh.
Ma lenh D lieu tc thi

a ch tc thi. f. a ch tng i: a ch tng i c dng trong cc lnh nhy 8051/8031 dng gi tr 8 bit c du cng thm vo thanh ghi m chng trnh (PC). Tm nhy ca lnh ny trong khong t 128 n 127 nh. Trc khi cng , thanh ghi PC s tng n a ch theo sau lnh nhy ri tnh ton a ch offset cn thit nhy n a ch yu cu. Nh vy a ch mi l a ch tng i so vi lnh k tip ch khng phi l bn thn lnh nhy. Thng lnh ny c lin quan n nhn c nh ngha trc.
Ma lenh
a ch tng i.

Offset tng oi

g. a ch tuyt i: a ch tuyt i ch dng trong cc lnh ACALL v JIMP. Cc lnh 2 byte ny dng r nhnh vo mt trang 2 Kbyte ca b nh trng trnh bng cch cp 11 bit a ch thp (A0-A10) xc nh a ch ch trong trang m. Cn 5 bit cao ca a ch ch (A11-A15) chnh l 5 bit cao hin hnh trong thanh ghi m chng trnh. V vy a ch ca lnh theo sau lnh r nhnh v a ch ch ca lnh r nhnh v a ch ch ca lnh r nhnh cn phi cng trang m 2 Kbyte (c cng 5 bit a ch cao). A15 A11 A10 A0

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xc nh trang m
A10-A8 Ma

xc nh a cch trong trang m

Offset tng oi

a ch tuyt i. h. a ch di: a ch di ch dng cho lnh LCALL v LJIMP. Cc lnh ny chim 3 byte v dng 2 byte sau (byte 2 v byte 3) nh a ch ch ca lnh (16 bit). u im ca lnh ny c th s dng trong ton b vng nh 64 Kbyte. Tuy nhin, lnh ny chim nhiu byte v l thuc vo v tr vng nh.
Ma len h A15-A8 A7-A0

a ch di. i. a ch tham chiu:

a ch tham chiu dng mt thanh ghi c bn (hoc thanh ghi m chng trnh PC hoc thanh ghi con tr d liu DPTR) v a ch offset (trong thanh ghi tch ly A) to a ch c tc ng cho cc lnh JMP hoc MOVC. Cc bng nhy v bng tm kim d dng c to ra s dng a ch tham chiu.

a ch c ban PC hoac DPTR +

Offset ACC =

a ch c tac ong

a ch tham chiu.

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VII. CC NHM LNH CA 8951

Tp lnh ca 8951 c chia thnh 5 nhm: - S hc. - Lun l. - Chuyn d liu. - Chuyn iu khin. Cc chi tit thit lp lnh: Rn :Thanh ghi R0 n R7 ca bank thanh ghi c chn. Data : 8 bit a ch vng d liu bn trong. N c th l vng RAM d liu trong (0-127) hoc cc thanh ghi chc nng c bit. @Ri : 8 bit vng RAM d liu trong (0-125) c nh gi a ch gin tip qua thanh ghi R0 hoc R1. #data : Hng 8 bit chc trong cu lnh. #data 16 : Hng 16 bit cha trong cu lnh. Addr16 : 16 bit a ch ch c dng trong lnh LCALL v LJMP. Addr11 : 11 bit a ch ch c dng trong lnh LCALL v AJMP. Rel Bit : Byte offset 8 bit c du c dng trong lnh SJMP v nhng lnh nhy c iu kin. : Bit c nh a ch trc tip trong RAM d liu ni hoc cc thanh ghi chc nng c bit.

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TRNG I HC TR VINH a. Nhm lnh x l s hc: ADD A,Rn (1byte, 1 chu k my) : cng ni dung thanh ghi Rn vo thanh ghi A. ADD A,data (2,1): Cng trc tip 1 byte vo thanh ghi A. ADD A,@Ri (1,1): Cng gin tip ni dung RAM cha ti a ch c khai bo trong Ri vo thanh ghi A. ADD A,#data (2,1):Cng d liu tc thi vo A. ADD A,Rn (1,1): Cng thanh ghi v c nh vo A. ADD A,data (2,1): Cng trc tip byte d liu v c nh vo A. ADDC A,@Ri (1,1): Cng gin tip ni dung RAM v c nh vo A. ADDC A,#data (2,1): Cng d liu tc thi v c nh vo A. SUBB A,Rn (1,1): Tr ni dung thanh ghi A cho ni dung thanh ghi Rn v c nh. SUBB A,data (2,1): Tr trc tip A cho mt s v c nh. SUBB A,@Ri (1,1): Tr gin tip A cho mt s v c nh. SUBB A,#data (2,1): Tr ni dung A cho mt s tc thi v c nh. INC A (1,1): Tng ni dung thanh ghi A ln 1. INC Rn (1,1): Tng ni dung thanh ghi Rn ln 1. INC data (2,1): Tng d liu trc tip ln 1. INC @Ri (1,1): Tng gin tip ni dung vng RAM ln 1. DEC A (1,1): Gim ni dung thanh ghi A xung 1. DEC Rn (1,1): Gim ni dung thanh ghi Rn xung 1. DEC data (2,1): Gim d liu trc tip xung 1 DEC @Ri (1,1): Gim gin tip ni dung vng RAM xung 1. INC DPTR (1,2): Tng ni dng con tr d liu ln 1. MUL AB (1,4): Nhn ni dung thanh ghi A vi ni dung thanh ghi B. DIV AB (1,4): Chia ni dung thanh ghi A cho ni dung thanh ghi B. DA A (1,1,): hiu chnh thp phn thanh ghi A. b. Nhm lnh lun l: ANL A,Rn (1,1): AND ni dung thanh ghi A vi ni dung thanh ghi Rn. ANL A,data (2,1): AND ni dung thanh ghi A vi d liu trc tip. ANL A,@Ri (1,1): AND ni dung thanh ghi A vi d liu gin tip trong RAM. ANL A,#data (2,1): AND ni dung thanh ghi vi d liu tc thi. ANL data,A (2,1): AND mt d liu trc tip vi A. ANL data,#data (3,2): AND mt d liu trc tip vi A mt d liu tc thi. ANL C,bit (2,2): AND c nh vi 1 bit trc tip. ANL C,/bit (2,2): AND c nh vi b 1 bit trc tip. ORL A,Rn (1,1): OR thanh ghi A vi thanh ghi Rn. ORL A,data (2,1): OR thanh ghi A vi mt d liu trc tip. ORL A,@Ri (1,1): OR thanh ghi A vi mt d liu gin tip. ORL A,#data (2,1): OR thanh ghi A vi mt d liu tc thi. ORL data,A (2,1): OR mt d liu trc tip vi thanh ghi A. ORL data,#data (3,1) :OR mt d liu trc tip vi mt d liu tc thi. ORL C,bit (2,2): OR c nh vi mt bit trc tip. ORL C,/bit (2,2): OR c nh vi b ca mt bit trc tip. XRL A,Rn (1,1): XOR thanh ghi A vi thanh ghi Rn. XRL A,data (2,1): XOR thanh ghi A vi m d liu trc tip. XRL A,@Ri (1,1): XOR thanh ghi A vi mt d liu gin tip. XRL A,#data (2,1): XOR thanh ghi A vi m d liu tc thi. XRL data,A (2,1): XOR mt d liu trc tip vi thanh ghi A. XRL dara,#data (3,1): XOR mt d liu trc tip vi mt d liu tc thi. SETB C (1,1): t c nh. SETB bit (2,1): t mt bit trc tip.

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TRNG I HC TR VINH CLR A (1,1): Xa thanh ghi A. CLR C (1,1): Xa c nh. CPL A (1,1): B ni dung thanh ghi A. CPL C (1,1): B c nh. CPL bit (2,1): B mt bit trc tip. RL A (1,1): Quay tri ni dung thanh ghi A. RLC A (1,1): Quay tri ni dung thanh ghi A qua c nh. RR A (1,1): Quay phi ni dung thanh ghi A. RRC A (1,1): Quay phi ni dung thanh ghi A qua c nh. SWAP (1,1): Quay tri ni dung thanh ghi A 1 nibble (1/2byte). c. Nhm lnh chuyn d liu: MOV A,Rn (1,1):Chuyn ni dung thanh ghi Rn vo thanh ghi A. MOV A,data (2,1): Chuyn d liu trc tip vo thanh ghi A. MOV A,@Ri (1,1): Chuyn d liu gin tip vo thanh ghi A. MOV A,#data (2,1): Chuyn d liu tc thi vo thanh ghi A. MOV Rn,data (2,2): Chuyn d liu trc tip vo thanh ghi Rn. MOV Rn,#data (2,1): Chuyn d liu tc thi vo thanh ghi Rn. MOV data,A (2,1): Chuyn ni dung thanh ghi A vo mt d liu trc tip. MOV data,Rn (2,2): Chuyn ni dung thanh ghi Rn vo mt d liu trc tip. MOV data,data (3,2): Chuyn mt d liu trc tip vo mt d liu trc tip. MOV data,@Ri (2,2): Chuyn mt d liu gin tip vo mt d liu gin tip. MOV data,#data (3,2): Chuyn mt d liu tc thi vo mt d liu trc tip. MOV @Ri,A (1,1): Chuyn ni dung thanh ghi A vo mt d liu gin tip. MOV @Ri,data (2,2): Chuyn mt d liu trc tip vo mt d liu gin tip. MOV @Ri,#data (2,1): Chuyn d liu tc thi vo d liu gin tip. MOV DPTR,#data (3,2): Chuyn mt hng 16 bit vo thanh ghi con tr d liu. MOV C,bit (2,1): Chuyn mt bit trc tip vo c nh. MOV bit,C (2,2): Chuyn c nh vo mt bit trc tip. MOV A,@A+DPTR (1,2): Chuyn byte b nh chng trnh c a ch l @A+DPRT vo thanh ghi A. MOVC A,@A+PC (1,2): Chuyn byte b nh chng trnh c a ch l @A+PC vo thanh ghi A. MOVX A,@Ri (1,2): Chuyn d liu ngoi (8 bit a ch) vo thanh ghi A. MOVX A,@DPTR (1,2): Chuyn d liu ngoi (16 bit a ch) vo thanh ghi A. MOVX @Ri,A (1,2): Chuyn ni dung A ra d liu ngoi (8 bit a ch). MOVX @DPTR,A (1,2): Chuyn ni dung A ra d liu bn ngoi (16 bit a ch). PUSH data (2,2): Chuyn d liu trc tip vo ngn xp v tng SP. POP data (2,2): Chuyn d liu trc tip vo ngn xp v gim SP. XCH A,Rn (1,1): Trao i d liu gia thanh ghi Rn v2 thanh ghi A. XCH A,data (2,1): Trao i gia thanh ghi A v mt d liu trc tip. XCH A,@Ri (1,1): Trao i gia thanh ghi A v mt d liu gin tip. XCHD A,@R (1,1): Trao i gia nibble thp (LSN) ca thanh ghi A v LSN ca d liu gin tip. d. Nhm lnh chuyn iu khin: ACALL addr11 (2,2): Gi chng trnh con dng a ch tuyt i. LCALL addr16 (3,2): Gi chng trnh con dng a ch di. RET (1,2): Tr v t lnh gi chng trnh con. RET1 (1,2): Tr v t lnh gi ngt. AJMP addr11 (2,2): Nhy tuyt i. LJMP addr16 (3,2): Nhy di. SJMP rel (2,2):Nhy ngn. JMP @A+DPTR (1,2): Nhy gin tip t con tr d liu.

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TRNG I HC TR VINH JZ rel (2,2): Nhy nu A=0. JNZ rel (2,2): Nhy nu A khng bng 0. JC rel (2,2): Nhy nu c nh c t. JNC rel (2,2): Nhy nu c nh khng c t. JB bit,rel (3,2): Nhy tng i nu bit trc tip c t. JNB bit,rel (3,2):Nhy tng i nu bit trc tip khng c t. JBC bit,rel (3,2): Nhy tng i nu bit trc tip c t , ri xa bit. CJNE A,data,rel (3,2): So snh d liu trc tip vi A v nhy nu khng bng. CJNE A,#data,rel (3,2): So snh d liu tc thi vi A v nhy nu khng bng. CJNE Rn,#data,rel (3,2): So snh d liu tc thi vi ni dung thanh ghi Rn v nhy nu khng bng. CJNE @Ri,#data,rel (3,2): So snh d liu tc thi vi d liu gin tip v nhy nu khng bng. DJNZ Rn,rel (2,2): Gin thanh ghi Rn v nhy nu khng bng. DJNZ data,rel (3,2): Gim d liu trc tip v nhy nu khng bng. e. Cc lnh r nhnh: C nhiu lnh iu khin ln chng trnh bao gm vic gi hoc tr li t chng trnh con hoc chia nhnh c iu kin hay khng c iu kin. Tt c cc lnh r nhnh u khng nh hng n c. Ta c th nh nhn cn nhy ti m khng cn r a ch, trnh bin dch s t a ch ni cn nhy ti vo ng khu lnh a ra.

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M t tp lnh :

Tm Tt Cc Lnh NHY (JMP)

1. Cu trc repeat until Repeat <action> Until <condition> Ngn ng Assembly LOOP: <action> JUMP_if_not_<condition>,LOOP VD: Cu trc repeat until Repeat ... Until A = 0 Ngn ng Assembly LOOP: ... JNZ LOOP

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TRNG I HC TR VINH 2. Cu trc while do while <condition> do <action> Ngn ng Assembly LOOP: JUMP_if_not_<condition>,DO SJMP STOP DO: <action> SJMP LOOP STOP: ... VD: Cu trc while do R7 = 0 while R7 10 do { ... R7 = R7 + 1 } Ngn ng Assembly MOV R7,#0 LOOP: CJNE R7,#10,DO SJMP STOP DO: ... INC R7 SJMP LOOP STOP: ... 3. Cu trc if then else if <condition> then <action 1> else <action 2> Ngn ng Assembly JUMP_if_not_<condition>,ELSE <action 1> SJMP DONE ELSE: <action 2> DONE: ... VD: Cu trc if then else if P0.1 = 0 then R7 = R7 + 1 else R7 = 0 Ngn ng Assembly JB P0.1,ELSE INC R7 SJMP DONE ELSE: MOV R7,#0 DONE: ...

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TRNG I HC TR VINH 4. Cu trc case of case P1 of #11111110b: P2.0 = 1 #11111101b: P2.1 = 1 #11111011b: P2.2 = 1 else P2 = 0 end Ngn ng Assembly SKIP1 SKIP1: CJNE SETB SJMP CJNE SETB SJMP CJNE SETB SJMP MOV ... P1,#11111110b, P2.0 EXIT P1,#11111101b,SKIP2 P2.1 EXIT P1,#11111011b,SKIP3 P2.2 EXIT P2,#0

SKIP2:

SKIP3: EXIT:

Sau y l s tm tt tng hot ng ca lnh nhy. JC rel : Nhy n rel nu c Carry C = 1. JNC rel : Nhy n rel nu c Carry C = 0. JB bit, rel : Nhy n rel nu (bit) = 1. JNB bit, rel : Nhy n rel nu (bit) = 0. JBC bit, rel : Nhy n rel nu bit = 1 v xa bit. ACALL addr11: Lnh gi tuyt i trong page 2K. (PC) (PC) + 2 (SP) (SP) + 1 ((SP)) (PC7PC0) (SP) (SP) + 1 ((SP)) (PC15PC8) (PC10PC0) page Address. LCALL addr16: Lnh gi di chng trnh con trong 64K. (PC) (PC) + 3 (SP) (SP) + 1 ((SP)) (PC7PC0) (SP) (SP) + 1 ((SP)) (PC15PC8) (PC) Addr15Addr0. RET : Kt thc chng trnh con tr v chng trnh chnh. (PC15PC8) (SP) (SP) (SP) - 1 (PC7PC0) ((SP)) (SP) (SP) -1. RETI : Kt thc th tc phc v ngt quay v chng trnh chnh hot ng tng t nh RET. AJMP Addr11 : Nhy tuyt i khng iu kin trong 2K. (PC) (PC) + 2 (PC10PC0) page Address.

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TRNG I HC TR VINH : Nhy di khng iu kin trong 64K Hot ng tng t lnh LCALL. SJMP rel :Nhy ngn khng iu kin trong (-128127) byte (PC) (PC) + 2 (PC) (PC) + byte 2 JMP @ A + DPTR:Nhy khng iu kin n a ch (A) + (DPTR) (PC) (A) + (DPTR) JZ rel : Nhy n A = 0. Thc hnh lnh k nu A = 0. (PC) (PC) + 2 (A) = 0 (PC) (PC) + byte 2 JNZ rel : Nhy n A 0. Thc hnh lnh k nu A = 0. (PC) (PC) + 2 (A) < > 0 (PC) (PC) + byte 2 CJNE A, direct, rel : So snh v nhy n A direct (PC) (PC) + 3 (A) < > (direct) (PC) (PC) + Relative Address. (A) < (direct) C = 1 (A) > (direct) C = 0 (A) = (direct). Thc hnh lnh k tip CJNE A, # data, rel : Tng t lnh CJNE A, direct, rel. CJNE Rn, # data, rel : Tng t lnh CJNE A, direct, rel. CJNE @ Ri, # data, rel : Tng t lnh CJNE A, direct, rel. DJNE Rn, rel : Gim Rn v nhy nu Rn 0. (PC) (PC) + 2 (Rn) (Rn) -1 (Rn) < > 0 (PC) (PC) + byte 2. DJNZ direct, rel : Tng t lnh DJNZ Rn, rel. Cc lnh dch chuyn d liu: Cc lnh dch chuyn d liu trong nhng vng nh ni thc thi 1 hoc 2 chu k my. Mu lnh MOV <destination>, <source> cho php di chuyn d liu bt k 2 vng nh no ca RAM ni hoc cc vng nh ca cc thanh ghi chc nng c bit m khng thng qua thanh ghi A. Vng Ngn xp ca 8951 ch cha 128 byte RAM ni, nu con tr Ngn xp SP c tng qu a ch 7FH th cc byte c PUSH vo s mt i v cc byte POP ra th khng bit r. Cc lnh dch chuyn b nh ni v b nh ngoi dng s nh v gin tip. a ch gin tip c th dng a ch 1 byte (@ Ri) hoc a ch 2 byte (@ DPTR). Tt c cc lnh dch chuyn hot ng trn ton b nh ngoi thc thi trong 2 chu k my v dng thanh ghi A lm ton hng DESTINATION. Vic c v ghi RAM ngoi (RD v WR) ch tch cc trong sut qu trnh thc thi ca lnh MOVX, cn bnh thng RD v WR khng tch cc (mc 1). Tt c cc lnh dch chuyn u khng nh hng n c. Hot ng ca tng lnh c tm tt nh sau: LJMP Addr16 PUSH direct : Ct d liu vo Ngn xp (SP) (SP) + 1 (SP) (Drirect) POP direct : Ly t Ngn xp ra direct (direct) ((SP)) (SP) (SP) - 1 XCH A, Rn : i ch ni dung ca A vi Rn

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TRNG I HC TR VINH (A) (Rn) XCH A, direct : (A) (direct) XCH A, @ Ri : (A) ((Ri)) XCHD A, @ Ri : i ch 4 bit thp ca (A) vi ((Ri)) (A3A0) ((Ri3Ri0)) Cc lnh xen vo (Miscellamous Intstruction): NOP : Khng hot ng g c, ch tn 1 byte v 1 chu k my. Ta dng delay nhng khong thi gian nh.

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Chng 2 : KHO ST VI MCH GIAO TIP NGOI VI 8255.

I CU TRC PHN CNG 8255A: 8255A l IC ngoi vi c ch to theo cng ngh LSI dng giao tip song song gia Microprocrssor v thit b iu khin bn ngoi. S chn
PIN OUTS 8255A (PDIP) TOP VIEW
1 2 3 4 5 6 7 8 9 10 11 12 13 40 39 38 37 36 35 34 33 32

S Logic
PA4 PA5 PA6 PA7 WR\ RESET DO D1 D2 D3

PA3 PA2 PA1 PA0 RD\ CS\ GND A1 A0 PC7 PC6 PC5 PC4

D0-D7

PA7-PA0

PC7-PC4 RD\ WR\ RESET A0 A1 CS\ PB7-PB0 PC3-PC0

8255A

31 30

D4 29 D5
28 27 26 25 24 23 22

D6 D7 VCC PB7 PC6 PC5 PC4

PC0 14 PC1 PC2 PC3 PB0 PB1 PB2

15 16 17 18 19 20

Hnh 3.1: S chn v s logic 8255A.

21 PC3

Tn cc chn 8255A: D7-D0 Data bus (Bi-Direction). RESET Reset input. CS\ Chip select RD\ Read input WR\ Write input A0A1 Prot Address PA7-PA0 Port A PB7-PB0 Port B PC7-PC0 Port C 8255A giao tip vi Microprocrssor thng qua 3 bus : bus d liu bit D7-D0 bus a ch A1A0, bus iu khin RD\,WR\.SC\.Reset. M lnh, thng tin trng thi v d liu u truyn trn 8 ng d liu D7D0. Microprocrssor gi d liu n 8255A hoc Microprocrssor c d liu t 8255A

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ty thuc vo lnh diu khin. Cc ng tn hiu RD\,WR\ ca 8255A c kt ni vi cc ng RD\, WR\ ca Microprocrssor. Tn hiu Reset dng khi ng 8255A khi cp in, khi b Reset cc thanh ghi bn trong ca 8255A u b xa v 8255A trng thi sn sng lm vic. Khi giao tip vi Microprocrssor, ng vo tn hiu Reset ny c kt ni tn hiu Reset Out ca Microprocrssor. Tn hiu Chip select CS\ dng la chn 8255A khi Microprocrssor, giao tip vi nhiu 8255A. 8255A c 3 Port xut nhp (I/O) c tn l Port A,Port B, Port C, mi Port 8255A bit. Port A gm PA0-PA7, Port B gm PB0-PB7, Port C gm cc bit PC0-PC7. Cc Port ny c th l cc Port Input hay Output ty thuc vo lnh iu khin, lnh iu khin do Microprocrssor gi n cha trong thanh ghi lnh (cn gi l thanh ghi iu khin) iu khin 8255A . cc ng a ch A1A0 ca 8255A dng la chn cc Port v thanh ghi A1A0=002 dng chn Port A, A1A0=012 dng chn Port B, A1A0=102 dng chn Port C, A1A0=112 dng chn thanh ghi iu khin. Trong s khi ca 8255A , cc Port I/O ca 8255A chia ra lm 2 nhm : nhm A gm Port A v bit cao ca Port C,nhm B gm Port B v 4 bit thp ca Port C. s dng cc Port ca 8255A ngi lp trnh phi gi t iu khin ra thanh ghi iu khin 8255A nh cu hnh cho cc Port ng theo yu cu m ngi lp trnh mong mun.

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TRNG I HC TR VINH Cu trc t iu khin ca 8255A. D7 D6 D5 D4 D3 D2 D1 D0 GROUP B

PORT C(LOWER) 1=INPUT 0=OUTPUT PORT B 1=INPUT 0=OUTPUT MODE SELECTION 1=MODE 1 0=MODE 0

GROUP A PORT C(UPPER) 1=INPUT 0=OUTPUT PORT A 1=INPUT 0=OUTPUT

MODE SELECTION 00=MODE 0 01=MODE 1 1X=MODE 2 MODE SET FLAG 1=ACTIVE

II. CU TRC PHN MM CA 8255.

Do cc Port ra ca 8255A c chia ra lm 2 nhm A v nhm B tch ri nn t iu khin ca 8255A cng c chia lm 2 nhm.

Cc bit D2D1D0 dng nh cu hnh cho nhm B: Bit D0 dng thit lp 4 bit thp ca Port C, D0=0 Port C xut d liu (output), D0=1 Port thp l port nhp d liu (Input). Bit D1 dng thit lp Port B , D1=0- Port B l Port xut d liu (output), D1=1 Port B l Port nhp d liu (input). Bit D2 dng thit lp Mode iu khin ca nhm B: D2=0: nhm B hot ng modem 0. D2=1: nhm B hot ng modem 1. Cc bit D6D5D4D3 dng nh cu hnh cho nhm A: Bit D3 dng thit lp 4 bit cao ca Port C, D3=0-Port C l Port xut d liu (output),D3=1 Port C l Port nhp d liu (input).

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Bit D4 dng thit lp Port A, D4=0- Port A l Port xut d liu (output), D4=1-Port A l Port nhp d liu (input). Bit D6D5 dng thit lp Mode iu khin ca nhm B: D6D5=00:nhm A hot ng modem 0. D6D5=01: nhm A hot ng modem 1. D6D5=1x: nhm A hot ng modem 2. III. GIAO TIP GIA VI X L VI 8255A . - Vi mch 8255A c th giao tip vi vi x l theo hai kiu xut nhp (I/O) v kiu b nh. - Khi vi x l giao tip vi 8255A. Theo kiu I/O th n ch dng 8255A ng a ch t A0 n A7, cn khi giao tip theo kiu b nh th n dng 16 ng A0 n A15 giao tip, v vy dung lng giao tip theo kiu I/O thp hn dung lng giao tip theo kiu b nh. 1. Giao tip kiu I/O. Khi thit k vi x lgiao tip vi 8255A theo kiu I/O th vic giao tip thng qua hai lnh: In addr Port v Out addr Port. D liu giao tip lun cha trong thanh ghi A, a ch port(addr port) c di 8255A bit.
Cng ging nh b nh. Vi x l c th giao tip vi nhiu vi mch 8255A. Vi 8255A bit a ch, nu xem mi mt a ch truy xut mt nh th vi x l c kh nng truy xut 255 nh(vi 256 a ch). Mi vi mch 8255A chim 4 a ch 93 port v 1 thanh ghi iu khin, nn s lng vi mch 8255A c th giao tip vi vi x l l 64.

khi kt ni gia vi x l v vi mch 8255A th ng a ch A0 v A1 dng la chn cc cng v thanh ghi iu khin, cn cc ng A2-A7 dng la chn vi mch hot ng, thng thng cc ng a ch ny c a vo vi mch gii m ri cc ng ra ca vi mch gii m s a chn CS\ ca cc vi mch 8255A. V d: thit k 2 vi mch 8255 A giao tip vi vi x l theo kiu I/O. Ta c bng a ch cc vi mch 8255A. IC 8255I A7 0 0 0 0 A6 0 0 0 0 A5 A4 0 0 0 0 0 0 0 0 A3 0 0 0 0 A2 0 0 1 1 A1 0 1 0 1 A0 0 1 0 1 HEX 00 03 04 07

8255II

8255I chim 1 vng a ch t 00H n 03H a ch ca port A=00H, port B=01H ,port C=02H v a ch ca thanh ghi iu khin =03H. 8255-I chim mt vng a ch t 04H n 07H, a ch ca: port A=04H, port B=05H, port C=06H v a ch ca thanh ghi iu khin=07H. 2. Giao tip kiu b nh. Khi thit k giao tip 8255 vi vi x l theo kiu b nh; v chc nng ca 8255 khng c g thay i ch thay i v a ch truy xut. Kiu I/O, a ch ca port hay thanh ghi c di 8255A bit, kiu b nh, a ch ca port hay thanh ghi s c di 16 bit ging nh b nh nn gi l kiu b nh. Khi thit k IO theo kiu b nh th mi port hay thanh ghi iu khin ca 8255, c xem l tng nh. Khi vi x l giao tip vi 8255 ging nh b nh v 2 lnh IN v OUT khng cn tc dng.

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Kiu b nh ch s dng trong cc h thng nh n gin.

A B C E0 E1 E2 O0 O1 O2 O3 O4 O5 O6 O7

DATA

+5V

a e n ngo va o CS\ cu a ca c 8255A

MicroProcessor

A1-A0 CS\ 8255A 1 WR\ RD\ CS\ 8255A 2 WR\ RD\ CS\ 8255A 8 WR\ RD\

D7-D0 CONTROL BUS

Hnh 3.2: Giao tip IC8255A vi Microprocessor. 3. ng dng ca 8255:

IC giao tip IO 825 c rt nhiu ng dng trong cc h thng iu khin dng MicroProcessor, 8255 ng vai tr l IC giao tip gia MicroProcessor v i tng iu khin. Cc ng dng ca 8255 l truyn d liu, gii m hin th, gii m bn phm, giao tip iu khin ty theo yu cu.

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Chng 3 :

KHO ST B NH BN DN

Vi iu khin (Microcontroller) l IC chuyn v x l d liu iu khin theo mt chng trnh, mun vi iu khin thc hin mt cng vic g th ngi s dng phi lp trnh. Chng trnh phi c lu tr mt b phn no , vi iu khin nhn lnh v thi hnh, i khi trong lc x l,chng trnh ca vi iu khin cn ni lu tr tm thi d liu chnh ca b nh. Cc b nh ca vi iu khin l cc IC, cc IC nh ny c th c d liu ra, ghi d liu vo hoc ch c d liu ra. i khi b nh ca vi u khin khng lu tr nhng thng tin cn thit khi chy chng trnh, khi o phi dng k thut m rng b nh. B NH CH C(ROM:Read Only Memory) Loi b nh ny c thit k lu tr cc d liu c nh. Trong lc hot ng bnh thng d liu mi khng th no ghi c vo ROM, m d liu ch n ra t ROM. ROM dng lu tr cc chng trnh ca my tnh do khng b mt d liu khi mt in S ROM c dung lng 32 x4bit
Ao A1 A2 A3 D0 D1 ROM CS\ RD\ WR\ D7

Add Bus

Data

ROM c 3 bus:bus d liu,bus a ch,bus iu khin.Vi b nh ROM trn bus a Control ch c 4 ng nn c dung lng b nh l 24=16.Bus d liu c 8 ng,t d liu l 8bit hay 1byte,vy b nh ROM ny c dung lng l 16byte.Bus iu khin cho php ROM hot ng c hay vit, c d liu ca nh no phi cung cp a ch ca nh ti cc ng vo a ch tc ng n ng vo cho php CS\.

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1. Cu trc bn trong ca ROM

Row0 A0 A1

1of 4 deco

R1
Row3

R4

R8

R1

R1
D7

R5

R9

R13

D0 CS

Out put buff er

R2

R6

R1

R1

R3

R7

R1

R1

A2 A3

Cu trc ca ROM rt phc tp,t s trn th cu trc ca ROM gm c 4 phn chnh + Gii m hng + Gii m ct + Ma trn thanh ghi +m ng ra - Ma trn thanh ghi: Lu tr d liu c lp trnh t ROM,mi thanh ghi cha mt t d liu,nh trong trng hp trn mi thanh ghi lu tr bn t d liu bit. Ng ra ca t d liu 8 bit c kt ni vi bit d liu bn trong. Mi thanh ghi c hai ng vo cho php.Thanh ghi no c hai ng vo cho php mc cao th d liu s gi l bus d liu. - Gii m a ch: m a ch A3A2A1A0 dng xc nh thanh ghi no trong ma trn c php t t d liu 8bit ln bus d liu .Hai bit a ch A0A1 c a n b gii m hai ng sang bn ng la chn mt trong bn dng,hai bit a ch A2A3 c a n b gii m th hai chn mt trong bn ct. Ch duy nht mt thanh ghi trong mt hng v mt ct c chn bi mt a ch ng vo,v thanh ghi ny c php gi d liu ln bus. - m ng ra: d liu do thanh ghi gi ra s c a vo b m,b m s gi d liu ra cc ng d liu bn ngoi,khi tn hiu iu khin CS mc cao. Nu CS mc thp th b m ng ra trng thi tng tr cao v cc ng d liu D0 D7 s c th ni 2. Thi hng truy xut b nh ROM C mt khong thi gian t lc p t a ch ti cc ng vo a ch ca ROM n lc d liu xut hin ng ra(trong lc ROM hot ng) thi gian ny gi l thi gian tr hay thi gian truy xut.Khong thi gian t lc ng vo cho php CS\ n lc d liu xut hin gi l thi gian cho php xut d liu. Gin thi hng truy xut ca Rom

Column 0 Hnh 1of 4 4.1 S cu trc n gin ca ROM16 x8 decod -er Column 3

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Add input Old address

tacc
CS

toe High-Z

0 1

t0

t1

t2

t3

3. Cc loi b nh ROM Maskable Programmed ROM(ROMmt n): y l loi ROM do nh sn xut np sn chng trnh,khi np chng trnh th cc bit tring ROM ny khng c thay i na. Programmable ROM(PROM): loi ROM ny ngi s dng c th np chng trnh v ch np mt ln khng th xa c. ErasableProrammable ROM(EPROM): loi ROM ny c th lp trnh bi ngi s dng v c th xa np nhiu ln . xa d liu trong EPROM phi dng nh sng cc tm xa, lp trnh cho ROM phi dng mch np EPROM. EPROM c hai im bt li: phi ly EPROM ra khi soket xa v lp trnh li khi mun thay i chng trnh .Khi mun thay i d liu nh th phi xa d liu ca nh ,nhnng khi dng nh sng cc tm th tt c d liu trong EPROM b xa sch v phi np li ton b d liu. 4. Kho st b nh EPROM 2764 Trong cc mch iu khin dng vi x l PROM c s dng rt ph bin v n cho php ngi s dng c th np v xa cc chng trnh d dng theo yu cu ca mi ngi. EPROM 2764 c dung lng 8kbyte c s chn v s logic nh sau:

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Vpp A12 A7 A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 GND

2764

Vcc PGM NC A8 A9 A11 OE\ A10 CE\ D7= D6 D5 D4 D3

A0

D0 D1 D2 D3 D4 D5 D6 D7

2764
A12
CE\

OE\ PGM\ VPP

Hnh 4.2 S chn v s logic EPROM 2764 EPROM 2764 c 13 ng a ch v 8 ng d liu nn dung lng ca 2764 l 213=8192byte d lu hay 8kbyte ,c 2 ngun cung cpVcc v Vpp ng vo Vcc lun ni ti ngun 5v ng vo Vpp c ni ti ngun+5v khi EPROM ang lm vic ch c d liu v ni ti ngun 26v khi lp trnh cho EPROM Hai ng vo iu khin: OE\ c dng iu khin b m cho php d liu ca EPROM xut ra ngoi hay khng . CE\ l ng vo cho php c hai chc nng :khi hot ng bnh thngCE\ l it1n hiu cho php dc d liu t EPROM,CE\ phi mc thp mch in bn trongla chn d liu v chuyn n n output buffer kt hp vi tn hiu cho OE\ mc thp,th d liu mi xut cc ng raD0-D7.Khi CE\ mc cao th EPROM trng thi ch(Standby).cng sut tiu tn lc ny 132mw. Bng trng thi lm vic ca EPROM

MODE READ STANDBY PROGAM PROGRAM VERYFY PROGRAM INHIBIT

CE\ Vil Vih Vil Vil Vih

OE\ Vil X X Vil

PGM\ Vih X Vil Vih X

Vpp Vcc Vcc Vpp Vpp Vpp

Vcc Vcc Vcc Vcc Vcc Vcc

Output Dout HighZ Din Dout HighZ

II.B NH RAM -Ram l b nh truy xut ngu nhin, c ngha l bt k nh no cng d dng truy xut nh nhng nh khc. -Khuyt im ca Ram l d liu lu tr trong Ram s mt khi mt in. -u im chnh ca Ram l c th c v ghi nhanh chng 1.Cu Trc Ca Ram Tng t nh b nh Rom,b nh Ram cng gm c mt s thanh ghi .mi thanh ghi lu tr 1 t d liu duy nht v mt d liu duy nht.Dung lng ca b nh

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Ram l 1K,2K ,8K, 16K ,32K, 64K, 128K, 256K, 512K, v 1024K.v t 72 d liu l 8 hoc 4 bit.
Data
INPUT BUFFER

RW

Register 0
A5 A4 A3 A2 A1 A0

Register 1 Register 2 Deco der 6 line

CS\

Address

Register Register 63 Output

Oo O1 O2 O3

Selects One

Hnh 4.3 S cu Data bn trong Ram 64x4 trc a.Hot ng c d liu t Ram M a ch ca nh cn c d liu c a n ng vo a ch cu Ram ng thi ng tn hiu iu khin R/W phi mc logic 1 v ng vo cho php(CS) phi mc logic1.khi d liu mi xut hin ng ra d liu. Khi R/W=1 s khng cho php b m ng vo, do d liu ng vo khng nh hng g n nh ang truy xut. b. Hot ng ghi d liu ln Ram ghi d liu vo thanh ghi c la chn bi cc ng vo a ch ca b nh Ram,i hi ng voR/W=0 v CS=1.T hp hai mc logic ny s cho php b m ng vo a t d liu (4bit) cc ng vo s c np thanh ghi c chn KhiR/W mc thp s khng cho php b m ng ra v ng ra trng thi tng tr cao(trong lc ghi d liu).Khi ghi d liu vo nh th d liu trc s mt i . c. Chip selet (cs) Hu ht cc b nh u c hot nhiu ng vo CS ,c dng cho php hoac khng cho php b nh hot ng trong nhiu trng hp kt ni nhiu b nh.Khi khng cho tt c cc ng vo d liu v ng ra d liu trng thi tng tr cao. d. Nhng chn data input-output gim s chn cho mt Icnh ch to kt hp 2 chc nng data input v data output thnh mt chn Input/output, chng c chc nng ca cc chn I/O.Khi hot

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ng c,c chn I/O hot ng nh l cc chn xut d liu.Khi ghi d liu, cc chn I/o hot ng nh l cc chn d liu. 2 . Cc loi Ram Ram c chia lm 2 loi: -SRAM(Static RAM);l mt loi linh kin m vic lu tr d liu da vo nguyn tc hot ng ca flip flop D.D liu vo tn ti mt trong haitrng thi logic ca mch s.
DRAM(Dynamic Ram):l loi linh kin nh m d liu lu tr nh in tch tr trong t in.

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Chng 5 : CHUYN I TNG T S

I. KHI NIM CHUNG Ngy nay vic truyn t tn hiy cng nh qu trnh iu khin v ch th phn ln c thc hin theo phng php s. Trong khi tn hiu t nhin c dng tng t nh:nhit ,p sut ,cng nh sng,tc quay,tn hiu m thanh kt ni gia ngun tn hiu tng t vi cc h thng x l s ngi ta dng cc mch chuyn i tng t sang s(ADC) nhm bin i tn hiu tng t sang s hoc trong trng hp ngc li cn bin i tn hiu s sang tng t thi dng cc mch DAC (Digital Analog Converter). II. NGUYN TT THC HIN CHUYN I ADC Mch chuyn i tin hiu tng t sang s,chuyn mt tn hiu ng vo tng t (dng in hay in p) thnh dng m s nh phn c gi tr tng ng. Chuyn i ADC c rt nhiu phng php.Tuy nhin,mi phng php iu c nhng thng s c bn khc nhau: + chnh xc ca chuyn i AD. + Tc chuyn i . + Di bin i ca tn hiu tng t ng vo
Startcommand VA VA Comparator
D/A converter

Control Unit

clock

Register

Hnh 6.1 S khi tng qut ca mch ADC Digital output Hot ng -u tin kch xung start b ADC hot ng -Ti mt tn s c xc nh bng xung clock b iu khin lm thay i thnh s nh phn c lu tr trong thanh ghi(Register).-S nh phn trong thanh ghi c chuyn thnh dng in p Va bng b chuyn i DA. -B so snh,so snh Va vi in p ng vo Va .Nu Va < Va th ng ra ca b so snh vn gi mc cao. Khi Va > Va ng ra ca b so snh xung mc thp v qu trnh thay i s ca thanh ghi ngng. Lc ny Va gn bng Va , nhng s trong thanh ghi l nhng s cn chuyn i . III. CC PHNG PHP CHUYN I AD 1. Phng php tch phn (Intergration method) Phng php tch phn cng ging nh phng php chuyn i ADC dng tn hiu dc i (Dual-Slope-ADC). Cu trc mch in n gin hn nhng tc chuyn i chm.

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C Vin Vref in p chun R _ _ + + Mch tch phn Mch so snh

Clock

Mch logic iu khin

Start

B m

Hnh 6.2 : S nguyn l c bn ca mch chuyn i AD dng phng php tch phn * Hot ng -Khi c xung start mch m a v trng thi reset. Mch logic iu khin kha K v tri 1, in p tng t Vin c np vo t in C vi thi hng t1 tn hiu ng ra ca mch tch phn gim dn,v cho n khi nh hn 0V th ng ra ca b so snh ln mc 1,do mch logic iu khin m cng cho xung clock vo mch m. Sau khong thi gian t1 mch m trn mch logic iu khin kha K v tr 0,khi in p m Vref c a vo ng vo ca mch tch phn,t in C x in vi tc khng i, sau khong thi gian t2 tn hiu ng ra ca mch tch phn tng dn,do ng ra ca mch so snh xung ,mc thp lm cho mch logic iu khin ng cng v bo kt thc chuyn i. Trong sut khong thi gian x in t2 mch m vn tip tc m kt qu ca mch m cng chnh l tn hiu s cn chuyn i tng ng vi in p tng t ng vo Vin . Mi quan h gia in p ng vo Vin v in p chun Vref vi t1,t2
t2=t1.vin/vref Ng ra s

t1=2n/fck :thi gian mch m t 0 n khi trn t2=N/fck : thi gian mch m t khi trn n kt qu sau cng -Biu thc ny khng ph thuc vo thi hng RC,cng nh s xung clock(nu mch lm vic n nh). -Cc tn hiu tng t Vin qua mch tch phn nn cc tn hiu nhiu u b loi b.

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-Nhc im ca mch ny l thi gian chuyn i chm,gia 2n chu k xung clock trong ln ly tch phn trong thi gian t1 va N chu k trong ln ly tch phn trong thi gian t2. Thi gian chuyn i ln nht khi t1=t2. Thi gian chuyn i: T = t1+t2 2. Phng php ADC xp x lin tip(Successive- Approximation ADC) y l mt trong nhng phng php d9uo75c s dng rng ri. Tuy nhin,mch in c phc tp nhng thi gian chuyn i ngn hn. Phng php chuyn i ADC xp x lin tip c thi gian chuyn i c nh khng ph thuc vo in p ng vo.
VA VA + _ Clock Logic iu khin MSB LSB Thanh ghi iu khin Start EOC

DAC

Hnh 6.3 : S khi chuyn i ADC dng phng php xp x lin tip. * Hot ng Khi tc ng cnh xung ca xung start th ADC bt u chuyn i . -Mch logic iu khin t bit c ngha ln nht(Most Signifi cant Bit )ca thanh ghi iu khin ln mc cao v tt c cc bit cn li mc thp.S nh phn ra mch thanh ghi iu khin cqua mch DAC to ra in p tham chiu Va. Nu Va >Va th ng ra b so snh xung mc thp ,lm cho mch logic iu khin xa bit MSB xung mc thp. Nu Va<Va th ng ra ca b so snh vn mc cao v lm cho mch logic iu khin gi bit MSB mc cao. Tip theo mch logic iu khin a bit c ngha k bit MSB ln mc cao v to ng ra khi DAC mt in p tham chiu va ri em so snh tng t nh bit MSB trn .Qu trnh ny c tip tc cho n bit cui cng trong thanh ghi iu khin. Lc va gn bng Va ng ra ca mch logic iu khin bo kt thc chuyn i. Nh vy mch i ra n bit ch mt n chu k xung clock nn c th t tc rt cao. Tuy nhin mch ADC xp x lin tip li khng th p ng vi tn hiu tng t vo bin i cc nhanh . 3. Phng php song song (paralled method)

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Mch ADC dng nguyn tc chuyn i song song hay cn gi l phng php ADC nhanh, c cu trc mch in phc tp nhng tc chuyn i rt cao . Trong vi trng hp ngi ta cn mch chuyn i ADC c tc rt cao v nhng tn hiu bin i nhanh nn khi chuyn sang dng s ngi ta c mch ADC c tc cao .

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Vref
R/2

+ + +

13 ULSB 2 11 ULSB 9 ULSB 2 7 U 2 LSB 55 U 2 LSB 2 3 U 2 LSB 1 U 2 LSB

R/2

1D C1 1D C1 1D C1

X1

X2

X3

+
1D C1 X4

D2 D1 D0

+
1D C1 X5

+
1D C1 X6

+
1D C1 X7

Vin Hnh 6.4 S khi mch chuyn i AD dng phng php song song

* Hot ng Mch bao gm: khi so snh song song v mch m ho. Tn hiu tng t c vo cc mch so snh cng mt lc, cc trng thi ra ca mch so snh c a vo cc flip flop D a n b m ha,u ra ca mch m ha chnh l u ra ca mch ADC. Mch so snh v mch m ha l loi mch c tc x l rt cao nn tng thi gian tr ch vi chc ns,nh vy s chuyn i xy ra rt nhanh. Tuy nhin vi mch ADC nhanh 3 bit th n i hi by b so snh khi 6 bit th cn n 63 b so snh l nhc im ca mch ADC dng phng php so snh . Bng s tht ca mch chuyn i

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NG HU PHC

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NG HU PHC

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PH LC MCH GIAO TIP LED N V LED 7 ON

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NG HU PHC

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NG HU PHC

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NG HU PHC