K YU HI NGH SINH VIN NGHIN CU KHOA HC NM 2009

NG DNG CNG NGH FPGA THIT K BO MCH THC HNH MN K THUT S

SVTH: L VN SU Lp 04DT3, Trng i hc Bch khoa, i hc Nng GVHD: Ths.D QUANG BNH, NGUYN TRUNG KIN Khoa in T - Vin Thng, Trng i hc Bch khoa, i hc Nng

TM TT ti nghin cu c s l thuyt ASIC, nguyn l hot ng ca chip FPGA v quy trnh thit k FPGA, t xut mt phng php thit k IC s da trn cng ngh FPGA v nghin cu ng dng phng php ny xy dng ng dng Bo mch thc hnh cho b mn K thut s. Bo mch c thi cng trn nn tng IC XC2C256-CoolRunner II ca hng Xilinx. ti xy dng xong th vin nh cc IC s v s dng cc IC ny xy dng mt s bi thc hnh t cn bn n phc tp.

ABSTRACT This thesis researched ASICs theories, FPGAs specification and flow char in FPGA design, and building a method to design digital electronic circuit base on FPGA technology. Then apply this method in bulding the application Electronic board use for Digital experiment. This board is implemented with IC CoolRunner II XC2C256 of Xilinx. This thesis finished building small digital IC library and some sample circuits that use this library for basic to advanced digital experiment.

I.M u
Trong o to i hc, vic nng thi gian thc hnh, thit b th nghim ng vai tr quan trng trong vic cng c l thuyt v nng cao k nng thc t ca sinh vin. Thc hnh, th nghim k thut s l mn khng th thiu i vi sinh vin ngnh in t- Vin thng nhng thit b th nghim trng thng nhp t nc ngoi v vi gi thnh t v s lng ch p ng c mt phn nh nhu cu cn th nghim ca sinh vin. Hn na qua mt thi gian s dng cc bi thc hnh c xy dng trn cc thit b ny b li thi so vi gio trnh hc mi v khng s dng c na gy lng ph. Trong cc cng ngh mi trong lnh vc in t, cng ngh chip ASIC c nhiu tnh nng vt tri v thng c s dng trong cc ng dung chuyn bit. ASIC c ng dng thit k th nghim cc cc chip mi trn cc chip FPGA trc khi a vo sn xut. Ti sao khng s dng tnh cht ny xy dng cc IC s c bn v ghp ni cc IC to thnh mch logic trong cc bi thc hnh mn K thut s? Vic thc hnh K thut s bng cc IC s ring bit em li nhiu u im thc t nhng thit k v th nghim mch s trn chip FPGA em li nhiu li ch v thi gian, cng sc v chi ph hn.

II.Tng quan
ASIC (Application-Specific Integrated Circuit) l mt thut ng ch cc vi mch tch hp chuyn dng trong in t hc. ASIC l mt vi mch IC c thit k dnh cho mt ng dng c th. ASIC ngy nay c ng dng hu nh khp mi ni, v d nh vi x l ca in thoi di ng, hay chip x l trong cc my mc t ng, cc phng tin truyn thng, xe c, tu v tr, cc h thng x l, cc dy chuyn cng nghip...

K YU HI NGH SINH VIN NGHIN CU KHOA HC NM 2009

FPGA (Field programmable Gate Array) mng cng lp trnh c dng trng l mt nhnh ca ASIC lp trnh c. Mt s nh sn xut gi n l PLD (Programmable Logic Device_ Cc linh kin lp trnh c) phc tp CPLD (complex PLD). FPGA thuc h ASIC lp trnh c. N l dng sn phm mi nht ca h ASIC v pht trin nhanh chng, thay th TTL trong cc h thng vi in t. Vi cc tnh cht: Cc ti nguyn c bn giu c c kh nng lp trnh kt ni nh cc ma trn cc kt ni bao quanh; cc cng I/O lp trnh c chiu v mode hot ng (1,2 V ; 3.3V; n 5V); vic thit k v th nghim mch s mi c th hon thnh trong vi gi. FPGA l tng trong vic to ra cc mu u tin cho vic to ra mu u tin cho cc h thng s hoc i vi ng dng chuyn bit sn xut s lng thp.

Hnh 1: S khi qui trnh thit k IC trn CPLD

Verilog l mt ngn ng m t phn cng c dng rng ri trong thit k mch s v tng t. N l ngn ng chun cng nghip, c s dng rng ri trong thc t. Cng vi tnh cht ch ca n lm cho qu trnh gi ri thun li, d kim sot m hnh c to ra, gim thi gian kim tra, th nghim. Trn c s quy trnh thit k IC s trn FPGA ca Xilinx, ta c th ng dng cc cng c c h tr trong quy trnh ny xy dng mt quy trnh thit k cc mch s da trn cc th vin IC s c xy dng trc. Tt nhin quy trnh thit k c bn c s dng cho thit k th vin IC s v s dng ngn ng Verilog trong thit k v kim tra thit k. ti cng xy dng c bo mch thc hnh trn chip CPLD CoolRunnerII (mt nhnh con trong FPGA) v mt s mch thc hnh i km. Vi Bo mch ny ngi dng c th: 1.S dng phng php trn t xy dng cc bi thc hnh K thut s khc; 2.Trin khai th nghim thit k cc IC mi; 3.Xy dng mch in t s cho cc ng dng trong thc t khc.

III. Nhng nghin cu thc nghim hoc l thuyt

1. Xy dng quy trnh thit k mch s trn CPLD s dng cng c Schematic Quy trnh xy dng thit k chip trn FPGA ca Xilinx gip cho ngi thit k c th lm c nhng d n n gin n phc tp, bng cch s dng mt trong nhng ngn ng VHDL, Verilog ..... Trn c s quy trnh thit k gc, ti nghin cu xut xy dng quy trnh thit k th vin IC s v bi thc hnh s trn nn tng chip CPLD_mt h ca FPGA s dng cng c Schematics ca phn mm Xilinx ISE. Libraries (th vin): Sau khi c thng tin v linh kin, chng ta tin hnh phn tch cc c tnh ca n v dng ngn ng m t phn cng (HDL) xy dng linh kin a vo h thng th vin linh kin. Cc IC trong th vin c kim tra nh gi hot ng ng n trc khi a vo s dng Specification ( c im k thut). S dng th vin linh kin trn v s mch bng 2 phng php: Schematic Capture v Synthesis. Trong phng php Schematic c th cho sinh vin s dng thc hnh thit k mch. Synthesis dng to th vin IC hoc v mch s bng Verilog dng cho nghin cu thit k cc mch s phc tp.

K YU HI NGH SINH VIN NGHIN CU KHOA HC NM 2009

Verification (kim nh ) Bc m phng (simulation) kim tra cho php sinh vin c th phn tch hot ng ca mch thit k nh trc khi trin khai trn bo mch thc hnh ti phng th nghim. Implemention (trin khai thit k): Mi bc kim tra c hon thnh. Do y l lc ta cn t thit k ny ln chip XC2C256 ca bo mch th nghim chy th. Tin hnh o c kim tra kt qu hot ng trn thc t. Sau khi np mch thit k ln CPLD cc mch u cui c th c ghp ni cho ng dng cui. 2. Quy trnh kim tra thit k ti xy dng mt th vin vi kh nhiu IC s. Cc IC ny trc khi a vo ng dng u phi c kim tra tnh ng n ca n. C 2 cp kim tra c thc hin trn ti: m phng hot ng trn cng c ISE Simulator v kim nghim hot ng thc t trn CPLD CoolRunner 2 bng my phn tch logic GLA-1132. Kt qu c i chiu vi Hnh 2: S khi qui trnh thit chc nng hot ng ca IC c cho bi nh k IC trn CPLD sn xut nh gi. Di y l mt trong cc kt qu kim nghim: Kim nghim nh gi IC DM74LS193 thc t v IC DM74LS193 thit k trn CPLD 2.1.Kim nghim thit k IC DM74LS193 IC DM74LS193 l IC c chc nng m ln hoc m xung cho php np xa cc gi tr ban u. Vi u ra l m BCD cho php d dng ghp ni vi mch hin th lm chc nng chuyn i BCD sang Led by on DM7447A.

Hnh 3: Kt qu m phng hot ng ca IC

Hnh 4: Kt qu kim nghim hot ng thc

K YU HI NGH SINH VIN NGHIN CU KHOA HC NM 2009

DM74LS193 trn CPLD(Xc2C256) t bng my phn tch logic GLA-1132

V nguyn l hot ng: IC DM74LS193 thit k trn CPLD thc thi y cc trng thi hot ng ca IC DM74LS193 ca cc nh sn xut. V cc c tnh in:
Thng s iu kin DM74LS193 thc t Vcc = Vmin , Vil =0.8V, Vih = 2V, Iol = 16mA Vcc = Vmin , Vil =0.8V, Vih = 2V, Ioh = 0.4mA iu kin DM74LS193 trn XC2C256 Vccio = 3V Iol = 8mA Vccio = 3V Iol = -8mA 2.4 DM74LS193 Min 4.75 Max 5.25 0.4 DM74LS193 trn XC2C256 Min Max 1.7 3.6 0.4 UNIT

Vcc Vol Voh Vih Vil Iil Iih

V V V

0.4 2
0.8

2
-0.3

3.9
0.8

V V

Vcc = Vmax; Vi = 0.4V Vcc = Vmax; Vi = 2.4V

VCCIO to 3.0V VCCIO to 3.0V

- 1.6mA
40mA

- 8mA 8 mA

Nhn xt: T bng so snh trn ta thy c tnh in ca 2 dng IC ny tng i ging nhau tuy nhin CPLD linh hot hn v c nhiu ch cu hnh cho IO cho php giao tip c vi rt nhiu h IC khc nhau. Tn s hot ng ti a thit k trn CPLD cng ln ti 240MHz (Theo ti liu k thut ca CPLD CoolRunner II.) . Hnh 5: bng cu hnh IO CPLD 2.2 Kim nghim mch thc hnh m xung s dng IC DM7490 v DM7447 ng dng phng php xy dng mch s s dng cng c Schematic ca Xilinx ISE, s dng 2 IC c thit k v kim tra hot ng trong th vin: IC m BCD DM7490A v IC chuyn i BCD sang Led 7 on DM7447A xy dng b m thp phn hin th ra Led 7 on. Mch c kim tra qua m phng ri o c trn my phn tch s GLA 1132 kim tra tnh ng n. Cui cng th nghim trn mch thc t cho hin th ra Led 7 oan.

Hnh 6: S mch m thit k trn CPLD

K YU HI NGH SINH VIN NGHIN CU KHOA HC NM 2009

Hnh 7. Gin xung o c khi m phng bng ISE Simulator

Hnh 8. Gin xung o c t my phn tch s GLA 1132

Nhn xt: Mch thc t kt ni mch trn vi Led 7 on bn ngoi chy n nh v ng nguyn l hot ng. iu ny chng t c s linh hot vt tri ca mch s thit k trn cng ngh FPGA so vi cc mch IC s truyn thng m khng cn cc cng on mua IC, lm mch ng, hn mch. Ngi dng ch cn tp trung chnh vo phn thit k mch ng dng.

IV. nh gi kt qu
Bo mch thit k thnh cng, c th np xa c chng trnh trn chip CPLD Cool RunnerII qua cng Parallel ca my tnh bng phn mm Webpack ISE. Qu trnh thit k, kim tra, th nghim th vin IC s v mt s bi thc hnh K thut s trn bo mch chy n nh. Nu bo mch s dng chip FPGA vi s lng ti nguyn v chn IO ln, mch s thit k s ln hn tc cao hn c th s dng cho mn hc Thit k h Vi x l v nhiu mn hc khc.

V. Kt lun
Bo mch thc hnh mn k thut s ny h tr tt vic ging dy mn k thut s trong vic to ra nhiu bi thc hnh khc nhau t n gin n phc tp trong lnh vc in t s. Ngoi ra bo mch c th c s dng phc v vic nghin cu, ch to v kim tra c tnh ca mt IC mi hoc mt mch phc tp gm nhiu IC s kt ni vi nhau m khng cn tn kinh ph v thi gian lm mch c bit l mch nhiu lp. Bo mch cn c th dng cho mc ch thng mi, ngi thit k ch vic s dng cc module c thit k i km to ra cc mch s dng cho mc ch ring ca mnh. Li cm n Em xin cm n thy Bnh, thy Kin. Cc thy hng dn, gip rt nhit tnh em c th hon thnh c ti ny. Mt ln na em xin chn thnh cm n cc thy! TI LIU THAM KHO [1] Thy Hunh Vit Thng, Bi ging mn K Thut S, i hc Bch Khoa, i hc Nng [2] Cc ti liu k thut ca Xilinx [3] Verilog-2001 Behavioral and Synthesis Enhancements, Clifford E. Cummings cliffc@sunburst-design.com / www.sunburst-design.com