Giao Trinh Thuc Hanh VDK

Trng i Hc Khoa Hc T Nhin Khoa in T - Vin Thng
B Mn My Tnh H Thng Nhng Gio trnh Thc Hnh Vi iu Khin
MC LC
BI 1. QUI TRNH LP TRNH PIC ......................................................................................3
1. 2. 3. 4. 1. 2. 3. 1. 2. 1. 2. 3. 1. 2. 3. 1. 2. 3. 1. 2. 3.
GII THIU BOARD PIC EXPLORER 16 ....................................................... 3 GII THIU CNG C LP TRNH PIC ........................................................ 4 CC BC LP TRNH PIC ........................................................................... 5 BI TP ............................................................................................................ 9 TNG QUAN .................................................................................................. 11 CHNG TRNH MU ................................................................................. 12 BI TP .......................................................................................................... 13 TNG QUAN V TIMER TRN PIC 24F ...................................................... 14 BI TP .......................................................................................................... 20 TNG QUAN V NGT TRN PIC 24F ....................................................... 23 CC BC XY DNG NG DNG LIN QUAN N NGT ............... 26 BI TP .......................................................................................................... 27 TNG QUAN V ADC TRN PIC 24F .......................................................... 29 CHNG TRNH MU ................................................................................. 36 BI TP .......................................................................................................... 37 GII THIU LCD TRN BOARD PIC EXPLORER 16 ................................. 38 GIAO TIP PMP.............................................................................................. 41 BI TP .......................................................................................................... 43 KHI NIM UART ......................................................................................... 45 MODULE UART TRN PIC 24F .................................................................... 45 BI TP .......................................................................................................... 53
ThS. Nguyn Quc Khoa CN. Nguyn c Tin Trang 1
BI 2. GIAO TIP I/O N GIN ....................................................................................... 11
BI 3. TIMER ....................................................................................................................... 14
BI 4. NGT ......................................................................................................................... 23
BI 5. ADC ........................................................................................................................... 29
BI 6. GIAO TIP LCD ........................................................................................................ 38
BI 7. GIAO TIP UART ..................................................................................................... 45
LI M U Gio trnh ny c bin son nhm phc v vic ging dy hc phn thc hnh Vi iu Khin v c p dng k t hc k II nm hc 2010-2011. Gio trnh gm 7 bi, gip sinh vin nm c kin thc v xy dng ng dng cho vi iu khin PIC. Theo qui ch o to tn ch, vic chun b trc nh l bt buc i vi sinh vin. Tc gi xin gi li cm n n cc bn nhm Vi iu Khin v nhng kin ng gp cho gio trnh c hon thin. Li cm n cng xin c gi ti hng Microchip cung cp thit b v ti liu tham kho. y l ln u tin tc gi bin son gio trnh thc hnh cho hc phn ny nn khng th trnh khi sai st. Tc gi rt mong nhn c kin phn hi ng gp ca cc bn sinh vin nhng ln bin son sau c tt hn. Mi kin ng gp, xin vui lng gi v email nguyentienkhtn@gmail.com.
ThS. Nguyn Quc Khoa CN. Nguyn c Tin
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BI 1.
QUI TRNH LP TRNH PIC
MC CH Thng qua bi ny, sinh vin s nm r: Cch thc s dng board PIC Explorer 16 trong qu trnh hc tp. Cch s dng cng c MPLAB v cc gi h tr xy dng chng trnh, tng hp v np xung board. Cch debug chng trnh bng cng c MPLAB
1. GII THIU BOARD PIC EXPLORER 16
Hnh 1-1. Board PIC Explorer 16 dng PIC24FJ128GA010 PIC Explorer 16 l board thc tp cho php sinh vin lm quen vi lp trnh Vi iu khin PIC cng nh thit k cc h thng t n gin n phc tp. Cc thnh phn trn board Pic Explorer 16 bao gm: 1. Vi iu khin PIC24FJ128GA010 2. Cng cm 9V cung cp in th ng vo +3.3V v +5V cho board 3. LED bo hiu ngun 4. Cng cm RS232 5. B cm bin nhit 6. Cng kt ni USB 7. Khe cm In-Circuit Debugger (ICD)
8. Nt gt chn la phn cng 9. LCD (2 dng, 16 ct) 10. Khe cm PCB kt ni LCD mu 11. Nt nhn dng reset hoc dnh cho ng dng 12. B ng vo analog 13. 8 LEDs bo hiu dnh cho ng dng 14. B gii m gii a hp 74HCT4053 15. EEPROM ni tip 16. Thch anh 8 MHz v Real-Time Calendar/ Clock (RTCC) 32.768 KHz 17. Vng m rng cho cc ng dng 18. Socket cm vo PCI 19. Giao tip vi PIC Kit 2 Programmer 20. Giao tip JTAG
Hnh 1-2. V tr cc thnh phn trn board Pic Explorer 16
2. GII THIU CNG C LP TRNH PIC

Qui trnh lp trnh PIC c th theo cc bc sau: Xy dng m chng trnh Bin dch m chng trnh Np m chng trnh xung board thc tp v kim tra kt qu
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a) Gii thiu cng c MPLAB IDE MPLAB IDE l gi cng c ca hng Microchip cung cp mi trng cho php ngi lp trnh xy dng m chng trnh, bin dch, debug v np m chng trnh xung board c s dng PIC. Ti liu ny s dng MPLAB phin bn 8.63. b) Gii thiu cng c MPLAB C Compiler (mplabc30) for PIC24 MCUs y l cng c bin dch v lin kt m chng trnh vit bng ngn ng C cho cc dng PIC 24. Sinh vin c th download cng c ny ti trang web ca Microchip. Bi thc hnh ny s dng phin bn 3.25.
3. CC BC LP TRNH PIC
Chun b: sinh vin cn ci t sn MPLAB v MPLAB C Compiler for PIC24 MCUs cho PC. a) To project trn MPLAB IDE Bc 1. Khi ng MPLAB Bc 2. Menu Project Project Wizard Next Bc 3. Chn PIC24FJ128GA010 trong hp thoi Device Next Bc 4. La chn Microchip C30 Toolsuite v tr ng dn ti cc thnh phn trng ng (th mc ci MPLAB C Compiler for PIC24 MCUs) Next
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Hnh 1-3. Tr ti ng dn ca cc thnh phn trong Microchip C30 Toolsuite Bc 5. La chn ng dn ca project v t tn project Next
Hnh 1-4. To project tn begin trong ng dn D:\Exercises\PIC\tut

Bc 6. Add file lin kt (p24FJ128GA010.gld) Tr ti file p24FJ128GA010.gld (Thu_muc_cai_dat_mplabc30\ v3.25\support\PIC24F\gld) Add Next. tin cho to project sau ny, sinh vin nn copy file ny vo th mc d tm thy hn ( a hay ng dn ti th mc ch project).
Hnh 1-5 Tr ti file lin kt Bc 7. Finish Bc 8. Menu File New. Sinh vin c th xy dng m chng trnh trong ca s mi ny v lu vi nh dng .c. #include <p24fj128ga010.h> main() { TRISA = 0; // all PORTA pins output PORTA = 0xff; } Bng 1. Chng trnh v d kim tra chc nng PORT A b) Build project Bc 1. Add m ngun vo project Menu View Project click chut phi vo project Add files tr ti file cha m chng trnh Bc 2. Menu Project Build All hoc phm Buil All trn Task Bar
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Hnh 1-6. Build Project c) Np chng trnh xung PIC C rt nhiu cng c h tr cho vic np m chng trnh cho PIC (mch np). Bi thc hnh ny s hng dn sinh vin s dng cng c MPLAB ICD 2 LE c sn xut bi hng Microchip. Qui nh bt buc khi s dng MPLAB ICD 2 LE: Sinh vin phi lm theo trnh t: Cm MPLAB ICD 2 LE vo PC Cm MPLAB ICD 2 LE vo board thc tp vi mt hin th MPLAB ICD 2 LE quay vo socket cm PIC Cp ngun t adapter. Lu : c th s dng xut d liu PORTA ra led, sinh vin cn tt chc nng JTAG bng cch vo menu Configure Configuration bits b du check ti Configuration Bits set in code v chn gi tr JTAG port is disabled.
Hnh 1-7. Tt chc nng JTAG Bc 1. La chn cng c

Menu Programmer Select Programmer MPLAB ICD 2
Hnh 1-8. La chn cng c np chng trnh Bc 2. Kt ni thit b Menu Programmer Connect. Board phi c cp ngun trc khi kt ni.Sinh vin cn kim tra cc thng s trong ca s output m bo thit b c kt ni ng trc khi tip tc. Bc 3. Np m chng trnh xung board thc tp Menu Programmer Program Bc 4. Kim tra kt qu Ngt kt ni gia board thc tp v MPLAB ICD 2 LE v kim tra kt qu chng trnh. d) Debug m chng trnh Sinh vin c th s dng MPLAB ICD 2 LE hoc MPLAB SIM debug m chng trnh. la chn cng c, sinh vin vo menu Debugger Select Tool MPLAB ICD 2 hay MPLAB SIM. Sinh vin phi kt hp thm cc chc nng chy tng bc v cc ca s trong menu View c kt qu mong mun. Sinh vin c th tham kho thm trong ti liu Programming 16-Bit PIC Microcontrollers in C
4. BI TP
Sinh vin thc hin cc bc trn vi nhng m chng trnh (code) mu sau
#include <p24fj128ga010.h> void delayms( unsigned t) {
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T1CON = 0x8000; // enable tmr1, Tcy, 1:1 while (t--) { TMR1 = 0; while (TMR1<2000); } } // Delayms main() { TRISA = 0; // all PORTA pins output while(1) { PORTA = 0xff; delayms(500); PORTA = 0; delayms(500); } } #include <p24fj128ga010.h> void delayms( unsigned t) { T1CON = 0x8000; // enable tmr1, Tcy, 1:1 while (t--) { TMR1 = 0; while (TMR1<2000); } } // Delayms main() { TRISA = 0; // all PORTA pins output int i; i = 1; while(1) { PORTA = i; delayms(500); i=i << 1; if(i==16) i = 0x1; } }
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BI 2.
GIAO TIP I/O N GIN
MC CH Bi thc hnh gip sinh vin lm quen vi cc giao tip I/O n gin (Led, nt nhn) trn board PIC Explorer 16.
1. TNG QUAN
a) Mi lin h gia cc port trong PIC v giao tip I/O trn board Trong gii hn bi thc hnh ny, sinh vin ch tm hiu hai PORT l Port A v D. Cc LEDs c ni vo 7 bits thp ca port A. Port A c 16 chn gm PIN_A0, PIN_A1, , PIN_A15, trong PIN_A7 n PIN_A0 c ni vi 8 LEDs. Cc switches t SW3 n SW6 c ni vo cc chn PIN_D6, PIN_D13, PIN_A7 v PIN_D7 theo ng th t. Cc switches tc ng mc thp (khi nhn vo bng 0, khi th ra bng 1)
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b) Khi to port
Hnh 2-1. S ca mt Port I/O in hnh ca Pic24 Theo s trn, chng ta c th thy c nhiu chc nng ngoi vi c a hp trn mt port. Ngi s dng c th qui c hng d liu trn port thng qua vic cu hnh cc thanh ghi thch hp. Trong gii hn bi thc hnh ny, sinh vin ch quan tm n hai port A v D. Vi hai port ny, thanh ghi c s dng qui c chiu d liu l TRISA v TRISD. Tng bit trong thanh ghi TRIS qui nh chiu d liu cho tng bit trn Port. D liu s l output nu bit tng ng trong thanh ghi TRIS c thit lp gi tr 0 v ngc li.
2. CHNG TRNH MU
Sinh vin tham kho mt s chng trnh mu sau a) Sng 4 led
#include <p24fj128ga010.h> main()
{ TRISA = 0; // all PORTA pins output PORTA = 0x0f; }
b) Led m ln mi khi nhn SW3

#include<p24fj128ga010.h> #define DELAY 1000 void delay() { T1CON = 0x8030; TMR1 = 0; while ( TMR1 < DELAY); TMR1 = 0; } main() { TRISDbits.TRISD6 = 1; TRISA = 0x0; int i = 0; while(1) { if(PORTDbits.RD6 == 0) { delay(); if(PORTDbits.RD6 == 0) i = i+1; } PORTA= i; } }
3. BI TP
BI 1. Lp trnh hai led rt ui nhau BI 2. Lp trnh h thng sng dn ln mi khi SW1 c nhn, hin th kt qu ra led. BI 3. Vit chng trnh sau: khi nhn SW3 th LEDs dch t tri sang phi, SW2 th LEDs dch t phi sang tri.
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BI 3.
TIMER
MC CH Bi thc hnh gip sinh vin hiu cu trc ca cc b nh thi (Timer) trong PIC 24F v xy dng cc ng dng lin quan n nh thi.
1. TNG QUAN V TIMER TRN PIC 24F

a) Gii thiu v Timer Vi iu khin PIC24FJ128GA010 gm nm b Timer: Timer1, Timer2, Timer3, Timer4 v Timer5. Mi Timer l b nh thi/ m 16-bits gm nhiu thanh ghi c kh nng c v ghi: TMRx: Thanh ghi m Timer 16 bits PRx: Thanh ghi chu k Timer 16 bits TxCON: Thanh ghi iu khin Timer 16 bits Tng Timer c cc bits iu khin ngt ring bit Interrupt Enable Control bit (TxIE): bit iu khin cho php ngt hot ng Interrupt Flag Status bit (TxIF): bit c trng thi ca ngt Interrupt Priority Control bits (TxIP<2:0>): bit iu khin u tin ngt b) Cc loi Timer Cc Timers c chia thnh ba loi: loi A, loi B v loi C. Mt vi Timers 16bit c th kt hp vi nhau to thnh Timers 32-bit. i. Timer loi A Timer1 thuc loi A. N c th hot ng vi dao ng cng sut thp 32 KHz hoc ch Asynchronous mode vi clock cp t ngoi vo. Thanh ghi iu khin TxCON
Hnh 3-1. Thanh ghi TxCON loi A Cc bit trong thanh ghi TxCON loi A
Bit 15
TON: Timerx On bit
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Bit 14 Bit 13
Bit 127 Bit 6
Bit 54
Bit 3 Bit 2
Bit 1
Bit 0
1 = Timer bt u hot ng 0 = Timer ngng hot ng Khng s dng, xem nh 0 TSIDL: Stop in Idle Mode bit 1 = Timer ngng hot ng khi thit b ch Idle 0 = Timer tip tc hot ng ch Idle Khng s dng, xem nh 0 TGATE: Timerx Gated Time Accumulation Enable bit Khi TCS = 1: bit ny b b qua Khi TCS = 0: 1 = cho php gated time accumulation 0 = khng cho php gated time accumulation TCKSP<1:0>: Timerx Input Clock Prescale Select bits 11 = 1:256 prescale value 10 = 1:64 prescale value 01 = 1:8 prescale value 00 = 1:1 prescale value Khng s dng, xem nh 0 TSYNC: Timerx External Clock Input Synchronization Select bit Khi TCS = 1: 1 = ng b vi clock bn ngoi cp vo 0 = Khng ng b vi clock bn ngoi cp vo Khi TCS = 0: Bit ny b b qua (xem nh l 0). Timerx s dng clock trong khi TCS =0 TCS: Timerx Clock Source Select bit 1 = Clock ngoi t chn TxCK 0 = Clock trong (FOSC/2) Khng s dng, xem nh 0
Bng 2. ngha cc bit trong thanh ghi TxCON loi A ii. Timer loi B Timer2 v Timer4 thuc loi B. Timer loi B c th ghp vi Timer loi C to thnh Timer 32 bits. Khi ny, thanh ghi TxCON ca Timer loi B pht tn hiu iu khin T32 cho php hot ng ch 32 bits.
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Thanh ghi iu khin TxCON
Hnh 3-2. Thanh TxCON loi B Cc bit trong thanh ghi TxCON loi B
Bit 15 TON: Timerx On bit Khi T32 = 1 ( ch Timer 32 bits) 1 = Bt u hot ng cp Timer TMRx:TMRy 0 = Ngng hot ng cp Timer TMRx:TMRy Khi T32 = 0 ( ch Timer 16 bits) 1 = Bt u hot ng Timer 16 bits 0 = Ngng hot ng Timer 16 bits Khng s dng, xem nh 0 TSIDL: Stop in Idle Mode bit 1 = Timer ngng hot ng khi thit b ch Idle 0 = Timer tip tc hot ng ch Idle Khng s dng, xem nh 0 TGATE: Timerx Gated Time Accumulation Enable bit Khi TCS = 1: bit ny b b qua Khi TCS = 0: 1 = cho php gated time accumulation 0 = khng cho php gated time accumulation TCKSP<1:0>: Timerx Input Clock Prescale Select bits 11 = 1:256 prescale value 10 = 1:64 prescale value 01 = 1:8 prescale value 00 = 1:1 prescale value T32: 32-Bit Timerx Mode Select bit 1 = TMRx v TMRy c cu hnh nh Timer 32 bits 0 = TMRx v TMRy c cu hnh nh cc Timer 16 bits c lp Khng s dng, xem nh 0 TCS: Timerx Clock Source Select bit 1 = Clock ngoi t chn TxCK 0 = Clock trong (FOSC/2)
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Bit 14 Bit 13
Bit 127 Bit 6
Bit 54
Bit 3
Bit 2 Bit 1
Bit 0
Khng s dng, xem nh 0
Bng 3. Cc bit trong thanh ghi TxCON loi B iii. Timer loi C Timer3 v Timer5 thuc loi C. Timer loi C c ghp vi Timer loi B to thnh Timer 32 bits. Ngoi ra, Timer loi C cn dng to trigger cho qu trnh chuyn i tng t sang s (ADC). Thanh ghi iu khin TxCON
Hnh 3-3. Thanh ghi TxCON ca Timer loi C Cc bit trong thanh ghi TxCON ca timer loi C
Bit 15 TON: Timery On bit 1 = Bt u hot ng Timery 16 bits 0 = Ngng hot ng Timery 16 bits Khng s dng, xem nh 0 TSIDL: Stop in Idle Mode bit 1 = Timer ngng hot ng khi thit b ch Idle 0 = Timer tip tc hot ng ch Idle Khng s dng, xem nh 0 TGATE: Timery Gated Time Accumulation Enable bit Khi TCS = 1: bit ny b b qua Khi TCS = 0: 1 = cho php gated time accumulation 0 = khng cho php gated time accumulation TCKSP<1:0>: Timerx Input Clock Prescale Select bits 11 = 1:256 prescale value 10 = 1:64 prescale value 01 = 1:8 prescale value 00 = 1:1 prescale value Khng s dng, xem nh 0 TCS: Timery Clock Source Select bit 1 = Clock ngoi t chn TxCK 0 = Clock trong (FOSC/2) Khng s dng, xem nh 0
Bit 14 Bit 13 Bit 12 7 Bit 6
Bit 5 4
Bit 3 2 Bit 1
Bit 0
Bng 4. Cc bit trong thanh ghi TxCON ca Timer loi C

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Lu : Khi ch 32 bits c kch hot (TxCON<3> = 1), cc bits ny khng tc ng n hot ng ca Timer; tt c chc nng c thit lp thng qua cc bit trong thanh ghi TxCON ca cc Timer loi B. c) Cc ch hot ng Cc ch hot ng ca Timer: nh thi B m ng b (Synchronous counter) s dng clock ngoi Gated timer B m khng ng b (Asynchronous counter) Ch Timer c cu hnh thng qua cc bit sau: TCS (TxCON<1>): Timer Clock Source Control bit TSYNC (TxCON<2>): Timer Synchronization Control bit (ch dnh ring loi A) TGATE (TxCON<6>): Timer Gate Control bit i. Ch nh thi Tt c cc loi Timer u c th hot ng ch nh thi. Trong ch ny, xung ng vo cho b m c cung cp bi xung ca h thng (Fosc/2). Khi hot ng, b m s tng mt ln trong n chu k lnh nu prescale thit lp l 1:n. Ch nh thi c la chn bng cch xa bit TCS (TxCON<1>). Cng thc tnh thi gian nh thi: Trong , Tdelay: thi gian nh thi M: tc x l lnh ca PIC, v d PIC 24F c th x l 4 triu lnh/s 8 MHz M = 4,000,000. DELAY: tham s ngi dng t nh ngha ii. B m ng b (Synchronous counter) s dng clock ngoi Khi bit TCS c set ln 1, clock ca timer c cp t bn ngoi v b m trong timer s tng mt ln ti mi cnh ln ca chn TxCK. Xung clock ngoi phi tha cc yu cu v thi gian mc cao v thi gian mc thp khi c s dng trong ch m ng b. Sinh vin c th tham kho thm ti liu 24F Timers Reference Chapter 39704a trong PIC24F Family Reference Manual iii. Ch Gated Timer Ch ny cho php b m ca timer tng da trn thi gian mc cao ca chn TxCK. Trong ch ny, timer s dng clock ni (Fosc/2). Khi chn TxCK
mc cao, b m s m ln cho n khi chn TxCK chuyn trng thi xung mc 0. Ngt c th xy ti thi im ny (chn TxCK chuyn trng thi t cao xung thp). Timer c th hot ng trong ch ny, cc bit sau y phi c set gi tr ph hp: TGATE (TxCON<6>) = 1, TON (TxCON<15>) = 1 v TCS (TxCON<1>) = 0. iv. B m bt ng b Ch c Timer loi A c kh nng hot ng ch m bt ng b s dng xung clock p vo chn TxCK. B m s tng bt ng b vi clock ni. Ch ny c mt s u im: Timer c th hot ng trong ch Sleep v c th sinh ra ngt khi phc h thng t ch Sleep theo thi gian thit lp. Timer c th s dng ngun dao ng 32 KHz v. Hot ng ca timer vi clock ngoi c tn s ln Trong trng hp ngi lp trnh mun s dng timer vi clock ngoi c tn s ln, cc timer loi A v B s thch hp nht v vic ng b ca cc timer ny xy ra sau mch prescaler. d) Ngt Timer Timer 16 bit c kh nng sinh ra ngt (bit TxIF set ln 1)nu c cho php v mt trong nhng s kin: B m t mt gi tr c thit lp trong thanh ghi period (PRx) v timer khng hot ng trong ch Gated Timer. C mt cnh xung xy ra ti chn TxCK khi timer hot ng trong ch Gated timer. Bit TxIF phi c xa bi phn mm. cho php Timer sinh ra ngt, bit Timer Interrupt Enable (TxIE) phi c bt ln 1 ng thi gi tr u tin ngt (c thit lp qua cc bit TxIP<2:0>) phi khc 0.
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Hnh 3-4. V d ngt Timer e) Prescale Gi tr ny qui nh t l s chu k lnh so vi s ln tng ca b m trong timer. V d, khi thit lp prescale l 1:4 th sau 4 chu k lnh, b m trong timer s tng mt gi tr. Vi PIC 24F, ngi lp trnh c th la chn mt trong 4 gi tr cho prescale: 1:1, 1:8, 1:64 v 1:256. Gi tr prescale s b xa trong cc trng hp sau: Ghi gi tr xung thanh ghi TMRx Xa bit TON Thit b reset f) Cu hnh Timer 32 bit Timer loi B v C c th kt hp to thnh timer 32 bit. Timer loi C s tr thnh most significant word (msw) v timer loi B s tr thnh least significant word (lsw). Trong timer 32 bit, nhng bit iu khin loi B s iu khin hot ng ca timer. Bit iu khin ca timer loi C khng c ngha. Ngc li, vic iu khin ngt ca timer 32 bit c thit lp qua cc bit iu khin ngt loi C, cc bit iu khin ngt loi B khng c tc dng. Sinh vin c th tham kho thm trong ti liu 24F Timers Reference Chapter 39704a
2. BI TP
Bi mu Lp trnh cc led trn PORTA chp tt theo chu k 1 s s dng timer 1 ch nh thi. Chng trnh mu
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#include <p24fj128ga010.h> #define DELAY 4000 void delay_ms(int t) { TMR1 = 0; T1CON = 0x8000; while(t--) { while(TMR1 <DELAY); TMR1=0; } } main() { TRISA = 0; while(1) { PORTA = 0; delay_ms(1000); PORTA = 0xff; delay_ms(1000); } } Lu : timer c th chy ng theo yu cu, sinh vin cn thit lp dao ng trn MPLAB bng cch vo menu Configure Configure bits B du check ti Configuration Bits set in code thit lp cc gi tr theo hnh sau:
Hnh 3-5. Thit lp Configuration Bit cho Timer
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BI 1. Lp trnh h thng m ln sau 500 ms s dng Timer 2 ch nh thi, xut kt qu ra led. BI 2. Lp trnh h thng tha mn yu cu sau: Khi nhn SW3 1 ln th LED7 chp tc 1s, nhn 2 ln th chp tc s, , nhn 8 ln th chp tc s, nu nhn 9 ln th quay li trng thi ban u.
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BI 4.
NGT
MC CH Bi thc hnh gip sinh vin tm hiu c ch ngt, cch cu hnh ngt trn PIC 24F v xy dng cc ng dng ngt lin quan n nt nhn v Timer.
1. TNG QUAN V NGT TRN PIC 24F

a) Gii thiu Module iu khin ngt trn PIC 24F gim s lng tn hiu yu cu ngt ti CPU xung cn 1 tn hiu. Module iu khin ngt trn PIC 24F c nhng c im sau: Ti a 8 ngoi l (processor exception) v by phn mm (software trap). Ngi dng c th la chn 7 mc u tin. Bng vector ngt ti a 118 vectors Bng vector ngt thay th (Alternate Interrupt Vector Table AIVT) h tr vic debug b) Bng vector ngt Mt phn vector ngt PIC 24F c nh ngha trong MPLAB C Compiler theo bng sau. Nhng vector ngt khc (_Interrupt69 _Interrupt117) hin vn cha c s dng.
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Bng 5. Vector ngt PIC 24F c nh ngha trong MPLAB C Compiler (Phn 1)
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Bng 6. Vector ngt PIC 24F c nh ngha trong MPLAB C Compiler (Phn 2)
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Mi ngun ngt c iu khin bi 5 bit iu khin nm nhiu thanh ghi khc nhau: Bit Interrupt Enable (tn cc bit ny thng c hu t -IE): khi bt ln 1, bit ny cho php ngun ngt sinh ra ngt. Bit Interrupt Flag (tn cc bit ny thng c hu t -IF): bit ny c set mi khi mt s kin c th gy ngt xy ra. Bit ny khng ph thuc vo bit Interrupt Enable. Lu : bit ny phi c xa trong hm phc v ngt. Cc bit qui nh mc u tin (tn cc bit ny thng c hu t -IP): ba bit ny qui nh mc u tin cho mt ngt. Gi tr u tin t 0 7. Trong hai ngt xy ra ng thi, ngt no c mc u tin cao hn s c phc v trc. Ti thi im thit b khi ng, mi ngt s c mc u tin mc nh l 4. c) Ngt chng (Nesting of interrupts): Mt ngt c mc u tin thp c th b ngt bi mt ngt c mc u tin cao hn. c im ny c th kim sot bng bit NSTDIS trong thanh ghi INTCON1. Khi bit ny c set, CPU s phc v mt ngt trc khi phc v ngt khc, bt chp ngt xy ra sau c mc u tin cao hn ngt CPU ang phc v. Ni cch khc, khi bit ny c set, ngt chng khng xy ra.
2. CC BC XY DNG NG DNG LIN QUAN N NGT

a) Thit lp ngt mt ngun c th sinh ra ngt, ngi lp trnh phi c nhng thit lp nht nh (c th theo th t sau): qui nh mc u tin ngt xa c ngt cho php ngt xy dng chng trnh phc v ngt. tc ng vo cc bit iu khin ngt, sinh vin c th s dng tn cc bit theo MPLAB C Compiler. Tn bit = tn ngt (primary name trong bng Vector ngt b i t Interrupt)+ hu t (IE, IF, IP). V d, cc bit iu khin ngt Timer1: _T1IF (c ngt), _T1IE (cho php ngt) v _T1IP (mc u tin ngt). b) Xy dng hm phc v ngt Mt s yu cu vi hm phc v ngt: Khng c tham s v kiu tr v l void Khng gi hm phc v ngt trong chng trnh chnh Hm phc v ngt khng nn gi cc hm khc.
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C php ca hm phc v ngt:

void __attribute__ (( interrupt)) Interrupt_name ( void) { // interrupt service routine code here... }
Vi Interrupt_name chnh l primary name trong bng Vector ngt. V d: chng trnh phc v ngt cho timer1: void __attribute__ (( interrupt)) _T1Interrupt ( void) { // interrupt service routine code here... _T1IF = 0; } // _InterruptVector Ngi lp trnh c th s dng c php sau vi cc hm ngt n gin:
void __ISR Interrupt_name ( void) { // interrupt service routine code here... }
Lu :Sinh vin phi xa c ngt trong hm x l ngt.
3. BI TP
BI 1. Lp trnh h thng m ln sau 0.5 s, xut kt qu ra led, sinh vin phi s dng ngt timer. Hng dn: Sinh vin cn tnh ton gi tr cho thanh ghi PR v cu hnh Timer ph hp trc khi thit lp ngt.Chu k ngt ca timer c th tnh theo cng th sau:
Khung m chng trnh: #include<> void _ISR _T1Interrupt(void) { _T1IF = 0; } main()

{ _T1IP = ; TMR1 = 0; PR1 = 25000-1; T1CON = ; _T1IF = ; //Xoa co ngat _T1IE = ; // Cho phep ngat //your main code } BI 2. Vit chng trnh led dch phi mi khi nhn Switch 6. Hng dn: ngt Switch ni vi PORTD thuc loi ngt Change Notification (_CNInterrupt). Cc Switch S3, S4, S6 c ni vi cc ngt Change Notification CN15, CN19 v CN16. cho php ngt sinh ra t cc ngun ny, sinh vin cn bt hai bit: bit cho php ngt ca tng ngun c tin t _CNx, vi x = 15, 16, 19(_CN15IE, _CN16IE, _CN19IE) v bit cho php ngt Change Notification ton cc _CNIE. Tt cc cc ngt sinh ra t nhng ngun ny s dng chung cc bit iu khin ngt khc: _CNIF,_CNIP. BI 3. Vit chng trnh led dch phi mi khi nhn Switch 6 v dch tri khi nhn Switch 3.
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BI 5.
ADC
MC CH Bi thc hnh gip sinh vin lm quen vi khi nim ADC, tm hiu cu trc v cch cu hnh b ADC trn PIC 24F v xy dng cc ng dng lin quan n ADC trn board thc tp.
1. TNG QUAN V ADC TRN PIC 24F

Vi iu khin PIC24F gm mt b ADC c nhim v chuyn i tn hiu tng t sang d liu s 16-bit. B ADC gm 16 ng vo tng t t AN0 n AN15 m t nh Hnh 5-1.
Hnh 5-1. Cu trc bADC trn PIC 24F
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Trn board PIC Explorer 16, c hai tn hiu c th lm ng vo ca ADC l bin tr 10 K (ni vi AN5) v cm bin nhit TC1047A (ni vi AN4). a) Cc thanh ghi ca ADC trn PIC 24F Module ADC trn PIC 24F c 22 thanh ghi. Tt c cc thanh ghi c map vo vng nh d liu. i. Thanh ghi iu khin Module gm 6 thanh ghi iu khin v trng thi: AD1CON1, AD1CON2, AD1CON3: cc thanh ghi iu khin AD1CHS: thanh ghi la chn knh ADC AD1PCFG: thanh ghi cu hnh port ADC AD1CSSL: thanh ghi la chn ch scan ng vo ADC Cc thanh ghi AD1CON1, AD1CON2, AD1CON3 iu khin hot ng chung ca ADC: bt ADC, cu hnh xung chuyn i v ngun tham chiu, la chn ngun kch ly mu v chuyn i v cho php ngi dng iu khin chui ly mu/chuyn i. Thanh ghi AD1CHS cho php la chn ng no c ni vi b khuch i S/H, la chn b a hp v ngun tham chiu cho vic ly mu vi phn (differential sampling). Thanh ghi AD1PCFG cu hnh chn I/O l ng vo tng t hay s. Thanh ghi AD1CSSL la chn knh trong chui knh c scan. ii. B m kt qu Module ADC tch hp RAM 16 word d liu k hiu gi l ADC1BUF lu tr kt qu chuyn i. 16 v tr m c k hiu ADC1BUF0 ADC1BUFF. Cc v tr u c map vo vng nh d liu v c th nh a ch c lp nhau. Vng m kt qu khng cho php ghi d liu. Thanh ghi AD1CON1:
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Bit 15
14 13
1210 98
75
43 2
M t ADON: A/D Operating Mode bit 1: cho php ADC hot ng 0: tt ADC Khng c ngha ADSIDL: Stop in Idle Mode bit 1: tt module ADC khi CPU ch Sleep 0: cho php ADC hot ng khi CPU ch Sleep Khng c ngha FORM1:FORM0: Data Output Format bits 11: dng thp phn c du (sddd dddd dd00 0000) 10: dng thp phn khng du (dddd dddd dd00 0000) 01: s nguyn c du (ssss sssd dddd dddd) 00: s nguyn (0000 00dd dddd dddd) SSRC2:SSRC0: Conversion Trigger Source Select bits 111: b m ni kt qu trnh ly mu v bt u chuyn i (t ng) 110: cha c s dng 10x: cha c s dng 100: cha c s dng 011: Timer3 kt thc qu trnh ly mu v bt u qu trnh chuyn i 001: s thay i trng thi trn chn ngt ngoi INT0 kt thc qu trnh ly mu v bt u qu trnh chuyn i 000: vic xa bit SAMP kt thc qu trnh ly mu v bt u qu trnh chuyn i Khng c ngha ASAM: A/D Sample Auto-Start bit 1: giai on ly mu bt u t ng sau khi giai on chuyn i trc kt thc, bit SAMP c set t ng 0: giai on ly mu bt u khi bit SAMP c set SAMP: A/D Sample Enable bit 1: t nht mt b khuch i S/H (sample/hold) ang ly mu 0: B khuch i S/H ang gi mu DONE 1: qu trnh chuyn i kt thc 0: qu trnh chuyn i cha kt thc hoc cha bt u
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Thanh ghi AD1CON2:
Bit M t 1513 VCFG2:VCFG0: cu hnh in th tham chiu
12 11 10
98 7
6 52
Cha c s dng Khng c ngha CSCNA: thit lp ch scan ng vo cho b a hp A 1: bt ch scan 0: tt ch scan Khng c ngha BUFS: Buffer Fill Status bit 1: d liu ang c lm y ADC1BUF8-ADC1BUFF, ngi dng nn truy xut d liu t ADC1BUF0-ADC1BUF7 0: d liu ang c lm y ADC1BUF0-ADC1BUF7, ngi dng nn truy xut d liu t ADC1BUF8-ADC1BUFF Khng c ngha SMPI3:SMPI0: s lng chui ly mu/chuyn i trong mt ln sinh ngt 1111: ngt sau khi hon thnh 16 chui ly mu/chuyn i 1110: ngt sau khi hon thnh 15 chui ly mu/chuyn i 0001: ngt sau khi hon thnh 2 chui ly mu/chuyn i 0000: ngt sau khi hon thnh 1 chui ly mu/chuyn i BUFM: Buffer Mode Select bit 1: b m c chia thnh 2 b m 8 word: (ADC1BUF0 ADC1BUF7 v ADC1BUF8 ADC1BUFF)
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0: b m c cu hnh thnh mt b m 16 word (ADC1BUF0 ADC1BUFF) 0 ALTS: Alternate Input Sample Mode Select bit 1: Chn b a hp A cho mu u tin v thay i gia b a hp B v A trong nhng mu tip theo 0: lun lun la chn b a hp A Thanh ghi AD1CON3
M t ADRC: A/D Conversion Clock Source bit 1: ADC s dng xung t b RC ni 0: ADC s dng xung clock h thng 1413 Khng c ngha 128 SAMC4:SAMC0: Auto-Sample Time bits 1111: 31 TAD 1110: 30 TAD 0001: 1 TAD 0000: 0 TAD 70 ADCS7:ADCS0: A/D Conversion Clock Select bits 11111111: 128TCY 11111110: 127TCY 00000001: 2TCY 00000000: 1TCY
Bit 15
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Thanh ghi AD1CHS:
M t CH0NB: la chn cc m ca knh 0 cho b a hp B 1: cc m l AN1 0: cc m l VR1412 Khng c ngha 118 CH0SB3:CH0SB0: la chn cc dng ca knh 0 cho b a hp B 1111: cc dng l AN15 1114: cc dng l AN14 0001: cc dng l AN1 000: cc dng l AN0 7 CH0NA: la chn cc m ca knh 0 cho b a hp A 1: cc m l AN1 0: cc m l VR64 Khng c ngha 30 CH0SA3:CH0SA0: la chn cc dng ca knh 0 cho b a hp A 1111: cc dng l AN15 1114: cc dng l AN14 0001: cc dng l AN1 000: cc dng l AN0
Bit 15
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Thanh ghi AD1PCFG
Bit 150
M t PCFG15:PCFG0: Analog Input Pin Configuration Control bits 1: chn tng ng c cu hnh l ng vo Digital; c th c gi tr t port, cc ng vo b a hp c ni vi AVSS 0: chn tng ng c cu hnh l ng vo Analog; gi tr c t port khng c ngha, ADC ly mu trn cc chn ny Thanh ghi AD1CSSL
Bit 150
M t CSSL15:CSSL0: A/D Input Channel Scan Selection bits 1: knh ANxx tng ng c a vo chui scan b a hp A 0: knh ANxx tng ng b b qua khi scan
b) Cu hnh ADC Sinh vin nn tun th cc bc sau cu hnh ADC trn PIC 24F i. Cu hnh module ADC La chn ngun in th tham chiu ph hp vi khong in th ca tn hiu analog
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ii.
La chn xung clock chuyn i tng thch vi tc d liu Thit lp thng s cho giai on ly mu Xc nh ng vo kt ni vi knh S/H La chn chui ly mu/chuyn i mong mun Cu hnh b m lu d liu La chn chu k sinh ngt Bt module ADC
Cu hnh ngt (nu c) Xa c ngt AD1IF Thit lp mc u tin Sinh vin c th tham kho thm ti liu 24F ADC Reference Chapter 39705a trong PIC24F Family Reference Manual
2. CHNG TRNH MU
Lp trnh iu khin led dch bng bin tr s dng ngt ADC.
#include <p24fj128ga010.h> #define AN_VOLT_PIN AD1PCFGbits.PCFG5//voltage input on AN5 #define ADC_VOLTAGE 5 void adc_init() { AD1CON1 = 0x80E4; AD1CON2 = 0; AD1CON3 = 0x1F05; AD1CHS = ADC_VOLTAGE; AN_VOLT_PIN = 0; AD1CSSL = 0; _AD1IE = 1; _AD1IP = 4; _AD1IF = 0; } void _ISR _ADC1Interrupt(void) { int a; a= ADC1BUF0 >>7; PORTA = (0x80 >> a); _AD1IF = 0; } main() { TRISA = 0xff00; adc_init(); while(1);
3. BI TP
BI 1. Lp trnh h thng c gi tr in th ng ra ca bin tr v hin th kt qu ra led s dng ngt ADC. Hng dn:ga tr thc ca in th ng ra ca bin tr c tnh theo cng thc: V = ADC1BUF * (Vref+ - Vref-)/1024 BI 2. Lp trnh h thng c gi tr ti ng ra ca cm bin nhit v hin th kt qu trn led. Hng dn:cm bin nhit trn board PIC Explorer 16 l TC1047A, ng ra ca cm bin c ni vi chn AN4. Mi lin h gia in th ng ra v nhit mi trng c biu din theo hm sau: Vout = 0.01T + 0.5 (V) Vi T l nhit mi trng n v 0C. T = 100Vout 50 (1) Gi tr Vout c th tnh c t gi tr c c t b m ca ADC theo cng thc: Vout = ADC1BUF * (Vref+ - Vref-)/1024 (2) Thay (2) vo (1), ta c c ng thc lin h gia T v gi tr c c t b m ADC:
( )
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BI 6.
GIAO TIP LCD
MC CH Bi thc hnh gip sinh vin lm quen vi b iu khin trn LCD v giao tip Parallel Master Port (PMP) trn PIC 24F.
1. GII THIU LCD TRN BOARD PIC EXPLORER 16

Thng thng, board PIC Explorer 16 c tch hp sn mt mn hnh 2 dng x 16 k t v module LCD tng thch vi nhng b iu khin HD44780 theo chun cng nghip.
Hnh 6-1. Kt ni cc module LCD trn board PIC Explorer 16 K t c hin th trn mn hnh c sinh ra bi mt bng sinh k t c tch hp bn trong ROM ca b iu khin. Bng sinh k t c th sinh tp k t ASCII v mt s k t ting Nht. Ngoi ra, ngi dng c th t nh ngha thm mt s k t (ti a 8 k t ty loi).
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Hnh 6-2. Bng sinh k t c s dng bi cc b iu khin tng thch HD44780 Cc lcd c b iu khin tng thch HD44780 ch dng hai thanh ghi (c th nh a ch c lp): mt cho d liu v mt cho lnh. Tp lnh sau y c th s dng thit lp v iu khin hin th trn lcd: M lnh Lnh
RS R/ W DB DB DB DB DB DB DB DB 7 6 5 4 3 2 1 0
Miu t Xa mn hnh v a con tr v u a con tr v u. Ni dung trong DDRAM
Thi gian thc thi 1.64ms 1.64 ms
Clear display Cursor home
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 1
1 *
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Entry mode set
I/D
Display On/Off control
Cursor/ display shift
S/ C
R/ L
Function set
DL
Set CGRAM address
a ch CGRAM
Set DDRAM address Read busyag and address counter Write to CGRAM or DDRAM Read from
a ch DDRAM
BF
a ch CGRAM / DDRAM
1 1
0 1
D liu ghi D liu c
khng i. Thit lp hng di chuyn (I/D) con tr v la chn ch dch chuyn (S). Ni dung trong DDRAM khng i. Bt/tt hin th (D), bt/tt con tr (C), nhp nhy con tr (B) Thit lp con tr di chuyn hoc hin th di chuyn (S/C) v chn hng di chuyn (R/L) Thit lp chiu di d liu (DL), s dng hin th (N), font ch (F) Thit lp a ch CGRAM, CGRAM trao i d liu sau thit lp ny Thit lp a ch DDRAM, DDRAM trao i d liu sau thit lp ny. BF = 1 lnh ang c thc thi. Ni dung b m a ch ca CGRAM/DRAM. Ghi d liu vo CGRAM hay DDRAM c d liu t
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40 us
40 us
40 us
40 us
40 us
40 us
0 us
40 us 40 us
CGRAM or DDRAM Bit I/D S D C B S/C R/L DL N F BF
CGRAM hay DDRAM Bng 7. Tp lnh HD44780 Setting/Status 0 = gim v tr con tr 1 = tng v tr con tr 0 = khng di chuyn hin th 1 = di chuyn hin th 0 = khng hin th 1 = hin th 0 = khng hin th con tr 1 = hin th con tr 0 = khng nhp nhy con tr 1 = nhp nhy con tr 0 = dch chuyn con tr 1 = dch chuyn hin th 0 = dch chuyn tri 1 = dch chuyn phi 0 = d liu 4 bit 1 = d liu 8 bit 0 = 1 dng 1 = 2 dng 0 = font 5x7 1 = font 5x10 0 = b iu khin sn sng nhn 1 = b x l ang x l lnh lnh Bng 8. Bit lnh HD44780
2. GIAO TIP PMP

a) Gii thiu PMP c s dng giao tip vi cc thit b ngoi vi song song: ADC, b m RAM, cc thit b giao tip ISA, LCD, a cng v th CompactFlash. c tnh ca PMP: D liu hai chiu 8 hoc 16 bit 16 ng a ch 6 tn hiu iu khin: o Enable o Address Latch o Read o Write o V 2 tn hiu Chip Select Tc v c v ghi vi PMP c th cu hnh ph hp vi thit b v m bo yu cu v tc ca thit b. b) Cu hnh PMP s dng cho LCD Cng nh cc giao tip ngoi vi khc ca PIC 24F, PMP cha nhng thanh ghi cu hnh cho vic trao i d liu: PMCON, PMMODE, PMADDR, PMSTAT, PMPEN v PADCFG. Sinh vin cn tham kho ti liu 24F PMP Reference
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Chapter 39713a trong PIC24F Family Reference Manual hiu cc cu trc v chc nng ca cc thanh ghi ny. Sinh vin c th cu hnh PMP theo ngh sau s dng PMP trong giao tip vi LCD: Cho php PMP Khng a hp a ch v d liu Cho php tn hiu Enable Cho php tn hiu Read Tn hiu Enable tch cc mc cao Tn hiu Read tch cc mc cao, tn hiu Write tch cc mc thp Ch Master vi tn hiu Read v Write trn cng mt chn (RD5) Bus d liu 8 bit Ch cn mt tn hiu a ch nn ch c PMA0 v PMA1 c s dng. LCD l thit b p ng chm nn ngi dng cn thm cc trng thi ch trong mi chui c/ghi. Khi s dng PMP, ngi dng c th s dng s trng thi ch ti a: Ch d liu n nh trc khi c ghi: 4 Tcy Gia hai tn hiu R/W v Enable: 15 Tcy Ch d liu n nh sau tn hiu Enable tch cc: 4 Tcy Khi to PMP s dng cho LCD: PMCON = 0x83BF; PMMODE = 0x3FF; PMAEN = 0x0001; Sau nhng cu lnh trn, ngi s dng c th giao tip vi module LCD v cu hnh LCD theo tiu chun nh sn xut. Vic cu hnh LCD phi tha mn yu cu thi gian. Sinh vin coi li bng 7 bit thm chi tit yu cu thi gian khi cu hnh LCD.Ch :Khng th cu hnh LCD trong khong thi gian nh hn 30 ms k t khi LCD c cp ngun. n gin, sinh vin c th s dng timer ch nh thi to tr trong chui cu hnh LCD. Trc khi ghi d liu vo module LCD, ngi lp trnh cn kim tra bit Busy (Busy Flag) ca module LCD thng qua cc bc sau: kim tra bit Busy ca PMP, c d liu t PMP xa d liu trn bus d liu PMP, kim tra bit Busy ca PMP ln 2, c d liu t PMP ln 2. Bit Busy chnh l bit th 7 ca d liu va c c.
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a lnh hay d liu vo module LCD, ngi dng phi la chn thanh ghi lnh hay d liu (thit lp a ch PMA0 = RS = 0 cho lnh v PMA0 = RS = 1 cho d liu) v a lnh cn thc thi hay d liu vo b m d liu PMP. V d:
PMADDR = 0; // select the command register (ADDR = 0) PMDIN1 = 0b00111000; // function set: 8-bit interface, 2 lines, 5x7
3. BI TP
BI 1. Vit chng trnh hin th mt chui k t ln LCD Chng trnh mu:
#include <p24fj128ga010.h> #include <stdlib.h> #define LCDDATA 1 // RS = 1 ; access data register #define LCDCMD 0 // RS = 0 ; access command register #define PMDATA PMDIN1 // PMP data buffer #define LCDbusy() LCDread(LCDCMD) & 0x80 #define LCDaddr() LCDread(LCDCMD) & 0x7F #define getLCD() LCDread(LCDDATA) #define putLCD(d) LCDwrite(LCDDATA,(d)) #define LCDcmd(c) LCDwrite(LCDCMD,(c)) #define LCDhome() LCDwrite(LCDCMD,2) #define LCDclr() LCDwrite(LCDCMD,1) void lcd_init() { // PMP initialization PMCON = 0x83BF; // Enable the PMP, long waits PMMODE = 0x3FF; // Master Mode 1 PMAEN = 0x0001; // PMA0 enabled // init TMR1 T1CON = 0x8030; // Fosc/2, prescaled 1:256, 64us/tick // wait for >30ms TMR1 = 0; while( TMR1<500); // 500 x 64us = 32ms PMADDR = LCDCMD; // select the command register (ADDR = 0) PMDATA = 0b00111000; // function set: 8-bit interface, 2 lines, 5x7 TMR1 = 0; while( TMR1<1); // 1 x 64us = 64us PMDATA = 0b00001100; // display ON, cursor off, blink off TMR1 = 0; while( TMR1<1); // 1 x 64us = 64us PMDATA = 0b00000001; // clear display TMR1 = 0; while( TMR1<25); // 25 x 64us = 1.6ms PMDATA = 0b00000110; // increment cursor, no shift TMR1 = 0; while( TMR1<25); // 25 x 16us = 1.6ms } char LCDread( int addr) {
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int dummy; while( PMMODEbits.BUSY); PMADDR = addr; dummy = PMDATA; while( PMMODEbits.BUSY); return( PMDATA); } // LCDread void LCDwrite( int addr, char c) { while( LCDbusy()); while( PMMODEbits.BUSY); PMADDR = addr; PMDATA = c; } // LCDwrite void putsLCD( char *s) { while(*s) putLCD( *s++); } //putsLCD main( void) { // initializations lcd_init(); // put a title on the first line putsLCD("test lcd"); } // main
// wait for PMP to complete previous commands // select the command address // initiate a read cycle, dummy read // wait for PMP to complete the sequence // read the status register
// wait for PMP to be available
BI 2. Lp trnh h thng c gi tr in th ti ng ra trn bin tr v hin th ln LCD di dng s thp phn c hai ch s phn thp phn s dng ngt ADC. BI 3. Lp trnh h thng hin th nhit mi trng trn LCD dng thp phn c 2 ch s phn thp phn s dng ngt ADC.
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BI 7.
GIAO TIP UART
MC CH Bi thc hnh gip sinh vin tip cn khi nim UART,cch cu hnh UART viPIC 24F v xy dng cc ng dng iu khin lin quan n cng giao tip RS232.
1. KHI NIM UART

UART l vit tt ca thut ng Universal asynchronous receiver/transmitter (b truyn nhn ni tip bt ng b). Khi nim UART thng ch cc thit b phn cng, khng phi l mt chun giao tip. Trong truyn thng ni tip, d liu c gi i tng bit. B truyn s chuyn cc byte d liu thnh cc bit ni tip s dng thanh ghi dch vo - song song - ra - ni tip. B nhn s chuyn cc bit ny thnh cc byte d liu s dng thanh ghi dch vo - ni tip - ra - song song. Truyn thng bt ng b c ngha l d liu c truyn theo khung chun v khng ph thuc vo tn hiu nh thi (xung Clock). Cc khi nim lin quan giao tip UART: Tc baud: s bit truyn trong 1 s. Frame: bao gm cc qui nh s bit trong mi ln truyn, cc bit bo (Start Bit, Stop Bit), cc bit kim tra Parity. Start bit:l bit u tin c truyn trong khung, bit ny ch bo cho thit b khi mt gi d liu sp ti. Data: d liu cn truyn i, s bit data khng bt buc l 8, LSB s c truyn trc. Parity: kim tra d liu truyn i. Stop bit: bit ch bo gi d liu c truyn xong.
Hnh 7-1. Mt khung d liu UART tiu biu
2. MODULE UART TRN PIC 24F

a) Gii thiu Module UART l mt trong nhng module giao tip ni tip trn PIC 24F. Module ny c th c dng trao i d liu vi cc thit b ngoi vi hay PC
thng qua cc giao thc RS232, RS485, LIN 1.2 hay IrDA. Module UART h tr giao thc bt tay phn cng v tch hp b m ha v gii m IrDA. Module UART trn PIC 24F cha mt FIFO cho mi chiu truyn nhn.
Hnh 7-2. S khi n gin module UART trn PIC 24F b) Cc thanh ghi iu khin i. Thanh ghi UxMODE
Hnh 7-3. Thanh ghi ch UARTx

Bit 15 UARTEN: UARTx Enable bit 1 = cho php UARTx, cc chn UARTx c iu khin bi UARTx theo nh ngha t cc bit iu khin UEN<1:0> v UTXEN 0 = tt UARTx, cc chn UARTx c iu khin bi cc thanh ghi PORT, LAT v TRIS UFRZ: Freeze in Debug Mode bit 1 = module khng hot ng trong ch debug 0 = module hot ng trong ch debug
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Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9-8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2-1
Bit 0
USIDL: Stop in Idle Mode bit 1 = module khng hot ng khi CPU idle 0 = Module hot ng khi CPU idle IREN: IrDA Encoder and Decoder Enable bit 1 = cho php b m ha v gii m IrDA 0 = khng cho php b m ha v gii m IrDA RTSMD: Mode Selection for Pin bit 1 = chn hot ng ch bn cng 0 = chn hot ng trong ch iu khin ALTIO: UARTx Alternate I/O Selection bit 1 = UARTx s dng cc chn UxATX v UxARX 0 = UARTx s dng cc chn UxTX v UxRX UEN<1:0>: UARTx Enable bits 11 = UxTX, UxRX v BCLKx c cho php v s dng, chn c iu khin bi cht 10 = UxTX, UxRX, v c cho php v s dng 01 = UxTX, UxRX and c cho php v s dng, c iu khin bi cc cht 00 = UxTX v UxRX c cho php v s dng, cc chn , v BCLKx c iu khin bi cc cht WAKE: Enable Wake-up on Start bit Detect During Sleep Mode bit 1 = cho php ch WAKE 0 = khng cho php ch WAKE LPBACK: UARTx Loopback Mode Select bit 1 = bt ch loopback 0 = tt ch loopback ABAUD: Auto-Baud Enable bit 1 = cho php xc nh tc Baud ti k t tip theo, bit ny c xa bi phn cng khi kt thc truyn d liu 0 = khng cho php xc nh tc Baud ti k t tip theo RXINV: Receive Polarity Inversion bit 1 = Trng thi Idle ca chn UxRX l 0 0 = Trng thi Idle ca chn UxRX l 1 BRGH: High Baud Rate Select bit 1 = tc cao 0 = tc thp PDSEL<1:0>: Parity and Data Selection bits 11 = 9-bit data, no parity 10 = 8-bit data, odd parity 01 = 8-bit data, even parity 00 = 8-bit data, no parity STSEL: Stop Selection bit 1 = 2 Stop bits 0 = 1 Stop bit
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ii.
thanh ghi UxSTA
Bit 15, 13
Bit 14
Bit 12 Bit 11
Bit 10
Bit 9
Bit 8
Bit 7, 6
Hnh 7-4. Thanh ghi trng thi v iu khin UTXISEL<1:0> Transmission Interrupt Mode Selection bits 11 = Reserved 10 = ngt sinh ra khi mt k t c chuyn ti thanh ghi dch Transmit 01 = ngt sinh ra khi vic truyn k t kt thc 00 = ngt sinh ra khi c bt c k t no c chuyn ti thanh ghi dch Transmit (iu ny c ngha c t nht mt ch trng trong b m gi) UTXINV: Transmit Polarity Inversion bit IREN = 0: 1 = UxTX Idle l 1 0 = UxTX Idle l 0 IREN = 1: 1 = IrDA encoded UxTX Idle state is 1 0 = IrDA encoded UxTX Idle state is 0 Khng c s dng UTXBRK: Transmit Break bit 1 = Chn UxTX c a xung thp bt chp trng thi b truyn 0 = khng cho php truyn k t break UTXEN: Transmit Enable bit 1 = cho php b truyn, chn UxTX c iu khin bi UARTx (nu UARTEN = 1) 0 = khng cho php b truyn, b m b reset, chn UxTX c iu khin bi thanh ghi PORT UTXBF: Transmit Buffer Full Status bit (read-only) 1 = b m y 0 = b m cha y, c th a thm k t vo b m TRMT: Transmit Shift Register is Empty bit (read-only) 1 = thanh ghi dch v b m b truyn rng 0 = thanh ghi dch khng rng URXISEL<1:0>: Receive Interrupt Mode Selection bits 11 = c ngt c thit lp khi b m y 10 = c ngt c thit lp khi b m y
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Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0x = c ngt c thit lp khi nhn c mt k t ADDEN: Address Character Detect bit (bit 8 of received data = 1) 1= bt ch Address Detect, nu truyn 9 bit, bit ny khng c ngha 0 = khng bt ch Address Detect RIDLE: Receiver Idle bit (read-only) 1 = b nhn ang trong trng thi Idle 0 = d liu ang c nhn PERR: Parity Error Status bit (read-only) 1 = Li Parity 0 = Khng c li Parity FERR: Framing Error Status bit (read-only) 1 = li frame 0 = frame khng c li OERR: Receive Buffer Overrun Error Status bit (clear/read-only) 1 = b m nhn b trn 0 = b m nhn khng b trn Nu bit ny b xa sau khi thit lp, b m nhn v thanh ghi dch ca b nhn s b xa v trng thi rng URXDA: Receive Buffer Data Available bit (read-only) 1 = b m nhn c d liu 0 = b m nhn khng c d liu thanh ghi UxRXREG
iii.
iv.
Hnh 7-5. Thanh ghi cha d liu nhn c thanh ghi UxTXREG
Hnh 7-6. Thanh ghi cha d liu gi i

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v.
thanh ghi UxBRG
Bit 15 0
Hnh 7-7. Thanh ghi tc Baud BRG<15:0>: Baud Rate Divisor bits
c) B to tc Baud Module UART c tch hp mt b to tc Baud 16-bit. Thanh ghi UxBRG iu khin mt b nh thi 16 bit chy t do. Cng thc tnh tc Baud: Vi BRGH = 0, ( Vi BRGH = 1, ( ) Trong : UxBRG l gi tr thanh ghi do ngi dng thit lp, Fcy l tn s lnh. d) Cu hnh UART Module UART s dng chun nh dng Non-Return-to-Zero (NRZ) (1 start bit, 8 hay 9 bit d liu v 1 hay 2 bit stop). Parity c h tr bi phn cng v c th thit lp l parity chn, l hay khng c parity. nh dng ph bin nht l 8 bit, no parity v mt stop bit (k hiu l 8,N,1). S lng bit data, stop bit v parity c nh ngha trong cc bit PDSEL[1:0] v STSEL. Mt b sinh tc Baud on-chip c s dng to tc Baud da vo clock h thng. B nhn v b truyn d liu c th hot ng c lp nhau nhng phi c chung nh dng d liu. Cho php module UART: module UART c cho php thng qua bit UARTEN v bit UTXEN. Mt khi module UART c bt, cc chn UxTX, UxRX c cu hnh thnh cc chn output v input bt chp trng thi ca cc bit trong thanh ghi TRIS. Khi khng truyn d liu, UxTX mc logic 1. )
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Tt module UART: module UART c th tt bng cch xa bit UARTEN. y l trng thi mc nh sau khi reset h thng. Nu UART b tt, cc chn UART s hot ng nh chn bnh thng c iu khin bi thanh ghi PORT v TRIS. Tt UART s lm cho b m b xa. Tt c cc k t truyn ti b m s b mt. S dng chn thay th: mt vi dng PIC 24F c th s dng cc chn thay th cho cc chn UART khi cc chn UART c s dng vo mc ch khc. e) B truyn UART B phn ch yu ca b truyn l thanh ghi dch UxTSR. Thanh ghi ny nhn d liu thanh ghi UxTXREG. Thanh ghi UxTSR s khng nhn d liu t UxTXREG cho n khi stop bit ca d liu trc c truyn i. Vic truyn d liu c cho php bng cch bt bit UTXEN sau khi d liu c gi xung thanh ghi UxTXREG v b to tc Baud cp xung. Xa bit UTXEN trong khi truyn s kt thc truyn d liu v reset b truyn, chn UxTX ng thi c trng thi tr khng cao. B truyn c th sinh ra ngt. Cc bit iu khin UTXISEL<1:0> xc nh thi im sinh ra ngt. UTXISEL<1:0> = 00: c ngt UxTXIF c set khi mt k t c chuyn ti thanh ghi dch UxTSR. iu ny c ngha l b m c t nht mt ch trng nhn thm d liu. UTXISEL<1:0> = 01: UxTXIF c set khi k t cui cng c chuyn ra khi thanh ghi dch UxTSR. iu ny c ngha l tt c d liu c truyn. UTXISEL<1:0> = 10: UxTXIF c set khi k t c chuyn n thanh ghi dch UxTSR v b m rng. Thit lp b truyn UART: Khi to thanh ghi UxBRG c tc Baud mong mun Thit lp s data bit, stop bit v parity thng qua cc bit PDSEL<1:0> v STSEL Trong trng hp s dng ngt, sinh vin cn thit lp cc bit iu khin ngt (_UxTXIE, _UxTXIP) v la chn ch ngt ca UART thng qua cc bit UTXISEL[1:0]. Bt module UART Cho php truyn d liu bng cch bt bit UTXEN
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Truyn d liu cn gi xung thanh ghi UxTXREG. kim tra b truyn c sn sng nhn d liu hay khng, sinh vin c th kim tra bit UTXBF.
Hnh 7-8. Truyn d liu qua UART f) B nhn UART B phn chnh trong b nhn UART l thanh ghi dch UxRSR. D liu c ly tng bit t chn UxRX v c gi n b khi phc d liu. B khi phc d liu hot ng tn s gp 16 ln tc Baud. Sau khi nhn c stop bit, d liu hon chnh s c gi n FIFO (nu FIFO rng). B m d liu nhn l mt FIFO c kch thc 4 word x 9 bit. Thanh ghi UxRXREG c th dng truy xut d liu t ng ra ca FIFO. Khi mt li xy ra trong qu trnh nhn d liu, cc bit bo li s c v sinh ra ngt nu c cho php. B nhn d liu c th sinh ra ngt. Cc bit URXISEL[1:0] xc nh thi im sinh ra ngt: URXISEL[1:0] = 00 hay 01: ngt sinh ra mi khi c mt word c truyn t thanh ghi dch UxRSR n b m. URXISEL[1:0] = 10: ngt sinh ra khi b m c 3 hoc 4 word. URXISEL[1:0] = 11: ngt sinh ra khi b m c 4 word. Thit lp b nhn UART: Khi to thanh ghi UxBRG c tc Baud mong mun Thit lp s bit data, stop bit v parity thng qua cc bit PDSEL[1:0] v STSEL Trong trng hp s dng ngt, sinh vin cn thit lp cc bit iu khin ngt (_UxRXIE, _UxRXIP) v cc bit chn ch ngt ca b nhn URXISEL[1:0]. Cho php module UART
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Nu khng s dng ngt, sinh vin c th kim tra bit URXDA bit b nhn d liu hay cha. g) S dng UART vi 9 bit data Kiu trao i d liu ny c th c dng trong mi trng a b x l.
3. BI TP
BI 1. BI 2. BI 3. Lp trnh h thng c th gi mt k t qua cng RS232. Lp trnh h thng c th nhn mt chui k t qua cng RS232. Lp trnh h thng gi gi tr nhit qua cng RS232.
Trang 53
PHC LC
S DNG HYPER TERMINAL Hyper Terminal l chng trnh cho php my tnh trao i d liu thng qua cng giao tip ni tip. Trong bi thc hnh ny, sinh vin phi s dng Hyper Terminal. Bc 1. Vo Start All Programs Accessories Communications Hyper Terminal Bc 2. t tn kt ni
Bc 3. Chn cng COM
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Bc 4. Thit lp thng s cng COM
Bc 5. Thit lp hin th Vao file Properties tab Settings ASCII Setup
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nh du Echo typed characters locally
Trang 56

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