Mc lc

CHNG I GiI THIU V CM BIN, CM BIN QUANG O Cng nh sng Trang 1.1. Gii thiu chung v cm bin 1.2. Cm bin quang (T bo quang dn) Chng II tng quan v PSoC 2.1. Gii thiu v chp PsoC 2.2 . Gii thiu v chip PSoC CY8C27443-24PXI 2.2.1. Thng s ca CY8C27443-24PXI 2.2.2. Cc ch a ch trong PsoC 2.2.3. Ngt v b iu khin ngt 2.2.4. Cc cng vo ra a chc nng 2.2.5. Cc b to dao ng 2.2.6. Cc khi PSoC s 2.2.7 . H thng khi PSoC tng t. 2.3. Gii thiu chung v PSoC Designer. 2.4. Cc bc thit k v lp trnh trong PSoC Designer. Chng II Xy dng h o, IU KHIN Cng nh sng s dng chip PSOC CY8C27443-24PXI 3.1. S khi chc nng ca h thng. 81 10 11 11 15 17 21 29 33 37 43 45 3 7

3.2 .S nguyn l v chc nng ca cc thnh phn. 3.2.1. S mch ngun 3.2.2. S mch nh pha Dimmer 3.2.3. S mch cng sut 3.2.4. Modul giao tip my tnh 3.2.5. chp Psoc CY8C27443-24PXI 3.2.6. Cm bin quang (Quang tr) 3.3. Lu thut ton

81 81 82 83 84 86 87 90

CHNG I GiI THIU V CM BIN, CM BIN QUANG O Cng nh sng

1.1.Gii thiu chung v cm bin. Cm bin l cc phn t nhy cm dng bin i cc i lng o lng, kim tra hay iu khin t dng ny sang dng khc thun tin hn cho vic tc ng ca cc phn t khc. Cm bin l mt thit b chu tc ng ca i lng cn o ma khng c tnh cht in v cho mt c trng mang bn cht in (nh in tch, in p, dng in, tr khng) k hiu l s c s = F(m). Cm bin thng dng khu o lng v kim tra. Cc loi cm bin c s dng rng ri trong t ng ha cc qu trnh sn xut v iu khin t ng cc h thng khc nhau. Chng c chc nng bin i s thay i lin tc cc i lng u vo (i lng o lng - kim tra, l cc i lng khng in no thnh s thay i ca cc i lng u ra l i lng in, v d: in tr, in dung, in khng, dng in, tn s, in p ri, gc pha,...

Cn c theo dng i lng u vo ngi ta phn ra cc loi cm bin nh: cm bin chuyn dch thng, chuyn dch gc quay, tc , gia tc, m men quay, nhit , p sut, quang, bc x,... 1.1.1. Cc thng s c bn ca cm bin 1.1.1.1. nhy S=YX X: gia s i lng u vo.Vi: + Y: gia s i lng u ra.+ Trong thc t cn s dng nhy tng i: S0= Vi: Y l i lng ra. X l i lng vo. Cm bin c th l tuyn tnh nu S0=const hoc l phi tuyn nu S0= var. Cm bin phi tuyn c nhy ph thuc vo gi tr i lng vo (X). 1.1.1.2. Sai s S ph thuc ca i lng ra Y vo i lng u vo X gi l c tnh vo ra ca cm bin. S sai khc gia c tnh vo ra thc vi c tnh chun (c tnh tnh ton hay c tnh cho trong l lch) c nh gi bng sai s. Phn lm hai loi sai s + Sai s tuyt i X=X'#X X': gi tr o c; X: gi tr thc. + Sai s tng i a=XX Cc nguyn nhn nh hng ti sai s C nhiu nguyn nhn khch quan v ch quan nh hng ti sai s, trong thc t ngi ta a ra cc tiu chun v cc iu kin k thut hn ch mc nh hng ny trong phm vi cho php.

Sai s gi tr nh mc do yu t ca bn ngoi gi l sai s c bn. Nu yu t ca bn ngoi vt ra khi gii hn nh mc th xut hin sai s ph. gim sai s ph phi gim nhy ca cm bin vi yu t ngoi hoc hn ch nh hng ca chng bng mn chn hay mi trng khc. 1.1.2. Cc yu cu ca cm bin Mun c nhy cao, sai s nh, cm bin cn c cc tnh cht sau: + C di thay i i lng vo cn thit. + Thch ng v thun tin vi s o lng, kim tra. + nh hng t nht n i lng u vo. + C qun tnh nh. Hin nay c rt nhiu loi cm bin, chng lm vic theo nhiu nguyn l khc nhau, do vy kt cu ca cm bin rt a dng v phong ph. Bng 7-1 l nguyn l lm vic v lnh vc ca cm bin cm ng, l loi ph bin trong t ng ha v iu khin t ng. 1.1.3. Phn loi cm bin C th phn cc cm bin lm hai nhm chnh: l cm bin tham s (th ng) v cm bin pht (ch ng hay tch cc). * Nhm pht bao gm cc loi cm bin s dng hiu ng cm ng in t, hiu ng in p, hiu ng Holl v s xut hin sc in ng ca cp nhit ngu, t bo quang in. + Hiu ng cm ng in t: trong mt dy dn chuyn ng trong mt t trng khng i s xut hin mt sc in ng t l vi t thng ct ngang dy trong mt n v thi gian, ngha l t l vi tc dch chuyn ca dy dn. Hiu ng cm ng in t c ng dng xc nh tc dch chuyn ca vt thng qua vic o sc in ng cm ng. + Hiu ng quang pht x in t: l hin tng cc in t c gii phng thot ra khi vt liu to thnh dng c thu li di tc dng ca in trng.

Hiu ng quang in trong cht bn dn: l hin tng khi mt chuyn

tip P-N c chiu sng s pht sinh ra cc cp in t-l trng, chng chuyn ng di tc dng ca in trng chuyn tip lm thay i hiu in th gia hai u chuyn tip. + Hiu ng Holl: trong vt liu (thng l bn dn) dng tm mng c dng in chy qua t trong t trng B c phng to thnh mt gc vi dng in I s xut hin mt hiu in th U theo hng vung gc vi B v I. Hiu ng Holl c ng dng xc nh v tr ca mt vt chuyn ng. Vt s c ghp ni c hc vi mt thanh nam chm, mi thi im v tr ca thanh nam chm xc nh gi tr ca t trng v gc lch tng ng vi tm bn dn mng lm trung gian. Hiu in th o c gia hai cnh tm bn dn trong trng hp ny (gin tip) l hm ph thuc v tr ca vt trong khng gian.

Hnh 1 Cm bin loi ny l cm bin tch cc v trong trng hp ny ngun ca dng in I (ch khng phi i lng cn o) cung cp nng lng lin quan n tn hiu o. + Hiu ng in p: khi tc dng lc c hc ln mt vt lm bng vt liu p in (nh thch anh) s gy nn bin dng ca vt v lm xut hin lng in tch bng nhau nhng tri du nhau trn cc mt i din ca vt (l hiu ng in p). Hiu ng ny c ng dng xc nh lc hoc cc i lng gy nn lc

tc dng vo vt liu p in (nh p sut, gia tc,...) thng qua vic o in p trn hai bn cc t in. Ngoi ra cn cm bin nhit in, cm bin ha in,... * Cm bin tham s (th ng): thng c ch to t nhng tr khng c mt trong cc thng s ch yu nhy vi i lng cn o. Mt mt gi tr ca tr khng ph thuc vo kch thc hnh hc ca mu, nhng mt khc n cn ph thuc vo tnh cht in ca vt liu nh: in tr sut, t thm, hng s in mi. V vy gi tr ca tr khng thay i di tc dng ca i lng o nh hng ring bit n tnh cht hnh hc, tnh cht in hoc ng thi nh hng c hai. Thng s hnh hc hoc kch thc ca tr khng c th thay i nu cm bin c phn t chuyn ng hoc phn t bin dng. + Trng hp khi c phn t ng th mi v tr ca phn t s tng ng vi mt gi tr tr khng, o tr khng s xc nh c v tr i tng. y l nguyn l nhiu cm bin nh cm bin v tr, cm bin dch chuyn. + Trng hp cm bin c phn t bin dng, th s bin dng gy nn bi lc hoc cc i lng dn n lc (p sut, gia tc) tc dng trc tip hoc gin tip ln cm bin lm thay i tr khng. S thay i tr khng lin quan n lc tc ng ln cu trc, ngha l tc ng ca i lng cn o c bin i thnh tn hiu in (hiu ng p tr). Tr khng ca cm bin th ng v s thay i ca tr khng di tc dng ca i lng cn o ch c th xc nh c khi cm bin l mt thnh phn ca mch in. Trong thc t ty tng trng hp c th m ngi ta chn mch o thch hp vi cm bin 1.2. Cm bin quang (T bo quang dn) Cc t bo quang dn l mt trong nhng cm bin quang c nhy cao. C s vt l ca t bo quang dn l hin tng quang dn do kt qu ca hiu ng

quang in ni (hin tng gii phng ht ti in trong vt liu di tc dng ca nh sng lm tng dn in ca vt liu). 1.2.1.Vt liu ch to cm bin Cm bin quang thng c ch to bng cc cht bn dn a tinh th ng nht hoc n tinh th, bn dn ring hoc bn dn pha tp, v d nh: a tinh th :CdS, CdSe, CdTe, PbS, PbSe, PbTe. n tinh th:Ge, Si tinh khit hoc pha tp Au, Cu, Sb, In, SbIn, AsIn,PIn, CdHgTe. Vng ph lm vic ca cc vt liu ny khc nhau. 1.2.2. Cc c trng - in tr: gi tr in tr ti Rc0 ph thuc vo dng hnh hc, kch thc, nhit v bn cht l ha ca vt liu quang dn. in tr Rc ca cm bin khi b chiu sng gim rt nhanh khi ri tng ln. S ph thuc ca in tr vo thng lng nh sng khng tuyn tnh, tuy nhin c th tuyn tnh ha bng cch s dng mt in tr mc song song vi t bo quang dn. - nhy: dn ca t bo quang dn l tng ca dn trong ti v dn khi chiu sng. nhy ph l hm ca nhit ngun sng: khi nhit tng th nhy ph tng ln. T bo quang dn c ng dng nhiu bi chng c t l chuyn i tnh v nhy cao cho php n gin ha trong vic ng dng (v d iu khin cc rle hnh 7-14). Nhc im chnh ca t bo quang dn l: Hi p ph thuc mt cch khng tuyn tnh vo thng lng. Thi gian hi p ln. Cc c trng khng n nh (gi ha).

- nhy ph thuc vo nhit - Mt s loi i hi phi lm ngui.

Ngi ta khng dng t bo quang dn xc nh chnh xc thng lng. Thng thng chng c s dng phn bit mc sng khc nhau (trng thi ti- sng hoc xung nh sng). Thc t th t bo quang dn thng ng dng :Thu tn hiu quang dng bin i xung quang thnh xung in. S ngt qung ca xung nh sng chiu ln t bo quang dn s c phn nh trung thc qua xung in ca mch o, ng dn o tc quay ca a hoc m vt.

n v o cng nh sng: Lux (k hiu: lx) l n v ri trong SI. N c s dng trong trc quang hc nh gi cng nh sng cm nhn c. y l mt n v dn xut trong SI, ngha l n c nh ngha t cc n v "c bn" hn. C th, do ri bng quang thng trn din tch: 1 lx = 1 lm/m2 n v o quang thng trong SI, lumen, li l mt n v dn xut nn: 1 lx = 1 cd sr / m2 Mt vn phng sng sa c ri khong 400 lux.

Chng II tng quan v PSoC 2.1. Gii thiu v chp PSoC:

Ngy nay. Trong mt h thng nhng (Embeded system), hay sn phm, thit b phc tp khc th s kt hp ca cc khi ngoi vi nh: Cc b lc, khuych i, b iu ch rng xung PWM, hay cc b chuyn i tng t - s (ADC), s - tng t (DAC) ..., l rt cn thit v gip gii quyt rt nhiu bi ton t ra t cc h thng t ng phc tp n cc thit b in t vn phng, gia dng. Cng nhiu thnh phn trong mt h thng th cng chim nhiu khng gian, ny sinh cc vn trong vic thit k mch, kt hp cc thnh phn, v tng phc tp ca h thng. gii quyt vn trn th ngy nay cng ngh SoC (Sytem on chip) ra i vi xu hng tch hp h thng trong mt con chp. i u trong vic pht trin v ng dng cng ngh ny l hng Cypress MicroSystems vi vic cho ra i chip PSoC. Thut ng PSoC l vit tt ca cm t ting anh Programmable System on Chip, ngha l h thng kh trnh trong mt chip. Cc chp PSoC c th thay i cu hnh rt n gin bng cch gn cc chc nng cho cc khi ti nguyn c sn trn chip. Hn na ta cng c th kt ni tng i mm do cc khi chc nng vi nhau hay cc cng vo ra, em li s thun tin cho cc phng n thit k. Thnh phn ca cc chp PSoc gm c: B vi x l 8 bit, B nh chng trnh (EEROM) c th lp trnh c v b nh RAM kh ln ty thuc vo tng con khc nhau trong h. lp trnh cho PSoC. Cypress MicroSystems cung cp phn mm PSoC Designer. Phn mm ny c thit k trn c s hng i tng vi cu trc m un ha. Mi khi chc nng l mt m un mm. Cc khi chc nng c chia lm hai loi, khi tng t v khi s. Cu hnh ca chp c thc hin bng cch s dng cc chc nng c sn. s dng cc chc nng no, ngi s dng ch cn ko chc nng v gn vo cc khi ti nguyn. Ty vo nhim v c th mi chc nng s chim mt s lng cc khi s, khi tng t hoc c khi s

v khi tng t nht nh. Ngi lp trnh cho PSoC c th thit lp chc nng v ch hot ng cho tng chn vo ra ca chip. Vi kh nng thit lp cu hnh linh hot v mnh m nh vy mt thit b o lng, iu khin c th c gi gn trong mt chp. Chnh v vy hng Cypress MicroSystems khng gi PSoC l Micro controller (Vi iu khin), m gi l PSoC device hay Thit b PSoC vi hy vng rng ngi s dng s c c nhng thit b o lng, iu khin c kch thc nh gn, s hot ng n nh v gi thnh r. Thay th c cc thit b da trn vi x l v vi iu khin c trc y. 2.2 .Gii thiu v chip PSoC CY8C27443-24PXI : 2.2.1. Thng s ca CY8C27443-24PXI : * B vi x l vi cu trc harvard. - B vi x l c tc ln n 24MHz. - Lnh nhn 8bit x 8 bit, thanh ghi tch ly l 32bit. - C th hot ng tc cao m tiu tn t nng lng. - Di in p hot ng t 3.00V ti 5.25V - in p hot ng c th gim xung 1.0V s dng ch kch in p. - Di nhit chu ng t - 400C n 850C.

Hnh 2.1 S cu trc CY8C27443-24PXI

Cc khi ngoi vi c th c s dng c lp hoc kt hp ty vo chc nng s dng. C 12 khi ngoi vi tng t c thit lp lm cc nhim v: - Cc b ADC ln ti 14 bit. - Cc b DAC ln ti 9 bit. - Cc b khuych i c th ty chn c h s khuych i. - Cc b lc v cc b so snh c th lp trnh c. C 8 khi ngoi vi s c thit lp lm cc nhim v: - 8 ti 32 bit cho timers, counters, v b iu ch rng xung PWM - Cc modun kim tra li (CRC modunles). Xung nhp ca chip c th la chn c. - B to dao ng trong 24/48MHz c chnh xc 2,5%. - B to dao ng ngoi c th la chn ln ti 24MHz. - B dao ng thnh anh 32kHz bn trong. B nh linh hot trn chip. - B nh Flash c khng gian nh 16K vi 50.000 ln ghi xa. - 256 Byte khng gian b nh RAM - Chip c th lp trnh thng qua chun ni tip (ISSP) - C th nng cp tng phn b nh Flash. - Ch bo v linh hot v ng tin cy. C th lp trnh c cu hnh cho tng chn ca chp. - Cc chn vo ra ba trng thi s dng Trigger Schmitt. - u ra logic c th cung cp dng 25mA vi in tr treo cao hoc thp bn trong. - Cung cp ti 12 u vo tng t. - ng ra tng t c th cung cp dng ti 30mA.

- Thay i c ngt trn tng chn. * Ti nguyn h thng. - Module truyn thng I2C Master v I2C Slave tc ln ti 400KHz. - B nh thi Watchdog v Sleep phc v ch an ton v ch ngh. - Module pht hin in p thp c cu hnh bi ngi s dng. 2.2.2. Cc ch a ch trong PSoC 2.2.2.1. Ch a ch ngun tc thi (Source Immediate) Nhng lnh s dng ch a ch ny c gi tr ngun c lu gi trong ton hng 1 ca lnh, kt qu c lu gi trong thanh ghi A, thanh ghi F, thanh ghi SP hay thanh ghi X c ch r trong lnh. Lnh s dng ch a ch nay c di l 2 byte 2.2.2.2. Ch a ch ngun trc tip (Source Direct) Trong ch ny th a ch ngun c lu gi trong ton hng 1 ca lnh. Trong sut qu trnh thi hnh lnh th a ch c dng ly gi tr ngun t RAM hoc t khng gian a ch thanh ghi. Kt qu c ch r trong lnh l t vo thanh ghi X hay thanh ghi A. Tt c nhng lnh s dng ch a ch trc tip u l lnh c di 2 byte 2.2.2.3. Ch a ch ngun ch s. Trong ch ny th d liu ca ngun c truy sut trong RAM hoc khng gian a ch thanh ghi thng qua a ch l gi tr hin thi ca thanh ghi X cng vi mt ch s. Kt qu c ch r trong lnh l lu trong thanh ghi X hay thanh ghi A. Lnh c di l 2 byte. 2.2.2.4. Ch a ch ch trc tip (Destination Direct) Nhng lnh thuc ch a ch ny c a ch c lu trong m my ca lnh, a ch ngun c ch r trong lnh l thanh ghi A hay X. Tt c nhng lnh s dng ch a ch ny u l lnh 2 byte. 2.2.2.5: Ch a ch ch s (Destination Indexed)

Nhng lnh thuc ch a ch ny c ch c xc nh bng cch ly gi tr ca thanh ghi X cng vi mt ch s lm a ch truy xut vo b nh, ngun c xc nh trong lnh l thanh ghi A hoc mt gi tr tc thi. Nhng lnh s dng ch a ch ny u l lnh c di 2 byte. 2.2.2.6. Ch a ch ch trc tip, ngun tc thi tc thi (Destination Direct, Source Immediate) Nhng lnh thuc ch a ch ny c a ch ca ch c lu gi trong ton hng 1 ca lnh. Gi tr ca ngun c lu trong ton hng 2 cu lnh. Tt c nhng lnh thuc ch a ch ny u l lnh c di 3 byte. 2.2.2.7. Ch a ch ch ch s, ngun tc thi (Destination Indexed, Source Immediate) Trong ch ny th gi tr ca thanh ghi X cng vi mt ch s c ly lm a ch ly d liu trong b nh. Cn d liu ngun l mt s trc tip. Tt c nhng lnh thuc ch a ch ny u l lnh 3 byte. 2.2.2.8. Ch a ch ch trc tip, ngun trc tip (Destination Direct , Source Direct) Ch c duy nht mt lnh s dng ch a ch ny, a ch ca ch c lu gi trong ton hng 1 ca lnh cn a ch ca ngun c lu gi trong ton hng 2 ca lnh. Tt c nhng lnh s dng ch a ch ny u l lnh c di 3 byte. 2.2.2.9. Ch a ch s dng con tr t ng tng a ch Con tr l ton hng ngun (Source Indirect Post Increment). Ch c duy nht mt lnh s dng ch a ch ny, a ch ngun lu gi trong ton hng 1 hot ng nh a ch ca mt con tr. Trong sut qu trnh lnh thi hnh th gi tr ca con tr s quyt nh xem d liu no trong Ram s c c. Sau khi c xong d liu th gi tr ca con tr c tng ln 1. 2.2.3. Ngt v b iu khin ngt.

A Name d d r e s s 0 INT_CLR0 , D A h 0 INT_CLR1 , D B h 0 INT_CLR3 , D D h 0 INT_MSK3 , D E h 0 INT_MSK0 , E 0 h 0 INT_MSK1 , E 1 h 0 INT_VC , E 2 h X CPU_F , F 7

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

Access

VC3

Sleep

GPIO

Analog3

Analog2

Analog1

Analog0

V Monitor

RW:00

DCB13

DCB12

DCB11

DCB110

DCB03

DCB02

DCB01

DCB00

RW:00

I2C

RW:00

ENSWINT

I2C

RW:00

VC3

Sleep

GPIO

Analog3

Analog2

Analog1

Analog0

V Monitor

RW:00

DCB13

DCB12

DCB11

DCB10

DCB03

DCB02

DCB01

DCB00

RW:00

Pending Interrupt [7:0 ]

RC:00

XOI

Carry

Zero

GIE

RL:00

Bng 2.9 : Cc thanh ghi ca b iu khin ngt. B iu khin ngt cho php mt on m ca ngi lp trnh c thc hin mi khi c mt ngt sinh ra t cc khi chc nng trong chp PSoC. Mi mt khi s c mt ngt ring v mi ct khi tng t cng c mt ngt ring. Mi mt ngt cho ngun cp, ch ng, xung nhp thay i, v mt ngt ton cc cho cc chn vo ra a chc nng. B iu khin ngt cng vi nhng thanh ghi ca n cho php cc ngt c th b v hiu ho ng thi hoc c lp nhau. Cc thanh ghi cung cp mt cch thc ngi s dng c th xa tt c nhng ngt ang ch v thng bo ngt, hoc c th xo mt cch c lp hay ring bit thng bo ngt v ngt ch. Mc u tin ngt 0(Cao nht) 1 2 3 4 5 6 7 8 9 10 11 12 13 a ch Tn ngt 0000h 0004h 0008h 000Ch 0010h 0014h 0018h 001Ch 0020h 0024h 0028h 002Ch 0030h 0034h Reset Supply Voltage Monitor Analog Column 0 Analog Column 1 Analog Column 2 Analog Column 3 VC3 GPIO PSOC Block DBB 00 PSOC Block DBB 01 PSOC Block DBB 02 PSOC Block DBB 03 PSOC Block DBB 10 PSOC Block DBB 11

14 15 24 25(Thp nht)

0038h 003Ch 0060h 0064h

PSOC Block DBB 12 PSOC Block DBB 13 I2 C Sleep Timer

Bng 2.10 : Bng cc vecter ngt. Dy cc s kin xy ra khi mt ngt c thi hnh nh sau: 1. Khi mt ngt c kch hot, c th l do mt iu kin ngt c sinh ra (do trn b m chng hn) v trc thng bo ngt cho php bi thanh ghi mt n che ngt, hoc c mt ngt ang ch c x l v GIE (global Interrupt enable- cho php ngt ton cc) c t t 0 sang 1 trong thanh ghi c ca CPU. 2. Lnh thi hnh hin thi kt thc bin gii lnh (bin gii lnh l thi im CPU chuyn t lnh ny sang lnh khc). 3. Th tc ngt bn trong c thc hin, tiu tn 13 chu k my. Trong khong thi gian ny CPU thc hn nhng cng vic sau: - Lu byte cao, byte thp ca b m chng trnh (PCH v PCL) v thanh ghi c (CPU_F) vo trong Stack theo th t trn. - Thanh ghi c c xo trng v t bit GIE b xo v 0 v nhng ngt mi sinh ra tm thi b cm. - Byte cao ca b m chng trnh (PC[15:8]) c xo v 0. - Vector ngt c c t b iu khin vetor ngt v gi tr ca n c t vo trong byte thp ca b m chng trnh tr vo a ch thch hp trong bng vetor ngt. 4. Chng trnh s thi hnh vetor trong bng vetor ngt. Nhn chung th mt lnh LJMP trong bng vetor ngt s chuyn s thi hnh ca CPU ti trnh phc v ngt ca ngi dng phc v ngt ny. 5. Trnh phc v ngt c thi hnh. Lu rng tt c cc ngt u b v hiu ho k t khi bit GIE= 0. Cc ngt khc c th c m li trong trnh phc

v ngt nu cn thit bng cch t bit GIE=1 (hy cn thn trong vic ny bi v n s lm cho trn stack). 6. Khi phc v ngt kt thc vi lnh RETI th thanh ghi c (CPU_F), byte thp v byte cao ca b n chng trnh c ly ra khi Stack theo ng trnh t trn. T khi thanh ghi c (CPU_F) c khi phc li gi tr th n s cho php cc ngt (GIE=1). 7. Chng trnh s bt u thi hnh lnh k tip, ngay sau khi lnh c thc hin trc khi xy ra ngt. Tuy nhin, nu nh c ngt ang ch c phc v th n s c thc hin trc. 2.2.4. Cc cng vo ra a chc nng Cc cng vo ra a chc nng to cho CPU mt giao din vi bn ngoi. Chng i hi mt s lng ln thanh ghi cu hnh h tr cho nhiu hot ng vo, ra bao gm c s v tng t. Address Name Bit 7 0,xxh 0,xxh 0,xxh 0,xxh 1,xxh 1,xxh 1,xxh 1,xxh PRTxDR PRTxIE PRTxGS Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RW:00 RW:00 RW:00 RW:FF RW:00 RW:FF RW:00 RW:00 Access

Data Registor (Thanh ghi d liu ) Bit Interrupt Enable (Bit cho php ngt) Globol Select (La chn ton cc)

PRTxDM2 Driver Mode 2 (Thanh ghi hot ng ch 2) PRTxDM0 Driver Mode 0 (Thanh ghi hot ng ch 0) PRTxDM1 Driver Mode 1 (Thanh ghi hot ng ch 1) PRTxIC0 PRTxIC1 Interrupt Control 0 (Thanh ghi iu khin ngt 0) Interrupt Control 1 (Thanh ghi iu khin ngt 1)

Bng 2.11: Cc thanh ghi vo ra a chc nng.

Ch : K t X sau du phy trong trng a ch c ngha l cc cng vo ra u c ring bit cc thanh ghi trn. Mi mt cng th thanh ghi s c mt a ch ring. Nhng d hiu ta ch cn xt chung cho trng hp tng qut. Cc cng vo a chc nng u c rng l 8 bit/1cng. Mi mt cng vo/ra bao gm 8 khi GPIO ging ht nhau. Mi mt khi GPIO u c kt ni vi bit c s th t tng ng trong a ch v thanh ghi. Bi vy, nhng thanh ghi trong bng 2-22 thc s ch dnh cho mt cng (bao gm 8 khi GPIO). Trong th v tr ca cc bit s ch r l khi GPIO no trong 8 khi c iu khin vi cng vo ra. Mi mt khi GPIO c th c s dng cho nhng kiu vo ra sau: - Vo ra s (Vo ra s iu khin bi phn mm). - Vo ra ton cc (Vo ra cho cc khi PSoC s). - Vo ra tng t (Vo ra cho cc kh PSoC tng t). Mi mt chn vo ra u c vi ch hot ng cng nh l kh nng to ngt. Trong khi tt c chn u c ni vo ng vo ra s, th mt vi chn li khng c kt ni vi chc nng vo ra ca khi tng t hoc bus ton cc. Vo ra s. Mt trong nhng chc nng hot ng c bn ca cng vo ra a chc nng l cho php CPU gi thng tin ra ngoi chp v ly thng tin t bn ngoi vo. iu ny c thc hin nh thanh ghi d liu cng (Port Data RegisterPRTxDR). Vic vit d liu vo thanh ghi PTRxDR s lu li trng thi d liu, mi bit cho mt chn GPIO. Trong ch thng (Standart Non-Bypass) th mi chn GPIO s lp li bit d liu . Ngha l khi ta vit mt gi tr vo trong thanh ghi d liu PRTxDR th u ra ca cng tng ng s c gi tr ging nh trong thanh ghi d liu. in p thc chn ra ph thuc vo ch hot ng ca chn ti bn ngoi c ni vo chn (Xem cu trc ca mt chn vo ra hiu r thm).

CPU c th c gi tr ca mt cng bng cch c gi tr ca thanh ghi PRTxDR. Khi CPU c gi tr ca PRTxDR th gi tr in p hin thi ca chn vo ra s c chuyn i sang gi tr logic v c tr v cho CPU. Hot ng ny s c gi tr in p ca chn vo ra ch khng phi l c v gi tr cht ca thanh ghi PRTxDR. Vo ra ton cc (Global IO). Cc cng vo ra a chc nng cng c ni lin vi cc khi s thng qua cc vo ra ton cc. Tnh nng vo ra ton cc ca mi cng c mc nh trng thi tt. s dng c tnh nng ny th c 2 thng s cn phi thay i. Th nht cu hnh cho mt chn GPIO hot ng nh l mt u vo ton cc th bit la chn cng ton cc cn phi c set yu cu GPIO s dng thanh ghi PRTxGS. Th hai l ch hot ng ca GPIO cn phi a v trng thi cao tr. cu hnh cho chn GPIO hot ng nh l mt u ra ton cc th bit la chn cng ton cc cn phi c set ln na. Nhng trong trng hp ny th ch hot ng ca GPIO l bt k tr khi cao tr Vo ra tng t. Tn hiu tng t c th c truyn dn gia CPU v chn ca chp thng qua chn AOUT ca khi. Chn ny c ni vi khi thng qua mt in tr (khong 300 ). Chn vo ra a chc nng cn phi a v ch cao tr trong trng hp ny. Cc ngt ca khi GPIO. Mi mt khi GPIO u c th c cu hnh mt cch c lp cho kh nng ngt. Cc khi GPIO c cu hnh cho php la chn ngt cho tng chn v cng c th la chn kiu ngt ph hp. Ngha l cc khi c th sinh ra ngt khi chn mc logic cao, thp hoc khi n thay i so vi ln c trc. Cc khi

u c mt u ra ngt ring (INT0), n c ni vi cc khi GPIO khc bng mt kiu ni dy loi OR. Do tt c cc chn u c ni vi nhau theo kiu OR s dng chung mt h thng ngt GPIO. Nu mt ngt GPIO c chia s cho nhiu chn vo ra th trnh phc v ngt ca ngi s dng cn phi s dng vi k thut c thit k sn quyt nh xem chn no c chn l ngun sinh ngt. S dng mt ngt GPIO yu cu nhng bc sau: 1. t ch ngt cho khi chn GPIO. 2. M bit ngt cho khi chn GPIO. 3. M bit mt n ngt cho ngt GPIO. 4. Xc nhn bit ngt ton cc GIE. S khi chnh ca mt khi GPIO c minh ho trong hnh 2-4. Lu rng mt vi chn khng c cc chc nng ngt nh hnh v m n ph thuc vo kt ni bn trong.

Hnh 2.3: S mt khiGPIO 2.2.5. Cc b to dao ng 2.2.5.1 B to dao ng chnh bn trong.

Address 1,E8h Name IMO_TR Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Trim [7:0] Access W:00

Bng 2.15: Thanh ghi ca IMO. u ra ca b IM0 c 2 loi, mt loi l SYSCLK c th l ngun xung nhp 24MHz bn trong hay ngun xung nhp bn ngoi, mt loi l SYSCLK2x c tn s xung nhp gp i SYSCLK. Khi khng c u vo chnh xc cao t b dao ng thch anh 32KHz th chnh xc ca ngun xung nhp 24/48MHz bn trong s l +/- 2,5% i vi gii nhit v hai mc in p hot ng (3.3V+/0.3V v 5.0V+/- 5%). Khng cn thm mt thnh phn bn ngoi no t c mc chnh xc ny. C mt la chn cht pha ca b dao ng bn trong ny sang b dao ng thch anh bn ngoi. V th vic la chn thch anh v chnh xc ca n quyt nh tnh chnh xc ca b dao ng ngoi. B dao ng thch anh bn ngoi cn phi n nh trc khi cht tn s dao ng ca b dao ng chnh bn trong vo ngun xung nhp ny. B IMO c th c kho khi s dng ngun xung nhp bn ngoi. Bi vy, mch nhn i tn s (SYSCLK2x) c th c ngt tit kim nng lng cho h thng. Lu rng khi s dng ngun xung nhp bn ngoi, nu nh SYSCLK2x c cn n th IMO khng th b kho. Thanh ghi IMO-TR (Internal Main Oscillator Trim Registor) Gi tr mc nh ca tn s chp cho ch hot ng 5V c ti vo thanh ghi IMO_TR ti thi im khi ng. B IMO s hot ng vi sai lch ring trong di in p t 4.75 n 5.25V khi gi nguyn gi tr ca thanh ghi ny. Nu nh chp hot ng in p thp, m ca ngi s dng cn thay i ni dung ca

thanh ghi ny. hot ng vi gii in p 3.0 V+/- 0.3V th phi thc hin vi mt lnh c bng ti SROM (Supervisor Rom), n c th cung cp mt gi tr cc tn s cho ch hot ng ny. hot ng gia hai gii in p ny m ca ngi s dng c th t ng thm vo gi tr tt nht s dng hai ct tn s c sn ca nh sn xut. Bit 7-0: Nhng bit ny lu gi gi tr ct tn s ca b IMO, gi tr ca thanh ghi cng ln th tn s dao ng ca b IMO cng ln. 2.2.5.2. B dao ng tc thp ni ti.
Address 1,E9h Name ILO_TR Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access W:00 Bias Trim [7:0] Freq Trim [3:0]

Bng 2.16 : Thanh ghi ILO. ILO l b pht xung nhp ni ti tc thp 32KHz. N c kh nng sinh ra ngt nh thc ch ng v reset li ng h Watchdog. B to dao ng ny cng c s dng nh l mt ngun xung nhp cho cc khi s. Thanh ghi ILO_TR Thanh ghi ny t iu chnh cho ILO. Gi tr mc nh c t vo nhng bit Trim ca thanh ghi trong qu trnh khi ng. N da vo mc nh ca nh sn xut. Nh sn xut khuyn co ngi s dng khng c thay i gi tr ca thanh ghi ny. Bt 7 v 6 : Khng dng n Bit 5 v 4: Bias Trim hai bit c s dng t dng in bias trong ngun dng PTAT. Bit 5 c nghch o v th ch bias trung bnh c chn khi c hai bit =0. Dng in bias c t theo bng sau. Bias Current Medium Bias Maximum Bias Minimum Bias Bit 5 0 0 1 Bit 4 0 1 0

Not Needed*

Bng 2.17 : Dng in bias trong PTAT. Cao hn khong 15% so vi ch Minimum Bias Bit 3 ti bit 0: Freq Trim bn bit c s dng ct tn s. Bit 0 l bit c trng s nh nht, bit 3 l bit c trng s ln nht. Bit 3 c nghch o bn trong thanh ghi, bi vy, m 8h s lm cho tt c cc ngun dng tt (tn s = 0KHz). Mt m 0h s bt ngun dng c trng s ln nht( tn s = trung bnh). Mt m 7h s bt tt c cc ngun dng (tn s = ln nht). 2.2.5.3. B to dao dng thch anh 32KHz (ECO) Mch to dao ng thch anh 32 KHZ cho php ngi s dng thay th b to dao dng bn trong (ILO) vi mt b to dao ng bn ngoi vi chnh xc cao hn, gi thnh thp v nng lng tiu hao t.
Addres s 1,E0h OSC_CR0 32k Select PLL Mode 1,EBh EC0_TR PSSDC[1: 0] X,Feh CPU_SC R1 ECO_EXW ECO_E X IRAMDI S No Buzz W:00 Sleep[1:0] CPU Speed [2:0] RW:00 Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access

Bng 2.18 : Cc thanh ghi ca b dao ng thch anh. Mch to dao ng thch anh s dng mt thch anhv hai t nh l thnh phn bn ngoi. Tt c cc thnh phn khc u nm trong chp PSoC. B dao ng thch anh c th cu hnh cung cp mt tham chiu n b to dao ng bn trong (IMO) trong ch PLL (Phase Lock Loop) to ra ngun xung nhp h thng 24 MHz vi chnh xc cao hn. Chn XTALIN v chn XTALOUT h tr kt ni vi thch anh 32.768 KHz. c th s dng b dao ng thch anh bn ngoi th bit 7 ca thanh ghi

iu khin b dao ng OSC_CR0 cn phi c t =1 (mc nh l 0). (Xem hnh 2.4).

Vdd Vdd

C1 XTALIn

C2 XTALOut

P1[1]
Thch anh

P1[1]

Hnh2.4: To b dao ng ngoi Cc bc ca chng trnh cn phi thc hin trong vic chuyn i gia b pht xung nhp chm ni ti sang b pht xung nhp thch anh 32 KHz nh sau: 1. Ti thi im reset, chp bt u hot ng v n s dng b pht xung nhp chm ni ti. 2. La chn khong thi gian ngh 1 giy bng bit[4:3] trong thanh ghi OSC_CRO nh l khong thi gian n nh b pht xung nhp. 3. Cho php b pht xung nhp thch anh 32 KHz bng cch t bit 7 trong thanh ghi OSC_CRO ln 1. 4. B pht xung nhp thch anh 32KHz tr thnh ngun xung nhp c la chn ti thi im kt thc mt giy ni trn. khong thi gian ngh cho php b pht xung nhp c thi gian n nh trc khi n tr thnh ngun cung cp xung nhp. Ngt sleep khng c m trong khi vic chuyn i ang din ra. Reset li Sleep Timer m bo khong thi gian ngh cn thit (Nu nh n khng giao tip vi bt k mt h thng thi gian thc no). Lu rng b pht xung nhp tc thp vn tip tc chy cho n khi chuyn hn sang b pht xung nhp ngoi nh vo ngt ca Sleep Timer.

2.2.6. Cc khi PSoC s

Bng 2.32: Thanh ghi ca khi PSoC s Tt c cc khi PSoC s u c th cu hnh thc hin bt c mt chc nng no trong 5 chc nng c bn sau: B nh thi, b m, b iu ch rng xung, PRS, kim tra chu k tha (CRC). Nhng chc nng ny c s dng bng cch cu hnh mt khi PSoC c lp hay mt chui vi khi PSoC lin nhau thc hin chc nng ln hn 8 bit. Cc khi PSoC s truyn thng c thm hai chc nng na l: SPI ch, SPI t hay truyn thng khng ng b hai chiu. M t cu trc mc cao nht, nhng thnh phn chnh ca khi PSoC s l ng d liu, b chn u vo, b chia u ra, bus ba trng thi PRSCRC, giao din bus h thng, cc thanh ghi cu hnh v di tn hiu. 2.2.6.1. B chn u vo Nhn chung, mi mt chc nng u c mt u vo xung nhp v mt u vo d liu c th c la chn t nhiu ngun khc nhau. Mi mt u vo c chn vi mt b chn vo 16 ra 1. Hn na, c mt b chn vo 4 ra 1 cung cp mt u vo ph cho chc nng SPI Slavo, chc nng yu cu 3 vo: Xung nhp, d liu, v SS_(tr khi l SS_c bt p hot ng cng vi bit cho php vo ra ph ). u vo b chn ny d nh c la chn t u vo GPIO.

2.2.6.2. ng b ho b xung nhp u vo. Nhng khi PSoC s cho php la chn xung nhp t 1 trong 16 ngun. Ngun c th l xung nhp h thng (VC1, VC2, VC3, SYSCLK v SYSCLKX2), cc chn u vo, u ra t cc khi PSoC khc c qun l c lch xung v m bo rng giao din gia cc khi c tnh ton thi gian ph hp trong tt c cc trng hp, tt c cc u vo xung nhp ca khi s cn phi c ng b ho li vi xung nhp h thng SYSCLK hoc SYSCLKX2. Xung nhp SYSCLK hoc SYSCLKX2 cng c th c s dng trc tip. Bit AUXCLK trong thanh ghi DxBxxOU c s dng ch r u vo ng b. Vic ng b ha u vo c thc hin theo lut sau: a. Nu xung nhp u vo bt ngun t SYSCLK (c th c chia nh) th s c khi PSoC s ng b ha li vi xung nhp SYSCLK. Hu ht cc xung nhp trong chip bt u thuc loi ny.V d, VC1,VC2 b. Nu xung nhp u vo bt ngun t SYSCLKX2, th n s c ng b ho vi xung nhp SYSCLKX2. c. Chn trc tip t xung nhp SYSCLK. d. Chn trc tip t xung nhp SYSCLKX2. e. ng b ha Bypass. Rt t khi la chn iu ny, bi v nu xung nhp khng c ng b th chng c th bt u sai vi lnh c v ghi ca CPU. Tuy nhin, n c th xy ra vi trng hp mt chn ngoi pht xung nhp cho khi s trng thi khng ng b. V d, nu ngi s dng mun ng b tc ng ca CPU bng ngt hay bng mt k thut no khc. Nhng lu sau y lit k nhng cu hnh khng c cho php, mc d phn cng khng h ngn cm chng. Bng tm tt ca nhng lu ny l b chia xung nhp khng c cu hnh nh l mt cch to xung nhp u ra bng vi SYSCLK hay SYSCLKX2.

1. Khi VC1 c cu hnh l chia bi 1 th la chn xung nhp VC1 l khng cho php. Vic cu hnh ny to ra mt xung nhp bng vi xung nhp h thng SYSCLK. Bi vy, SYSCLK nn c dng trc tip bng cc bit AUXCLK trong thanh ghi DxBxxOU ln 11b. 2. Khi c VC1 v VC2 u c cu hnh chia bi 1 th cng tng t vic chn xung nhp VC2 l khng cho php. Bi vy, s dng xung nhp trc tip nh trn. 3. Khi VC3 c cu hnh sao cho u ra c tn s bng vi xung nhp h thng SYSCLK hay SYSCLKX2 th vic chn xung nhp t VC3 cng khng c php. Bi vy, cng phi c s dng xung nhp trc tip SYSCLK hoc SYSCLKX2. Tt c nhng vn c cp trong phn ti ng b xung nhp thc c miu t trong hnh 2.15.

Hnh2.15 : Ti ng b xung nhp u vo. M 00 M t Bypass S Dng Ch s dng thit lp ny cho u vo trng thi khng ng b. Cng c s dng khi SYSCLK(48M) c la chn. 01 Ti ng b vi S dng thit lp ny cho bt k xung nhp no SYSCLK(24M) da trn SYSCLK. VC1, VC2, VC3, c iu khin bi SYSCLK, cc khi s vi ngun

xung nhp da trn SYSCLK, mng truyn tin vi ngun da trn SYSCLK. 10 Ti ng b vi S dng thit lp ny cho bt c xung nhp no SYSCLKX2 da trn SYSCLK2. VC3 c iu khin bi SYSCLK2, cc khi s vi xung nhp da trn SYSCLK2 , bus truyn tin vi ngun da trn SYSCLK2, u vo v du ra ca bng vi ngun da trn SYSCLK2. 11 SYSCLK tip trc S dng thit lp ny pht xung nhp SYSCLK trc tip vi cc khi s. Lu rng thit lp ny hon ton khng lin h vi xung nhp vi ti ng b nhng k t th SYSCLK khng th ti ng b vi chnh n. N cho php mt xin trc tip iu khin ngun SYSCLK Bng 2.33 Nhng la chn bit AUXCLK 2.2.7 . H thng khi PSoC tng t. Kin trc ca h thng tng t

Hnh2.17: S khi ca h thng tng t trong PSoC Cc khi PSoC l nhng ti nguyn c th cu hnh c. Cc khi tng t trn chp PSoC s gim thiu s cn thit cho nhiu loi chp v nhng thit b ngoi vi bn ngoi. Cc khi PSoC tng t c cu hnh cung cp nhng chc nng ngoi vi a dng. Phn mm PSoC Desiger tch hp vi mi trng pht trin s cung cp cho ta cu hnh t ng ca cc khi PSoC bng cch la chn nhng chc nng mong mun. Mi mt khi Analog c rt nhiu kh nng cho u vo v mt vi u ra. Nhng u vo ti nhng khi ny bao gm c nhng tn hiu tng t t nhng khi khc. Ngun in p tham chiu c th ly t trong chp hay ngoi chp tu . C ba loi khi PSoC: khi thi gian lin tc (Continues Time CT), khi chuyn mch cho t (Switch Capacitior SC) in loi C v loi D. Nhng khi tng t ny c t chc thnh cc ct. C bn ct trong dng h CY8C27xxx. Mt ct khi tng t bao gm 1 khi CT, 1 khi SC loi C v 1 khi SC loi D. Nhng khi trong cng mt ct s s dng ngun xung nhp nh nhau. Mi mt khi tng t c 3 u ra:

- Bus u ra tng t (ABUS) l mt u ra c chia s vi cc khi trong cng mt ct. Trong mt thi im ch c duy nht mt khi c php s dng bus u ra ny. y cng l bus u ra tng t duy nht trc tip kch thch cho chn ra tng t. - Bus so snh l mt bus s c chia s vi cc khi trong cng mt ct. Ti mt thi im ch c duy nht mt khi c php s dng bus so snh ny. - u ra ni b trong khi CT c dng kt ni vi cc khi lin k Mi hai khi PSoC tng t c th hot ng c lp hoc kt hp vi cc khi s c c nhng chc nng thch hp. Vi in p tham chiu chnh xc s cho php vic so snh tng t rt chnh xc. Giao din vi h thng tng t 2.2.7.1. Giao din Bus d liu tng t Giao din Bus tng t cch ly dy tng t v nhng thanh ghi giao din h thng tng t vi bus d liu h thng CPU gim thiu ti cho bus. B truyn nhn c b xung bi bus d liu h thng cch ly bus d liu tng t vi bus d liu h thng. iu ny i hi phi to ra mt h thng bus tng t ni b. 2.2.7.2. Giao din vi bus so snh tng t Mi mt ct tng t c mt bus so snh kt hp vi n. Tt c cc khi PSoC tng t u c u ra so snh c th trc tip kch thch bus so snh ny. Tuy nhin, ti mt thi im ch c mt khi duy nht trong mt ct c php kch thch cho bus so snh ny. u ra ca bus so snh ny c th kch thch cc khi s nh l mt u vo d liu. N cng c th phc v nh l mt u vo cho b decimator, hoc mt u vo ngt.

2.2.7.3. Ngun xung nhp cho cc khi tng t Cc khi SC yu cu hai pha khng gi ln nhau. Nhng khi ny c phn chia thnh 4 ct, hai khi cho mi ct. Mi ct c mt u vo xung nhp ring v ngun xung nhp ny s dng chung cho cc khi trong ct. C bn la chn xung nhp u vo l 24V1, 24V2, ACLK0, ACLK1. Ngun xung nhp 24V1, 24V2 l ngun xung nhp h thng. Hai ngun xung nhp ACLK0, ACLK1 l hai u vo la chn ngun xung nhp ly t cc khi PSoC s nhm c c mt ngun xung nhp thch hp 2.2.7.4. Giao din gia h thng tng t vi chn vo ra

Hnh 2.18 : S khi vo ra tng t vi chn ngoi

Bng 4-1 : Thanh ghi cu hnh vo ra tng t Thanh ghi AMX_IN Thanh ghi AMX_IN l thanh ghi la chn u vo t chn vo ra ca b MUX cho cc ct tng t. Cc gi tr c hai bit tng ng s cho php la chn c 4 u vo tng ng vi 4 chn c quy nh cho n. Ct ACI1 c thm b la chn ACOL1MUX cho php la chn gia hai u ra ca b ACI0 v ACI1. Tng t nh vy Ct ACI2 c thm b la chn ACOL2MUX cho php la chn gia hai u ra ca b ACI2 v ACI3. Nhng bit iu khin cho ACOL1MUX v ACOL2MUX c t ti thanh ghi ABF_CR0. Ngoi ra cn c thm 4 ng vo Analog trc tip ti cc khi SC. Thanh ghi ABF_CR0 y l thanh ghi iu khin u vo tng t t cng 0, v cc b khuch i m cho u ra ti cc chn ra tng t. Bit 7: ACoI1MUX: La chn u ra ca b ACI0 hay ACI1 cho ct tng t 1 Bit 6: ACoI2MUX: La chn u ra ca b ACI2 hay ACI3 cho ct tng t 2 Bit 5 ti 2: M v kho b khuch i u ra cho tng ct. Bit 1: Bypass. Ch Bypass s ni u vo ca b khuch i trc tip ti u ra ca b khuych i (Ngha l b qua b khuch i m trung gian). Khi bit ny c thit lp th ton b cc b khuch i iu khin bi thanh ghi ny s ch Bypass. Bit 0: PWR. Bit ny c s dng t mc nng lng cho b khuch i. Khi bit ny c t th ton b cc b khuch i s hot ng mc nng lng cao.

2.2.7.5 . Ngun tham chiu in p cho cc khi tng t. PSoC l mt thnh phn s dng ngun n, v vy n khng c in p m. Mt gii php t ra l to mt t gi l khong in p VCC/2. t ny s c ni ti tt c cc khi tng t v c m ngn cch gia cc khi. Lu rng c th c mt lch nh v in p gia cc b m t cho tn hiu tng t. t gi ny c to ra theo s sau

Hnh 2.19: S nguyn l mch to t gi Vic iu khin tham chiu in p c thc hin bng cch thay i gi tr ca thanh ghi ARF_CR. Vi vic iu chnh cc bit REF2:0 trong thanh ghi ARF_CR ta c th thit lp c in p tham chiu cho chp theo bng sau y: V d: P24=2.2V, P26=1.0V

Bng 2.34: Bng in p tham chiu c th to c trong PSoC 2.3. Gii thiu chung v PSoC Designer.

thit k cu hnh phn cng v lp trnh cho h cc chip PSoC, hng Cypress MicroSystems a ra phn mm PSoC Designer. y l mt cng c rt mnh cho php ta thit lp cu hnh cho chp, lp trnh v np chp rt d dng. Vic thit lp cu hnh cho chp c thit k theo hng mun ha cc chc nng s dng. Trong mi trng thit k ca PSoC Designer c cc khi chc nng, mi khi chc nng l mt mun mm v c chia lm hai loi: khi s v khi tng t. S lng cc khi chc nng cng khc nhau ty thuc vo tng chp trong h. Khi thit lp cc chc nng cho chp cc khi s v khi tng t c th c s dng c lp hoc kt hp vi nhau ty vo chc nng s dng. Cc chn vo ra cng c th c ty chn cu hnh s dng thun tin cho vic s dng chp trong cc ng dng thc t. Khi lp trnh trong PSoC Designer ta c th la chn ngn ng C hoc Assembler. PSoC Designer cung cp cho ngi lp trnh mt th vin phong ph

cc hm, lnh cho cc chc nng s dng, gip n gin hn trong vic lp trnh v bao qut chng trnh. Phng php thit k cu hnh chip theo khi chc nng ca PSoC Designer gip ngi lp trnh s dng d dng, nn thi gian thit k v lp trnh c rt ngn ng k. 2.4. Cc bc thit k v lp trnh trong PSoC Designer. Khi khi ng chng trnh ca s Start hin ra. to mt project mi ta chn Start new project

Ca s new Project hin ra. Ta nh tn project vo New project name

Tip theo trong ca s Create New Project ta chn loi chp s dng trong View catalog ( y ta s dng chip CYC27443-24PXI) v chn ngn ng lp trnh C hoc Assembler trong Generate Main file using: v kt thc qu trnh la chn ban u.

 thit lp cu hnh v lp trnh trong PSoC Designer ta s dng cc cng c chnh sau: User module selection view:

Cng c ny cho php ta la chn cc chc nng cn s dng trong qu trnh thit k. Nh trn ta thy c th vin ca cc b ADC, DAC, Ampliiers, Counters, Filters, PWM, Times. Sau khi la chn cc module cn s dng trong ca s Selected User Modules s c nhng module chn:

y ta s dng mt b ADC cho php bin i tn hiu tng t u vo sang tn hiu s, mt b khuych i (PGA), Mt b truyn thng s UART v mt modul iu ch rng ca xung PWM. ng thi trong ca s Resource

Meter cng cho ta bit tng s cc khi PSoC s, tng t, dung lng RAM, ROM c s dng.

Tip theo ta chn cng c Interconnect View: y l cng c ta thit lp cu hnh cho chip v thc hin kt ni cc khi c s dng vi chn vo ra. Nh trn ta thy chp CY8C27443-24PXI Gm c 8 khi PSoC s v 12 khi PSoC tng t. C 4 ng bus vo, ra 8 bit trong : 2 bus u vo 8 bit GIO[7:0], GIE[7:0] cho php tn hiu i t chn chp n CPU 2 bus u ra 8 bit GOO[7:0], GOE[7:0] cho php tn hiu i t CPU n cc chn chp. Cc ng bus RI0[0], RI0[1], RI0[2], RI0[3], RO0[0], RO0[1], RO0[2], RO1[3], RI1[0], RI1[1], RI1[2], RI1[3], RO1[0], RO1[1], RO1[2], RO1[3] dng kt ni cc khi PSoC s vi cc ng bus vo ra. Ca s Global resources thit lp ti nguyn ton cc cho chip. C th la chn kt ni cc chn vo ra v cc khi PSoC s, tng t c s dng trong cc module trc tip trn cc ng bus hoc trn ca s User Module parameters. Sau khi thit lp cu hnh c th ca tng chn c thy trong ca s sau:

Sau khi thit lp xong cc thng s ca cc Usermodul ta phi Generate Application (pht m cho qu trnh vit m ) bng cch chn nt cng c: ch cho n khi qu trnh pht m thnh cng ta s thy nh trong hnh v sau: v

Kt thc qu trnh kt ni v thit lp cu hnh ta chuyn sang lp trnh cho chip bng cng c
ca s lm vic s hin ra nh sau:

 lp trnh bng ngn ng C ta chn main.c Cc lnh c s dng trong cc module c cho trong th vin Library Source, Library Header Sau khi vit chng trnh xong ta chn cng c buil s thy nh trong hnh v sau: dch sang file .hex np vo chip. Nu qu trnh dch thnh cng v chng trnh khng c li ta

Chng III Xy dng h o, IU KHIN Cng nh sng s dng chip PSOC CY8C27443-24PXI 3.1. S khi chc nng ca h thng.

3.2. S nguyn l v chc nng ca cc thnh phn. 3.2.1. S mch ngun:

Mch ngun in p 220V xoay chiu, sau khi qua bin p nhn c in p xoay chiu 15V, v a n cu Diot 2A nn sang in p mt chiu. Chn (+) ca cu cp trc tip cho n p 7812, ,mc nh n nh dng 12V cp cho mch in. u ra ca n p dng 7812 ni vo chn ngun u vo n p 7805, cp ngun n nh 5V. Chn (-) ca cu diode ni vi chn u vo ca n p m 7912, n nh dng -12V. Cc t c mc trn c tc dng lc v l phng in p trc khi c a vo chp. 3.2.3. S mch cng sut:

Mch cng sut: Tn hiu iu khin t u ra ca Chp c a vo IC TL084CN, s dng 2 b khuch i o ca IC ny a u ra c dI t 0->12V, mc ch thay i gc m Thyristor iu chnh in p cp cho bng n, thay i cng sng ca bng n. Tng khuch i th nht khuch i tn hiu u vo di t 0->5V t Psc, cho u ra dI t -15V ->0V, b khuch i m tuyn tnh c h s khuch i l : K = R1 R3

Ta nn chn R1 = 10k, R3 = 4,7k, R8 = 10k. cho h s khuch i tuyn tnh (k = 2,4). Tng khuch i th 2 dng do cc tnh in p, in p u ra trong khong 0->12V, in p ny c cp cho chn iu khin gc m ca thyristor. H s khuch i ca tng ny l K = -1. in p xoay chiu ~220V cp cho n thng qua thyristor, s mc nh trn hnh v. Do gc m thyristor b thay i gc m nn in p chy qua cng thay i theo.

3.2.5. chp Psoc CY8C27443-24PXI.

L b vi x l trung tm .Chuyn i tn hiu in p t quang tr thnh gi tr cng nh sng hin th ln my tnh . X l thng tin a ln my tnh t to ra tn hiu iu khin a xung cc phn t chp hnh. 3.2.6. Cm bin quang (Quang tr). Quang tr c u ni tip vi bin tr iu chnh gi tr ca quang tr. Quang tr o cng nh sng v chuyn i thnh tn hiu in p a n chn Analog in ca chp.

S mch chip.

36

3.3 Chng trnh qu trnh iu khin o, iu khin v hin th cng nh sng. 3.3.1 Lu thut ton

3.3.2 Code: //==========================START================== =============== //-----------------------------------------------------------// C main line //----------------------------------------------------------------#include <m8c.h> // part specific constants and macros #include "PSoCAPI.h" // PSoC API definitions for all User Modules // 50 Point lookup table stored in ROM const char Table30[] = { 0,10,20,30,40,50, 60,70,80,90,100,110,

120,130,140,150,160, 170,180,190,200,210, 220,230,240,250,254 }; unsigned int ADC; BYTE Pointer,tudong,bangtay,tang,giam; unsigned char buf[],buf1[]; unsigned char gtfim,i; ///////////////////////////// #pragma interrupt_handler Timer8_1_ISR; void Timer8_1_ISR(void); void quet_phim(void); void delay(unsigned int c); ///////////////////////////// void Timer8_1_ISR() { quet_phim(); } //////////////////////////// void delay(unsigned int c) { int j; for(j=0;j<1000*c;j++); } /////////////////////////// void quet_phim(void) { tudong= PRT0DR & 0x01; //P0_0 bangtay= PRT0DR & 0x04;//P0_2 tang= PRT0DR & 0x10;//P0_4 giam= PRT0DR & 0x40;//P0_6 if(tudong==0x00)//tu dong { delay(10); gtfim = 1; } if(bangtay==0x00)//bang tay {

delay(10); gtfim = 2; } if(tang==0x00)// tang { delay(100); if(Pointer<24) { Pointer++; } else { Pointer=24;} } if(giam==0x00)// giam { delay(100); if(Pointer>0) { Pointer--;} else { Pointer=0;} } } /////////////////////////// void main() { PRT0DR = 0xff; LCD_1_Start(); LCD_1_Position(0,4); LCD_1_PrCString("HVKTQS"); DAC8_1_Start(DAC8_1_HIGHPOWER); PGA_1_Start(PGA_1_MEDPOWER);// khoi tao PGA ADCINC12_1_Start(ADCINC12_1_MEDPOWER);//khoi tao ADC ADCINC12_1_GetSamples(0);// lay mau lien tuc Timer8_1_Start();// Pointer = 0; gtfim=0; i=0; tudong=bangtay=tang=giam=1;

M8C_EnableGInt;// cho phep ngat toan cuc Timer8_1_EnableInt();// cho phep ngat timer while(1) { if(ADCINC12_1_fIsDataAvailable()!= 0)// neu AD bien doi xong { ADC = ADCINC12_1_iGetData()+2048; itoa(buf,ADC,10);// Converts an integer to a string //igetdata1=(igetdata+2015); ADCINC12_1_ClearFlag();// xoa co khoi tao lai LCD_1_Position(1,8); LCD_1_PrString(buf); } if(gtfim=0x00) { DAC8_1_WriteStall(Table30[0]);//tat den } if(gtfim==0x01) { for(i=0;i<=24;i++) { DAC8_1_WriteStall(Table30[i]); delay(100); } } DAC8_1_WriteStall(Table30[Pointer]); LCD_1_Position(1,1); itoa(buf1,Pointer,10); LCD_1_PrString(buf1); LCD_1_Position(1,4); LCD_1_PrHexByte(gtfim); }

} //===============================END============== ========