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KHI QUT:
Mch s c chia ra lm 2 loi ln:
Mch tun t (Sequential circuit) Mch t hp (Combinational circuit)
Tnh nh Tnh ng b
Mch tun t
Cht
Ng ra
Hnh: Mch cht RS Nhn xt: Mch c 2 ng vo l R v S v 2 ng ra Q v Q trong 2 ng ra bao gi cng b nhau
N1
N2
Ngoi ra c th thay 2 cng NAND thnh 2 cng NOR
S di
Trng thi ng ra ca mch logic c th thay i nhiu ln trc khi n nh trng thi ta mong mun.
Cay Viet.swf
3 in tr v 2 t in c lp thm vo. in tr phi c chn trng thi sao cho trng thi 2 cng khc 0 m trong vng tuyn tnh (gia 0.9V v 1.6V i vi TTL) s np x in ca 2 t s khin cho cc ng vo chuyn mch gia mc logic 0 v 1.
* Clock tc ng mc cao
Cnh xung
Cnh ln
Tn hiu ng h: l tn hiu hnh vung tun hon (thng thng: i xng) c kh rng xung nh hn hay bng phn na chu k T. Tnh hiu thc t cho d c thi tng v thi gim du nh nhng cng khc 0 nn cnh ln v cnh xung c mt dc no .
Khi ng h mc cao:
th ng vo thay i s lm ng ra thay i. Khi ng h mc thp: bt chp ng vo thay i th ng ra cng khng i
Clock tc ng mc thp:
Khi ng h mc thp:
th ng vo thay i s lm ng ra thay i.
Khi ng h mc cao:
bt chp ng vo thay i th ng ra cng khng i
S
CK
Q
Q
S
CK
Q
Q
Flip flop JK dng khc phc hin tng ng ra bt n (Q v Q tm thi cng trng thi) do c S v R cng mc cao
Flip flop JK c cu to gm flip flop RS c mc thm 2 cng AND trnh trng thi cm. Do s hi tip ca ng vo FF RS l S =J Q , R =KQ. Mch hot ng theo bng chn tr nh hnh v sau:
CK
1 0
Tng t i trng thi tc FF i trng thi khi t CK = 1 xung CK = 0 nn trong k hiu ca FF ch t, ngi ta thm du biu th iu ny. Mch FF ch t c ny bi mc hay bi xung.
| |
J CK
|
Q Q
CK
J 0 0 1 1
K 0 1 0 1
CK
Q Q0 0 1 Q0
J CK R
J 0 0 1 1
R 0 1 0 1
CK
Q Q0 0 1 Q0
Mch
to cnh dng 1 cng NOT v 1 cng AND. Chnh s tr hon qua cng NOT v AND tao nn 1 xung hp ng ra
1 CK 0 1 0 CK
1 0 1 0
CK
CK
1 CK 0
1 CK 0
flip flop dng ny bng cnh ca ng h cc ng vo nh S, C, J, K c gi l ng vo ng b (Synchronous input) c ngha l s tc ng logic ca cc ng vo ny xy ra ng b vi cnh ca ng h
Mc tiu : Hiu cch cu to nn Flip Flop D v Cht D. Hiu cch hot ng ca Flip Flop D v Cht D.
Gii thiu:
Flip
Flop D c mt ng vo nn rt thun tin trong vic s dng. ni 2 ng vo ca Flip Flop RS hoc JK vi mt ng vo (ng vo D vit tt ca Data or Delay), ta c Flip Flop D.
S(J) CK R(K)
Cu to:
Khi
D
CK
Bng: S tht
5.3 FLIP FLOP D, CHT D, K HIU IEEE/ANSI 1. Flip Flop D: ng dng: Flip Flop D thng l ni chuyn d liu t ng vo D n ng ra Q, cung cp d liu cho mch tip theo ( hiu ti sao ng vo vit tt l D - Data). D liu ng vo D phi ch n khi c xung ng h th mi xut hin ng ra c, th nn c th xem Flip Flop D nh mt mch tr hon. ( hiu ti sao ng vo vit tt l D Delay).
ng Dng
Lu tr d liu tm thi
p ng nhu cu logic rt cn thit c ng dng trong nhiu lnh vc chnh nh: iu khin (remote), my tnh (computer),
5.3 FLIP FLOP D, CHT D, K HIU IEEE/ANSI 3. K hiu IEEE/ANSI ca flip flop:
PR
J S Q
CK
C K R
CL
Flip Flop JK
5.3 FLIP FLOP D, CHT D, K HIU IEEE/ANSI 3. K hiu IEEE/ANSI ca flip flop:
PR
J S Q
CK
CL
Flip Flop D
5.3 FLIP FLOP D, CHT D, K HIU IEEE/ANSI 3. K hiu IEEE/ANSI ca flip flop:
EN
Cht D
FF JK 74LS76 5.4 IC FLIP FLOP TTL C TNH K THUT Flop TTL Mt s Flip
Mch ca FF JK 74L76
c Tnh K Thut
c tnh in
(V
cc
= 4.75V ,V IH = 2V ,V IL = 0.8V , I O L = 8m A)
A A A A
C C
= 15 pF
Q Q
L
0
= 15 pF
= 2 K
= 15 pF
= 2 K
P X N
CK
Ng ra chuyn i trng thi khi ng h chuyn t mc cao xung mc thp hoc t mc thp ln mc cao.
CK
Nhn xt: l 2 cng truyn T1, T4 c kch nh nhau (CK vo P, CK vo N) v 2 cng truyn T2, T3 c kch nh nhau( CK vo P, CK vo N).
T1
Cu to mch ca mch FF JK phc tp hn mch FF D do c 2 ng. hnh trn mt cng o ca mi mch cht c bn c i thnh cng NAND c thm ng vo Reset R. Mt s mch cht v FF CMOS, cng ging nh cc cng CMOS, cng gm nhiu lot nh CD4000, MC14000, 74C, 74HC, 74HCT, v.v
Vcc
3 4 5 6 7 8 9 10
IE
5.6 NG DNG CA FLIP FLOP V CHT 1. Mch chia i tn s (flip flop T):
T
C K
Q
0
J CK K
Q
Q
T=1 CK Q
1 0 1 0
Mun mch nh c nhiu bit??? Cc flip flop nhm li to thnh thanh ghi (register)
D liu vo ni tip
FFA
FFB
FFC
FFD
Ra ni tip
CK
CL
Ni tip -> Song song Ni tip -> Ni tip Song song -> Ni tip Song song -> Song song
Ghi dch CMOS c cu to t flip flop CMOS , y l cc ghi dch tnh( Static shift register), ngoi ra cn c ghi dch ng( Dynamite shift register) nh cc cng ngh MOS v CMOS
Tng ng 74164/LS164 ca cng ngh lng cc. Mch c ng ng h (CP) tc ng ln, ng MR tc ng mc thp, v 2 ng d liu ni tip DS1, DS2 (mt trong 2 ng cho php d liu vo mch hay khng)
DS1 DS2 CP
D
R
R R
R R
MR
Mt s c im: + S ta ra: Ng ra thng l 10 ti TTL-LS, ng ra thc bus l 15 ti TTL-LS + Khong nhit hot ng: -40- n 85OC + Tr hon truyn v cc thi gian chuyn tip cn xng + Lot 74HC: in th cp in VCC=2 n 6v; min nhiu cao, NIL= NIH =30%VCC VCC=5V + Lot 74HCT: in th cp in VCC=4.5V n 5.5 V;tng thch ng vo vi TTL-LS: VIL=0.8V max, VIH=2V max ; tng thch vi ng vo TTL: I1< 1uA VOL,VOH
MR CP
9 8
74HC/HCT194
1 DS1
2 DS2
3 Q0
4 Q1
5 Q2
6 Q4
7 GND
vo CP DS1
DS2
Q0
ra Q1-Q7
x L L H H
x h h l h
L l l l h
: cnh ln
h: mc cao ngay trc khi c cnh ln ca ng h l: mc thp ngay trc khi c cnh ln ca ng h q: trng thi ng vo ngay trc khi c cnh ln ca ng h
h to s dch chuyn cho cc bit d liu ang lu theo chiu Q0 n Q7 vng u tin ca phn di 2 khuyt c 2 ng vo d liu A,B v ng ra Q0. Du 1 ch d liu 1 cc vng khc ging nh vng u nn ko cn ghi ra. => ng h tc ng ln tt c FF.
dng c bn v cung kh ph bin c SR l lu tr d liu.SR n bit lu tr c n bit d liu mt thi gian m chng no mch cn c cung cp in Dch chuyn d liu la kh nng c bn th 2.Dch chuyn th c dch chuyn phi,dch chuyn tri,dch chuyn vng quanh.
1 0 0 0 1 1 0
dch chuyn tri 1 bit
1 1
0 1 0 0 0 1 1 0
dch chuyn phi 1 bit
0 0 0 1 1 0 1 0
(a) S chn
D liu 8bit