NI DUNG CHNH:

KHI QUT:
Mch s c chia ra lm 2 loi ln:
Mch tun t (Sequential circuit) Mch t hp (Combinational circuit)

Trng thi trc Mch t hp Trng thi ng vo

Tnh nh Tnh ng b

Mch tun t

5.1 MCH CHT RS V FLIP FLOP RS

S
Ng vo

Cht

Ng ra

Hnh: Mch cht RS Nhn xt: Mch c 2 ng vo l R v S v 2 ng ra Q v Q trong 2 ng ra bao gi cng b nhau

5.1 MCH CHT RS V FLIP FLOP RS 1. Cu to mch cht:

c to bi 2 cng NAND c hi tip cho. Hai ng vo c gi l S (vit tt cho Set) v R (vit tc cho Reset)

N1

N2
Ngoi ra c th thay 2 cng NAND thnh 2 cng NOR

* Khng i: so vi trng thi trc n.

5.1 MCH CHT RS V FLIP FLOP RS ng dng ca mch cht:

Mch chng di Mch dng nt nhn, nt bt. Mch logic c cng tc n tng i xa

S di

Trng thi ng ra ca mch logic c th thay i nhiu ln trc khi n nh trng thi ta mong mun.

5.1 MCH CHT RS V FLIP FLOP RS 2. ng dng ca mch cht:

Mch chng di

Cay Viet.swf

5.1 MCH CHT RS V FLIP FLOP RS 2. ng dng ca mch cht:

Dao ng to sng vung:

3 in tr v 2 t in c lp thm vo. in tr phi c chn trng thi sao cho trng thi 2 cng khc 0 m trong vng tuyn tnh (gia 0.9V v 1.6V i vi TTL) s np x in ca 2 t s khin cho cc ng vo chuyn mch gia mc logic 0 v 1.

5.1 MCH CHT RS V FLIP FLOP RS 3. Flip Flop RS:

S
N1 CK N2

* Clock tc ng mc cao

5.1 MCH CHT RS V FLIP FLOP RS

4. Flip Flop ny mc cao hay mc thp ca ng h:
Mc cao

Cnh xung

Cnh ln

Chu k T Hnh : Tnh hiu ng h Mc thp

Tn hiu ng h: l tn hiu hnh vung tun hon (thng thng: i xng) c kh rng xung nh hn hay bng phn na chu k T. Tnh hiu thc t cho d c thi tng v thi gim du nh nhng cng khc 0 nn cnh ln v cnh xung c mt dc no .

5.1 MCH CHT RS V FLIP FLOP RS

4. Flip Flop ny mc cao hay mc thp ca ng h:
Clock tc ng mc cao:

Khi ng h mc cao:
th ng vo thay i s lm ng ra thay i. Khi ng h mc thp: bt chp ng vo thay i th ng ra cng khng i

Clock tc ng mc thp:

Khi ng h mc thp:
th ng vo thay i s lm ng ra thay i.

Khi ng h mc cao:
bt chp ng vo thay i th ng ra cng khng i

S
CK

Q
Q

S
CK

Q
Q

5.2 FLIP FLOP JK: 1. Cu to mch cht:

Flip flop JK dng khc phc hin tng ng ra bt n (Q v Q tm thi cng trng thi) do c S v R cng mc cao

5.2 FLIP FLOP JK: 1. Cu to mch cht:

Flip flop JK c cu to gm flip flop RS c mc thm 2 cng AND trnh trng thi cm. Do s hi tip ca ng vo FF RS l S =J Q , R =KQ. Mch hot ng theo bng chn tr nh hnh v sau:

5.2 FLIP FLOP JK:

5.2 FLIP FLOP JK: 2. S ua vng quanh:

Flip

flop JK c ng h tc ng vo tng u thay v vo FF RS.

Mch ca FF JK v s a vng quanh

5.2 FLIP FLOP JK: 3. Cu to ch t:

trnh s ua vng quanh, ta cu to flip flop JK nh sau:

MASTER SLAVE

CK

1 0

5.2 FLIP FLOP JK: 3. Cu to ch t:

Tng t i trng thi tc FF i trng thi khi t CK = 1 xung CK = 0 nn trong k hiu ca FF ch t, ngi ta thm du biu th iu ny. Mch FF ch t c ny bi mc hay bi xung.
| |

J CK

|
Q Q

5.2 FLIP FLOP JK: 4. Flip Flop ny bng cnh (sn) ca ng h:

Ta c th trnh hin tng ua vng quanh nu xung ng h hp v cch lm cho flip flop chuyn mch theo cnh (sn) (Edge triggered) thay v theo mc.

FF 74LS109AN JK Possitive Edge Triggered flip flop

CK

J 0 0 1 1

K 0 1 0 1

CK

Q Q0 0 1 Q0

FF 74LS112AN JK Negative Edge Triggered Flip flop

J CK R

J 0 0 1 1

R 0 1 0 1

CK

Q Q0 0 1 Q0

 Mch

to cnh dng 1 cng NOT v 1 cng AND. Chnh s tr hon qua cng NOT v AND tao nn 1 xung hp ng ra

1 CK 0 1 0 CK

1 0 1 0

CK

CK

1 CK 0

1 CK 0

5.2 FLIP FLOP JK: 4. Flip Flop ny bng cnh (sn) ca ng h:

flip flop dng ny bng cnh ca ng h cc ng vo nh S, C, J, K c gi l ng vo ng b (Synchronous input) c ngha l s tc ng logic ca cc ng vo ny xy ra ng b vi cnh ca ng h

5.3 FLIP FLOP D, CHT D, K HIU IEEE/ANSI

Mc tiu : Hiu cch cu to nn Flip Flop D v Cht D. Hiu cch hot ng ca Flip Flop D v Cht D.

5.3 FLIP FLOP D, CHT D, K HIU IEEE/ANSI 1. Flip Flop D:

Gii thiu:
Flip

Flop D c mt ng vo nn rt thun tin trong vic s dng. ni 2 ng vo ca Flip Flop RS hoc JK vi mt ng vo (ng vo D vit tt ca Data or Delay), ta c Flip Flop D.
S(J) CK R(K)

Cu to:
Khi

D
CK

5.3 FLIP FLOP D, CHT D, K HIU IEEE/ANSI 1. Flip Flop D:

Hot ng logic: Ng ra c cng logic nh ng vo mi khi c cnh ng h ln (cnh ln hoc cnh xung cn ty thuc vo flip flop).

Bng: S tht

5.3 FLIP FLOP D, CHT D, K HIU IEEE/ANSI 1. Flip Flop D:

Cch hot ng: (iu kin cnh ca ng h i ln) Nu D = 0(mu xanh = 0, mu = 1)

5.3 FLIP FLOP D, CHT D, K HIU IEEE/ANSI 1. Flip Flop D:

Cch hot ng: (iu kin cnh ca ng h i ln) Nu D = 1(mu xanh = 0, mu = 1)

5.3 FLIP FLOP D, CHT D, K HIU IEEE/ANSI 1. Flip Flop D: ng dng: Flip Flop D thng l ni chuyn d liu t ng vo D n ng ra Q, cung cp d liu cho mch tip theo ( hiu ti sao ng vo vit tt l D - Data). D liu ng vo D phi ch n khi c xung ng h th mi xut hin ng ra c, th nn c th xem Flip Flop D nh mt mch tr hon. ( hiu ti sao ng vo vit tt l D Delay).

5.3 FLIP FLOP D, CHT D, K HIU IEEE/ANSI 1. Flip Flop D:

Dng sng ca Flip Flop D:

5.3 FLIP FLOP D, CHT D, K HIU IEEE/ANSI 2. Cht D:

Cu to: Cng ging nh Flip Flip D, Cht D cng ch c mt ng vo l D. iu khc bit vi Flip Flop D l: Ng vo ng h CK (D Flip Flop) c thay bi ng vo cho php Enable (D Latch) D
E R(K) S(J)

5.3 FLIP FLOP D, CHT D, K HIU IEEE/ANSI 2. Cht D:

Hot ng logic v bng s tht: Khi ng vo cho php E mc cao, ng ra Q s c c mc logic ging vi ng vo D , Khi ng vo cho php E mc thp, trng thi ca ng vo D ngay trc khi E xung thp s c cht vo. Nh vy, trng thi ny c lu gi bi Q, v ng ra Q s ko thay i cho ti khi ng vo cho php E ln cao tr li.

5.3 FLIP FLOP D, CHT D, K HIU IEEE/ANSI 2. Cht D:

Gii thch cch hot ng: (E = 1) Nu D = 1: (mu xanh = 0, mu = 1)

5.3 FLIP FLOP D, CHT D, K HIU IEEE/ANSI 2. Cht D:

Gii thch cch hot ng: (E = 1) Nu D = 0: (mu xanh = 0, mu = 1)

5.3 FLIP FLOP D, CHT D, K HIU IEEE/ANSI 2. Cht D:

ng Dng

Lu tr d liu tm thi

p ng nhu cu logic rt cn thit c ng dng trong nhiu lnh vc chnh nh: iu khin (remote), my tnh (computer),

5.3 FLIP FLOP D, CHT D, K HIU IEEE/ANSI 3. K hiu IEEE/ANSI ca flip flop:

PR
J S Q

CK

C K R

CL
Flip Flop JK

5.3 FLIP FLOP D, CHT D, K HIU IEEE/ANSI 3. K hiu IEEE/ANSI ca flip flop:

PR
J S Q

CK

CL
Flip Flop D

5.3 FLIP FLOP D, CHT D, K HIU IEEE/ANSI 3. K hiu IEEE/ANSI ca flip flop:

EN

Cht D

5.4 IC FLIP FLOP TTL C TNH K THUT Flip Flop TTL 1. Mt s

FF JK 74LS76 5.4 IC FLIP FLOP TTL C TNH K THUT Flop TTL Mt s Flip

Mch ca FF JK 74L76

Bng chn tr ca FF JK 74L76

5.4 IC FLIP FLOP TTL C TNH K THUT

iu kin hot ng khuyn co

c Tnh K Thut

c tnh in

c tnh chuyn mch

5.4 IC FLIP FLOP TTL C TNH K THUTkin hot ng khuyn co Cc iu

5.4 IC FLIP FLOP TTL C TNH K THUT

c tnh in:

(V cc = 4.75V ,V IH = 2V ,V IL = 0.8V , I O H = 400 A)

(V

cc

= 4.75V ,V IH = 2V ,V IL = 0.8V , I O L = 8m A)

A A A A

5.4 IC FLIP FLOP TTL C TNH K THUTchuyn mch: c tnh

C C

= 15 pF

Q Q
L
0

= 15 pF

= 2 K

= 15 pF

= 2 K

5.5 Flip Flop v cht CMOS

Gii thiu:
CK

P X N
CK

Ng ra chuyn i trng thi khi ng h chuyn t mc cao xung mc thp hoc t mc thp ln mc cao.

5.5 Flip Flop v cht CMOS

1. Mch cht CMOS

CK

Hnh: Mch Cht dng cng truyn

5.5 Flip Flop v cht CMOS

2. Flip Flop D CMOS

Nhn xt: l 2 cng truyn T1, T4 c kch nh nhau (CK vo P, CK vo N) v 2 cng truyn T2, T3 c kch nh nhau( CK vo P, CK vo N).

T1

Hnh: Mch Flip Flop D dng cng truyn

5.5 Flip Flop v cht CMOS

3. Flip Flop JK CMOS

Cu to mch ca mch FF JK phc tp hn mch FF D do c 2 ng. hnh trn mt cng o ca mi mch cht c bn c i thnh cng NAND c thm ng vo Reset R. Mt s mch cht v FF CMOS, cng ging nh cc cng CMOS, cng gm nhiu lot nh CD4000, MC14000, 74C, 74HC, 74HCT, v.v

5.5 Flip Flop v cht CMOS

4. Kho st mt s IC Flip Flop v mt s cht CMOS
74HC/HCT 533, 563: tm cht trong sut o ra 3 trng thi (Octal intering transparent latch 3- state output) 74HC/HCT 533, 563 l 8 cht tc cao ch to theo cng ngh CMOS cng silicium, c cng sut tiu tn thp v c th thc 15 ti TTL-LS. Khi ng cho php cht (latch enable) LE cao d liu vo D n mch ra, nu ng cho php ra (output enable) OE thp d liu s ra Q nhng o li (Q=D). Khi OE cao ng ra trng thi tr khng cao. Khi ng LE thp d liu D ngay trc c cht vo xem bng s tht.

5.5 Flip Flop v cht CMOS

4. Kho st mt s IC Flip Flop v mt s cht CMOS S chn v bng chn tht ca 74HC/HCT563
L= mc thp, H= mc cao, l= mc thp trong 1 thi gian thit lp trc chuyn tip cao xung thp ca LE, h= mc cao trong 1 thi gian thip lp trc chuyn tip cao xung thp ca LE, x= mc cao hoc thp, Z= trng thi Z cao.
OE 0D 1D 2D 3D 4D 5D 6D 7D GND 20 19 18 17 16 15 14 13 12 11
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7

Vcc

3 4 5 6 7 8 9 10

IE

5.5 Flip Flop v cht CMOS

4. Kho st mt s IC Flip Flop v mt s cht CMOS S ca 1 cht ca 74CH/HCT563

5.5 Flip Flop v cht CMOS

4. Kho st mt s IC Flip Flop v mt s cht CMOS S ca 1 cht ca 74CH/HCT173

5.5 Flip Flop v cht CMOS

Sau y l mt s Flip Flop D khc:

5.6 NG DNG CA FLIP FLOP V CHT 1. Mch chia i tn s (flip flop T):
T
C K
Q
0

J CK K

Q
Q

T=1 CK Q
1 0 1 0

Flip flop JK mc nh flip flop T thc hin s chia i tn s CK

5.6 NG DNG CA FLIP FLOP V CHT 2. Mch bo ng khi tia sng b ct

5.6 NG DNG CA FLIP FLOP V CHT

3. Mch ng v tt tn hiu ng h c chng di

Hnh: Mch ng v tt tnh hiu ng h c chng di

Hnh: Mch cho s nguyn xung ng h ng ra.

5.6 NG DNG CA FLIP FLOP V CHT

4. Mch pht hin tun t ca cc d liu:

5.6 NG DNG CA FLIP FLOP V CHT

5. m:

5.6 NG DNG CA FLIP FLOP V CHT

6. Lu d liu song song:

5.7 MCH GHI DCH

5.7 MCH GHI DCH

Flip flop c kh nng nh 1 bit

Mun mch nh c nhiu bit??? Cc flip flop nhm li to thnh thanh ghi (register)

5.7 MCH GHI DCH

1. Cu to ca ghi dch c bn:
QA QB QC QD

D liu vo ni tip

FFA

FFB

FFC

FFD

Ra ni tip

CK
CL

5.7 MCH GHI DCH

1. S hot ng ca ghi dch:

5.7 MCH GHI DCH

5.7 MCH GHI DCH

2. Cc loi ghi dch:

4 bit 5 bit 8 bit SR 16 bit

Ni tip -> Song song Ni tip -> Ni tip Song song -> Ni tip Song song -> Song song

D/c phi D/c tri D/c phi + tri

5.7 MCH GHI DCH

2. Cc loi ghi dch: Np song song:

Hnh: np song song vo ghi dch

5.7 MCH GHI DCH

2. Cc loi ghi dch: Dch chuyn tri:
Mun dch chuyn tri d liu lu tr ta ch cn ni ngc chiu cc FF.

5.7 MCH GHI DCH

3. Kho st vi IC ghi dch

GHI DCH 4 BIT

5.7 MCH GHI DCH

3. Kho st vi IC ghi dch
GHI DCH 5 BIT

5.7 MCH GHI DCH

3. Kho st vi IC ghi dch
bng s tht ca 7496

5.8 GHI DCH CMOS, K HiU IEEE/ANSI

1. Ghi dch CMOS:

Ghi dch CMOS c cu to t flip flop CMOS , y l cc ghi dch tnh( Static shift register), ngoi ra cn c ghi dch ng( Dynamite shift register) nh cc cng ngh MOS v CMOS

5.8 GHI DCH CMOS, K HiU IEEE/ANSI

1. Ghi dch CMOS:
Ghi dch CMOS c cc loi nh SR TTL( phn ln l cng m s) nh 74194/LS194/HC194/HCT194. Ng Clear thng c gi l MR( Master Reset)

5.8 GHI DCH CMOS, K HIU IEEE/ANSI

1. Ghi dch CMOS:
74HC164/HCT164: Ghi dch 8bit vo ni tip ra song song

Tng ng 74164/LS164 ca cng ngh lng cc. Mch c ng ng h (CP) tc ng ln, ng MR tc ng mc thp, v 2 ng d liu ni tip DS1, DS2 (mt trong 2 ng cho php d liu vo mch hay khng)

5.8 GHI DCH CMOS, K HiU IEEE/ANSI

DS1 DS2 CP

D
R

R R

R R

MR

5.8 GHI DCH CMOS, K HiU IEEE/ANSI

1. Ghi dch CMOS:
74HC164/HCT164: Ghi dch 8bit vo ni tip ra song song

Mt s c im: + S ta ra: Ng ra thng l 10 ti TTL-LS, ng ra thc bus l 15 ti TTL-LS + Khong nhit hot ng: -40- n 85OC + Tr hon truyn v cc thi gian chuyn tip cn xng + Lot 74HC: in th cp in VCC=2 n 6v; min nhiu cao, NIL= NIH =30%VCC VCC=5V + Lot 74HCT: in th cp in VCC=4.5V n 5.5 V;tng thch ng vo vi TTL-LS: VIL=0.8V max, VIH=2V max ; tng thch vi ng vo TTL: I1< 1uA VOL,VOH

5.8 GHI DCH CMOS, K HiU IEEE/ANSI

VCC 14 Q7 13 Q6 12 Q5 11 Q4 10

MR CP
9 8

74HC/HCT194

1 DS1

2 DS2

3 Q0

4 Q1

5 Q2

6 Q4

7 GND

Ch hot MR ng Reset Dch chuyn phi L H H H H

vo CP DS1

DS2

Q0

ra Q1-Q7

x L L H H

x h h l h

L l l l h

L-L q0- q6 q0- q6 q0- q6 q0- q6

H: mc cao(1), L:mc thp(0),

: cnh ln

h: mc cao ngay trc khi c cnh ln ca ng h l: mc thp ngay trc khi c cnh ln ca ng h q: trng thi ng vo ngay trc khi c cnh ln ca ng h

5.8 GHI DCH CMOS, K HiU IEEE/ANSI

1. Ghi dch CMOS:
4731B: Bn ghi dch 64 bit vo ni tip ra ni tip: IC 4731B gm 4 ghi dch ging nhau c chung ngun VCC v t. Mi ghi dch gm 64 tng FF ni tip, ng vo ni tip vo tng u , ng ra ni tip l ng ra ca FF cui cng v ng vo ng h p ng cnh xung Cng dng ca ghi dch l tr hon d liu 64 chy k

5.8 GHI DCH CMOS, K HiU IEEE/ANSI

2. K hiu IEEE/ANSI ca ghi dch:
K hiu IEEE/ANSI khc vi k hiu thng, v d 74164 Phn trn hai khuyt l phn iu khin v phn di c chia lm 8 vng hp biu th 8bit MR tc ng mc thp, CP( clock pulse) tc ng cnh ln ng ng h vo ghi dch C1 ni ng h ny ch tc ng ln FF c s 1 i trc. Du / sau C1 l ly cch C1 vi l cnh tc ng ca ng h.

5.8 GHI DCH CMOS, K HiU IEEE/ANSI

2. K hiu IEEE/ANSI ca ghi dch:
ng

h to s dch chuyn cho cc bit d liu ang lu theo chiu Q0 n Q7 vng u tin ca phn di 2 khuyt c 2 ng vo d liu A,B v ng ra Q0. Du 1 ch d liu 1 cc vng khc ging nh vng u nn ko cn ghi ra. => ng h tc ng ln tt c FF.

5.9 NG DNG GHI DCH

Gii thiu:

5.9 NG DNG GHI DCH

1. Lu tr v dch chuyn d liu:
ng

dng c bn v cung kh ph bin c SR l lu tr d liu.SR n bit lu tr c n bit d liu mt thi gian m chng no mch cn c cung cp in Dch chuyn d liu la kh nng c bn th 2.Dch chuyn th c dch chuyn phi,dch chuyn tri,dch chuyn vng quanh.

5.9 NG DNG GHI DCH

1. Lu tr v dch chuyn d liu:
V d dch bit:
B1 b2 b3 b4 b5 b6 b7 b8

1 0 0 0 1 1 0
dch chuyn tri 1 bit

1 1

0 1 0 0 0 1 1 0
dch chuyn phi 1 bit

0 0 0 1 1 0 1 0
(a) S chn

5.9 LU TR V DCH CHUYN D LIU

2. To k t hoc dng iu khin: Dng to tn hiu (dng sng) tun hon ra ni tip. Thay i dng sng bng cch thay i m s nh phn np vo ghi dch,v thay i chu k sng bng cch thay i tc ng h m i vi cc ghi dch c th t 0 n 200MHz

5.9 LU TR V DCH CHUYN D LIU

3. Chuyn i d liu t ni tip sang song song v ngc li:
MY TNH 1 MY TNH 2

D liu 8bit

Ghi dch song song sang ni tip

Ghi dch ni tip sang song song