Hi ngh ton quc v iu khin v T ng ho - VCCA-2011

VCCA-2011
Nghin cu cu trc Hybrid Sparse Matrix Converter ghp a bc s dng
gii thut iu ch sng mang PWM
Research on Multilevel Hybrid Sparse Matrix Converter topology using
Carrier-based PWM modulation strategy
Trn V, Nguyn Vn Nh
PTN H Thng Nng Lng, Khoa in-in t, H Bch Khoa TP.HCM

Tm tt
Cu trc Hybrid Sparse Matrix ghp 3 bc c a
ra trong bi bo ny. So vi cc cu trc ca b bin
i ma trn truyn thng t s truyn t p ln nht
trong vng tuyn tnh ch c 0.866 ln p li th cu
trc Hybrid Sparse Matrix ghp 3 bc c nhiu u
im hn. Vi cu trc Hybrid Sparse Matrix ghp 3
bc, vng iu khin p u ra c m rng v cht
lng p u ra c ci thin. Trong bi bo, gii
thut iu ch sng mang PWM c p dng cho
cu trc Hybrid Sparse Matrix ghp 3 bc. Ton b
gii thut iu khin cho Hybrid Sparse Matrix ghp
3 bc c thit k hon ton trn Xilinx
XC3S1600E Spartan-3E FPGA Development kit.
Hiu qu ca gii thut c kim chng qua m
phng v thc nghim. Cc kt qu thc nghim
dng sng u vo u ra ca Sparse Matrix ghp 3
bc c a ra phn tch.
Abstract: A novel 3-level Hybrid Sparse Matrix
Converter (HSMC) topology is proposed in this
paper. In comparison to conventional Matrix
Converter topologies which maximum output voltage
range in linear region is just 0.866, the 3-level Hybrid
Sparse Matrix Converter topology has some more
advantages. The 3-level HSMC topology will help to
extend the output voltage range and improve the
output voltage quality. In this paper, a novel carrier-
based PWM modulation strategy is applied on this
topology. Whole control algorithm of 3-level HSMC
was entirely designed on Xilinx XC3S1600E
Spartan-3E FPGA Development kit. The algorithm's
efficiency for HSMC is verified through simulation
and experimental work. Experimental results of input
and output waveforms of HSMC are presented and
analyzed.
K hiu
K hiu
, ,
sa sb sc
V V V
n v
volt
ngha
in p ngun
ba pha u vo.
cos , cos , cos
a b c
u u u
rad Gc pha ca p
ngun u vo
i
w
rad/s Tn s gc p
ngun u vo.
Vdc
volt Gi tr trung bnh
p DC trong mt
chu k ng ngt
ca tng chnh
lu.
_ Vdc p
volt in th nhnh
trn p DC ca
tng chnh lu.
_ Vdc n
volt in th nhnh
di p DC ca
tng chnh lu.
Ch vit tt
HSMC Hybrid Sparse Matrix Converter
1. Gii thiu
Trong cc b bin i xoay chiu AC-AC hin nay,
b bin i ma trn ang thu ht c nhiu s
quan tm nghin cu do c nhiu u im nh: cu
trc tt c u l kha bn dn v khng c bt c
thnh phn d tr nng lng no, b bin i ma
trn c th to ra dng sng u vo, u ra c dng
sin vi h s cng sut u vo c th gi c
bng 1. Cc b bin i ma trn hin nay c 2 cu
trc chnh l: cu trc trc tip vi 9 kha bn dn
kp[1] v cu trc gin tip vi tng chnh lu xung
PWM u vo v tng nghch lu p 2 bc u
ra[2][3][4].
Tuy nhin hn ch ca cc b bin i ma trn hin
nay[1][2][3][4] l t s truyn t p ln nht trong
vng tuyn tnh ch t c 0.866 ln p li m
p nh mc ca cc thit b in lun bng p li,
do vy vng iu khin p ra ca cc b bin i
ma trn n lun di nh mc cc thit b in.
vt qua hn ch v vng iu khin p ra cu
trc Hybrid Sparse Matrix Converter(HSMC) ghp
3 bc c a ra trong bi bo ny. HSMC 3 bc
c cu hnh gin tip bao gm tng chnh lu xung
PWM u vo v 2 b nghch lu p 2 bc c
ghp song song tng nghch lu u ra nh trn
Hnh 1. Vi cu hnh ghp a bc ny vng iu
khin p ra c m rng t s truyn t p ln
nht trong vng tuyn tnh c th t 1.5 ln p li
v cht lng p u ra c ci thin so vi cc b
bin i ma trn hin nay.
684
Hi ngh ton quc v iu khin v T ng ho - VCCA-2011


VCCA-2011
Trong bi bo ny, gii thut iu ch sng mang
PWM c p dng cho cu trc HSMC ghp 3
bc. Ton b gii thut iu khin cho HSMC 3 bc
c thc hin trn card Xilinx XC3S1600E
Spartan-3E FPGA. M hnh m phng cho HSMC
ghp 3 bc c xy dng s dng MATLAB/
Simulink.
M hnh phn cng ca HSMC ghp 3 bc c
xy dng kim chng tnh kh thi thc t ca
gii thut. Cc kt qu thc nghim v dng sng
u vo u ra ca gii thut iu ch sng mang
PWM c phn tch.
















Hnh 1. Hybrid Sparse Matrix Converter 3 bc
2. PWM cho tng chnh lu v iu ch
sng mang PWM cho tng nghch lu
2.1 Phng php PWM iu ch p cao cho tng
chnh lu:
in p ba pha u vo:
cos cos( )
cos cos( 120)
cos cos( 120)
sa m a m i
sb m b m i
sc m c m i
V V V wt
V V V wt
V V V wt
u
u
u
= =

= =

= = +

(1)
Vi
i
w : tn s gc ca p ngun u vo
Chu k ca in p ba pha u vo c chia thnh 6
khong nh Hnh 2.
-
6

2
0
5
6
7
6
3
2
11
6

Hnh 2. Su khong chia ca in p ba pha u vo vi
phng php PWM th 1 iu ch p cao cho tng chnh
lu
Gi s ti thi im ly mu in p ba pha ang
nm trong khong 1 thuc on [-/6, /6]. Trong
khong ny ln in p
sa
V ln hn in p
sb
V
v
sc
V .
Do vy trong sut chu k ng ngt thuc on [-
/6, /6]. Kha S
a
s ng duy tr trong mt chu k
v 2 kha cn li S
b
v S
c
s ng vi t s ng ct
d
b
v d
c
nh sau[2]:
cos cos
,
cos cos
sb b sc c
b c
sa a sa a
V V
d d
V V
u u
u u
= = = =
(2)
Khi kha S
b
c ng, in p V
dc
s bng in p
V
ab
vi t s d
b
. Khi kha S
c
ng, in p V
dc
s
bng in p V
ac
vi t s d
c
. Gi tr trung bnh p
V
dc
trong mt chu k s l:
( ) . ( )
b sa sb c sa sc
Vdc d V V d V V = +
(3)
Th (1) v (2) vo phng trnh (3), gi tr trung
bnh in p V
dc
trong mt chu k thu c nh
sau:
3
2. cos
m
a
V
Vdc
u
=
(4)
Tng qut gi tr trung bnh p V
dc
trong mt chu
k s l:
3
2.cos
m
in
V
Vdc
u
=
(5)
Vi ( ) cos max( cos , cos , cos )
in a b c
u u u u =
Vsa
Vsc
Vsb
iA
iB
iC
isa
isc
isb
idc
Sa Sc
Vdc
Sb
Tng chnh lu
Vdc_p
Vdc_n
SHAp SHBp SHCp
SHBn SHCn SHAn
Tng nghch lu
SLAp SLBp SLCp
SLAn SLBn SLCn
685
Hi ngh ton quc v iu khin v T ng ho - VCCA-2011


VCCA-2011
ab
ac
i
bc
ba
ca
cb
u
Vsa
Vsb
d
c
d
b
Vsc

Hnh 3. Lc gic vector khng gian dng u vo
Vector dng u vo s c tng hp t 2 vector
gn nht v c iu khin cng pha vi vector p
u vo. Khi vector dng nm trong sector 1 th
vector dng s c tng hp bi 2 vector ab v ac
nh Hnh 3 vi t s ng ct d
b
v d
c
nh din t
trong cng thc (2).
Bng 1: Cc trng thi ng ngt tng chnh lu
Sa Sb Sc Vdc_p Vdc_n Vdc ia ib ic
Vsa>Vsc Vsa Vsc Vac idc 0 -idc
Vsa<Vsc Vsc Vsa Vca -idc 0 idc
Vsb>Vsc Vsb Vsc Vbc 0 idc -idc
Vsb<Vsc Vsc Vsb Vcb 0 -idc idc
Vsb>Vsa Vsb Vsa Vba -idc idc 0
Vsb<Vsa Vsa Vsb Vab idc -idc 0
1 1 0
1 0 1
0 1 1

2.2 Phng php sng mang PWM cho tng
nghch lu kp
Tng nghch lu ca Hybrid Sparse Matrix ghp 3
bc bao gm 2 b nghch lu ngun p 2 bc c
ghp song song li vi nhau vi mc in p DC
trung bnh ca tng chnh lu tng ng l:
3
2.cos
m
in
V
Vdc
u
=
Ti dng cho tng nghch lu ghp ca Hybrid
Sparse Matrix 3 bc l ti 6 u dy nh Hnh 4a.
HA
HB
HC
SHAp SHBp SHCp
SHAn SHBn SHCn
SLAp SLBp SLCp
SLAn SLBn SLCn
Vdc
LA
LB
LC
O

(a)
HA
HB
HC
LA
LB
LC
O
VH
AO
VH
BO
VH
CO
VL
AO
VL
BO
VL
CO
VH
AO
VH
BO
VH
CO
VL
AO
VL
BO
VL
CO
V
AO
V
BO
V
CO
O
O
(b) (d)
Hnh 4. M hnh gii tch ca mch nghch lu ghp a
bc.
T s mch nghch lu ghp, khi xt cc mc p
pha HA, HB, HC v LA, LB, LC so vi im 0 ta c
c m hnh gii tch mch nghch lu ghp nh
Hnh 4.
T Bng 2, ta thy cc mc p nghch lu V
XO
=
(V
AO
,V
BO
,V
CO
) c 3 trng thi gi tr khc nhau (-Vd,
0, Vd). Do tng nghch lu p vi 2 b nghch lu
p 2 bc ghp song song l dng 3 bc.
Bng 2: Cc trng thi ng ngt tng nghch lu
SHXp SLXp VHXO VLXO VXO
0 1 0 Vd Vd
1 1 Vd Vd 0
0 0 0 0 0
1 0 Vd 0 Vd

Vi X=(A, B, C)
T gin phi hp ng ct ta thy tng chnh lu
chuyn mch t in p Vab sang in p Vbc th
pha nghch lu t s na chu k ca 2 sng mang
thay i tng ng nh theo t s chuyn mch d
b

v d
c
bn pha chnh lu .










(c)
0
1
2
Vab
Vac
V
cdk

V
bdk

V
adk

Nghch
lu
Chnh
lu
T
s
*d
c
T
s
*d
b
T
s

686
Hi ngh ton quc v iu khin v T ng ho - VCCA-2011


VCCA-2011
Hnh 5. Gin phi hp ng ct gia tng chnh lu
v nghch lu
3. Kt qu m phng v thc nghim
M hnh m phng cho HSMC c xy dng bi
MATLAB/Simulink.
Bng 3: Thng s m phng gii thut iu ch
sng mang PWM ca HSMC.
p ba pha u vo 50V/50Hz
Ti cn bng ba pha RL R=30, L=30mH
Tn s u ra 40Hz
T s iu ch 1.2
Tn s ng ct 10KHz
Lc u vo L=1mH, C=20F

S iu khin FPGA cho HSMC c trnh by
nh Hnh 6. M hnh thit k phn cng ca HSMC
trn Hnh 7.
Sensor
p
Khi iu
khin tng
chnh lu
Khi iu
khin tng
nghch lu
Tng chnh lu Tng nghch lu
Cosin
d1
XC3S1600E FPGA
Mch li cho cc kha link kin
ADC
Vsb Vsa
iA
iB
iC
isa isc isb
idc
Sa Sc
Vdc
Sb
SAp SBp SCp
SAn SBn SCn
L

u

v

o

L
C
Vsc
SAp SBp SCp
SAn SBn SCn
Hnh 6. S khi iu khin ca Hybrid Sparse Matrix
ghp 3 bc

Hnh 7. M hnh thc hin phn cng ca Hybrid Sparse
Matrix 3 bc
Gii thut iu khin sng mang PWM cho HSMC 3
bc c thit k ton b trn FPGA Spartan-3E
XC3S1600E Development kit ca Xilinx.
Gi tr tc thi in p ba pha u vo c o bi
3 cm bin p LEM LV 25-P. Gi tr analog t 3
cm bin p c chuyn sang gi tr s bi mch
ADC s dung IC AD7864. Cng kt ni m rng
trn card Xilinx FPGA XC3S1600E Spartan-3E
c ni ti mch ADC nhn gi tr s ca p ba
pha u vo t mch ADC v a ra cc xung kch
ti mch li IGBT. Mch li IGBT c thit k
da trn opto quang TLP251 cch ly mch iu
khin v mch cng sut. Khi cng sut ca
Hybrid Sparse Matrix ghp 3 bc s dng 15 kha
bn dn IGBT GT60M323 v 12 diode nhanh
RHR30120.
Bng 4: Ti nguyn logic c s dng thit k
gii thut iu khin trn FPGA cho Hybrid Sparse
Matrix ghp 3 bc

Bng 5: Thng s thc nghim ca HSMC 3 bc
p ba pha u vo 50V/50Hz
Ti cn bng ba pha RL R=30, L=30mH
Tn s u ra 40Hz
T s iu ch 1.2
Tn s ng ct 10KHz
Lc u vo L=1mH, C=20F


Cc kt qu m phng v thc nghim ca Gii
thut iu ch sng mang PWM cho Hybrid
Sparse Matrix ghp 3 bc

(a) M phng (b) Thc nghim (1
div=50V)
Hnh 8. Dng sng p pha ca ti.
Design Summary
--------------
Target Device : xc3s1600e
Target Package : fg320
Target Speed : -4
Number of Slice Flip Flops: 221 out of
29,504 1%
Number of occupied Slices: 8,983 out of
14,752 60%
Number of 4 input LUTs: 15,907 out of
29,504 53%
Number of bonded IOBs: 32 out of 250 12%
Number of BUFGMUXs: 2 out of 24 8%
Number of MULT18X18SIOs: 4 out of 36 11%

687
Hi ngh ton quc v iu khin v T ng ho - VCCA-2011


VCCA-2011



(a) M phng (b) Thc nghim (1
div=100V)
Hnh 9. Dng sng p dy ca ti.

(a) M phng (b) Thc nghim

(c) Ph FFT dng ti
Hnh 10. Dng ti ba pha RL


(a) M phng


(b) Thc nghim


(c) Ph FFT dng ngun
Hnh 11. Dng ngun v p ngun u vo
Cc sng p pha ti v p dy ti gia kt qu thc
nghim v kt qu m phng cho gii thut iu ch
sng mang PWM cho Hybrid Sparse Matrix ghp 3
bc hon ton trng khp nhau.
Vi cu trc ghp 3 bc vng iu khin p ra c
m rng. Kt qu thc nghim ca Hybrid Sparse
Matrix vi t s iu ch m
v
=1.2 cho thy p pha
ti c dng 3 bc v p dy c dng 5 bc. Cht
lng p ra c ci thin so vi cc b bin i
ma trn n.
Dng ti RL ca Hybrid Sparse Matrix l sin, ph
FFT cho thy dng ti khng c hi bc thp.
Dng ngun u vo sau khi lc c dng sin vi
cht lng cao, ph FFT ca dng ngun u vo
cho thy khng c hi bc thp v lch pha so
vi p ngun l rt thp h s cng sut u vo
bng 1.
4. Kt lun
Bi bo a ra cu trc HSMC ghp 3 bc v
gii thut iu ch sng mang PWM c a ra
p dng cho cu trc ny. Cc kt qu m phng v
thc nghim l trng khp nhau. Gii thut iu
khin cho HSMC 3 bc c thit k ton b trn
FPGA v vy kh nng thc thi song song v tc
tnh ton c ci thin ng k. Thi gian tnh
ton cho ton b gii thut iu ch sng mang
PWM trn FPGA ch khong 1us.
Kt qu thc nghim ca gii thut iu ch sng
mang PWM trn cu trc HSMC 3 bc cho thy
kh nng to ra sng dng ti c dng sin vi sng
dng ngun c dng sin cht lng cao v cng pha
so vi p ngun, h s cng sut u vo l bng 1.
Vng iu khin p ra c m rng v cht lng
p u ra c ci thin vi cu trc HSMC ghp 3
bc.
Ti liu tham kho
[1] M. Venturini and A. Alesina, The generalised
transformer: A new bidirectional sinusoidal
waveform frequency converter with continuously
adjustable input power factor, IEEE PESC. 1989.
688
Hi ngh ton quc v iu khin v T ng ho - VCCA-2011


VCCA-2011
[2] L. Wei and T.A. Lipo, A novel matrix
converter with simple commutation, Proceedings
of 36
th
IEEE Industry Applications Society
Conference (IAS2001), vol.3, pp. 1749-1754,
Chicago, IL, USA, 2001
[3] J.W. Kolar, F. Schafmeister, S.D. Round, H. Ertl,
Novel three-phase AC-AC sparse matrix converter,
IEEE Transactions on Power Electronics, Vol. 22,
Issue 5, Sept. 2007, pp. 1649 1661.
[4] Trn V, Nguyn Vn Nh, Space vector PWM
method for Ultra Sparse Matrix Converter using
FPGA XC3S500E, Tp ch Khoa hc Gio dc K
thut, s 15, trang7-15, Trng i hc S Phm K
Thut Tp H Ch Minh, 2010.

Trn V sinh nm 1985 ti
Thnh ph H Ch Minh, Vit
Nam. Anh nhn bng thc s
ngnh Thit b, mng v nh my
in ca trng i hc Bch
Khoa Thnh ph H Ch Minh
(HCMUT) nm 2011.
Hin anh ang l nghin cu vin
Phng Th nghim H thng nng lng (PERL
Lab) trng i hc Bch Khoa TP.HCM. Hng
nghin cu chnh l in t cng sut, Sparse Matrix
Converter v thit k cc b iu khin PWM trn nn
FPGA.

Nguyn Vn Nh tt nghip
k s nm 1988 v ph tin s
nm 1991 ti trng i hc
Ty Tip, Cng ha Sc. Anh
tham gia ging dy ti trng
i hc Bch khoa TP.HCM
t nm 1992, c phong
hm ph gio s nm 2007.
TS. Nh nghin cu v in
t cng sut v ng dng, c bit k thut iu ch
rng xung cho cc b bin tn a bc, b bin i
ma trn.

689