Cu 2.1 S khi chc nng ca mt h thng my tnh.

Khi x l trung tm (Central Processing Unit - CPU) l thnh phn quan trng nht - c xem l b no ca my tnh. CPU m nhim vic c cc lnh ca chng trnh t b nh, gii m v thc hin lnh. B nh trong, cn gi l b nh chnh (Internal Memory hay Main Memory) l kho cha lnh v d liu ca h thng v ca ngi dng phc v CPU x l. B nh trong thng l b nh bn dn, bao gm hai loi: (1) B nh ch c (Read Only Memory ROM) v (2) B nh truy cp ngu nhin (Random Access Memory RAM). ROM thng c s dng lu lnh v d liu ca h thng. B nh RAM thng c s dng lu lnh v d liu ca c h thng v ca ngi dng. Cc thit b vo ra (Input Output devices), hay cn gi l cc thit b ngoi vi (Peripheral devices) m nhim vic nhp d liu vo, iu khin h thng v kt xut d liu ra. C hai nhm thit b ngoi vi: (1) Cc thit b vo (Input devices) v (2) Cc thit b ra (Output devices). Cc thit b vo dng nhp d liu vo v iu khin h thng, cc thit b ra dng xut d liu ra. Bus h thng (System Bus) l mt tp cc ng dy kt ni CPU vi cc thnh phn khc ca my tnh. Bus h thng thng gm ba bus con: Bus a ch Bus A (Address bus), Bus d liu Bus D (Data bus), Bus iu khin - Bus C (Control bus). Bus a ch c nhim v truyn tn hiu a ch t CPU n b nh v cc thit b ngoi vi; Bus d liu vn chuyn cc tn hiu d liu theo hai chiu i v n CPU; Bus iu khin truyn tn hiu iu khin t CPU n cc thnh phn khc, ng thi truyn tn hiu trng thi ca cc thnh phn khc n CPU.

Cu 2.2

Kin trc von-Neumann da trn 3 khi nim c s: (1) Lnh v d liu c lu tr trong b nh c ghi chia s - mt b nh duy nht c s dng lu tr c lnh v d liu, (2) B nh c nh a ch theo vng, khng ph thuc vo ni dung n lu tr v (3) Cc lnh ca mt chng trnh c thc hin tun t. Qu trnh thc hin lnh c chia thnh 3 giai on (stages) chnh: (1) CPU c (fetch) lnh t b nh, (2) CPU gii m v thc hin lnh; nu lnh yu cu d liu, CPU c d liu t b nh; v (3) CPU ghi kt qu thc hin lnh vo b nh (nu c). Cu 2.3

Kin trc my tnh Harvard chia b nh trong thnh hai phn ring r: B nh lu chng trnh (Program Memory) v B nh lu d liu (Data Memory). Hai h thng bus ring c s dng kt ni CPU vi b nh lu chng trnh v b nh lu d liu. Mi h thng bus u c y ba thnh phn truyn dn cc tn hiu a ch, d

liu v iu khin. Kin trc my tnh Harvard c nhng u im so vi kin trc my tnh vonNeumann: My tnh da trn kin trc Harvard c kh nng t c tc x l cao hn my tnh da trn kin trc von-Neumann do kin trc Harvard h tr hai h thng bus c lp vi bng thng ln hn. Ngoi ra, nh c hai h thng bus c lp, h thng nh trong kin trc Harvard h tr nhiu lnh truy nhp b nh ti mt thi im, gip gim xung t truy nhp b nh, c bit khi CPU s dng k thut ng ng (pipeline). Cc my tnh hin i ngy nay s dng kin trc my tnh von-Neumann ci tin cn gi l kin trc my tnh von-Neumann hin i. Cu 2.4

Chu trnh x l lnh 1. Khi mt chng trnh c kch hot, h iu hnh (OS - Operating System) np m chng trnh vo b nh trong; 2. a ch ca nh cha lnh u tin ca chng trnh c np vo b m chng trnh PC; 3. a ch nh cha lnh t PC c chuyn n bus a ch thng qua thanh ghi MAR; 4. Bus a ch chuyn a ch nh n n v qun l b nh (MMU

Memory Management Unit); 5. MMU chn ra nh v thc hin lnh c ni dung nh; 6. Lnh (cha trong nh) c chuyn ra bus d liu v tip theo c chuyn tip n thanh ghi MBR; 7. MBR chuyn lnh n thanh ghi lnh IR; IR chuyn lnh vo b iu khin CU; 8. CU gii m lnh v sinh cc tn hiu iu khin cn thit, yu cu cc b phn chc nng ca CPU, nh ALU thc hin lnh; 9. Gi tr a ch trong b m PC c tng ln 1 n v lnh v n tr n a ch ca nh cha lnh tip theo; 10. Cc bc t 3-9 c lp li vi tt c cc lnh ca chng trnh. Cu 2.5

Khi iu khin (Control Unit CU) l mt trong cc khi quan trng nht ca CPU. CU m nhim vic iu khin ton b cc hot ng ca CPU theo xung nhp ng h. CU s dng nhp ng h ng b cc n v chc nng trong CPU v gia CPU vi cc b phn bn ngoi. Khi iu khin CU nhn ba tn hiu u vo: (1) Lnh t thanh ghi lnh IR, (2) Gi tr cc c trng thi ca ALU v (3) Xung nhp ng h CLK v CU sn sinh hai nhm tn hiu u ra: (1) Nhm tn hiu iu khin cc b phn bn trong CPU (Internal control signal) v (2) Nhm tn hiu iu khin cc b phn bn ngoi CPU (External control signal).

Khi s hc v logic (Arithmetic and Logic Unit ALU) m nhim chc nng tnh ton trong CPU. ALU bao gm mt lot cc n v chc nng con thc hin cc php ton s hc trn s nguyn v logic: B cng (ADD), b tr (SUB), b nhn (MUL), b chia (DIV), .... Cc b dch (SHIFT) v quay (ROTATE) B ph nh (NOT), b v (AND), b hoc (OR) v b hoc loi tr (XOR) Cu 2.6 Lnh my tnh (Computer Instruction) l mt t nh phn (binary word) c gn mt nhim v c th. Cc lnh ca chng trnh c lu trong b nh v chng ln lt c CPU c, gii m v thc hin. Chu k thc hin lnh (Instruction execution cycle) c nh ngha l khong thi gian m CPU thc hin xong mt lnh. Mt chu k thc hin lnh c th gm mt s giai on thc hin lnh v mt giai on thc hin lnh c th gm mt s chu k my. Chu k thc hin lnh c th gm cc thnh phn sau: Chu k c lnh Chu k c b nh (d liu) Chu k ghi b nh (d liu) Chu k c thit b ngoi vi Chu k ghi thit b ngoi vi

Chu k bus ri. Dng tng qut ca lnh my tnh gm c 2 phn chnh: (1) m lnh (opcode operation code) v (2) a ch ca cc ton hng (Addresses of Operands). Opcode Opcode Cu 2.7 Cc dng a ch Ton hng dng 3 a ch Dng: V d: ADD R1, R2, R3; R1 R2 + R3; R2 cng vi R3, kt qu lu vo R1. Ton hng dng 2 a ch Dng: opcode addr1, addr2 Mi a ch addr1, addr2 tham chiu n mt nh hoc mt thanh ghi. V d: ADD R1, R2; R1 ghi ca CPU. Dng: opcode addr2 a ch addr2 tham chiu n mt nh hoc mt thanh ghi. Ngoi ra, thanh ghi tch lu Racc c s dng v c vai tr nh addr1 trong ton hng dng 2 a ch. V d: ADD R2; Racc Racc + R2; Racc cng vi R2, kt qu lu vo Racc. Ton hng dng 1,5 a ch Dng: opcode addr1, addr2 Mt a ch tham chiu n mt nh v a ch cn li tham chiu n mt thanh ghi. Dng 1,5 a ch l dng ton hng hn hp gia nh v thanh ghi. V d: ADD R1, A; R1 R1 + M[A]; R1 + R2; R1 cng vi R2, kt qu lu vo R1. Ri l thanh opcode addr1, addr2, addr3 Mi a ch addr1, addr2, addr3 tham chiu n mt nh hoc mt thanh ghi. Addresses of Operands Destination addr. Source addr.

Hnh 19 Dng v cc thnh phn ca lnh

Ton hng dng 1 a ch

Ly ni dung ca R1 cng ni dung ca nh A, kt qu lu vo R1. R1 l thanh ghi ca CPU v A l a ch nh. Ton hng dng 0 a ch Ton hng 0 a ch thng c s dng trong cc lnh thao tc vi ngn xp: PUSH v POP. Cu 2.8 C ch ng lnh (pipeline) hay cn gi l c ch thc hin xen k cc lnh ca chng trnh l mt phng php thc hin lnh tin tin, cho php ng thi thc hin nhiu lnh, gim thi gian trung bnh thc hin mi lnh v nh vy tng c hiu nng x l lnh ca CPU. Vic thc hin lnh c chia thnh mt s giai on v mi giai on c thc thi bi mt n v chc nng khc nhau ca CPU. Nh vy CPU c th tn dng ti a nng lc x l ca cc n v chc nng ca mnh, gim thi gian ch cho tng n v chc nng. Vic thc hin lnh c chia thnh 5 giai on: Instruction Fetch - IF: c lnh t b nh (hoc cache); Instruction Decode - ID: gii m lnh v c cc ton hng; Execute - EX: thc hin lnh; nu l lnh truy nhp b nh: tnh ton a ch b nh; Memory Access - MEM: c/ghi b nh; no-op nu khng truy nhp b nh; no-op l giai on ch, tiu tn thi gian CPU, nhng khng thc hin thao tc c ngha; Write Back - WB: Ghi kt qu vo cc thanh ghi.

Cu 2.9

Cu trc phn cp h thng nh, gm cc phn chnh: cc thanh ghi ca CPU (CPU Registers), b nh cache (Cache), b nh chnh (Main Memory) v b nh ngoi (Secondary / Tertiary Storage). Trong cu trc phn cp h thng nh, dung lng cc thnh phn tng theo chiu t cc thanh ghi ca CPU n b nh ngoi. Ngc li, tc truy nhp hay bng thng v gi thnh mt n v nh tng theo chiu t b nh ngoi n cc thanh ghi ca CPU. Cu trc phn cp trong h thng nh c th gip tng hiu nng h thng l do n gip dung ho c CPU c tc cao v phn b nh chnh v b nh ngoi c tc thp. CPU s ch yu trc tip truy cp b nh cache c tc cao, v cache s c nhim v chuyn trc cc d liu cn thit v t b nh chnh Cu trc phn cp trong h thng nh c th gip gim gi thnh ch to h thng. C s chnh l trong h thng nh phn cp, cc thnh phn c tc cao v t tin c s dng vi dung lng rt nh, cn cc thnh phn c tc thp v r tin c s dng vi dung lng ln hn. Cu 2.10 RAM tnh (Static RAM hay SRAM) v RAM ng (Dynamic RAM hay DRAM). Mi bit RAM tnh cu to da trn mt mch lt (flip flop) cn gi l mch trig lng n (bistable latching circuit). Thng tin trong SRAM lun n nh v khng phi lm ti nh k. Tc truy nhp SRAM cng nhanh hn nhiu so vi DRAM. Ngc li, mi bit DRAM cu to da trn mt t in. Do bn cht ca t in lun c khuynh hng t phng in tch, thng tin trong bit DRAM s dn b mt. V vy, DRAM cn c lm ti (refresh) nh k bo ton thng tin. DRAM thng c tc truy cp thp hn so vi SRAM, nhng b li, DRAM c cu trc gn nh nn c th tng mt cy linh kin dn n gi thnh mt n v nh DRAM thp hn

SRAM. Cu 2.11 Cache hay cn gi l b nh m, b nh khay l mt thnh phn ca cu trc phn cp ca h thng b nh. Cache ng vai trong trung gian, trung chuyn d liu t b nh chnh v CPU v Ngc li. Vai tr ca cache tng t nh vai tr ca cu trc phn cp h thng nh: tng hiu nng h thng vo gim gi thnh sn xut. S d cache c th gip tng hiu nng h thng l nh cache c kh nng dung ho c CPU c tc cao v b nh chnh c tc thp, cache l mt loi b nh thng minh c kh nng on v chun b trc cc d liu cn thit cho CPU x l nn xc xut CPU phi trc tip truy nhp d liu t b nh chnh l kh thp. Cache c gi thnh trn mt n v nh cao hn b nh chnh, nhng do tng dung lng cache thng kh nh nn cache khng lm tng gi thnh h thng nh qu mc Nguyn l ln cn v khng gian c th pht biu nh sau: Nu mt nh ang c truy nhp th xc xut cc nh lin k vi n c truy nhp trong tng lai gn l rt cao. Ln cn v khng gian thng c p dng cho nhm lnh hoc d liu c tnh tun t cao trong khng gian chng trnh. Do cc lnh trong mt chng trnh thng tun t, cache c th c c khi lnh t b nh chnh v khi lnh c c bao ph c cc nh ln cn (neighbour cell) ca nh ang c truy nhp (current cell). Nguyn l ln cn v thi gian ch trng hn n tnh lp li ca vic truy nhp cc mu thng tin trong mt khong thi gian tng i ngn. C th pht biu nguyn l ny nh sau: Nu mt nh ang c truy nhp th xc xut n c truy nhp li trong tng lai gn l rt cao. Ln cn v thi gian c p dng cho d liu v nhm cc lnh trong vng lp. Vi cc phn t d liu, chng c CPU cp nhp thng xuyn trong qu trnh thc hin chng trnh nn c tnh ln cn cao v thi gian. Vi cc lnh trong vng lp, chng thng c CPU thc hin lp i lp li nhiu ln nn cng c tnh ln cn cao v thi gian; nu cache np sn khi lnh cha c vng lp s ph c tnh ln cn v thi gian. Cu 2.12 Chun ghp ni ATA/IDE/PATA Chun ghp ni ATA/IDE/PATA s dng cp dt 40 hoc 80 si ghp ni cng vi bng mch chnh ca my tnh. Mi cp thng h tr ghp ni vi 2 a: mt a ch (master) v mt a t (slave). Bng thng ng truyn l 16 bt, t cc

mc thng lng theo tn s lm vic: 16, 33, 66, 100 v 133MB/s. Chun ghp ni SATA Chun SATA s dng cng tp lnh mc thp nh chun ATA nhng SATA s dng ng truyn tin ni tip tc cao qua 2 i dy vi b iu khin SATA s dng chun AHCI (Advanced Host Controller Interface). SATA h tr nhiu tnh nng tin tin vt tri so vi ATA, nh truyn d liu nhanh v hiu qu hn v c bit l tnh nng cm nng (hot plug). SATA cung cp tc truyn d liu cao hn nhiu so vi ATA. Vi SATA th h 1, tc t 1,5 Gb/s v ln lt t 3,0 Gb/s v 6,0 Gb/s vi cc th h 2 v th h 3. Chun ghp ni SCSI SCSI l mt tp cc chun v kt ni vt l v truyn d liu gia my tnh v thit b ngoi vi, thng c s dng trong cc my ch. Tt c cc thit b SCSI u kt ni n bus SCSI theo cng mt kiu v mi bus SCSI c th kt ni 8-16 thit b SCSI. Tng t SATA, chun SCSI cng cung cp nhiu tnh nng tin tin nh tc truyn d liu v tnh n nh rt cao v tnh nng cm nng. Tnh nng cm nng rt hu dng trong cc my ch do SCSI cho php thm, bt cc cng m khng phi tt my, gim thi gian ngng cung cp dch v. SCSI t c tc truyn d liu: 5, 10, 20, 40MB/s vi cc SCSI c v 160, 320, 640 MB/s vi cc SCSI mi. Cc cng SCSI thng rt t tin v c thng c s dng cho cc my ch v cc h thng lu tr tin tin nh RAID, NAS v SAN.

Cu 2.13

Vic c thng tin trn a quang c thc hin trong a quang (Optical Disk Drive), nh minh ho trn Hnh 59 theo cc bc: 1. Tia laser t it pht laser i qua b tch tia n gng quay; 2. Gng quay c iu khin bi tn hiu c, li tia laser n v tr cn c trn mt a; 3. Tia phn x t mt a phn nh mc li lm trn mt a quay tr li gng quay; 4. Gng quay chuyn tia phn x v b tch tia v sau n b cm bin quang in; 5. B cm bin quang in chuyn i tia laser phn x thnh tn hiu in u ra. Cng ca tia laser c biu din thnh mc tn hiu ra. Cu 2.14

Nguyn l hot ng ca my in laser T rng cm quang c np mt lp in tch nh 1 in cc; Tia laser t ngun sng laser i qua mt gng quay v b iu ch tia c iu khin bi tn hiu cn in n mt trng; nh sng laser lm thay i mt in tch trn mt trng; Nh vy, mt in tch trn mt trng thay i theo tn hiu cn in; Khi trng cm quang quay n hp mc th in tch trn trng ht cc ht mc c tch in tri du. Cc ht mc dnh trn trng biu din m bn ca vn bn/thng tin cn in; Giy t khay c ko ln cng c in cc np in tch tri du vi in tch ca mc nn ht cc ht mc khi trng cm quang. Giy tip tc i qua trng sy nng lm cc ht mc chy ra v b p cht vo giy. Cu 2.15