Bi 1: Mt b cng y c m t trong hnh di y:

Hinh 2.1.a. S tng qut v b cng y Trong , a , b l cc bit vo cho b cng, cin l bit nh. u ra s l bit tng, cout l bit nh ra. Hot ng ca mch c ch ra di dng bng chn l:

Hnh 2.1.b. Bng chn l ca b cng y a. Vit chng trnh m t b cng trn bng ngn ng VHDL. b. M phng kim tra nguyn l ca b cng trn phn mm ISE. Bi 2: H gii m 2-4.

Hnh 2.2 B gii m 2 4 Bng s tht INPUT En B 0 X 1 0 1 0 1 1 1 1 A X O 1 0 1 Y0 0 0 0 0 1 OUTPUT Y1 Y2 0 0 0 0 0 1 1 0 0 0 Y3 0 1 0 0 0

a. Vit on chng trnh m t b gii m 2 sang 4 bng ngn ng VHDL. b. M phng kim tra nguyn l hot ng ca b gii m trn phn mm ISE.

Bi 3: GII M 3-8:

Hnh 2.3: Gii m 3-8 Bng s tht nh sau: En 0 1 1 1 1 1 1 1 1 INPUT C B X X 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 A X 0 1 0 1 0 1 0 1 Y7 0 0 0 0 0 0 0 0 1 Y6 0 0 0 0 0 0 0 1 0 Y5 0 0 0 0 0 0 1 0 0 OUTPUT Y4 Y3 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 Y2 0 0 0 1 0 0 0 0 0 Y1 0 0 1 0 0 0 0 0 0 Y0 0 1 0 0 0 0 0 0 0

a. Vit on chng trnh m t b gii m 3 sang 8 bng ngn ng VHDL. b. M phng kim tra nguyn l hot ng ca b gii m trn phn mm ISE. Bi 4: B chn knh Mux 41

Hnh 2.4 Mux 41 a. Vit on chng trnh m t b chn knh 4 1bng ngn ng VHDL. b. M phng kim tra nguyn l hot ng ca Mux 4 1 trn phn mm ISE. Bi 5: B chn knh Mux 81

Hnh 2.5 Mux 81 a. Vit on chng trnh m t b chn knh 8 1bng ngn ng VHDL. b. M phng kim tra nguyn l hot ng ca Mux 8 1 trn phn mm ISE. Bi 6: GII M BCD- LI LED 7 ON. Bng s tht nh sau. OE O 1 INPUT D C B X X X 0 0 0 DISPLAY OUTPUT A X 0 blank 0

1 0 0 0 1 1 1 0 0 1 0 2 1 0 0 1 1 3 1 0 1 0 0 4 1 0 1 0 1 5 1 0 1 1 0 6 1 0 1 1 1 7 1 1 0 0 0 8 1 1 0 0 1 9 1 1 0 1 0 blank 1 1 0 1 1 blank 1 1 1 0 0 blank 1 1 1 0 1 blank 1 1 1 1 0 blank 1 1 1 1 1 blank a. Vit on chng trnh m t b gii m BCD sang led 7 on bng ngn ng VHDL. b. M phng kim tra nguyn l hot ng b gii m trn phn mm ISE. Bi 7: Thit k b m ln 4 bit
clk Counter 4 bit Reset cnt[30]

Hnh 5.3 B m ln 4 bit a. Vit chng trnh m t b counter 4 bit bng ngn ng VHDL. b. M phng kim tra kt qu trn phn mm ISE. Bi 7: Mch iu khin 8 Led sng dn ri tt dn nh hnh 4.6 a. Vit chng trnh m t mch trn bng ngn ng VHDL. b. M phng kim tra kt qu bng phn mm ISE.

Hnh 5.6: Mch iu khin 8 LED sng dn tt dn Bng s tht: A[3..0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 LED7 LED6 LED5 LED4 LED3 LED2 LED1 LED0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 0 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 1 0 0 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 0 0 0 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0

Bi 9: Mch iu khin 8 LED sng t trong sng ra ngoi ri tt dn t ngoi vo trong.

Hnh 5.8 Mch iu khin 8 led Bng s tht A[2..0] LED7 LED6 LED5 LED4 LED3 LED2 LED1 LED0 000 0 0 0 1 1 0 0 0 001 0 0 1 1 1 1 0 0 010 0 1 1 1 1 1 1 0 011 1 1 1 1 1 1 1 1 100 0 1 1 1 1 1 1 0 101 0 0 1 1 1 1 0 0 110 0 0 0 1 1 0 0 0 111 0 0 0 0 0 0 0 0 a. Vit chng trnh mch iu khin 8 LED sng t trong sng ra ngoi ri tt dn t ngoi vo trong bng ngn ng VHDL. b. M phng kim tra hot ng ca mch bng phn mm ISE. Bi 10: a. Vit chng trnh theo m t mch m ln cc s chn t 6 n 15 b. M phng kim tra kt qu trn phn mm ISE BI 1: HNG DN S DNG PHN MM ISE A. MC TIU: - Cc bc ca qu trnh nhp file ngun. - Kim tra li c php - To file m phng - M phng kim tra kt qu
B. DNG C - THIT B, VT T TH NGHIM CHO MT SV : 1. Vt t cn thit cho mt nhm : STT Chng loi Quy cch vt t S lng n v Ghi ch

Kit thc hnh Spartan 3E

2. Dng c - Thit b cn thit cho mt nhm : STT Chng loi Quy cch vt t S lng 1 n v 1 Ghi ch

1 Computer C. NI DUNG THC HNH

1.1 Bin son file ngun 1.1.1 Khi ng chng trnh ISE

Kch p vo biu tng ISE trn destop

Giao din ca chng trnh

ng ca s Tip of the day

To project mi:

Vo file New Project

Nhp tn project

Sau khi nhp tn project xong, chn next

C th b qua bc ny hoc ci t ging nh hnh

Ci t xong tip tc chn Next

Chn New source

Chn New soure

Nhp tn file v chn VHDL module, sau chn Next

Nhp tn cc chn ca tn hiu vo v ra, sau chn Next

Chn Finish

Chn Finish

Chn Next

Tip tc chn Next v finish cho n khi giao din nhp file VHDL xut hin

Nhp file VHDL vo. library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity and2 is Port ( A : in STD_LOGIC; B : in STD_LOGIC; C : out STD_LOGIC); end and2; architecture Behavioral of and2 is begin C<= A and B; end Behavioral; Chn Behavior Simulation

Chn Behavior Simulation

Kch vo du + Xilinx ISE Simulator

Kch vo du +

1.2 Kim tra li c php v bin dch. Chn Save lu file, Kich p vo Check Syntax kim tra li

Kich p vo Check Syntax

Kim tra li c php v bin

dch thnh cng

1.3 To file m phng

Kch phi vo file and2.vhd, sau chn New Source

Nhp tn file and2_tb v chn Test Bench WaveForm

Chn Next.

Chn Next

Tip tc chn Finsh giao din ca ca s m phng xut hin. Ci t thi gian m phng.

Ng vo A c thit lp, n dng xung clock.

Ng vo A c thit lp sn dng Xung clock

Thit lp tn hiu vo B.

Kch tri chut ti v tr ln v xung tng ng vi khong thi gian mc cao ca B to dng sng cho ng vo B nh hnh

Chn biu tng Save lu file

Chn biu tng Save lu file

1.4 M phng thit k

Chn Processes

Kch tri vo du +

Kch p vo chc nng Simulate Behavioral Model

Kt qu m phng