VI IU KHIN PIC16F877A

1. GII THIU CHUNG V PIC

Hnh 1. S chn ca PIC16F877A PIC l tn vit tt ca My tnh kh trnh thng minh (Programable Intelligent Computer) do hng General Instrument t tn, con vi iu khin u tin ca h l PIC1650. Hng Microchip tip tc pht trin cc dng sn phm ny. Cho n nay, cc sn phm vi iu khin PIC ca Microchip gn 100 loi, t h 10Fxxx n cc h 12Cxxx, 17Cxx, 16Fxx, 16Fxxx, 16FxxxA, 16LFxxxA, 18Fxxx 18LFxxx, 2. PHN LOI PIC THEO K T: Nhm th nht c k t C, h PIC xxCxxx c a vo mt nhm, gi l OTP (One Time Programable) ch c th lp trnh mt ln duy nht. Nhm th hai c k t F, LF, h PIC xxFxxx, xxFxxx, gi l Flash, cho php ghi/xa nhiu ln bng cc mch in thng thng.

3. PHN LOI PIC THEO K S: Loi th nht l dng PIC c bn (Base-Line), gm cc PIC 12Cxxx, c di lnh l 12 bit. Loi th hai l cc dng PIC 10F, 12F, v 16F, gi l dng ph thng (MidRange), c di lnh l 14 bit. Loi th ba l dng PIC 18F (High-End), c di lnh l 16 bit. PIC l mt vi iu khin vi kin trc RISC, s dng microcode n gin t trong ROM, chy mt lnh mt chu k my (4 chu k ca b dao ng). PIC nh c EEPROM nn to thnh 1 b iu khin vo ra kh trnh, c rt nhiu dng PIC vi hng lot cc m-un ngoi vi tch hp sn (nh USART, PWM, ADC...), vi b nh chng trnh t 512 Word n 32K Word. PIC16F877A l dng PIC ph bin nht, mnh v tnh nng, 40 chn, b nh ln cho hu ht cc ng dng thng thung. 4. Cu trc tng qut PIC16F877A gm: 8 K Flash ROM 368 bytes RAM 256 bytes EEPROM 5 Port I/O (A, B, C, D, E), ng vo/ra vi tn hiu iu khin c lp 2 b nh thi 8 bit Timer 0 v Timer 2 1 b nh thi 16 bit Timer 1, c th hot ng trong c ch tit kim nng lng (Sleep Mode) vi ngun xung clock ngoi 2 b CCP, Capture/Compare/PWM - tm gi l: Bt gi / So snh / iu Bin xung 1 b bin i tng t - s (ADC) 10 bit, 8 ng vo 2 b so snh tng t (Comparator) 1 b nh thi gim st (WDT - Watch Dog Timer) 1 cng song song ( Parallel Port ) 8 bit vi cc tn hiu iu khin 1 cng ni tip ( Serial Port )

 15 ngun ngt (Interrupt) Ch tit kim nng lng (Sleep Mode) Np chng trnh bng cng ni tip ICSPTM (In-Circuit Serial Programing) Ngun dao ng lp trnh c to bng cng ngh CMOS 35 tp lnh c di 14 bit. Tn s hot ng ti a l 20 MHz * Cu trc phn cng PIC16F877A: PIC l mt vi iu khin vi kin trc RISC, chy mt lnh mt chu k my (4 chu k ca b dao ng). PIC16F877A l h vi iu khin c 40 chn, mi chn c mt chc nng khc nhau. Trong c mt s chn a cng dng (a hp), mi chn c th hot ng nh mt ng xut/nhp (I/O) c lp hoc l mt chc nng c bit dng giao tip vi cc thit b ngoi vi.

Hnh . S khi ca vi iu khin PIC16F877A 5. T CHC B NH Cu trc b nh ca vi iu khin PIC16F877A bao gm b nh ( Program memory) v b nh d liu ( Data memory). 5.1. B nh chng trnh:

Hnh 3. B nh chng trnh PIC16F877A B nh chng trnh ca vi iu khin PIC16F877A l b nh flash, dung lng b nh 8K word ( 1 word = 14 bit) v c phn thnh nhiu trang ( t page 0 n page 3). Nh vy b nh chng trnh c kh nng cha c 8*1024=8192 lnh ( v mt lnh sau khi m ha s c dung lng mt word( 14 bits). m ha c a ch ca 8K word b nh chng trnh, b m chng trnh c dung lng 13 bit( PC<12:0>). Khi vi iu khin c reset, b m chng trnh s ch n a ch 000h ( Reset vector). Khi c ngt xy ra, b m chng trnh s ch n a ch 0004h ( Interrupt vector).

B nh chng trnh khng bao gm b nh stack v khng c a ch ha bi b m chng trnh. B nh stack s c cp c th phn sau. 5.2.B nh d liu B nh d liu ca PIC l b nh EEPROM c chia ra lm nhiu bank. i vi PIC16F877A b nh d liu c chia ra lm bn bank. Mi bank c dung lng 128 bytes, bao gm cc thanh ghi c chc nng c bit SFG ( Special Function Register) nm cc vng a ch thp v cc thanh ghi mc ch chung GPR ( General Purpose Register) nm vng a ch cn li trong bank. Cc thanh ghi SFR thng xuyn c s dng ( v d nh thanh ghi STATUS) s c t tt c cc bank ca b nh d liu gip thun tin trong qu trnh truy xut v lm gim bt lnh ca chng trnh. S c th ca b nh d liu PIC16F877A nh sau:

Hnh 4. S b nh d liu PIC16F877A 5.2.1.THANH GHI CHC NNG C BIT SFR y l cc thanh ghi c s dng bi CPU hoc c dung thit lp v iu khin cc khi chc nng c tch hp bn trong vi iu khin. C th phn thanh ghi SFR ra lm hai loi: thanh ghi SFR lin quan n chc nng

bn trong ( CPU) v thanh ghi SFR dng thit lp v iu khin cc khi chc nng bn ngoi ( v d nh ADC, PWM,). Phn ny s cp n cc thanh ghi lin quan n cc chc nng bn trong. Thanh ghi STATUS (03h,83h,103h,183h): thanh ghi cha kt qu thc hin php ton ca khi ALU, trng thi reset v cc bit chn bank cn truy xut trong b nh d liu.

Thanh ghi OPTION_REG( 81h,181h): thanh ghi ny cho php c v ghi, cho php iu khin chc nng pull-up ca cc chn trong PORTB, xc lp cc tham s v xung tc ng, cnh tc ng ca ngt ngoi vi v b m ca Timer0. Thanh ghi INTCON (0Bh,8Bh,10Bh,18Bh): thanh ghi cho php c v ghi, cha cc bit iu khin v cc bit c hiu khi timer0 b trn, ngt ngoi vi RB0/INT v ngt interrupt-on-change ti cc chn ca PORTB. Thanh ghi PIE1 (8Ch): cha cc bit iu khin chi tit cc ngt ca cc khi chc nng ngoi vi. Thanh ghi PIR1 ( 0Ch) cha c ngt ca cc khi chc nng ngoi vi, cc ngt ny c cho php bi cc bit iu khin cha trong thanh ghi PIE1. Thanh ghi PIE2( 8Dh): cha cc bit iu khin cc ngt ca cc khi chc nng CCP2, SSP bus, ngt ca b so snh v ngt ghi vo b nh EEPROM. Thanh ghi PIR2 (0Dh): cha cc c ngt ca cc khi chc nng ngoi vi, cc ngt ny c cho php bi cc bit iu khin cha trong thanh ghi PIE2. Thanh ghi PCON ( 8Eh): cha cc c hiu cho bit trng thi cc ch reset ca vi iu khin. 5.2.2. THANH GHI MC CH CHUNG GPR Cc thanh ghi ny c th c truy xut trc tip hoc gin tip thng qua thanh ghi FSG ( File Select Register). y l cc thanh ghi d liu thng thng, ngi s dng c th ty theo mc ch chng trnh m c th dng cc thanh ghi ny cha cc bin s, hng s, kt qu hoc cc tham s phc v cho chng trnh. 5.2.3. STACK Stack khng nm trong b nh chng trnh hay b nh d liu m l mt vng nh c bit khng cho php c hay ghi. Khi lnh CALL c thc hin hay khi mt ngt xy ra lm chng trnh b r nhnh, gi tr ca b m chng trnh PC t ng c vi iu khin ct vo trong stack. Khi mt

lnh RETURN, RETLW hay RETFIE c thc thi, gi tr PC s t ng c ly ra t trong stack, vi iu khin s thc hin tip chng trnh theo ng qui trnh nh trc. B nh Stack trong vi iu khin PIC h 16F87xA c kh nng cha c 8 a ch v theo c ch xoay vng. Ngha l gi tr ct vo b nh Stack ln th 9 s ghi ln gi tr ct vo Stack ln u tin v gi tr ct vo b nh Stack ln th 10 s ghi ln gi tr ct vo Stack ln th hai. Cn ch l khng c c hiu no cho bit trng thi Stack, do ta khng bit c khi no Stack trn. Bn cnh tp lnh ca vi iu khin dng PIC cng khng c lnh POP hay PUSH, cc thao tc vi b nh Stack s hon ton c iu khin bi CPU. 6. CC CNG XUT NHP CA PIC16F877A Cng xut nhp (I/O port) chnh l phng tin m vi iu khin dng tng tc vi th gii bn ngoi. S tng tc ny rt a dng v thng qua qu trnh tng tc , chc nng ca vi iu khin c th hin mt cch r rng. Mt cng xut nhp ca vi iu khin bao gm nhiu chn ( I/O pin), ty theo cch b tr v chc nng ca vi iu khin m s lng cng xut nhp thng thng, mt s chn xut nhp cn c thm chc nng khc th hin s tc ng ca cc c tnh nu trn i vi th gii bn ngoi. Chc nng ca tng chn xut nhp trong mi cng hon ton c th c xc lp v iu khin c thng qua cc thanh ghi SFR lin quan n chn xut nhp . Vi iu khin PIC16F877A c 5 cng xut nhp, bao gm PORTA, PORTB, PORTC, PORTD v PORTE. Cu trc v chc nng ca tng cng xut nhp s c cp c th trong phn sau. 6.1 PORTA PORTA (RPA) bao gm 6 I/O pin. y l cc hai chiu ( bidirectional pin ), ngha l c th l xut v nhp c. Chc nng I/O ny c iu khin bi thanh ghi TRISA ( a ch 85h). Mun xc lp chc nng ca mt chn trong PORTA l output, ta clear bit iu khin tng ng vi chn trong thanh ghi TRISA. Thao tc ny hon ton tng t i vi cc PORT v cc thanh ghi iu khin tng ng TRIS ( i vi PORTA l TRISA, i vi PORTB l TRISB, i vi PORTC l TRISC, i vi PORTD l TRISD v i vi PORTE l TRISE). Bn cnh PORTA cn l ng ra ca b ADC, b so snh, ng vo analog ng vo xung clock ca Timer0 v ng vo ca b giao tip MSSP ( Master Synchronous Serial Port ). c tnh tnh ny s c trnh by phn sau.

Cc thanh ghi SFR lin quan n PORTA bao gm:

PORTA ( a ch 05h) : cha gi tr cc pin trong PORTA. TRISA ( a ch 85h): iu khin xut nhp. CMCON ( a ch 9Ch): thanh ghi iu khin b so snh. CVRCON ( a ch 9Dh): thanh ghi iu khin b so snh in p. ADCON1 ( a ch 9Fh): thanh ghi iu khin b ADC. 6.2. PORTB PORTB ( RPB) gm 8 pin I/O. Thanh ghi iu khin xut nhp tng ng l TRISB. Bn cnh mt s chn ca PORTB cn c s dng trong qu trnh np chng trnh cho vi iu khin vi ch np khc nhau. PORTB cn lin quan ngt ngoi vi v b Timer0. PORTB cn c tch hp chc nng in tr ko ln c iu khin bi chng trnh. Cc thanh ghi SFR lin quan n PORTB bao gm: PORTB ( a ch 06h,106h): cha gi tr cc pin trong PORTB TRISB ( a ch 86h,186h): iu khin xut nhp OPTION_REG ( a ch 81h, 181h): iu khin ngt ngoi vi v b Timer0. Chi tit cc thanh ghi s c trnh by c th ph lc 2. 6.3. PORTC PORTC ( RBC) gm 8 pin I/O. Thanh ghi iu khin xut nhp tng ng l TRISC. Bn cnh PORTC cn cha cc chc nng ca b so snh, b Timer1, b PWM v cc chun giao tip I2C, SPI, SSP, USART. Cc thanh ghi iu khin lin quan n PORTC: PORTC ( a ch 07h): cha gi tr cc pin trong PORTC TRISC ( a ch 87h): iu khin xut nhp. Cc chi tit v cc thanh ghi s c trnh by c th trong ph lc 2. 6.4. PORTD PORTD gm 8 chn I/O, thanh ghi iu khin xut nhp tng ng TRISD. PORTD cn l cng xut d liu ca chun giao tip PSP ( Parallel Slave Port ). Cc thanh ghi lin quan n PORTD bao gm: Thanh ghi PORTD: cha gi tr cc pin trong PORTD.

Thanh ghi TRISD: iu khin xut nhp. 6.5. PORTE PORTE (RPE) gm 3 chn I/O. Thanh ghi iu khin xut nhp tng ng l TRISE. Cc chn ca PORTE c ng vo l analog. Bn cnh cn c cc chn iu khin ca chun giao tip PSP. Cc thanh ghi lin quan n PORTD bao gm Thanh ghi PORTE: cha gi tr cc pin trong PORTE. Thanh ghi TRISE: iu khin xut nhp PORTE v chun giao tip PSP. ADCON1: thanh ghi iu khin khi ADC. 7.TIMER0 y l mt trong ba b m hoc b nh thi ca Vi iu khin PIC16F877A. Timer0 l b m 8 bit c kt ni vi b chia tn s (prescaler) 8 bit. Cu trc ca Timer 0 cho php ta la chn xung clock tc ng v cnh tch cc ca xung clock. Ngt Timer 0 s xt hin hki Timer 0 b trn. Bit TMR0IE (INTCON<5>) l bit iu khin ca Timer 0. TMR0IE=1 cho php ngt Timer 0 hot ng v ngc li. Mun Timer 0 hot ng ch Timer ta clear bit TOSC (OPTION_REG<5>), khi gi tr thanh ghi TMR0 s tng theo tng chu k ng h. Khi gi tr thanh ghi TMR0 t gi tr FFh v 00h, ngt Timer 0 s xut hin. Thanh ghi TMR0 cho php ghi v xa c gip ta n nh thi im ngt Timer0 xut hin mt cch linh hot. Mun Timer0 hot ng ch Counter ta set bit TOSC ( OPTION_REG<5>). Khi xung tc ng ln b m c ly t chn RA4/ TOCK1. Bit TOSE ( OPTION_REG<4>) cho php la chn cnh tc ng vo b m. Cnh tc ng s l cnh ln nu TOSE=0 v cnh tc ng s l cnh xung nu TOSE=1. Khi thanh ghi TMR0 b trn, bit TMR0IF ( INTCON<2>) s c set. y chnh l c ngt ca Timer0. C ngt ny phi c xa bng chng trnh trc khi b m bt u thc hin li qu trnh m. Ngt Timer0 khng th nh thc vi iu khin t ch sleep. B chia tn s ( prescaler) c chia s gia Timer0 v WDT ( Watchdog Timer). iu c ngha l nu prescaler c s dng cho Timer0 th WDT s khng c c h tr ca prescaler v ngc li. Prescaler c iu khin bi thanh ghi OPTION_REG. Bit PSA ( OPTION_REG <3>) xc nh i tng tc ng ca prescaler. Cc bit PS2:PS0 ( OPTION_REG<2:0>) xc nh t s chia tn s ca prescaler. Xem li thanh ghi OPTION_REG xc nh li mt cch chi tit v cc bit iu khin trn. Cc lnh tc ng ln gi tr thanh ghi TMR0 s xa ch hot ng ca prescaler. Khi i tng tc ng l Timer0, tc ng ln gi tr thanh ghi TMR0 s xa cc

prescaler nhng khng lm thay i i tng tc ng ca prescaler. Khi i tng tc ng l WDT, lnh CLRWDT s xa prescaler, ng thi prescaler s ngng tc v h tr cho WDT. Cc thanh ghi iu khin lin quan n Timer0 bao gm: TMR0 ( a ch 01h,101h): cha gi tr m ca Timer0. INTCON( a ch 0Bh, 8Bh, 10Bh, 18Bh): cho php ngt hot ng ( GIE v PEIE). OPTION_REG ( a ch 81h, 181h): iu khin prescaler. Chi tit cc thanh ghi s c trnh by c th trong ph lc 2. 8. TIMER1 Timer1 l b nh thi 16 bit, gi tr ca hai Timer1 s c lu trong hai thanh ghi ( TMR1H:TML1R). C ngt ca Timer1 l bit TMR1IF ( PIR<0>). Bit iu khin ca Timer1 s l TMR1IE ( PIE<0>). Tng t nh Timer0, Timer1 cng c hai ch hot ng: ch nh thi ( timer) vi xung kch l xung clock ca oscillator ( tn s ca timer bng tn s ca oscillator) v ch m ( counter) vi xung kch l xung phn nh cc s kin cn m ly t bn ngoi thng qua chn RC0/T1OSO/T1CKI ( cnh tc ng l cnh ln). Vic la chn xung tc ng ( tng ng vi vic la chn ch hot ng l timer hay counter) c iu khin bi bit TMR1CS (T1CON<1>). Ngoi ra Timer1 cn c chc nng reset input bn trong c iu khin bi mt trong hai khi CCP ( Capture/ Compare/ PWM). Khi bit T1OSCEN ( T1CON<3>) c set, Timer1 s ly xung clock t hai chn RC1/T1OSI/CCP2 v RC0/T1OSO/T1CKI lm xung n. Timer1 s bt u m sau cnh xung u tin ca xung ng vo. Khi PORTC s b qua s tc ng ca hai bit TRISC<1:0> v PORTC<2:1> c gn gi tr 0. Khi clear bit T1OSCEN Timer1 s ly xung m t oscillator hoc t chn RC0/T1OSO/T1CKI. Timer1 c hai ch m l ng b ( Synchronous) v bt ng b ( Asynchronous). Ch m c quyt nh bi bit iu khin (T1CON<2>). Khi =1 xung m ly t bn ngoi s khng c ng b ha vi xung clock bn trong, Timer1 s tip tc qu trnh m khi vi iu khin ang ch sleep v ngt do Timer1 to ra khi b trn c kh nng nh thc vi iu khin. ch m bt ng b, Timer1 khng th c s dng lm ngun xung clock cho khi CCP ( Capture/ Compare/ Pulse width modulation). Khi =0 xung m vo Timer1 s c ng b ha vi xung clock bn trong. ch ny Timer1 s khng hot ng khi vi iu khin ang ch sleep. Cc thanh ghi lin quan n Timer1 bao gm: INTCON ( a ch 0Bh, 8Bh, 10Bh, 18Bh): cho php ngt hot ng ( GIE v PEIE).

PIR1 ( a ch 0Ch): cha c ngt Timer1 ( TMR1IF). PIE1 ( a ch 8Ch): cho php ngt Timer1 ( TMR1IE). TMR1L ( a ch 0Eh): cha gi tr 8 bit thp ca b m Timer1. TMR1H ( a ch 0Eh): cha gi tr 8 bit cao ca b m Timer1. T1CON ( a ch 10h): xc lp cc thng s cho Timer1. Chi tit cc thanh ghi s c trnh by c th trong ph lc 2. 9. TIMER2 Timer2 l b nh thi 8 bit v c h tr bi hai b chia tn s prescaler v postscaler. Thanh ghi cha gi tr m ca Timer2 l TMR2. Bit cho php ngt Timer2 tc ng l TMR2ON ( T2CON<2>). C ngt ca Timer2 l bit TMR2IF ( PIR1<1>). Xung ng vo ( tn s bng tn s oscillator) c a qua b chia tn s prescaler 4 bit ( vi cc t s chia tn s l 1:1, 1:4 hoc 1:16 v c iu khin bi cc bit T2CKPS1:T2CKPS0 (T2CON<1:0>)). Timer2 cn c h tr bi thanh ghi PR2. Gi tr m chng trnh trong thanh ghi TMR2 s tng t 00h n gi tr cha trong PR2, sau c reset v 00h. Khi reset thanh ghi PR2 c nhn gi tr mc nh FFh. Ng ra ca Timer2 c a qua b chia tn s postscaler vi cc mc chia t 1:1 n 1:16. Postscaler c iu khin bi 4 bit T2OUTPS3:T2OUTPS0. Ng ra ca postscaler ng vai tr quyt nh trong vic iu khin c ngt. Ngoi ra ng ra ca Timer2 cn c kt ni vi khi SSP, do Timer2 cn ng vai tr to ra xung clock ng b cho khi giao tip SSP. Cc thanh ghi lin quan n Timer2 bao gm: INTCON ( a ch 0Bh, 8Bh, 10Bh, 18Bh): cho php ton b cc ngt ( GIE v PEIE). PIR1( a ch 0Ch): cha c ngt Timer2 ( TMR2IF). PIE1 ( a ch 8Ch): cha bit iu khin Timer2 ( TMR2IE). TMR2 ( a ch 11h): cha gi tr m ca Timer2. T2CON ( a ch 12h): xc lp cc thng s cho Timer2. PR2 ( a ch 92h): thanh ghi h tr cho Timer2. Chi tit cc thanh ghi s c trnh by c th trong phn ph lc 2. Ta c mt s nhn xt v Timer0, Timer1 v Timer2 nh sau:

Timer0 v Timer2 l b m 8 bit ( gi tr m ti a l FFh), trong khi Timer1 l b m 16 bit ( gi tr m ti a l FFFFh). Timer0, Timer1 v Timer2 u c hai ch hot ng l timer v counter. Xung clock c tn s bng tn s ca oscillator. Xung tc ng ln Timer0 c h tr bi prescaler v c th c thit lp nhiu ch khc nhau ( tn s tc ng, cnh tc ng) trong khi cc thng s ca xung tc ng ln Timer1 l c nh. Timer2 c h tr bi hai b chia tn s prescaler v postcaler c lp, tuy nhin cnh tc ng vn c c nh l cnh ln. Timer1 c quan h vi khi CCP, trong khi Timer2 c kt ni vi khi SSP. Mt vi so snh s gip ta d dng la chn c Timer thch hp cho ng dng. 10. ADC ADC ( Analog to Digital Converter) l b chuyn i tn hiu gia hai dng tng t v s. PIC16F877A c 8 ng vo analog ( RA4:RA0 v RE2:RE0). Hiu in th chun VREF c th c la chn l VDD, VSS hay hiu in th chun c xc lp trn hai chn RA2 v RA3. Kt qu chuyn i t tn hiu tng t san tn hiu s l 10 bit s tng ng v c lu trong hai thanh ghi ADRESH: ADRESL. Khi khng s dng b chuyn i ADC, cc thanh ghi ny c th c s dng nh cc thanh ghi thng thng khc. Khi qu trinh chuyn i hon tt, kt qu s c lu vo hai thanh ghi ADRESH: ADRESL, bit GO/ ( ADCON0<2>) c xa v 0 v c ngt ADIF c set. Qui trnh chuyn i t tng t sang s bao gm cc bc sau: 1. Thit lp cc thng s cho b chuyn i ADC: Chn ng vo analog, chn in p mu ( da trn cc thng s ca thanh ghi ADCON1). Chn knh chuyn i AD ( thanh ghi ADCON0). Chn xung clock cho knh chuyn i AD ( thanh ghi ADCON0) Cho php b chuyn i AD hot ng ( thanh ghi ADCON0). 2. Thit lp cc c ngt cho b AD Clear bit ADIF. Set bit ADIE. Set bit PEIE Set bit GIE. 3. i cho ti khi qu trnh ly mu hon tt.

4. Bt u qu trnh chuyn i ( set bit GO/ S). 5. i cho ti khi qu trnh chuyn i hon tt bng cch:

Kim tra bit GO/ . Nu GO/ =0, qu trnh chuyn i s hon tt. Kim tra c ngt. 6. c kt qu chuyn i v xa c ngt, set bit GO/ ( nu cn tip tc chuyn i). 7. Tip tc thc hin cc bc 1 v 2 cho qu trnh chuyn i tip theo.

Cc thanh ghi lin quan n b chuyn i ADC bao gm: INTCON ( a ch 0Bh, 8Bh, 10Bh, 18Bh): cho php cc ngt ( cc ngt GIE, PEIE). PIR1 ( a ch 0Ch): cha c ngt AD ( bit ADIF). PIE1 ( a ch 8Ch): cha bit iu khin AD ( ADIE). ADRESH ( a ch 1Eh) v ADRESL ( a ch 9Eh): cc thanh ghi cha kt qu chuyn i AD. ADCON0 ( a ch 1Fh) v ADCON1 ( a ch 9Fh): xc lp cc thng s cho b chuyn i AD. PORTA ( a ch 05h) v TRISA ( a ch 85h): lin quan n cc ng vo analog PORTA. PORTE ( a ch 09h) v TRISE ( a ch 89h): lin quan n cc ng vo analog PORTE. Chi tit cc thanh ghi s c trnh by c th phn ph lc 2. 11. COMPARATOR B so snh bao gm hai b so snh tn hiu analog v c t PORTA. Ng vo b so snh l cc chn RA3:RA0, ng ra l hai chn RA4 v RA5. Thanh ghi iu khin b so snh l CMCON. Cc bit CM2:CM0 trong thanh ghi CMCON ng vai tr la chn cc ch hot ng cho b Comparator. C ch hot ng ca b Comparator nh sau: Tn hiu analog chn VIN+ s c so snh vi in p chun chn VIN- v tn hiu ng ra b so snh s thay i tng ng nh hnh v. Khi in p chn VIN+ ln hn in p chn VIN+ ng ra s mc 1 v ngc li. Da vo hnh v ta s thy p ng ti ng ra khng phi l tc thi so vi thay i ti ng vo m cn c mt khong thi gian nht nh ng ra thay i trng thi

( ti a l 10 us). Cn ch n khong thi gian p ng ny khi s dng b so snh. Cc tnh ca cc b so snh c th thay i da vo cc gi tr t vo cc bit C2INV v C1INV ( CMCON <4:5>). Cc bit C2OUT v C1OUT ( CMCON < 7: 6>) ng vai tr ghi nhn s thay i tn hiu analog so vi in p t trc. Cc bit ny cn c x l thch hp bng chng trnh ghi nhn s thay i ca tn hiu ng vo. C ngt ca b so snh l bit CMIF ( thanh ghi PIR1). C ngt ny phi c reset v 0. Bit iu khin b so snh l bit CMIE ( thanh ghi PIE). Cc thanh ghi lin quan n b so snh bao gm: CMCON ( a ch 9Ch) v CVRCON ( a ch 9Dh): xc lp cc thng s cho b so snh. Thanh ghi INTCON ( a ch 0Bh, 8Bh, 10Bh, 18Bh): cha cc bit cho php cc ngt ( GIE v PEIE). Thanh ghi PIR2 ( a ch 0Dh): cha c ngt ca b so snh ( CMIF). Thanh ghi PIE2 ( a ch 8Dh): cha bit cho php b so snh ( CNIE). Thanh ghi PORTA ( a ch 05h) v TRISA ( a ch 85h): cc thanh ghi iu khin. 12. CC C TNH CA OSCILLATOR PIC16F877A c kh nng s dng mt trong bn loi oscillator, l: LP: ( Low Power Cystal). XT: Thch anh bnh thng. HS: ( High Speed Cystal). RC: ( Resistor/ Capacitor) dao ng do mch RC to ra. i vi cc loi LP, HS, XT, oscillator c gn vo vi iu khin thng qua cc pin OSC1/CLKI v OSC2/CLKO. i vi cc ng dng khng cn cc loi oscillator tc cao, ta c th s dng mch dao ng RC lm ngun cung cp xung hot ng cho vi iu khin. Tn s to ra ph thuc vo cc gi tr in p, gi tr in tr v t in, bn cnh l s nh hng ca cc yu t nh nhit , cht lng ca linh kin. Hnh . RC oscillator Cc linh kin s dng trong oscillator phi bo m cc gi tr sau: REXT CEXT> 20 pF.

Vic mc thm t lc gip tng thm tnh n nh ca b dao ng, tuy nhin gi tr ca t khng qu ln hay qu nh dao ng n nh va thi gian khi ng ngn. Vi in th Vdd>4.5V th nn dng t c tr s 33pF. i vi mt s ng dng m chnh xc ca thi gian khng quan trng, c th dng dao ng RC nh mt gii php tit kim. Tn s dao ng c xc nh bi gi tr ca in tr R v t C. 13. CC CH RESET C nhiu ch Reset cho vi iu khin, bao gm: Power on Reset POR ( Reset khi cp ngun hot ng cho vi iu khin) . reset trong qu trnh hot ng. t ch sleep. Brown-out reset ( BOR). Ngoi tr reset POR trong trng thi cc thanh ghi l khng xc nh v WDT khng nh hng n trng thi cc thanh ghi, cc ch reset cn li u a gi tr cc thanh ghi v gi tr ban u c n nh sn. Cc bit v ch th trng thi hot ng, trng thi reset ca vi iu khin v c iu khin bi CPU. reset: Khi pin mc logic thp, vi iu khin s c reset. Tn hiu reset s c cung cp bi mt mch ngoi vi vi cc yu cu c th sau: Khng ni pin trc tip ln ngun VDD. R1 phi nh hn 40K m bo cc c tnh in ca vi iu khin. R2 phi ln hn 1K hn dng i vo vi iu khin.