PHN 1 Trong thit k s, My trng thi (vit tt l FSM) l mt thnh phn quan trng v khng th thiu i vi cc thit k phc

tp. Li im ca my trng thi l gip ngi thit k d dng kim sot quy trnh hot ng ca mt thit k. thc hin tt mt my trng thi chng ta phi hiu c bn cht ca n. Vi mong mun gip cc bn hiu thm v vn ny, mnh xin trnh by mt lot bi nh i t sch v n nhng phn tch ring ca mnh. My trng thi (FSM) l mt mch tun t: By gi hy xem FSM nh mt khi ring bit c ng vo v ng ra.

Ng vo ca FSM l g?

Xung nhp (clock) ng b Tn hiu reset khi ng FSM vo trng thi ban u trc khi hot ng Cc tn hiu dng xc nh vic chuyn trng thi v cc tn hiu ny c th tham gia xc nh gi tr ng ra.

Ng ra ca FSM l g? L mt hoc nhiu tn hiu thay i gi tr da trn hot ng ca FSM. Ng ra FSM dng iu khin mt mch s khc hay lm ng ra ca mt thit k; c th c ng b li qua cc Flip-Flop hoc khng l ty vo mc ch thit k. Cu trc FSM? Cu trc c bn ca mt my trng thi gm ba thnh phn l Mch t hp xc nh trng thi k tip (next state), Mch t hp xc nh gi tr ng ra v mt thanh ghi (register) lu gi trng thi hin ti (current state). D l Mealy hay Moore th cu trc FSM cng gm 3 phn nh vy thi (bn nn lu iu ny v nm r iu ny s gip bn d dng hiu, thit k v vit code cho FSM sau ny v vit code thc hin cng mt FSM bn c th trnh by nhiu cch khi bn thm k ci ny).

Qua y bn thy r ti sao FSM l mt mch tun t (mch tun t = mch t hp + phn t nh). My trng thi Mealy: Vi FSM Mealy, ng ra ph thuc vo trng thi hin ti v gi tr ng vo. Ngha l, ng ra FSM thay i khi trng thi ca FSM thay i hoc gi tr ng vo thay i. V cc bn thng thy hnh minh ha sau cho FSM Mealy

Thc cht mch t hp (combinational logic) y l tng hp ca Mch t hp xc nh trng thi k tip v Mch t hp xc nh gi tr ng ra nh ni trong phn trn.

Cn thnh phn b nh (memory elements) chnh l ci thanh ghi lu gi trng thi hin ti. My trng thi Moore: Vi FSM Moore, ng ra ch ph thuc vo trng thi hin ti. Ngha l, ng ra FSM ch thay i khi trng thi ca FSM thay i. V ng ra chng lin quan g n ng vo c nn chng ta thng thy hnh mnh ha nh sau:

Hai mch combinational logic ring bit, mt dnh cho xc nh trng thi k tip, mt dnh cho xc nh gi tr ng ra. Vy mt my trng thi ch c th l thun kiu Moore hoc Mealy? Khng hn nh vy. Mt my trng thi phc tp c nhiu ng ra. Trong cc ng ra , c ng ra ch ph thuc vo trng thi hin ti (Moore) nhng cng c ng ra va ph thuc trng thi hin ti v va ph thuc ng vo (Mealy). y l ty vo mc ch thit k ca bn. My trng thi ny tm gi l "kiu hn hp" c minh ha nh sau

PHN 2 Qua phn 1 chng ta ch cc im sau:

My trng thi l mch tun t. My trng thi gm 3 thnh phn. C ba kiu my trng thi l Kiu Moore, Mealy v kt hp c hai.

minh ha vic thc hin my trng thi chng ta hy thc hin v d sau y: Thit k b pht hin chui bit 1011 (c th bn gp bi ny u ). Nh vy ta phi thit k mt my trng thi c cc ng vo/ra nh sau

Trong :

clock: l xung nhp ng b ca FSM. reset_n: l tn hiu reset FSM sau khi mi bt ngun FSM vo trng thi khi ng. Reset ng b tch cc mc thp. serial_input: ng vo ca chui bit d liu. y: ng ra ca b pht hin (ng ra FSM). Trng thi mc nh ca y l 0 v y s bng 1 nu chui 1011 xut hin.

By gi ta bt u vi kiu Moore u tin chng ta phi xc nh chui trng thi c bn c th pht hin c chui bit 1011.

Trong :

IDLE l trng thi khi ng khi tn hiu reset_n tch cc (= 0) th my trng thi s v IDLE. D1 l trng thi pht hin c bit 1. Ngha l ti IDLE, nu serial_input bng 1 th s nhy qua trng thi ny.

D10 l trng pht hin c bit 0 sau khi pht hin bit 1, tc l trng thi nhn c chui 10. D101 l trng thi pht hin c bit 1 sau khi pht hin c chui 10. D1011 l trng thi pht hin c bit 1 sau khi pht hin c chui 101. y chnh l trng thi pht hin c y chui 1011. Chnh trng thi ny ta s cho gi tr ng ra y = 1.

V y l kiu moore, nn gi tr y nm ngay trong tng trng thi nh sau

Sau y ta bt u xt iu kin cn li trong tng trng thi: 1. Ti IDLE: Nu serial_input khng bng 1 th my trng thi s nhy i u? Cu tr li l s vn gi IDLE, d qu ng khng. 2. Ti D1: Nu serial_input khng bng 0 th my trng thi s nhy i u? Cu tr li l s v li IDLE th l sai bt ri. Chnh xc th FSM vn gi D1. Nn nh rng D1 l trng thi pht hin c bit 1. Nu bn D1 m nhn pht hin thm mt bit 1 na lc ny bn c chui 11, bn ngh s khng th to c chui 1011 nn cho v IDLE l sai lun. V bit 1 pha sau (th 2) c kh nng l bt u ca mt chui 1011 nn D1 nu nhn c thm mt bit 1 th vn D1 ng nh ngha D1 l trng thi pht hin c bit 1. 3. Ti D10: Tip tc vi cu hi Nu serial_input khng bng 1 th my trng thi s nhy i u? Cu tr li l v IDLE. Khi n D1 v nhn thm mt bit 0 th bn va c chui 100, khng c kh nng to c 1011 th ch c quay li IDLE m thi. 4. Ti D101: Nu nhn c mt bit 0 th FSM s nhy v D10. Ti sao? Nu D101 bn nhn thm mt bit 0 th bn c chui 1010, y d nhin khng phi chui mong mun ca bn nhng hy hai bit cui ca chui ny l 10, tc l c kh nng bn s nhn tip c 11 na c 1011, nh vy FSM phi v D10 ng nh ngha ca n l trng thi nhn c chui bit 10 5. Ti D1011: y l trng thi kt thc v mt chui 1011 va c pht hin. V y l trng thi kt thc cho mt qu trnh pht hin chui 1011 nn v IDLE ngh ngi cho khe ch chui mi thi, nu bn ngh vy th i xong. y ta phi tr li hai cu hi:

Mt: nu Nu serial_input bng 1 th my trng thi s nhy i u? tr li: v D1 Hai: nu Nu serial_input bng 0 th my trng thi s nhy i u? tr li: v D10

Cui cng ta c mt my trng thi nh sau:

Thng ta ch cn ghi iu kin trn mt nhnh v ngm hiu l nu khng tha iu kin nhnh ny th FSM s nhy theo nhnh cn li nn ta c:

Nh vy l ta thit k xong FSM kiu moore dng pht hin chui bit 1011. Cui cng, bn hy bt tay vit RTL code cho FSM ny. PHN 3 Sau y chng ta bt u coding cho my trng thi trong v d phn 2.

C nhiu cch vit thc hin chc nng ca FSM ny. Sau y xin i t cch c bn nht. Nh phn 1 chng ta bit FSM c ba phn v vy ta c vit 3 on code tng ng vi 3 phn l c ngay mt FSM hon chnh (xem hnh sau)

Ta s bt u t tri qua phi nh, tng ng vi 1->2->3 trn hnh v. on code cho Mch t hp xc nh trng thi k tip
always @ (*) begin if (~reset_n) next_state = IDLE; else begin case (current_state) IDLE: begin if (serial_input) next_state = D1; else next_state = IDLE; end

D1: begin if (~serial_input) next_state = D10; else next_state = D1; end D10: begin if (serial_input) next_state = D101; else next_state = IDLE; end D101: begin if (serial_input) next_state = D1011; else next_state = D10; end D1011: begin if (serial_input) next_state = D1; else next_state = D10; end default: next_state = IDLE; endcase end end

on code cho thanh ghi trng thi

always @ (posedge clock) begin if (~reset_n) current_state <= IDLE; else current_state <= next_state; end

on code cho mch t hp xc nh gi tr ng ra

always @ (*) begin case (current_state) D1011: y = 1'b1; default: y = 1'b0; endcase end

Rp 3 on li + khai bo cc bin v tham s l ta c mt m-un FSM hon chnh nh sau

module fsm_1011_detector (clock, reset_n, serial_input, y); //input input clock; input reset_n; input serial_input; //output output y; reg y;

//bien trang thai reg [2:0] current_state; reg [2:0] next_state; //gan tham so cho moi trang thai parameter IDLE = 3'd0; parameter D1 = 3'd1; parameter D10 = 3'd2; parameter D101 = 3'd3; parameter D1011 = 3'd4; //Mach to hop xac dinh trang thai ke tiep always @ (*) begin if (~reset_n) next_state = IDLE; else begin case (current_state) IDLE: begin if (serial_input) next_state = D1; else next_state = IDLE; end D1: begin if (~serial_input) next_state = D10; else next_state = D1; end D10: begin if (serial_input) next_state = D101; else next_state = IDLE; end D101: begin if (serial_input) next_state = D1011; else next_state = D10; end D1011: begin if (serial_input) next_state = D1; else next_state = D10; end default: next_state = IDLE; endcase end end //Thanh ghi trang thai always @ (posedge clock) begin if (~reset_n) current_state <= IDLE; else current_state <= next_state; end //Mach to hop xac dinh ngo ra always @ (*) begin case (current_state) D1011: y = 1'b1; default: y = 1'b0;

endcase end

endmodule
Nh vy l hon thnh xong my trng thi v y l cch c bn nht. Ngoi ra chng ta cn cc cch vit code khc nhng cho cng mt kt qu.