MicroBlaze Overview

Theresa Chou

Agenda
MB OverView MB Bus & IP SW Flow MB OS & 3th party tool

MB architecture
Embedded soft RISC Processor 32-bit data 32-bit instruction word (three addresses and two addressing modes) 32 registers (32-bit wide) 3 pipe stages (single issue) Big-endian format Buses Full Harvard-architecture OPB (CoreConnect), instruction and data LMB for connecting to local BRAM (faster), instruction and data

MicroBlaze is a soft processor core that can be implemented into any Virtex architecture:

MB architecture

ADD/SUB

PROGRAM COUNTER

SHIFT/LOGICAL MULTIPLY

BUS IF INSTRUCTION DECODE INSTRUCTION BUFFER REGISTER FILE 32b X 32b

BUS IF

MICROBLAZE CORE

ee more in http://www.xilinx.com/ipcenter/processor_central/microblaze/architecture.htm

MB performance
All instruction takes one clock cycle except Load and store (two clock cycles) Multiply (two clock cycles) Branches (three clock cycles, can be one clock cycle)

See more in http://www.xilinx.com/ipcenter/processor_central/microblaze/performance.htm

MicroBlaze Memory Space

Memory and peripherals The MicroBlaze processor uses 32-bit addresses Special addresses MicroBlaze processors must have user-writable memory from 0x00000000 through 0x00000017 BRAM size limits The amount of BRAM memory that can be assigned is limited The largest supported BRAM memory size for Virtex and Virtex-E is 16 kilobytes; for Virtex-II, it is 64 kilobytes
0xFFFF_FFFF Peripherals

OPB Memory

0x0000_0018 0x0000_0010 0x0000_0008 0x0000_0000

LMB Memory Interrupt Address Exception Address Reset Address

IBM CoreConnect Bus

The IBM CoreConnect standard provides three buses for interconnecting cores, library macros, and custom logic: Processor Local Bus (PLB) On-chip Peripheral Bus (OPB) Device Control Register (DCR) bus

Arbiter Master Slave Master/ Slave

Master

Arbiter

Slave

Slave

See more in http://www-3.ibm.com/chips/products/coreconnect/

IBM CoreConnect Busses

MicroBlaze Busses
Local Memory Bus (LMB) 32-bit high speed memory access Single-cycle to on-chip BRAM ILMB (Instruction LMB) DLMB (Data LMB) On-Chip Peripheral Bus (OPB) 32-bit processor interface 8/16/32-bit peripheral interface IOPB (Instruction OPB) DOPB (Data OPB)

MicroBlaze Bus Example

IOPB Bus ILMB Bus
MicroBlaze ILMB BRAM DLMB DOPB IOPB Ext Mem GPIO Ethernet LCD IIC UART

DLMB Bus

DOPB Bus

BRAM INTC OPB ARB

All buses are 32 bits

Example MicroBlaze System

DLMB

DOPB

UART JTAG UART

RS-232 JTAG Header DIP Switches 7-Segment LED

OPB Interface

GPIO Input GPIO Output

MicroBlaze Processor
Data Memory Memory Controller Dual Port Memory (8K Bytes) Instruction Memory

50MHz Clock Reset Switch

ILMB

FPGA

External

Free Cores
OPB Arbiter OPB TimeBase/WDT OPB Timer/Counter OPB GPIO OPB UART-Lite OPB JTAG UART OPB EMC Memory Controller
Flash SRAM ZBT System ACE

PPC System Reset DCR Interrupt Controller DCR Interface PLB Arbiter PLB EMC Memory Controller PLB BRAM Controller PLB DDR Controller PLB SDRAM Controller PLB2OPB Bridge OPB2PLB Bridge OPB2OPB Bridge OPB2OPB Bridge-Lite

OPB BRAM Controller OPB DDR Controller OPB SDRAM Controller

Bus-to-Bus communication

Custom IP - dkgpio
OPB Bus

dkgpio
opb_ipif_ssp0 dk_logic

OPB IPIF Interface

IPIC Interface

LED[0:3]

IPIC is a simplified IPIF interface

Hardware / Software Flow

Hardware Flow
HW Block Diagram

Software Flow
SW Flow Chart

HW Description

EDK

Create SW source

Synthesize P&R

Compile Simulate

ISE
BIT File/ Download DATA2BRAM ELF File/ Download

Design Debug (HW and SW)

Xilinx EDK

Embedded Development Kit Xilinx Platform Studio (XPS) GUI interface Supports MicroBlaze and PPC development Tools for HW and SW platform specification Xilinx Microprocessor Debug (XMD) Board Support Package (BSP) generator Interface to industry standard simulation tools MicroBlaze Core & License Peripheral IP (Parameterizable) GNU Tools (Compiler, Debugger) Application Examples

Hardware Flow
Specify Processor, Bus & Peripherals, Hardware Configuration

Automatic Hardware Platform Generation

Xilinx Implementation Flow

Bitstream
JTAG CNTL PPC405

PLB EMC

OPB GPIO

PLB / Arbiter

PLB2OPB Bridge OPB2PLB Bridge

OPB / Arbiter

Download to FPGA

PLB BRAM I/F

BRAM Block

OPB UART

Hardware Flow MHS

Microprocessor Hardware Specification File (MHS) A text file that describes the hardware structure Processor Bus architecture Peripherals Connectivity of the system Interrupt request priorities Address space
MHS
Specify Processor, Bus & Peripherals, Hardware Configuration

Automatic Hardware Platform Generation

Xilinx Implementation Flow

Bitstream

Download to FPGA

Hardware Flow MHS

Auto-Generated MHS File
# Parameters PARAMETER VERSION = 2.0.0 # Global Ports PORT sys_clk = sys_clk, DIR = IN PORT sys_rst = sys_rst, DIR = IN PORT rx = rx, DIR = IN PORT tx = tx, DIR = OUT # Sub Components BEGIN bram_block PARAMETER INSTANCE = bram_lmb PARAMETER HW_VER = 1.00.a BUS_INTERFACE PORTA = ilmb_porta BUS_INTERFACE PORTB = dlmb_portb END BEGIN lmb_bram_if_cntlr PARAMETER INSTANCE = my_ilmb_cntlr PARAMETER HW_VER = 1.00.b PARAMETER C_BASEADDR = 0x0000_0000 PARAMETER C_HIGHADDR = 0x0000_1FFF BUS_INTERFACE SLMB = i_lmb BUS_INTERFACE BRAM_PORT = ilmb_porta END BEGIN lmb_bram_if_cntlr PARAMETER INSTANCE = my_dlmb_cntlr PARAMETER HW_VER = 1.00.b PARAMETER C_BASEADDR = 0x0000_0000 PARAMETER C_HIGHADDR = 0x0000_1FFF BUS_INTERFACE SLMB = d_lmb BUS_INTERFACE BRAM_PORT = dlmb_portb END BEGIN microblaze PARAMETER INSTANCE PARAMETER HW_VER = PORT CLK = sys_clk BUS_INTERFACE DLMB BUS_INTERFACE ILMB BUS_INTERFACE DOPB END = mblaze 2.00.a = d_lmb = i_lmb = myopb

IO Port Delcarations

MicroBlaze port connections, bus organization and parameters

BEGIN lmb_v10 PARAMETER INSTANCE = d_lmb PARAMETER HW_VER = 1.00.a PARAMETER C_EXT_RESET_HIGH = 0 PORT LMB_Clk = sys_clk PORT SYS_Rst = sys_rst END

Peripherals (memory, etc)

BEGIN lmb_v10 PARAMETER INSTANCE = i_lmb PARAMETER HW_VER = 1.00.a PARAMETER C_EXT_RESET_HIGH = 0 PORT LMB_Clk = sys_clk PORT SYS_Rst = sys_rst END BEGIN opb_v20 PARAMETER INSTANCE = myopb PARAMETER HW_VER = 1.10.b PARAMETER C_EXT_RESET_HIGH = 0 PORT OPB_Clk = sys_clk PORT SYS_Rst = sys_rst END

LMB/OPB Bus Specifications

Hardware Flow MPD

Microprocessor Peripheral Definition (MPD) Template that specifies ports and parameters of peripherals and IP Lists ports and default connectivity for bus interfaces Lists parameters and default values Any MPD parameter is overwritten by the equivalent MHS assignment
MHS MPD
Specify Processor, Bus & Peripherals, Hardware Configuration

Automatic Hardware Platform Generation

Xilinx Implementation Flow

Bitstream

Download to FPGA

Hardware Flow MPD Format

BEGIN opb_uartlite, IPTYPE=PERIPHERAL, EDIF=TRUE, HDL=BOTH OPTION SIM_MODELS = BEHAVIORAL : STRUCTURAL BUS_INTERFACE BUS=SOPB, BUS_STD=OPB, BUS_TYPE=SLAVE # Generics for vhdl or PARAMETER C_BASEADDR PARAMETER C_HIGHADDR PARAMETER C_OPB_DWIDTH PARAMETER C_OPB_AWIDTH PARAMETER C_DATA_BITS PARAMETER C_CLK_FREQ PARAMETER C_BAUDRATE PARAMETER C_USE_PARITY PARAMETER C_ODD_PARITY # Global ports PORT OPB_Clk = PORT OPB_Rst = PORT Interrupt = # OPB slave signals PORT OPB_ABus = PORT OPB_BE = PORT OPB_RNW = PORT OPB_select = PORT OPB_seqAddr = PORT OPB_DBus = PORT UART_DBus = PORT UART_errAck = PORT UART_retry = PORT UART_toutSup = PORT UART_xferAck = # uart signals PORT RX = PORT TX = END parameters for = 0xFFFF8000, = 0xFFFF80FF, = 32, = 32, = 8, = 125_000_000, = 9600, = 1, = 1, verilog DT=std_logic_vector DT=std_logic_vector DT=integer DT=integer DT="integer range 5 to 8" DT=integer DT=integer DT=integer DT=integer

Peripheral name, type and HDL source code type Bus interface information

Parameters/Generics that can be customized by user. Includes default values and variable type.

"", OPB_Rst, "", OPB_ABus, OPB_BE, OPB_RNW, OPB_select, OPB_seqAddr, OPB_DBus, Sl_DBus, Sl_errAck, Sl_retry, Sl_toutSup, Sl_xferAck, "", "",

DIR=IN, BUS=SOPB, SIGIS=CLK DIR=IN, BUS=SOPB DIR=OUT, EDGE=RISING, SIGIS=INTERRUPT DIR=IN, DIR=IN, DIR=IN, DIR=IN, DIR=IN, DIR=IN, DIR=OUT, DIR=OUT, DIR=OUT, DIR=OUT, DIR=OUT, DIR=IN DIR=OUT BUS=SOPB, BUS=SOPB, BUS=SOPB BUS=SOPB BUS=SOPB BUS=SOPB, BUS=SOPB, BUS=SOPB BUS=SOPB BUS=SOPB BUS=SOPB VEC=[0:C_OPB_AWIDTH-1] VEC=[0:C_OPB_DWIDTH/8-1]

VEC=[0:C_OPB_DWIDTH-1] VEC=[0:C_OPB_DWIDTH-1]

OPB Port Declarations. These get automatically connected since they are specified to be part of the OPB Slave Bus Interface

User Ports.

Hardware Flow Platform Generator

Platform Generator (PlatGen) Uses MHS and MPD files to create the hardware platform Creates netlist files Creates support files for downstream tools Creates HDL wrappers
MHS MPD
Specify Processor, Bus & Peripherals, Hardware Configuration

Automatic Hardware Platform Generation

Xilinx Implementation Flow

Bitstream

Download to FPGA

Hardware Flow Implementation

Implementation Flow XFLOW Batch Mode Place & Route flow. ProjNav ISE Project Navigator GUI Place & Route flow
MHS MPD
Specify Processor, Bus & Peripherals, Hardware Configuration

Automatic Hardware Platform Generation

Xilinx Implementation Flow

Xflow / ProjNav
Bitstream

Download to FPGA

Software Flow
Specify Software Architecture

After peripheral hardware definition, the software flow is independent of the hardware flow.

Automatic Software BSP/Library Generation

Software Compilation
Executable in on-chip memory

Executable Executable in off-chip memory

Hardware Flow Data2BRAM

Bitstream

Download to FPGA

GDB / XMD

PLB OPB JTAG EMC GPIO CNTL PLB2OPB PLB / BridgeOPB / PPC405 OPB2PLB Arbiter Arbiter Bridge PLB BRAM OPB BRAM Block UART I/F

Download to FPGA

Software Flow MSS

Specify Software Architecture

MSS

Automatic Software BSP/Library Generation

Microprocessor Software Specification (MSS) Auto-generated/user modifiable file Contains all project software options (Ccompiler options, driver info, etc.)

Software Compilation
Executable in on-chip memory

Executable

Hardware Flow Data2BRAM

Bitstream

Executable in off-chip memory

Download to FPGA

GDB / XMD

PLB OPB JTAG EMC GPIO CNTL PLB2OPB PLB / BridgeOPB / PPC405 OPB2PLB Arbiter Arbiter Bridge PLB BRAM OPB BRAM Block UART I/F

Download to FPGA

Software Flow MSS Format

Auto-Generated MSS File
PARAMETER VERSION = 2.0.0 PARAMETER HW_SPEC_FILE = system.mhs BEGIN PROCESSOR PARAMETER HW_INSTANCE = my_microblaze PARAMETER DRIVER_NAME = cpu PARAMETER DRIVER_VER = 1.00.a PARAMETER EXECUTABLE = executable.elf PARAMETER COMPILER = mb-gcc PARAMETER ARCHIVER = mb-ar PARAMETER DEBUG_PERIPHERAL = my_jtaguart PARAMETER STDIN = my_uartlite PARAMETER STDOUT = my_uartlite END BEGIN DRIVER PARAMETER HW_INSTANCE = myethernet PARAMETER DRIVER_NAME = emac PARAMETER DRIVER_VER = 1.00.b PARAMETER LEVEL = 0 PARAMETER LIBRARY = XilNet END BEGIN DRIVER PARAMETER HW_INSTANCE = my_uartlite PARAMETER DRIVER_NAME = uartlite PARAMETER DRIVER_VER = 1.00.b PARAMETER LEVEL = 0 END

Software Flow Library Generator

Specify Software Architecture

MSS

Automatic Software BSP/Library Generation

Software Compilation

Library Generator (LibGen) Configures libraries and device drivers Creates xparameters.h include file for driver definitions Creates libc.a, libm.a, libxil.a libraries that contain functions that the processor can access

Executable

Software Flow Compiler

XPS Supports GNU Compiler for MicroBlaze

Specify Software Architecture Automatic Software BSP/Library Generation Software Compilation

MSS

.c

Executable

Easy to Use Flow

Design your Cpu and Cpu Bus by Graphic Set each component attribute , port , memory mapping Finish your CPU design Use tool bar to run your HW and SW flow

Starting a New Project

Step through the XPS Hardware Flow Create a new project Setup project options Insert peripherals Make connections Create ports Set parameters Set STDIO

Starting a New Project

Open XPS by selecting Start>Programs>Xilinx Embedded Development Kit>Xilinx Platform Studio

Select the location of the Project File (.xmp) If you have an existing MHS file, Browse to Import Select the Target Device Peripheral Repository Directory Allows you to select the location of your peripherals if they are not local to your project area.

Project Options Device and Repository

From the XPS Menu Options>Project Options Target Device Allows you to retarget the design to another device Peripheral Repository Directory Allows you to specify the location of your peripherals

Project Options Hierarchy and Flow Design Hierarchy Allows you to place the design as a sub-module within another design Netlist Generation Targets the synthesis tool and allows for flat netlist creation Implementation Tool Flow Targets Xflow or ISE Project Navigator

Project Options HDL and Simulation HDL Selects the language of the peripheral wrappers Simulator Selects between ModelSim or Verilog-XL ModelSim Libraries Path Browse to the directories where you have compiled the Xilinx Models Simulation Models Select the models desired for simulation Refer to Getting Started Guide for library compile info

Processor Block Diagram

Processor Block Diagram (PBD)

Auto-generated/user modifiable file Block diagram format of MHS file Good as reference, but keep closed to avoid MHS conflicts

Define Hardware Platform

All hardware information is stored in the MHS file and can be edited in multiple ways using XPS Select Project>Add/Edit Cores(dialog) This dialog allows you to add Peripherals, Bus Connections, Ports, Parameters, etc.

Hardware Implementation

Generate Netlist Hardware Directories Generate Bitstream

Software Implementation

Generate Libraries
MicroBlaze BSP
MHS MSS

Library Structure Library Driver

LibGen
Xmdstub.elf *.h *.a

Libraries

MDD MDD MDD

Drivers for IP

Downloading Bitstreams

Downloading Bitstreams Tools>Download Runs iMPACT in batch mode Uses download.cmd batch file from the etc directory to properly describe JTAG chain User must create download.cmd for their system

DEMO Flow