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References
Dally & Poulton, Chapters 4, 12.1 Kang & Leblecici, Chs 3-7
MOS Transistors
N-channel Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET): Simplest Equivalent Circuit:
Voltage controlled switch Majority carrier gate
Structure:
Designer determines length and width Nodes: G, S, B, D
Materials
Gate : Polysilicon Drain, Source : diffused silicon
Operation
Gate Voltage modulates channel and determines current.
I DS
I DS
kn W (VGS VT ) 2 = 2 L
Cox = Gate capacitance per unit area (r0/tox) kn = nCox = Process transconductance (A/V2) n = electron mobility n = kn(W/L) = device transconductance VT = Threshold (turn-on) voltage
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Gate Design
Add pMOS FET to deliver complementary FETs (CMOS) Negative gate voltage turns gate on Majority carriers = holes
p 0.3 0.5 n
Entire Process: n Well process Parasitic PNP bipolar transistor Diode PNPN SCR
Other Effects
Channel-length modulation Depletion region around pn junction becomes significant part of channel length More important for short-channel devices Determines slope in saturation region Body Effect Threshold voltage changes with VSB Velocity Saturation I stops increasing with field (VDS) at high VDS=Vsat Enters saturation for lower VDS Sub-Threshold Conduction VDS lowers barrier to conduction Important in Dynamic Circuits
p<n
Other Effects
Short Channel Effects Channel length shortening
Leff < Ldrawn Velocity Saturation decreases VDS(linear-sat) and IDS(sat)
Mobility decreases with increasing VGS Threshold volage reduced due to increased relative size of depletion region Hot Carrier Effects High E fields can inject hot electrons into gate oxide, causing damage and degrading transconductance
Sample Parameters
Device Parasitics
Important in determining performance
Gate Capacitance:
Drops around VT
Thin-Ox capacitor
CGS dominates
Miller effect issue X = VDS/(VGS-VT)
2003, Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html 9
Other Parastitics
CSB and CDB: Reverse biased diode depletion region 0.25 0.5 CG Device Resistances normally small Drain/Source capacitance and parasitic resistances reduced through good layout:
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Sample Models
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Example
Example using these equations (0.35 m technology)
Assume = 0.2 m (gate is 0.4 m as drawn) 0.4 m (2) 0.8 m (4) 0.2 m () 0.6 m (3)
0.8 m (4)
Drain or Source Capacitance = area * CJ + gate-perimeter * CGSO + other-perimeter * CJSW = (0.6*0.2 + 0.8*0.8)E-12 * 5E-4 + 0.6E-6 * 1E-10 + (0.8*3+0.2)E-6 * 2E-10 = 0.38 + 0.06 + 0.52 = 1.5 fF Gate Capacitance (Leff = 0.35 m) = 0.35*0.6E-12*3.9*8.85e-12/70e-10 = 10 Ff (C0=4.9E-3 F/m2)
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Example
VDD = 3.3 V What is the gate on resistance in the linear region?
1 / Ron = I DS / VDS
Ron = 570
W = nCox (VGS VT ) L
I DS
kn W (VGS VT ) 2 = 2 L
= 600E-4 * 4.9E-3 *0.6/0.35 * (3.3-0.5)2 = 4 mA
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