Thi t k m ch t h p

Nguy n Qu c C ng 3i

N i dung
M t s quy nh khi vi t ti li u Bi u th i gian c a cc m ch Cc PLD t h p Cc m ch m ha Cc m ch gi i m Multiplexer So snh Cc m ch s h c

Combinational logic design

Ti li u tham kh o
Digital Design: Principles & Practices John F Wakerly Printice Hall

Combinational logic design

M t s quy nh khi vi t ti li u
S kh i K hi u cc gate M c tch c c cho cc chn

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S kh i
Th hi n cc kh i ch c nng chnh c a h th ng Khng qu chi ti t C g ng th hi n trong m t trang

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K hi u cc gate

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cc k hi u tng ng s d ng nh l DeMorgan

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M c tch c c cho cc chn

Th ng quy nh n u c vng trn nh ch tch c c m c th p N u khng c vng trn nh th hi u l tchc c c m c cao

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 (a): n u c hai input = HIGH th output = HIGH (b): n u c hai input = HIGH th output = LOW (c): n u c hai input = LOW th output = LOW

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Tn hi u:
N u c h u t _L th hi u l tch c c m c th p N u khng c ha a t _L th hi u l tch c c m c cao

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Bi u th i gian
Bi u di n ho t ng c a cc tn hi u l hm c a th i gian S d ng cc mi tn ch quan h nhn-qu c a cc tn hi u trong m ch

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M ch logic t h p PLD
PLD: Programmable Logic Device Lo i PLD u tin c g i l PLA (Programmable Logic Arrays):
M ch logic t h p 2 t ng AND-OR c trng b i:
S inputs: n S output: m S cc tch: p (th ng p nh hn r t nhi u 2^n)

T ng h p cc hm logic theo ki u t ng cc tch

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 input n i v i m t buffer t o ra:

chnh tn hi u input (buffer) b c a input (inverter)

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Cc dy tn hi u c n i s n trong m ch X : dng k hi u ni c th thi t l p cc k t n i hay khng thng qua cc c t ch Cc input c a t ng AND khi h (khng n i v i buffer) s c thi t l p l HIGH Cc input c a t ng OR khi h (khng n i v i output c a t ng AND) s c thi t l p l LOW

Cch th hi n khc c a PALs

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 th c hi n cc hm logic

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th c hi n cc output l h ng s

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 output = const = 0 nn s d ng phng php O2 hn l O3:

Khi t t c input thay i ng th i, O3 c kh nng s chuy n 0 1 0 (glitch)

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PALs
PALs: Programmable Array Logic:
Ch c m ng AND l programmable M ng OR l fixed

Ph bi n nh t l PAL16L8:
64 hng, 32 c t, 32 x 64 = 2048 c t ch M i AND gate c 32 input ng v i 16 bi n v ph n b PAL 16L8 c a cc bi n 8 AND gate lin k t v i m t pin:
7 AND gate c n i v i 7 input c a m t c ng OR AND th 8 c n i v i output-enable gate, n u AND = 1 th output m i c a ra pin
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PAL16L8 ch th c hi n c cc hm t ng c a 7 tch ho c t hn Trong s chn c a PAL16L8: c 20 pin

2 pin cho VCC v GND 10 pin cho I1 n I10 8 pin cho O1 n O8 c bi t: chn O2 n O7 l shared:
Input Output

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PLD v i cng ngh bipolar

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Hng u: cc m ch open-collector c n i v i nhau th c hi n ch c nng nh m t m ng AND:

Ch m t output c a buffer l pull-low th c c t s c m c LOW Cc c t n i v i m t m ch o g p l i nh m t m ng NAND

Tng t cho m ng th hai NAND V i c u trc NAND-NAND c tc d ng gi ng nh AND-OR

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 t o s k t n i v i cc c t s d ng m t c t ch nh C t ch s c t nng v lm b c hi khi thi t l p m t i n p c 20V n 30V

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PLD v i cng ngh CMOS

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 Vi c t c t ch cho cc ph n t c th c hi n ngay t i b c ch t o IC:

khng linh ho t, c n t hng v i nh s n xu t IC h p v i cc ng d ng c s l ng s n ph m l n

linh ho t hn s d ng EPLD (Erasable Programmable Logic Device)

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EPLD

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 C c th n i (floating gate) c a MOS transistor:

Bao quanh b i cc ch t cch i n Ban u khng c i n tch MOS transistor ho t ng bnh th ng:
n u input = LOW n u input = HIGH connected n-MOS transistor s off n-MOS transistor s on

Khi c i n p cao t vo nonfloating gate:

floating gate s nhi m i n tch m do tc d ng c a i n tr ng m nh i n tch m v n b gi l i t i floating gate khi b i n p cao i n tch m t i floating gate ngn c n ho t ng c a MOS transistor:
n u input = LOW n u input = HIGH disconnected
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MOS transistor off MOS transistor s v n off

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xa tr ng thi disconnected:
Thi t l p i n p trn nonfloating gate i n p cao v i n tch trn floating gate s phng ng c d u

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Cc b gi i m (decoder)
Gi i m: bi n i m output:
n input 2n m t h p, m output Th ng n < m B gi i m s d ng nhi u:
M i t h p input s ng v i m t bit trong m bit output

input sang m t m khc

2m m t h p

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Chn EN (Enable):
Tch c c: cc t m input s c nh x n cc t m output Khng tch c c: t t c cc t m input u c gn n m t t m duy nh t u ra

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74x139

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74x138

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B gi i m 7 thanh
B gi i m 7 thanh:
input m BCD output i u khi n hi n th 7 thanh

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74x49

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B m ha (encoder)
M ha: bi n i m output:
n input 2n m t h p, m output Th ng n > m B gi i m s d ng nhi u:
M i bit input s ng v i m t t h p c a m bit output

input sang m t m khc

2m m t h p

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M ha u tin 74x149

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D n knh (Multiplexer)
Multiplexer:
kha s n i n input t i u ra c a n ph thu c vo tn hi u i u khi n s th ng n = 2, 4, 8,... s = log2(n)

Khng nh d n knh tng t , d n knh s ch cho tn hi u i theo m t chi u: input output

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74x151

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74x157

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m r ng nhi u multiplexer

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Demultiplexer
B tch knh: ng c l i v i Multiplexer
1 input v i n output s tn hi u ch n knh output

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Multiplexer Demultiplexer

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EXCLUSIVE OR
Exclusive OR (XOR) v XNOR

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th c hi n XOR

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Ki m tra ch n l
M ts
s bit 1 trong dy s l ch n (even) ? s bit 1 trong dy s l l (odd) ?

ng d ng (truy n tin) c n xem xt:

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B so snh
S d ng trong cc h th ng my tnh S d ng trong cc giao di n thi t b ki m tra ID So snh 2 s nh phn:
So snh b ng ho c khng b ng So snh b ng, l n hn, nh hn comparator comparator magnitude

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74x86

B so snh b ng v khng b ng (comparator) s d ng 74x86 k t h p v i NOR (74x02) v NAND (74x00)

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74x85

So snh =, > , < (magnitude comparator)

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n i t ng 74x85

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B c ng
B c ng m t n a (halft adder): c ng hai ton h ng X v Y 1 bit, k t qu c t trong 2 bit:
bit th p c a k t qu k hi u HS (halft sum) bit cao c a k t qu ky hi u CO (carry out)

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 B c ng y (full adder): dng c ng hai bit v tr b t k trong dy s c a s h ng nhi u bit X v Y:

C n c bit carry-in ( nh n carry-out t bit th p) T ng c t trong 2 bit:
bit th p k hi u S bit cao k hi u l COUT

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b c ng y

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Ripple adder
C ng hai s nh phn n bit:
S d ng full adder c ng t ng bit n full adder c n i t ng c ng n bit

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ALU
ALU (Arithemetic and Logic Unit): L m ch t h p:
th bi L i c hi n cc php tnh s h c v logic trn 1 ho c 2 n n bit: a ch n ch ho t ng thng qua cc tn hi u u khi n

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74x181

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 minus: tr (s h c) plus: c ng (s h c)

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B nhn
Tham kh o

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