Application of TMS320C6400 in 3G Wireless Infrastructure Transceiver (BTS)

Tom Horner,
Member, Group Technical Staff

Jelena Nikolic-Popovic,
Technical Staff

DSP Applications, Texas Instruments

Outline
!3G BTS Functionality !3G BTS Architecture !C6400 Features !Symbol-Rate functions on C6400
! CRC

Encoding/Decoding ! Convolutional/Turbo Encoding/Decoding ! Interleaver/Deinterleaver ! Rate Matching

!Summary and Conclusion

3G BTS Functionality
RX/TX RX

Baseband (BB)
E1/T1 or Packet Network

Amplifiers
MCPA

BSC/RNC Interface

Circuit Switch Control Packet Switch Control

PHY Interface LNA Symbol Decode Symbol User Detection Combining Chip-rate Demodulation De-spreading Channel Estimation Symbol Encode Chip-rate Modulation Spreading Filtering + Pre-distortion ADC

RF TX

RF RX

DAC

ADC

Network Interface

BB Interface

Filtering + Diversity

TRX

3G BTS Baseband Architecture

ASIC 1
Backplane I/F to A/D/A & RF C64X
Net I/F
McBSP 1 Par IF JTAG Symbol-rate RTDX processing Network control acq & track chan estimation EMIF Host I/F JTAG RTDX

Net I/F
McBSP 1 EMIF

Antennas

Symbol-rate processing Network control acq & track chan estimation Host I/F

C64X

DRAM

Par IF

To ASIC 1

ASIC 2
Backplane I/F to Network

Network

Spreader Correlator
LC Generator Walsh Spread I&Q PN Sequence Complex Spread Searcher, Rake Complex De-spread

DRAM
Host I/O

DRAM
To DRAM Flash & DRAM EMIF McBSP 1

Micro
To ASIC 1 Host I/F Par IF

DRAM
Par IF McBSP 1 Host I/F Symbol-rate processing Network control acq & track chan estimation EMIF

Net I/F

Net I/F
JTAG RTDX

C64X

C64X

Symbol-rate processing Network control acq & track chan estimation

JTAG RTDX

Flash

C6400 Features
"Scalable speed up to 1.1GHz - firdt device at 800MHz "Software compatible with C62X (re-use all the existing code), but:
! ! ! ! !

More flexible resources (instructions available across more functional units); New special-purpose instructions (Gmpy4, Deal, Swap4, Bitc4); Extended parallelism (SIMD, pack/unpack,non-aligned loads); Program code saving enhancements (special branch instructions, execution spans packet boundaries); Double the bandwidth (64 registers, 64 bit data paths);

"Advanced emulation (non-intrusive debug, RTDX); "Fast development environment with eXpressDSP. "Diverse set of peripherals: multliple parallel and serial I/O s "Two-level cache (L2, L1D/L1P) - various sizes

Symbol-Rate Functions - TX
CRC Encoder Convolutional Encoder Turbo Interleaver Turbo Encoder 1st Interleaver Rate Match 2nd Interleaver

Turbo Interleaver Table Generator

!low user data rate (voice) or high user data rate (data) !3GPP or cdma2000

Symbol-Rate Functions - RX
CRC Decoder Viterbi Decoder 1st Deinterleaver Rate Match 2nd DeInterleaver

Turbo Decoder

Turbo Interleaver Table Generator

!low user data rate (voice) or high user data rate (data) !3GPP or cdma2000

CRC
!Algorithm:
"Cyclic Redundancy Check "8th,12th or 16th order generator polynomial

!Implementation:
! Based

on look-up table; ! 512 bytes for 16th order generator polynomial ! native C code
" 38 cycles / 32 input bits

Convolutional Encoder
!Algorithm
M U X

!Implementation:
! block-XOR

operation (16 bits at a time) ! tuned C, uses _pack2() and _shfl() intrinsics
" 12 cycles/32 bits for rate 1/2 " 37 cycles/32 bits for rate 1/3

Viterbi Decoder
!Algorithm (stages, butterfly, traceback)
0 1 2 3 ... ... ... ... 254 255

y=in[0..2]

y=in[3..5]

y=in[6..8]

y=in[9.11]

y=in[12..14] y=in[15,..17] y=in[18,..20] y=in[21,..,23]

!Implementation
"(10 cycles/8 butterflies)*128 butterflies / stage "5 cycles for branch metrics/stage "5 cycles for traceback/stage

Turbo Encoder
!Algorithm
D
Interleaver

M U X

!Implementation:
! bit-wise

XOR (block-wise XOR not possible) ! tuned C, uses _rotl()

" rate 1/2: 8 cycles/bit " rate 1/3: 9.7 cycles/bit

Turbo Decoder
!Algorithm (high-level decoder)
{L c y sk } {L c y p1k } {L c y p2k } {u k }
MAP1

{Le1 } k

MAP2

{Lek2 }

I-1

!Implementation
! 32-bit

alpha/beta/extrinsic accumulations ! tuned C (inner loop unrolling)

" max*: 10 cycles/alpha/stage; 20 cycles/(beta+extrinsic)/stage " max : ~40% less than max*

Interleaving/Deinterleaving
!Algorithm (block interleaver)
write
1 5 9 2 6 10 14 3 7 11 15 4 8 12 16

read

13

!Implementation
! Interleaver

operates on bits ! Deinterleaver operates on bytes

" tuned C, deinterleaver uses _pack4(); _unpack4()
! Only

small lookup tables required (64 bytes)

Rate Matching
!Algorithm:
1 2 3 4 1 1 2 2 3 3 4 4

puncture
1 2 4

!Implementation:
! bit-level

repeat

operation:

" tuned C, uses _sshvr() and _bitr() " 4-5 cycles/bit

! byte-level

operation

" native C " 3 cycles/bit

Performance Summary
FUNCTION Transmitter CRC Encoder Convolutional Encoder Turbo Interleaver Turbo Encoder 1st Interleaver Rate Match 2nd Interleaver TOTAL Receiver 2nd Deinterleaver Rate Dematch 1st Deinterleaver Viterbi Decoder Turbo Decoder CRC Decoder TOTAL CPU Performance (MHz) 3GPP cdma2000 voice data voice data 0.04 0.47 0.02 0.37 0.02 N/A 0.01 N/A N/A 1.17 N/A 1.00 N/A 3.75 N/A 2.47 0.06 2.31 0.08 1.28 0.17 4.65 N/A N/A 0.11 1.97 N/A N/A 0.40 14.32 0.11 5.12 0.04 0.12 0.01 1.50 N/A 0.04 1.71 0.04 0.12 0.01 N/A 225.00 0.04 225.21 N/A N/A 0.02 1.40 N/A 0.03 1.44 N/A N/A 0.55 N/A 180.00 0.38 180.93

!Data Rates
! !

voice = 8kbps (3GPP), 9.6kbps (cdma2000) data = 384kbps(3GPP), 307.2kbps(cdma2000) flat memory model, close in performance to data/program in L1D/L1P if data is in L2, average degradation is 5-7%

! Memory model
! !

Conclusions
!At 800 MHz, C6400 can support symbolrate processing of:
"2-3 384kbps channels "320-400 voice channels

!A multistandard solution could consist of:

"one C6400 for all symbol-rate processing "one ASIC for each standard for chip-rate processing