A 50% Power Reduction Scheme for CMOS Relaxation Oscillator

ByungJoon Song, Hwicheol Kim, Youngdon Choi, and Wonchan Kim School of Electrical Engineering, Seoul National University, Seoul 151-742, Korea Phone:+82-2-880-7280, Fax: +82-2-885-6993, emai1:bjsongQeltn20.snu.ac.kr
Abstract-In this paper, a CMOS relaxation oscillator is presented. The proposed oscillator has only one tail current source unlike the emitter coupled multivibrator. All the tail current flows through the timing capacitor and thus the charging slope of the timing capacitor is doubled. This enhances the operating speed without increasing the power consumption. The oscillator is fabricated in a standard 0.8prn CMOS process. The maximum operating frequency is 923MHz at a 3.3V single supply, while the oscillator draws 6mA.

changing rate of the timing capacitor is doubled. The power consumption in this structure is the same with the previous case, but the operating speed is improved by almost two times. 11. THEC I R C U I T
D E S C R I P T I O N O F THE

P R O P 0 S ED RELAX AT1 0N 0S C I LL AT 0 R

I. INTRODUCTION

A relaxation oscillator, especially emitter coupled multivibrator, is one of commonly used oscillator configurations because it can be easily impleniented in monolithic forms [l]. Other advant.ages are that it can provide symmetrical and high frequency output waveforms. Fig. l(a) shows the circuit schematic of a CMOS relaxation oscillator and an illustration of its operation is shown in Fig. l(b) [al. This structure is similar t o the emitter coupled multivibrator except the level shifting stage. Thus operating principles are almost same. The oscillation frequency of the relaxation oscillator is proportional to the value of the charging current and inversely proportional to the value of the timing capacitor. In other words, the oscillation frequency is determined by the charging and discharging slopes of the timing capacitor. Referring to Fig. 1, the total current supplied to the oscillator is 21, but only one-half of the total current contributes to the charging current of the timing capacitor. The rest current does not affect the operating speed and thus it becomes a waste in terms of the power consumption. In the proposed oscillator, this inefficiency is eliminated by introducing additional switching transistors between the timing capacitor and the tail current sources. The two tail current sources are merged t o a single current source, and thus the
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Fig. 2(a) and Fig. 2(b) show the detailed circuit schematic and the operating principle of the proposed relaxation oscillator, respectively. Only one tail current source is used for the proposed relaxation oscillator. The transistors MN1 and MN2 act as a gain stage. The cross coupling between the transistors MN1 and MN2 assures that only one of the transistors MN1 and MN:! turns on. The gain stage also controls the operation of the differential pair formed by the transistors MN3 and MN4, which determines the charging direction of the timing capacitor. The gain stage has equal load transistors MP1 and MP,. These load transistors operate at the triode region and can be regarded as linear resistors approximately. The transistor MN5 supplies the tail current, and its value is determined by the control voltage, Ncont. Assuming that the transistor MN1 is on and the T transistor MN2 is off, V ~ U is VDD and V m is V D D - 2 1 4 where 2 1 is the value of the tail current source and R is the 'equivalent resistance of the load PMOS transistor MPI. Since the gate voltage of the transistor MN4 is higher than that of the transistor MN3, the charging current of the timing capacitor flows through the transistor MN4. This causes the voltage of nl to ramp down with a constant slope of 2I/C until the transistor MN2 turns on and the transistor MN1 turns off. At this time, V ~ U pulls down to V D D 2 1 4 and T V m pulls up to V D D . The direction of the tail current through the timing capacitor is reversed and the circuit enters the other half-cycle. This
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state is maintained until the voltage of 6 ramps down and reaches the level causing the transistor MN1 to turn on again. At this point, the transistors MN1 and MN4 turn on again and a new clock cycle begins. Comparing the oscillator in Fig. 1 with the proposed oscillator, the charging slope of the timing capacitor is increased by a factor of two in the proposed oscillator. Thus the operating speed is also increased by the same amount without penalty of the power consumption. The oscillator in 2 has no elements to limit the voltage swing and thus some auxillary circuit is needed to keep the voltage swing constant. The operating frequency cannot be varied by changing the value of the tail current source because the voltage swing also changes proportionally. The replica biasing technique is used to control the operating frequency [3]. In replica biasing, the voltage swing is nearly kept constant and thus the operating frequency becomes a linear function of the tail current. The replica biasing uses an operational amplifier and a half circuit of the oscillator, as shown in Fig. 3. The gate nodes of the transistors MN1 and MN2 are tied to VDD and the same current as the tail current flows through MP1 in replica biasing circuit. Thus V,,, determines the voltage swing of the oscillator. The gate voltage of NIPl or Pcont is controlled so that the V,,, becomes equal to the reference voltage(V,,f). This control voltage is also applied to the load transistors in the oscillator, and thus the voltage swing of the oscillator has constant value of VDD - V,,j irrespective of the tail current. In actual implementation, the transistors in the replica biasing circuit was scaled down to reduce the power consumption.

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MEASUREMENT RESULTS

ever, this produces a large parasitic capacitor between the bottom plate and the substrate, which causes an asymmetry during the operation. In actual realization of the timing capacitor, the single timing capacitor was divided into two small capacitors. The connection of two capacitors are interchanged to maintain the symmetry. The nominal value of the floating capacitor was designed to have 0.5pF. The value of the total parasitic capacitance including junction capacitances was about 1.5pF. The previous oscillator in Fig. 1 and the proposed oscillator was simulated to compare the operating speed. The simulation results reveal that the operating frequency of the proposed oscillator was improved by more than 30%, although the speed can be improved by 50% ideally. This is due to the fact that the switching transistors MN3 and MN4 do not completely switch the tail current. The transistors MN3 and MN4 operate at the triode region, and thus the switching characteristics become poor. The 80% of the total tail current flows into MN3 when MN3 is maximally on. The source follower was used to drive external 50ohm load. Fig. 4 shows the measured output waveform. The running frequency was 923MHz at the supply voltage of 3.3V. The measured rms jitter was 22ps. The VCO output spectrum is shown in Fig 5. The current drawn from the power supply was about 6mA. The minimum supply voltage was 2V and the running frequency was 450MI-Iz at that condition. The supply sensitivity of the VCO has also been measured. The power supply sensitivity of the oscillator was O.Ol%/mV when the supply voltage changed from 3.3V to 3.8V. Fig. 6 shows the measured operating range of the VCO. The operating range was observed from 650MHz to 923MHz. The tuning range was approximately 42%. IV. CONCLUSIONS In this paper, a high speed CMOS relaxation oscillator has been proposed. The proposed oscillator uses a single tail current source in contrast to the previous oscillator. This greatly helps to enhance the operating speed by accelerating the changing rate of the timing capacitor without increasing the power consumption. The operating speed is improved by more than 30% from the

The proposed oscillator has been fabricated with a 0.8pm CMOS process having a single poly layer and two layers of metal. The fabricated oscillator was packaged with 100-pin QFP. The active area is 420pm x 340pm. The timing capacitor was made of sandwiched metal layers because the double poly process was not available. The thickness of the oxide between two metal layers is quite large, and thus large areas are required to build the timing capacitor. How-

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(b)
Fig. 1. The previous CMOS relaxation oscillator. (a) Schematic of CMOS relaxation oscillator. (b) Illustration of the operating principle.

simulations. The measured data shows that the oscillator can operate at 923MHz at a 3.3V supply and draws 6mA.

ACKNOWLEDGMENT
The authors would like to thank the Hyundai Electronics Industries Corporation for their sup(b) port in chip fabrication. Fig. 2. The proposed CMOS relaxation oscillator .

(a)

REFERENCES .
[l]

Schematic of the proposed oscillator. (b) Illustration of the operating principle.

[2] [3]

Paul R. Gray and Robert G. Meyer, Analysis and design of Analog Integrated circuits, 2nd ed., New York:Wiley, 1984. Behard Razavi, A Study of Phase noise inCMOS Oscillators,, IEEE J. Solid-state Circuits, vol. 31, pp. 331-343, Mar. 1996. Ian A. Young, Jeffrey K. Greason, and Keng L. Wong, A PLL Clock Generator with 5 t o 110 MHz of Lock Range for Microprocessors, IEEE J. Solid-State Circuits, vol. 27, pp. 1599-1607, NOV. 1992.

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Replica Bias

Oscillator
Pcont

OUT 0-

-0

....

. . . . . . ..... . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . ..............

Fig. 5. The spectrum of the oscillator. Fig. 3. Overall schematic of the VCO with frequency control circuit.

6
I

Fig. 4. The operating waveform of the fabricated oscilla. tor.

Fig. 6. Oscillation frequency versus control voltage.

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