Unit - I 8086- PROCESSORS

COMPUTER AND ITS ORGANIZATION A Computer is a programmable machine. It responds to a specific set of instructi ons in a well-defined manner. It can execute a prerecorded list of instructions (a program ).Modern computers are electronic and digital. The actual machinery w ires, transistors, and circuits is called hardware. The instructions and data ar e called software. All general-purpose computers require the following hardware components: Memory: Enables a computer to store, at least temporarily, data and programs. Mass storage device: Allows a computer to permanently retain large amounts of da ta. Common mass storage devices include disk drives and tape drives. Input device: Usually a keyboard and mouse are the input device through which da ta and instructions enter a computer. Output device: A display screen, printer, or other device that lets you see what the computer has accomplished. Central processing unit (CPU): The heart of the computer, this is the component that actually executes instructions. In addition to these components, many others make it possible for the basic comp onents to work together efficiently. For example, every computer requires a bus that transmits data from one part of the computer to another. Computers can be generally classified by size and power as follows, though there is considerable overlap: Personal computer: A small, single-user computer based on a microprocessor. In a ddition to the microprocessor, a personal computer has a keyboard for entering d ata, a monitor for displaying information, and a storage device for saving data. Working station: A powerful, single-user computer. A workstation is like a perso nal computer, but it has a more powerful microprocessor and a higherquality moni tor. Minicomputer: A multi-user computer capable of supporting from 10 to hundreds of users simultaneously. Mainframe: A powerful multi-user computer capable of supporting many hundreds or thousands of users simultaneously. Supercomputer: An extremely fast computer that can perform hundreds of millions of instructions per second. Minicomputer: A midsized computer. In size and power, minicomputers lie between workstations a nd mainframes. A minicomputer, a term no longer much used, is a computer of a size intermediate between a microcomputer and a mainframe. Typically, minicomputers have been stand-alone computers (computer systems with attached terminals and other devices) sold to small and mid-size businesses for general business applications and to large enterprises for department-level oper ations. Workstation: A type of computer used for engineering applications (CAD/CAM), desktop publishi ng, software development, and other types of applications that require a moderat e amount of computing power and relatively high quality graphics capabilities. Workstations generally come with a large, high- resolution graphics screen, at l east 64 MB (mega bytes) of RAM, built-in network support, and a graphical user i nterface. Microcomputer: The term microcomputer is generally synonymous with personal comp uter, or a computer that depends on a microprocessor. Microcomputers are designed to be used by individuals, whether in the form of PC s, workstations or notebook computers. A microcomputer contains a CPU on a microchip (the microprocessor), a memory

system (typically ROM and RAM), a bus system and I/O ports, typically housed in a motherboard. 8085 CPU Salient features 1.It is a 8 bit microprocessor 2.It is manufactured with N-MOS technology 3. It has 16-bit address bus and hence can address up to 216 = 65536 bytes (64KB) 4. The first 8 lines of address bus and 8 lines of data bus are multiplexed 5. Data bus is a group of 8 lines 6. It supports external interrupt request 7. A 16 bit program counter (PC) 8. A 16 bit stack pointer (SP) 9. Six 8-bit general purpose register arr anged in pairs: BC, DE, HL. 10. It requires a signal +5V power supply and operates at 3.2 MHZ single phase c lock. 11. It is enclosed with 40 pins DIP ( Dual in line package).

Functional Description: The 8085 is an 8-bit up capable of add. up to 64k bytes of memory. It has 8-addressable 8-bit registers, six of which can also be used as three pai rs of 16-bit There are five H/W Interrupts, in order of decreasing priority: 1.TRAP 2.RST7.5 3.RST6.5 4.RST5.5 5.INTR 8086 cpu The microprocessor was invented in the year 1971 in the Intel labs. The fir st processor was a 4bit processor and was called 4004.The following table gives chronologically the microprocessor revolution. Apart from Intel, Motorola, Zylog Corporation, Fairchild and Nat ional (Hitachi, Japan) are someof the other microprocessor manufacturers. Microprocessors are used in all modern appliances, which are Int elligent, meaning that they are capable of different modes of working. For examp le an automatic washing machine has different wash options, one for woolen and t he other for nylon etc., Also in a printing Industry right from type setting to page lay out to color photo scanning and printing and cutting and folding are al so taken care of by microprocessors. The applications of microprocessors can be sub divided into three categories. Th e first and most important one is the computer applications. The second one is t he control application (microcontrollers, embedded controllers etc.) and the thi rd is in Communication (DSP processors, Cellphones etc.). The basis of working of all the microprocessors is binary arithm etic and Boolean logic. The number system used is Hexadecimal (base 16) and the character code used is ASCII. Many assemblers are available to interface the mac hine code savvy processor to English language like programs of the users.(CP/M, MASM, TASM etc.). For Games we have joysticks, electronic guns and touch screens. Nowa days laptop and palmtop computers are proliferating and in future nano computing , bio computing, molecular and optical computing also are contemplated.

Different Components of Computers Microprocessor 8086, 8088, 80186, 80188, 80286, 80386, 80486, Pentium, Pentium Pro, Pentium II, Pentium III, Pentium IV Memory System DRAM, SRAM, Cache, ROM, Flash Memory, EEPROM, SDRAM, RAMBUS I/O System Printer, Serial communications, Floppy Disk Drive, Hard Disk Drive, Mouse, CD-ROM drive, Plotter, Keyboard, Monitor, Scanner, DVD, Pen Drive Summary of Simple Microcomputer Bus Operation 1. A microcomputer fetches each program instruction in sequence, decodes the instruction, and executes it. 2. The CPU in a microcomputer fetches instructions or reads data from memory by sending out an address on the address bus and a Memory Read signal on the contro l bus. The memory outputs the addressed instruction or data word to the CPU on t he data bus. 3. The CPU writes a data word to memory by sending out an address on the address bus, sending out the data word on the data bus, and sending a Memory write sign al to memory on the control bus. 4. To read data from a port, the CPU sends out the port address on the address b us and sends an I/O Read signal to the port device on the control bus. Data from the port comes into the CPU on the data bus. 5. To write data to a port, the CPU sends out the port address on the address bu s, sends out the data to be written to the port on the data bus, and sends an I/ O Write signal to the port device on the control b 8086 Internal Block diagram The block diagram of 8086 is as shown. This can be subdivided into two parts, na mely the Bus Interface Unit and Execution Unit. The Bus Interface Unit consists of segment registers, adder to generate 20 bit address and instruction prefetch queue. Once this address is sent out of BIU, the instruction and data bytes are fetched from memory and they fill a First in First out 6 byte queue. Execution Unit: The execution unit consists of scratch pad registers such as 16-bit AX, BX, CX a nd DX and pointers like SP (Stack Pointer), BP (Base Pointer) and finally index registers such as source index and destination index registers. The 16-bit scrat ch pad registers can be split into two 8-bit registers. For example, AX can be s plit into AH and AL registers. The segment registers and their default offsets a re given below. The Arithmetic and Logic Unit adjacent to these registers perform all the operat ions. The results of these operations can affect the condition flags. Different registers and their operations are listed below

There are three internal buses, namely A bus, B bus and C bus, which interconnec t the various blocks inside 8086.The execution of instruction in 8086 is as foll ows: The microprocessor unit (MPU) sends out a 20-bit physical address to the memory and fetches the first instruction of a program from the memory. Subsequent addre sses are sent out and the queue is filled upto 6 bytes. The instructions are dec oded and further data (if necessary) are fetched from memory. After the executio n of the instruction, the results may go back to memory or to the output periphe ral devices as the case may be. Memory segmentation The segment registers have contents of 16-bits. Hence, 216 = 64Kb of memory can be addressed by segment registers. Normally, the segment base register contains

three zeroes, so that each segment can start from say E0000 to EFFFF. The segmen ts namely code segment, data segment, stack segment and extra segment for a part icular program can be contiguous, separate or in case of small programs overlapp ing even. i.e., for example, code segment is supposed to have 64Kb and in case o f small programs data segment may be within the code segment. Fig: One way four 64-Kbyte segment might be positioned within the 1-Mbyte addres s space

The 20 bit address is generated from two 16-bit registers. The first 16-bit regi ster is called the segment base register. These are code segment registers to ho ld programs, data segment register to keep data, stack segment register for stac k operations and extra segment register to keep strings of data. The contents of the segment registers are shifted left four times with zeroes (0s) filling on th e right hand side. This is similar to multiplying four hex numbers by the base 1 6. This multiplication process takes place in the adder and thus a 20 bit number is generated. This is called the base address. To this a 16-bit offset is added to generate the 20-bit physical address. Segmentation helps in the following wa y. The program is stored in code segment area. The data is stored in data segmen t area. In many cases the program is optimized and kept unaltered for the specif ic application. Normally the data is variable. So in order to test the program w ith a different set of data, one need not change the program but only have to al ter the data. Same is thecase with stack and extra segments also, which are only different type of data storage facilities. ADDRESSING MODES Implied - the data value/data address is implicitly associated with the instructi on. Register - references the data in a register or in a register pair. Immediate - the data is provided in the instruction. Direct - the instruction operand specifies the memory address where data is locat ed. Register indirect - instruction specifies a register containing an address, where data is located. This addressing mode works with SI, DI, BX and BP registers. Based:- 8-bit or 16-bit instruction operand is added to the contents of a base re gister (BX or BP), the resulting value is a pointer to location where data resides. Indexed:- 8-bit or 16-bit instruction operand is added to the contents of an inde x register (SI or DI), the resulting value is a pointer to location where data resides Based Indexed:- the contents of a base register (BX or BP) is added to the conten ts of an index register (SI or DI), the resulting value is a pointer to location where data resides. Based Indexed with displacement:- 8-bit or 16-bit instruction operand is added to the contents of a base register (BX or BP) and index register (SI or DI), the result ing value is a pointer to location where data resides. INSTRUCTION SET OF 8086 The instructions of 8086 are classified into SIX groups. They are: 1. DATA TRANSFER INSTRUCTIONS 2. ARITHMETIC INSTRUCTIONS 3. BIT MANIPULATION INSTRUCTIONS 4. STRING INSTRUCTIONS 5. PROGRAM EXECUTION TRANSFER INSTRUCTIONS

6. PROCESS CONTROL INSTRUCTIONS 1. DATA TRANSFER INSTRUCTIONS The DATA TRANSFER INSTRUCTIONS are those, which transfers the DATA from any one source to any one destination. The datas may be of any type. They are again class ified into four groups. They are:

2. ARITHMETIC INSTRUCTIONS These instructions are those which are useful to perform Arithmetic calculations , such as addition, subtraction, Multiplication and division. They are again cla ssified into four groups. They are: 3. BIT MANIPULATION INSTRUCTIONS These instructions are used to perform Bit wise operations. 4. STRING INSTRUCTIONS The string instructions function easily on blocks of memory. They are user frien dly instructions, which help for easy program writing and execution. They can sp eed up the manipulating code. They are useful in array handling, tables and reco rds 5. PROGRAM EXECUTION TRANSFER INSTRUCTIONS These instructions transfer the program control from one address to other addres s. (Not in a sequence). They are again classified into four groups. They are:

6. PROCESS CONTROL INSTRUCTIONS These instructions are used to change the process of the Microprocessor. They ch ange the process with the stored information. They are again classified into two groups. They are:

Addition: There are two instructions ADD and ADC Register Addition: ADD AL, BL AL=AL+BL ADD CX, DI CX=CX+DI ADD CL, 10H CL=CL+10 ADD [BX], AL the contents of AL are added with the contents of a memory location addressed by BX and the result is stored in the same memory location Example ADD AL, BL AL=10H BL=30H the result AL=40H ADD AX,[SI+2] the word content of the data segment memory location addressed by sum of SI+2 is added with AX and the result is stored in AX Example AX=1234H SI=2000 SI+2=2002 and let the word stored in memory location 2002 be 11 22H The result AX=2356H ADD BYTE PTR [DI],3 3 is added to the byte contents of the data segment memory Lo cation addressed by DI Example DI=2000 and the contents of that memory location is 11H The contents of address 2000 will be 14H after the execution of this instruction The contents of the flag register change after the addition operation. The flags affected are SIGN, CARRY, ZERO, AUX CARRY, PARITY,OVERFLOW. The INTR, TRAP and

other flags not affected. Immediate Addition An 8 bit immediate data is added. Example MOV AL, 10H ADD AL, 30H The result AL=40H Memory to register addition Example MOV AX, 0 ADD AX, DI ADD AX, DI+1 Let DI=2000 the contents of this memory location is 22H After first add AX will have 22+0=22H Then DI+1=2001 let the contents be 11H The result will be 33H Array addition The offset address of the array is moved to the SI or DI register Example MOV AL, 0 MOV SI, OFFSET of Array ADD AL,[SI] ADD AL,[SI+2] ADD AL,[SI+4] Increment addition INC adds a 1 to a register or a memory location used for memory increments Example INC AX This instruction adds one to the contents ox AX let Ax=1234H the result will be AX=1235H INC BYTE PTR [DI] This instruction adds one to the byte contents of the data segment location addr essed by DI Addition with carry ADC adds the bit in carry flag to the operand data. Example ADC AL,BH AL=AL+BH+CARRY ADC CX,AX CX=CX+AX+CARRY ADC BX,[BP+2] the word contents of the stack segment memory location addressed b y BP+2 is added to BX with carry and the result is stored in BX. Subtraction Many forms of subtraction appears to use with any addressing mode 8 16 and 32 bi t data SUB SBB subtract with borrow Register Subtraction: SUB AL, BL AL=AL-BL SUB CL, 10H CL=CL-10 The carry flag holds the borrow. Decrement A 1 is subtracted from the register or the memory location. Example DEC AX DEC BYTE PTR [DI] DEC CL DEC BL Subtracts 1 to from a register or a memory location CMP This changes only the flag the destination operand never changes This instructio n is usually followed by conditional jump instructions and tests the condition a gainst the flags

Multiplication The multiplication is performed on bytes words or double words and can be a sign ed integer or unsigned integer MUL: unsigned IMUL: signed Flags CARRY, OVERFLOW 8 Bit multiplication Example MOV BL, 05H MOV AL, 10H MUL BL The multiplicand is in AL The multiplier is in BL (even a memory location can be used) 8 Bit multiplicatio n Example IMUL BYTE PTR [BX] AL is multiplied by the byte contents of the data segment memory location addres sed by BX the Signed product is placed in AX For signed multiplication the product is in true binary form if positive and in twos complement form if negative Example AL 00000010 BL 10000100 AL contains +2 and BL contains -4 IMUL BL The product is -8 The product is in twos complement form stored in AX AX 11111000 Division DIV, IDIV The dividend is always a double width dividend that is divided by the operand an 8 bit division divides a 16 bit number by a 8 bit number Errors: Divide by zero, divide overflow AX register stores the dividend that is divided by contents of any 8 bit registe r or memory Location. the Quotient(result) moves to AL and AH has the remainder. For signed division the remainder always assumes sign of dividend and is an int eger AX=0010H equivalent to +16 BL=FDH equivalent to -3 DIV BL AL=05H and AH=-1 11111111H AX=1111111100000101H AX=0010H equivalent to +16 BL=FDH equivalent to -3 DIV BL AL=-5 11111011 and AH=1 AX=0000000111111011H BCD Arithmetic: The microprocessor allows manipulation of BCD and ASCII data BCD used in Cash re gisters and ASCII used by many programs There are two instructions DAA decimal adjust after addition DAS decimal adjust after subtraction Both instructions correct the result. The BCD number is stored as packed form 2 digits/byte andif unpacked form means 1 digit/byte it functions with AL only. DAA decimal adjust after addition The result is in AL The Logic of this instruction If lower nibble>9 or AF=1 add 06 After adding 06 if upper nibble>9 or CF=1 add 60 DAA instruction follows ADD or ADC

Example1 ADD AL, CL DAA Let AL=53 and CL=29 AL=53+29 AL=7C AL=7C+06 (as C>9) AL=82 ASCII Arithmetic Functions with ASCII coded numbers The numbers range from 30-39H for 0-9 AAA AAD AAM AAS use AX as source and destination AAA Example add 31H and 39H the result is 6AH it should have been 10 decimal which is 31H an d 30H.AAA is used to correct the answer Converts resulting contents of AL to unp acked decimal digits.AAA instruction examines the lower 4 bits of AL for valid B CD numbers and checks AF=0 sets The 4 high order bits to 0 AH cleared before addition If lower digit of AL is between 0-9 and AF=1 06 is added The upper 4 digits are cleared and incremented by 1 If the lower value of the lower nibble is greater than 9 then increment AL by 06 AH by 1 AF and CF set The higher 4 bits of AL are cleared to 0 AH modified To get the exact sum add 3030H to AX AAS Correct result in AL after subtracting two unpacked ASCII operand. The result is in unpacked decimal format If the lower 4 bits of AL are>9 or if AF=1 then AL=AL-6 and AH=AH-1 CF and AF se t Otherwise CF and AF set to 0 no correction Result the upper nibble of AL is 00 and the lower nibble may be any number from 0-9 AAM Follows multiplication instruction after multiplying two unpacked BCD numbers Converts the product available in AL into unpacked BCD Lower byte of result is in AL and upper in AH Example let the product is 5D in AL D>9 so add 6 =13H LSD of 13H is lower unpacked byte Increment AH, AH=5+1=6 upper unpacked byte After execution AH=06 and AL=03 MOV AL, 5 MOV CL, 5 MUL CL AAM Accomplishes conversion by dividing AX by 10Benefit of AAM converts from binary t o unpacked BCD use of AAM for conversion XOR DX, DX MOV CX, 100 DIV CX AAM ADD AX, 3030H XCHG AX, DX

AAM ADD AX, 3030H AAD Appears before division requires AX to contain two digit unpacked BCD number(not ASCII) before executing After adjusting AX with AAD it is divided by an unpacke d BCD number to generate a single digit result in AL with remainder in AH Example .MODEL .CODE .STARTUP MOV AL, 48H MOV AH, 0 AAM ADD AX, 3030H MOV DL, AH MOV AH, 2 PUSH AX INT 21H POP AX MOV DL, AL INT 21H .EXIT END Logic instructions AND OR Exclusive OR NOT TEST The above instructions perform bitwise operation and the src and destination cou ld be register or Memory location. Their function is same as logic operations JUMP Group of Instructions Introduction: In almost any meaningful program, we need to alter the sequential flow of execut ion.

Instruction at reset CS:IP: At rest, 8086 begins execution at the address FFFF:0 000H.There are only 16 bytes from this location to the end of the memory space ( FFFFH)! It is unlikely that any meaningful program can be written within this sp ace. Thus the instruction at this reset location is usually a long jump instructio n that transfers control to some suitable lower address based on the available m emory. A Sorting Program: A comparison-based sorting program would need to swap or not swap two elements based on the outcome of the comparison of the two elements. Th is would mean that we need an instruction to conditionally jump to some other loca tion in the program. Any number of such examples can be given to illustrate the need for instructions that alter the linear flow of control, either unconditiona lly or conditionally. Unconditional and Conditional Jump Instructions allow such a control over the execution flow. Unconditional Jump: No testing of any flags is involved in deciding whether a jump is to be executed or not. Control transfer occurs always. Conditional Jump Conditional jumps are always short jumps (relative displacement is -128 to +127)

. Based on the values of one or more flags, jump to target address may occur or ex ecution may continue with the next sequential instruction. Usually preceded by instructions like CMP, SUB, TEST, AND etc which affect the flags. Conditional jumps following general relative magnitude comparison are more Complicated. Consider the comparison of FEH with 1AH. Is FEH > 1AH ? The answer depends on how we interpret the numbers! Interpreted as Unsigned integers, 0FE H = 254 in decimal and 1A H = 170 in decim al. Thus 0FE H > 1A H is true. Interpreted as Signed integers using 2s Complement system, 0FE H = -2 in Decimal And 1A H = 170 Decimal. Thus 0FE H > 1A H is false! Thus, we have one set of conditional jump instructions that are to be used if th e numbers are to be interpreted as Unsigned Integers and another set of conditional jump Instructions that are to be used if the numbers are to be interpreted as Signed Integers. After comparison of Unsigned integers: Mnemonic Condition Operation JA Z=0 and C=0 Jump if above JAE C=0 Jump if above or equal JB C=1 Jump if below JBE Z=1 or C=1 Jump if below or equal After comparison of Signed integers: Mnemonic Condition Operation JG Z=0 and S=O Jump if greater than JGE S=O Jump if greater or equal JL S< >O Jump if less than JLE Z=1 or S< >O Jump if less or equal (Both S and O Flags are required to test the condition when comparing signed num bers!) After comparison of Signed or Unsigned integers: Mnemonic Condition Operation JE or JZ Z=1 Jump if equal or Jump if Zero JNE or JNZ Z=0 Jump if not equal or Jump if not Zero Alternative, less often used mnemonics also exist. JA same as JNBE JG same as JNLE JAE same as JNB JGE same as JNL JB same as JNAE JL same as JNGE JBE same as JNA JLE same as JNG Other Conditional Jump Instructions: Mnemonic Condition Operation JC C=1 Jump if carry set JNC C=0 Jump if no carry JO O=1 Jump if overflow JNO O=0 Jump if no overflow JS S=1 Jump if sign is set JNS S=0 Jump if no sign Some more Conditional Jump Instructions: Mnemonic Condition Operation JP or JPE P=1 Jump if parity set or Jump if parity is even JNP or JPO P=0 Jump if no parity or Jump if parity is odd JCXZ CX = 0 Jump if CX = 0 (Note that the last instruction, JCXZ is somewhat different from the rest in the sense that it Tests the contents of CX register rather than flags. This instruction, generally used in loops, is illustrated in later sessions. Programs illustrating other co nditional jump instructions are also discussed in later sessions.)

LOOP Instruction: Program loops are quite common. Most of the counting loops have a typical struct ure that is shown below: Mov cx, 10h; initialize the count that determines the number of ; times the loop is to be executed. Start1: instructions constituting the loop body Dec cx; decrement counter Jnz start1; repeat if not over If the pair of instructions that test whether the loop body is to be executed ag ain or not,That is the instructions, DEC CX and JNZ Start1, could be combined in to one Instruction, we would get more elegant and clearer program. The LOOP instruction does so combine the above pair of instructions. Thus the single instruction: LOOP LAB1is equivalent in effect to the two instructions: DEC CX JNZ LAB1 Conditional LOOP Instructions: These instructions are similar to LOOP instruction except that equality (Z flag) is also tested. This allows a loop to be controlled by a count as well as a com parison test (like in the case of String instructions). There are two such instructions. LOOPE (Loop While Equal) or LOOPZ Exit the loop if the condition is not equal or if CX decrements to 0. LOOPNE (Loop While Not Equal) or LOOPNZ Exit the loop if the condition is equal or if CX decrements to 0. WAIT Instruction Monitors the test/ pin of 8086. At the time of executing this instruction, if te st/ pin is low, there is no effect; execution simply continues with the next ins truction. However, if test/ is high, then 8086 waits in an idle state until test/ returns to low.test/ is sampled during leading edge of clk in each clock cycle d uring waiting. NOP Instruction It is a no operation instruction. It takes a short time to execute; otherwise no effect. Used in early days to provide for manual code patches. Some nop instruct ions would be written every 100 bytes or so. When code was to be patched, the sp ace occupied by the nop instructions was used. However, this is irrelevant in mo dern times because the Program development usually is based on assemblers nad ma nual coding is no more Common. HLT Instruction It halts the program; the processor enters the halt state. An interrupt or a hardwar e reset will force the 8086 out of the halt state.it may be used when the program has to wait for an interrupt to occur; but rarely used so in Practice. LOCK Prefix LOCK can be prefix of an instruction. When such an instruction is executed, the L OCK/ pin of 8086 is activated (forced LOW). Now, another bus master cannot gain control of the bus until the end of the bus lock. Thus the Lock prefixed instructi on executes as an indivisible instruction even if it has several memory cycles. Shift instructions They manipulate binary numbers Used to control I/O Devices. Shift operation moves the number either to left or right within Memory location or a register. There are four instructions. There a re two types of shift (1) Arithmetic and (2) logical. The shift left operation i s equivalent to multiply operation and shift right is divide operation. The data is shifted to left or right only by one position. Shift left operation Logical left: The contents of the register or memory location are shifted left b y one position the MSB bit moves to Carry flag bit and a zero is added to the LS

B position Example SHL AX,1 AX=0000 1111 0000 1111 and Carry=1 After the execution of the instruction AX=0001 1110 0001 1110 and Carry =0 Example MOV CL, 3 SHL DX, CL The contents of the DX register are shifted left by three postions Arithmetical Left: It is same as logical left shift. Logical right: The contents of the register or memory location are shifted right by one position the LSB bit moves to carry flag bit and a zero is added to the MSB position Example SHR AX,1 AX=0000 1111 0000 1111 and Carry=0 Result AX=0000 0111 1000 0111 and carry=1 Arithmetic right: The contents of the register or memory location are shifted ri ght by one position the LSB bit moves to Carry flag bit and the sign bit is copied through the MSB position Example SAL AX,1 AX=1000 0000 0000 1111 and carry=0 Result AX=1100 0000 0000 0111 and carry=1 Example SAR SI,3 SI= 1010 1100 1010 0101 C=0 After first shift SI= 1101 0110 0101 0010 C=1 second shift SI=1110 1011 0010 1001 C=0 third shift SI= 1111 0101 1001 0100 C=1 All condition flags are affected Rotation instructions There are four rotate instructions. Rotate left: the contents of the memory location or the register are rotated lef t by the no of Positions indicated in the instruction through the carry or witho ut the carry. ROL BL,4 Let BL=0001 0110 C=0 After first rotate C= 0 BL= 0010 1100 After second rotate C=0 BL= 0101 1000 After third rotate C=0 BL= 1011 0000 After fourth rotate C=1 BL= 0110 0000 Rotate right The contents of the memory location or the register are rotated right by the no of positions indicated in the instruction through the carry or without the carry . Assembly Language programming Assembler: is a program that accepts an assembly language program as input and c onverts it into an object module and prepares for loading the program into memor y for execution. Loader (linker) further converts the object module prepared by the assembler int o executable form, by linking it with other object modules and library modules. the final executable map of the assembly language program is prepared by the loa der at the time of loading into the primary memory for actual execution. The assembler prepares the relocation and linkages information (subroutine, ISR) for loader. the operating system that actually has the control of the memory, w

hich is to be allotted to the program for execution, passes the memory address at which the program is to be loaded for execution and the map of the available memory to the loader. Based on this information and the information generated by the assembler, the lo ader Generates an executable map of the program and further physically loads it into the memory and transfers control to for execution. Thus the basic task of an assembler is to generate the object module and prepare the loading and linking information. Procedure for assembling a program assembling a program proceeds statement by statement sequentially. The first phase of assembling is to analyze the program to be converted. This ph ase is called Pass1 defines and records the symbols, pseudo operands and directi ves. It also analyses the Segments used by the program types and labels and thei r memory requirements. the second phase looks for the addresses and data assigned to the labels. It als o finds out Codes of the instructions from the instruction machine, code database and the pr ogram data. It processes the pseudo operands and directives. It is the task of the assembler designer to select the suitable strings for usin g them asDirectives, pseudo operands or reserved words and decides syntax. Directives Also called as pseudo operations that control the assembly process. They indicate how an operand or section of a program to be processed by the asse mbler. They generate and store information in the memory. Assembler Memory models Each model defines the way that a program is stored in the memory system. Tiny: data fits into one segment written in .COM format Small: has two segments data and memory. There are several other models too. Directive for string data in a memory segment DB define byte DW define word DD define double word DQ define 10 bytes Example Data1 DB 10H,11H,12H Data2 DW 1234H SEGMENT: statement to indicate the start of the program and its symbolic name. Example Name SEGMENT Variable_name DB . Variable_name DW . Name ENDS Data SEGMENT Data1 DB . Data2 DW . Data ENDS Code SEGMENT START: MOV AX,BX Code ENDS Similarly the stack segment is also declared. For small models .DATA ENDS The ENDS directive indicates the end of the segment.

Memory is reserved for use in the future by using a ? as an operand for DB DW or DD Directive. The assembler sets aside a location and does not initialize it to any specific value (usually stores a zero). The DUP (duplicate) directive creat es an array and stores a zero. ExampleData1 DB 5 DUP(?) This reserves 5 bytes of memory for a array data1 and initializes each Location with 05H ALIGN: memory array is stored in word boundaries. Example ALIGN 2 means storing from an even address Address 0 XX Address 1 YY Address 2 XX The data XX is aligned to the even address. ASSUME, EQU, ORG ASSUME tells the assembler what names have been chosen for Code, Data Extra and Stack Segments. Informs the assembler that the register CS is to be initialized with t he address Allotted by the loader to the label CODE and DS is similarly initialized with th e address of label DATA. Example ASSUME CS: Name of code segment ASSUME DS: Name of the data segment ASSUME CS: Code1, DS: Data1 EQU: Equates a numeric, ASCII (American Standard Code for Information Interchang e) or Label to another label. Example Data SEGMENT Num1 EQU 50H Num2 EQU 66H Data ENDS Numeric value 50H and 66H are assigned to Num1 and Num2 ORG: Changes the starting offset address of the data in the data segment Example ORG 100H 100 data1 DB 10H it can be used for code too. PROC & ENDP: indicate the start and end of the procedure. They require a label t o indicate the name of the procedure. NEAR: the procedure resides in the same code segment. (Local) FAR: resides at any location in the memory. Example Add PROC NEAR ADD AX,BX MOV CX,AX RET Add ENDP PROC directive stores the contents of the register in the stack. EXTRN, PUBLIC informs the assembler that the names of procedures and labels decl ared after this directive have been already defined in some other assembly langu age modules. Example If you want to call a Factorial procedure of Module1 from Module2 itmust be decl ared as PUBLIC in Module1. Example A sample for full segment definition

Data SEGMENT Num1 DB 10H Num2 DB 20H Num3 EQU 30H Data ENDS ASSUME CS:Code,DS:Data Code SEGMENT START: MOV AX,Data MOV DS,AX MOV AX,Num1 MOV CX,Num2 ADD AX,CX Code ENDS Example A sample for small model . MODEL SMALL .Data Num1 DB 10H Num2 DB 20H Num3 EQU 30H .Code HERE: MOV AX,@Data MOV DS,AX MOV AX,Num1 MOV CX,Num2 ADD AX,CX BYTE AND STRING MANIPULATION String instructions REP it is a prefix used with instruction REPE/REPZ REPNE/REPNZ These are used with CMPS and SCAS instructions These instructions are used in the program as prefix. CMPS Compare string byte or string word Only Flags affected Zero flag set if strings match otherwise reset DS:SI and ES:DI are used to point to the two strings SCAS Scans the string of bytes or words for an operand byte or word specified in regi ster AL or AX When match found the ZF=1 otherwise it is reset LODS Load string byte or string word. Loads the AL/AX register by the contents of a s tring pointed by DS:SI No flag affected STOS:Stores contents of AL/AX register to a location in a string pointed by ES:D I No flag affected Strings and String Handling Instructions: The 8086 microprocessor is equipped with special instructions to handle string o perations. By string we mean a series of data words or bytes that reside in cons ecutive memory locations. The string instructions of the 8086 permit a programme r to implement operations such as to move data from one block of memory to a blo ck elsewhere in memory. A second type of operation that is easily performed is t o scan a string and data elements stored in memory looking for a specific value. Other examples are to compare the elements and two strings together in order to determine whether they are the same or different. Move String: MOV SB, MOV SW:

An element of the string specified by the source index (SI) register with respec t to the current data segment (DS) register is moved to the location specified b y the destination index (DI) register with respect to the current extra segment (ES) register. The move can be performed on a byte (MOV SB) or a word (MOV SW) o f data. After the move is complete, the contents of both SI & DI are automatical ly incremented or decremented by 1 for a byte move and by 2 for a word move. Add ress pointers SI and DI increment or decrement Depends on how the direction flag DF is set. Example : Block move program using the move string instruction MOV AX, DATA SEG ADDR MOV DS, AX MOV ES, AX MOV SI, BLK 1 ADDR MOV DI, BLK 2 ADDR MOV CK, N CDF ; DF=0 NEXT : MOV SB LOOP NEXT HLT Load and store strings : (LOD SB/LOD SW and STO SB/STO SW) LOD SB: Loads a byte from a string in memory into AL. The address in SI is used relative to DS to determine the address of the memory location of the string ele ment. LOD SW: The word string element at the physical address derived from DS and SI i s to be Loaded into AX. SI is automatically incremented by 2. STO SB: Stores a byte from AL into a string location in memory. This time the co ntents of ES and DI are used to form the address of the storage location in memo ry Repeat String : REP The basic string operations must be repeated to process arrays of data. This is done by inserting a repeat prefix before the instruction that is to be repeated. Prefix rep causes the basic string operation to be repeated until the contents of register cx become equal to zero. Each time the instruction is executed, it c auses cx to be tested for zero, if cx is found to be nonzero it is decremented b y 1 and the basic string operation is repeated. Example : clearing a block of me mory by repeating stosb MOV AX, 0 MOV ES, AX MOV DI, A000 MOV CX, OF CDF REP STOSB NEXT: The prefixes REPE and REPZ stand for same function. They are meant for use with the CMPS and SCAS instructions. With REPE/REPZ the basic compare or scan operati on can be repeated as long as both the contents of CX are not equal to zero and zero flag is 1. REPNE and REPNZ works similarly to REPE/REPZ except that now the operation is re peated as long as Cx=1 and ZF=0. Comparison or scanning is to be performed as lo ng as the string elements are unequal (ZF=0) and the end of the string is not ye t found . Auto Indexing for String Instructions : SI & DI addresses are either automatically incremented or decremented based on t he setting of the direction flag DF. When CLD (Clear Direction Flag) is executed DF=0 permits auto increment by 1. When STD (Set Direction Flag) is executed DF=1 permits auto decrement by 1. 1. LDS Instruction: LDS register, memory (Loads register and DS with words from memory) This instruction copies a word from two memory locations into the register speci fied in the Instruction. It then copies a word from the next two memory location

s into the DS register. LDS is useful for pointing SI and DS at the start of the string before using one of the string Instructions. LDS affects no flags. Example 1: LDS BX [1234] Copy contents of memory at displacement 1234 in DS to B L. Contents of 1235H to BH. Copy Contents at displacement of 1236H and 1237H is DS to DS register. Example 2 : LDS, SI String Pointer (SI) [String Pointer] (DS) [String Pointer +2] DS, SI now points at start and desired string 2. LEA Instruction : Load Effective Address (LEA register, source) This instruction determines the offset of the variable or memory location named as the source and puts this offset in the indicated 16 bit register. LEA will no t affect the flags LEA BX, PRICES; Load BX with offset and PRICES in DS LEA BP, SS : STACK TOP ;Load BP with offset of stack-top in SS LEA CX, [BX] [DI] ;Loads CX with EA : (BX) + (DI) 3. LES instruction : LES register, memory Example 1: LES BX, [789A H] Example 2 : LES DI, [BX] MACRO Definition: A macro has a name. The body of the macro is defined between a pair of directive s, MACRO and ENDM. Two macros are defined in the example given below. Examples of Macro Definitions: Definition of a Macro named PA2C PA2C MACRO PUSH AX PUSH BX PUSH CX ENDM Another Macro named POPA2C is defined here POPA2C MACRO POP CX POP BX POP AX ENDM

Unit III

8086 is a 40 pin DIP using MOS technology. It has 2 GNDs as circuit complexity de mands a large amount of current flowing through the circuits, and multiple groun ds help in dissipating the accumulated heat etc. 8086 works on two modes of oper ation namely, Maximum Mode and Minimum Mode. Pin Description: GND Pin no. 1, 20 Ground CLK Pin no. 19 Type I Clock: provides the basic timing for the processor and bus controller. It is asy mmetric with a 33% duty cycle to provide optimized internal timing. VCC Pin no. 40 VCC: +5V power supply pin (ii) Address/ Data Lines AD15-AD0 Pin no. 2-16, 39 Type I/O Address Data bus: These lines constitute the time multiplexed memory/ IO address (T1) and data (T2, T3, TW, T4) bus. A0 is analogous to BHE for the lower byte o f the data bus, pins D7-D0.It is low when a byte is to be transferred on the low er portion of the bus in memory or I/O operations. Eight bit oriented devices tie d to the lower half would normally use A0 to condition Chip select functions. Th ese lines are active HIGH and float to 3-state OFF during interrupt acknowledge and local bus hold acknowledge.

A19/S6, A18/S5, A17/S4, A16/S3 Pin no. 35-38 Type O Address / Status: During T1 these are the four most significant address lines fo r memory Operations. During I/O operations these lines are low. During memory an d I/O operations, status information is available on these lines during T2, T3, TW and T4. The statuses of the interrupt enable FLAG bit (S5) is updated at the beginning of each CLK cycle. A17/S4 and A16/S3 are encoded as shown. This information indicates which relocation register is presently being used for data accessing.These lines float to 3-state OFF during local bus hold acknowledg e.

(iv) Status Pins S0 - S7 Pin Description S2, S1, S0 - Pin no. 26, 27, 28 Type O Status: active during T4, T1 and T2 and is returned to the passive state (1, 1, 1) during T3 or during TW when READY is HIGH. This status is used by the 8288 Bu s Controller to generate all memory and I/O access control signals. Any change b y S2 , S1 or S0 during T4 is used to indicate the beginning of a bus cycle and t he return to the passive state in T3 or TW is used to indicate the end of a bus cycle.These signals float to 3-state OFF in hold acknowledge. These status lines a re encoded as

Pin Description: NMI Pin no. 17 Type I Non Maskable Interrupt: an edge triggered input which causes a type 2 interrupt. A subroutine is vectored to via an interrupt vector lookup table located in sys tem memory. NMI is not maskable internally by software. A transition from a LOW to HIGH initiates the interrupt at the end of the current instruction. This inpu t is internally synchronized. INTR Pin No. 18 Type I Interrupt Request: is a level triggered input which is sampled during the last c lock cycle of each instruction to determine if the processor should enter into a n interrupt acknowledge operation. A subroutine is vectored to via an interrupt vector lookup table located in system memory. It can be internally masked by sof tware resetting the interrupt enable bit. INTR is internally synchronized.This s ignal is active HIGH. (vi) Min mode signals Pin Description: HOLD, HLDA Pin no. 31, 30 Type I/O HOLD: indicates that another master is requesting a local bus hold. To be acknowle dged, HOLD must be active HIGH. The processor receiving the hold request will issue HLDA (HIGH) as an acknowledgement in the middle of a T1 clock cycle. Simultaneous wi th the issuance of HLDA the processor will float the local bus and control lines . After HOLD is detected as being LOW, the processor will Lower the HLDA, and wh en the processor needs to run another cycle, it will again drive the local bus a nd control lines. The same rules as RQ/GT apply regarding when the local bus wil l be released. HOLD is not an asynchronous input. External synchronization shoul d be provided if the system can not otherwise guarantee the setup time. WR - Pin no. 29 Type O Write: indicates that the processor is performing a write memory or write I/O cy cle, depending on the state of the M/IO signal. WR is active for T2, T3 and TW o f any write cycle. It is active LOW, and floats to 3-state OFF in local bus hold acknowledge. M/IO - Pin no. 28 type O Status line: logically equivalent to S2 in the maximum mode. It is used to disti nguish a memory access from an I/O access. M/IO becomes valid in the T4 precedin

g a bus cycle and remains valid until the final T4 of the cycle (M=HIGH), IO=LOW ). M/IO floats to 3-state OFF in local bus hold acknowledge. DT/R -Pin no. 27 Type O Data Transmit / Receive: needed in minimum system that desires to use an 8286/82 87 data bus transceiver. It is used to control the direction of data flow throug h the transceiver. Logically DT/R is equivalent to S1 in the maximum mode, and i ts timing is the same as for M/IO .(T=HIGH, R=LOW). This signal floats to 3-stat e OFF in local bus hold acknowledge. DEN - Pin no. 26 Type O Data Enable: provided as an output enable for the 8286/8287 in a minimum system which uses the transceiver. DEN is active LOW during each memory and I/O access and for INTA cycles. For a read or INTA cycle it is active from the middle of T2 until the middle of T4, while for a write cycle it is active from the beginning of T2 until the middle of T4. DEN floats to 3-state OFF in local bus hold acknow ledge. ALE Pin no. 25 Type O Address Latch Enable: provided by the processor to latch the address into the 82 82/8283 address latch. It is a HIGH pulse active during T1 of any bus cycle. Not e that ALE is never floated. INTA - Pin no. 24 Type O INTA is used as a read strobe for interrupt acknowledge cycles. It is active LOW during T2, T3and TW of each interrupt acknowledge cycle. (vii) Max mode signals

Pin Description: RQ/GT0 , RQ/GT1 - Pin no. 30, 31 Type I/O Request /Grant: pins are used by other local bus masters to force the processor to release the local bus at the end of the processors current bus cycle. Each pin is bidirectional with RQ/GT0 having higher priority than RQ/GT1 . RQ/GT has an internal pull up resistor so may be left unconnected. The request/grant sequence is as follows: 1. A pulse of 1 CLK wide from another local bus master indicates a local bus req uest (hold) to the 8086 (pulse 1) 2. During a T4 or T1 clock cycle, a pulse 1 CLK wide from the 8086 to the reques ting master (pulse 2), indicates that the 8086 has allowed the local bus to fl oat and that it will enter the hold acknowledge state at the next CLK. The CPUs b us interface unit is disconnected logically from the local bus during hold ackno wledge. 3. A pulse 1 CLK wide from the requesting master indicates to the 8086 (pulse 3) that the hold request is about to end and that the 8086 can reclaim the local bu s at the next CLK.Each master-master exchange of the local bus is a sequence of 3 pulses. There must be one deadCLK cycle after each bus exchange. Pulses are a ctive LOW.If the request is made while the CPU is performing a memory cycle, it will release the local bus during T4 of the cycle when all the following conditi ons are met: 1. Request occurs on or before T2. 2. Current cycle is not the low byte of a word (on an odd address) 3. Current cycle is not the first acknowledge of an interrupt acknowledge sequen ce. 4. A locked instruction is not currently executing. LOCK - Pin no. 29 Type O LOCK : output indicates that other system bus masters are not to gain control of the system bus while LOCK is active LOW. The LOCK signal is activated by the LOC K prefix instruction and remains active until the completion of the next instruct ion. This signal is active LOW, and floats to 3-state OFF in hold acknowledge. QS1, QS0 Pin no. 24, 25 Type O

Queue Status: the queue status is valid during the CLK cycle after which the que ue operation is performed. QS1 and QS0 provide status to allow external tracking of the internal 8086 instruction queue.

Pin Description: RD - Pin no. 34, Type O Read: Read strobe indicates that the processor is performing a memory of I/O rea d cycle, depending on the state of the S2 pin. This signal is used to read devices which reside on the 8086 local bus. RD is active LOW during T2, T3 and TW of any read cycle, and is guaranteed to remain HIGH in T2 until the 8086 local bus has float ed.This signal floats to 3-state OFF in hold acknowledge. READY Pin no. 22, Type I READY: is the acknowledgement from the addressed memory or I/O device that it wi ll complete the data transfer. The READY signal from memory / IO is synchronized by the 8284A Clock Generator to form READY. This signal is active HIGH. The 808 6 READY input is not synchronized. Correct operation is not guaranteed if the se tup and hold times are not met. TEST - Pin No 23 Type I TEST: input is examined by the Wait instruction. If the TEST input is LOW executio n Continues, otherwise the processor waits in an idle state. This input is synchro nized internally during each clock cycle on the leading edge of CLK. RESET Pin no. 21 Type I Reset: causes the processor to immediately terminate its present activity. The s ignal must be active HIGH for at least four clock cycles. It restarts execution, as described in the instruction set description, when RESET returns LOW. RESET is internally synchronized. BHE/S7 - Pin No. 34 Type O Bus High Enable / Status: During T1 the Bus High Enable signal ( BHE )should be used to enable data onto the most significant half of the data bus, pins D15-D8. Eight bit oriented devices tied to the upper half of the bus would normally use BHE to condition chip select functions. BHE is LOW during T1 for read, write, a nd interrupt acknowledge cycles when a byte is to be transferred on the high por tion of the bus. The S,7 status information is available during T2, T3 and T4. T he signal is active LOW and floats to 3-state OFF in hold. It is LOW during T1 for the first Interrupt acknowledges cycle. MN/MX - Pin no. 33 Type - I Minimum / maximum: indicates what mode the processor is to operate in. If the local bus is idle when the request is made the two possible events will f ollow: 1. Local bus will be released during the next clock. 2. A memory cycle will start within 3 clocks. Now the four rules for a currently active memory cycle apply with condition number 1 already satisfied. A minimum mode of 8086 configuration depicts a stand alone system of computer wh ere noOther processor is connected. This is similar to 8085 block diagram with t he following Difference. The Data transceiver block which helps the signals trav eling a longer distance to get boosted up. Two control signals data transmit/ re ceive are connected to the direction input of transceiver (Transmitter/Receiver) and DEN* signal works as enable for this block.

Write Cycle Timing Diagram for Minimum Operation This is the same as Read cycle Timing Diagram except that the DT/R* line goes hi gh indicating it is a Data Transmission operation for the processor to memory / peripheral. Again DEN* line goes low to validate data and WR* line goes low, ind icating a Write operation.

Bus Request & Bus Grant Timings in Minimum Mode System

The HOLD and HLDA timing diagram indicates in Time Space HOLD (input) occurs fir st and then the processor outputs HLDA (Hold Acknowledge). Maximum Mode 8086 System In the maximum mode of operation of 8086, wherein either a numeric coprocessor o f the type 8087 or another processor is interfaced with 8086. The Memory, Addres s Bus, Data Buses are shared resources between the two processors. The control s ignals for Maximum mode of operation are generated by the Bus Controller chip 87 88. The three status outputs S0*, S1*, S2* from the processor are input to 8788. The outputs of the bus controller are the Control Signals, namely DEN, DT/R*, I ORC*, IOWTC*, MWTC*, MRDC*, ALE etc. These control signals perform the same task as the minimum mode operation. However the DEN is an active HIGH signal which h as to be converted to active LOW by means of an inverter. Memory Read Timing in Maximum Mode

Here MRDC* signal is used instead of RD* as in case of Minimum Mode S0* to S2* a re activeand are used to generate control signal. Memory Write Timing in Maximum Mode Here the maximum mode write signals are shown. Please note that the T states cor respond to the time during which DEN* is LOW, WRITE Control goes LOW, DT/R* is H IGH and data output in available from the processor on the data bus. RQ / GT Timings in Maximum Mode Request / Grant pin may appear that both signals are active low. But in reality, Request signal goes low first (input to processor), and then the processor gran ts the request by outputting a low on the same pin. Read and Write Cycle Timing diagram of 8088

DMA The Intel* 8257 is a 4-channel direct memory access (DMA) controller. It is spec ifically designed to simplify the transfer of data at high speeds for the Intel m icrocomputer systems. Its primary function is to generate, upon a peripheral req uest, a sequential memory address which will allow the peripheral to read or wri te data directly to or from memory. Acquisition of the system bus in accomplishe d via the CPU s hold function. The 8257 has priority logic that resolves the per ipherals requests and issues a composite hold request to the CPU. It maintains t he OMA cycle count for each channel and outputs a control signal to notify the p eripheral that the programmed number of OMA cycles is complete. Other output con trol signals simplify sectored data transfers. The 8257 represents a significant savings in component count for DMA-based microcomputer systems and greatly simp lifies the transfer of data at high speed between peripherals and memories.

FUNCTIONAL DESCRIPTION General The 8257 is a programmable. Direct Memory Access (DMA) device which, when coupled with a single Intel8212 I/O port device, provide s a complete four-channel DMA controller for use in Intel microcomputer systems.A fter being initialized by software, the 8257 can transfer ablock of data, contai ning up to 16.384 bytes, between memory and a peripheral device directly, withou t furtherintervention required of the CPU. Upon receiving a DMAtransfer request from an enabled peripheral, the 8257: 1. Acquires control of the system bus. 2. Acknowledges that requesting peripheral which is connected to the highest pri ority channel. 3. Outputs the least significant eight bits of the memory address onto system ad dress lines A0-A7. Outputs the most significant eight bits of the memory address to the 8212 I/O port via.the data bus (the 8212 places these address bits on li nes A8-A15), and 4. Generates the appropriate memory and I/O read/ write control signals that cau se the peripheral to receive or deposit a data byte directly from or to the addr essed location in memory.The 8257 will retain control of the system bus and repe at the transfer sequence, as long as a peripheral maintains its DMA request. Thu s, the 8257 can transfer a block of data to/from a high speed peripheral (e.g.. a sector of data on a floppy disk) in a single "burst". When the specified Number of data bytes have been transferred, the 8257 activates its Terminal Coun t (TC) output, informing the CPU that the operation is complete. The 8257 offers three different modes of operation: (1) DMA read which causes data to be transferred from memory to a peripheral: (2) DMA write, which causes data to be transferred from a peripheral to memory: and (3) DMA verifies which does not actually involve the transfer of data. When an 8257 channel is in the DMA verify mode, it will respond the same as desc ribed for transfer operations, except that no memory or I/O read/write control s ignals will be generated, thus preventing the transfer of data The 8257. However , will gain control of the system bus and will acknowledge the peripheral s DMA request for each DMA cycle. The peripheral can use these acknowledge signals to enable an internal access of each byte of a data block in order to execute some verification procedure, such as the accumulation of a CRC (Cyclic Redundancy Cod e) check word. For example, a block of DMA verify cycles might follow a block of DMA read cycles(memory to peripheral) to allow the peripheral to verify its new

ly acquired data. Block Diagram Description 1. DMA Channels The 8257 provides four separate DMA channels (labeledCH-0 to CH-3). Each channel includes two sixteen-bit registers: (1) a DMA address register, and (2) a termi nal count register. Both registers must be initialized before a channel is enabl ed. The DMA address register is loaded with the address of the first memory loca tion to be accessed. The value loaded into the low-order 14-bits of the terminal count register specifies the number of DMA cycles minus one before the Terminal Count (TC) output is activated. For instance, a terminal count of 0 would cause the TC output to be active in the first DMA cycle for that channel. In general, if N = the number of desired DMA cycles, load the value N-1 into the low-order 14-bits of the terminal count register. The most significant two bits of the ter minal count register specify the type of DMA operation for that channel.

3. Read/Write Logic When the CPU is programming or reading one of the 8257*s registers (i.e., when t he 8257 is a "slave" device on the system bus), the Read/Write Logic accepts the I/O Read (USE) or I/O Write (175OT) signal, decodes the least significant four address bits, (A0-A3), and either writes the contents of the data bus into the a ddressed register(if I/OW is true) or places the contents of the addressed regis ter onto the data bus (if I/OR is true). During DMA cycles (i.e., when the 8257 is the bus "master"), the Read/Write Logic generates the I/O read and memory wri te (DMA write cycle) or I/O Write and memory read (DMA read cycle) signals which control the data link with the peripheral that has been granted the DMA cycle. Note that during DMA transfers Non-DMA I/O devices should be de-selected (disabl ed) using "AEN" signal to inhibit I/O device decoding of the memory address as a n erroneous device address I/O Read: An active-low, bi-directional three-state line. In the "slave" mode, i t is an input which allows the 8-bit status register or the upper/lower byte of a 18-bit DMA address register or terminal count register to be read. In the "mas ter" mode, I/OR is a control output which is used to access data from a peripher al during the DMA write cycle. (I/OW):I/O Write: An active-low, bi-directional three-state line. Inthe "slave" mode, it is an input which allows the contents of the data bus to be loaded into the 8-bit mode set register or the upper/lower byte of a 18-bit DMA address reg ister or terminal count register. In the "master" mode. I/OW is a control output which allows data to be output to a peripheral during a DMA read cycle. (CLK) Clock Input: Generally from an Intel 8224 Clock Generator device. (*2 TTL) or Intel 8085A CLK output. (RESET) Reset: An asynchronous input (generally from an 8224or 8085 device) which disabl es all DMA channels by clearing the mode register and 3-states all control lines . Address Lines: These least significant four address lines are bi-directional. In the "slave" mode they are inputs which select one of the registers to be read o r programmed. In the "master" mode, they are outputs which constitute the least significant four bits of the 16-bitmemory address generated by the 8257. (CS) Chip Select: An active-low input which enables the I/O Read or I/O Write input w hen the 8257 is being read or programmed in the "slave" mode. In the "master" mo de. CS is automatically disabled to prevent the chip from selecting itself while performing the DMA function. 4. Control Logic This block controls the sequence of operations during all DMA cycles by generati

ng the appropriate control signals and the 16-bit address that specifies the mem ory locations be accessed. Address Lines: These four address lines are three-state outputs which constitute bits 4 through 7 of the 16-bit memory address generated by the 8257 during all OMA cycles. (READY) Ready: This asynchronous input is used to elongate the memory read and write cyc les in the 8257 with wait states if the selected memory requires longer cycles. READY must conform to specified setup and hold times. (HRQ) Hold Request: This output requests control of the system bus. In systems with on ly one 8257, HRQ will normally be applied to the HOLD input on the CPU. HRQ must conform to specified setup and hold times. (HLDA) Hold Acknowledge: This input from the CPU indicates that the 8257 has acquired c ontrol of the system bus. (MEMR) Memory Read: This active-low three-state output is used to read data from the ad dressed memory location during DMA Read cycles. (MEMW) Memory Write: This active-low three-state output is used to write data into the addressed memory location during DMA Write cycles. (AOSTB) Address Strobe: This output strobes the most significant byte of the memory addr ess into the 8212 device from the data bus. (AEN) Address Enable: This output is used to disable (float) the System Data Bus and t he System Control Bus. It may also be used to disable (float) the System Address Bus by useof an enable on the Address Bus drivers in systems to inhibit non-DMA devices from responding during DMA cycles. It may be further used to isolate th e 8257 data busfrom the System Data Bus to facilitate the transfer of the 8 most significant DMA address bits over the 8257 data I/O pins without subjecting the System Data Bus to any timing constraints for the transfer. When the 8257 is us edin an I/O device structure (as opposed to memorymapped), this AEN output shoul d be used to disable theselection of an I/O device when the DMA address is on th eaddress bus. The I/O device selection should bedetermined by the DMA acknowledg e outputs for the (TC) Terminal Count: This output notifies the currently selected peripheral that the present DMA cycle should be the last cycle for this data block. If the TC STOP b it in the Mode Set register is set. the selected channel will be automatically d isabled at the end of that DMA cycle. TC is activated when the 14-bit value in t he selected channel s terminal count register equals zero. Recall that the lowor der14-bits of the terminal count register should be loaded with the values (n-1) . Where n = the desired number of the DMA cycles. (MARK) Modulo 128 Mark: This output notifies the selected peripheral that the current D MA cycle is the 128th cycle since the previous MARK output. MARK always occurs at128 (and all multiples of 1 28) cycles from the end of the data block. Only if the total number of DMA cycle s (n) is evenly divisable by 128 (and the terminal count register was loaded wit h n-1). will MARK occur at 128 (and each succeeding multiple of 128) cycles from the beginning ofthe data block. 5. Mode Sat Register When set, the various bits in the Mode Set register enable each of the four DMA channels, and allow four different options for the 8257: The Mode Set register is normally programmed by the CPU after the DMA address re gister(s) and terminalcount register(s) are initialized. The Mode Set Register i

s cleared by the RESET input, thus disabling all options, inhibiting all channel s, and preventing bus conflicts on power-up. A channel should not be left enabled unless its DMA address and termin al count registers contain valid values; otherwise, an inadvertent DMA request f rom a peripheral could initiate a DMA cycle that would destroy memory data. The various options which can be enabled by bits in the Mode Set register are explai ned below: Rotating Priority Bit 4 In the Rotating Priority Mode, the priority o f the channels has a circular sequence. After each DMA cycle, the priority of ea ch channel changes. The channel which had just been serviced will have the lowes t priority. If the ROTATING PRIORITY bit is not set (set to a zero).each DMA cha nnel has a fixed priority. In the fixed priority mode. Channel 0 has the highest priority and Channel 3 has the lowest priority. If the ROTATING PRIORITY bit is set to a one. the priority of each channel changes after each DMA cycle (not ea ch DMA request). Each channel moves up to the next highest priority assignment, while the channel which has just been serviced moves to the lowest priority assi gnment: Note that rotating priority will prevent any one channel from monopolizi ng the PMA mode; consecutive DMA cycles will service different channels ifmore, than one channel is enabled and requesting service. There is no overhead penalty associated with this mode of operation. All DMA operations began with Channel 0 initially Assigned to the highest priority for the first DMA cycle. Extended Write Bit 5If the EXTENDED WRITE bit is set. the duration of both the MEMW and I/OW signals i s extended by activating them earlier in the DMA cycle. Data transfers within mi crocomputer systems proceed asynchronously to allow use of various types of memo ry and I/O devices with different access times. If a device cannot be accessed w ithin a specific amount of time it returns a "not ready" indication to the 8257 that causes the 8257 to insert one or more wait states in its internal sequencin g. Some devices are fast enough to be accessed without the use of waitstates, bu t if they generate their READY response with the leading edge of the f/SW or MEM W signal they would normally cause the 8257 to enter a wait state because it doe s not receive READY in time. For systems with these types of devices, the Extend ed Write option provides alternative timing for the I/O and memory write signals which allows the devices to return an early READY and prevents the unnecessary occurrence of wait states in the 8257. thus increasing system throughput.TC Stop Bit 6If the TC STOP bit is set. a channel is disabled (i.e.. its enable bit is reset) after the Terminal Count (TC) output goes true, thus automatically preven ting further DMA operation on that channel. The enable bit for that channel must be re-programmed to continue or begin another DMA operation. If the TC STOP bit is not set. The occurrence of the TC output has no effect on the channel enable bits. In this case, it is generally the responsibility of the peripheral to cea se DMA requests in order to terminate DMA operation. Auto Load Bit 7The Auto Loa d mode permits Channel 2 to be used for repeat block or block chaining operation s, without immediate software intervention between blocks. Channel 2 registers a re initialized as usual for the first data block; Channel 3 registers, however, are used to store the block re-initialization parameters After the first block of DMA cycles is executed by Channel 2 (i.e.. after the T C output goes true), the parameters stored in the Channel 3 registers are transf erred to Channel 2 during an update" cycle. Note that the TC STOP feature, descri bed above, has no effect on Channel 2 when the Auto Load bit is set. If the Auto Load bit is set. the initial parameters for Channel 2 are automatica lly duplicated in the Channel 3registers when Channel 2 is programmed. This perm its repeat block operations to be set up with the programming of a single channe l. Repeat block operations can be used in applications such as CRT refreshing. C hannels 2 and 3can still be loaded with separate values if Channel 2 is Loaded before loading Channel 3. Note that in the Auto Load mode, Channel 3 is s till available to the user if the Channel 3 enable bit is set. but use of this c hannel will change the values to be auto loaded into Channel 2 at update time. A

ll that is necessary to use the Auto Load feature for chaining operations is to reload Channel 3registers at the conclusion of each update cycle with the new pa rameters for the next data block transfer. Each time that the 8257 enters an upd ate cycle, the update flag in the status register is set and parameters in Chann el 3 are transferred to Channel 2. non-destructively for Channel 3. The actual r e-initialization of Channel 2 occurs sat the beginning of the next channel 2 DMA cycle after the TC cycle. This will be the first DMA cycle of the new data bloc k for Channel 2. The update flag is cleared at the conclusion of this DMA cycle. For chaining operations, the update flag in the status register can be monitore d by the CPU to determine when the re-initialization process has been completed so that the next block parameters can be safely loaded into Channel 3.-6. Status Register

UNIT IV 8259 Priority Interrupt Controller The intersil 82c59a is a high performance priority interrupt controller manufact ured using an advanced 2 m cmos process. The 82c59a is designed to relieve the sys tem cpu from the task of polling in a multilevel priority system. The high speed and industry standard configuration of the 82c59a make it compatible with micro processors such as 80c286, 80286, 80c86/88, 8086/88,8080/85 and nsc800.the 82c59 a can handle up to eight vectored priority interrupting sources and is cascadabl e to 64 without additional circuitry. Individual interrupting sources can be mas ked or prioritized to allow custom system configuration. Two modes of operation make the 82c59a compatible with both 8080/85and 80c86/88/286 formats. Static cir cuit design ensures low operating power. The intersil advanced cmos process resu lts in performance equal to or greater than existing equivalent products at a fr action of the power.

82C59A Functional Description The 82C59A is a device specifically designed for use in real time, interrupt dri ven microcomputer systems. It manages eight levels of requests and has built-in features for expandability to other 82C59As (up to 64 levels). It is programmed by system software as an I/O peripheral. A selection of priority modes is availa ble to the programmer so that the manner in which the requests are processed by the 82C59A can be configured to match system requirements. The priority modes ca n be changed or reconfigured dynamically at anytime during main program operatio n. This means that the complete interrupt structure can be defined as required, based on the total system environment. Interrupt Request Register (IRR) and In-Service Register (ISR) The interrupts at the IR input lines are handled by two registers in cascade, th

e Interrupt Request Register (lRR) and the In- Service Register (lSR). The IRR i s used to indicate all the interrupt levels which are requesting service, and th e ISR is used tostore all the interrupt levels which are currently being service d. Priority Resolver This logic block determines the priorities of the bits set in the lRR. The highe st priority is elected and strobed into the corresponding bit of the lSR during the INTA sequence. Interrupt Mask Register (IMR) The lMR stores the bits which disable the interrupt lines to be masked. The IMR operates on the output of the IRR. Masking of a higher priority input will not affect the interrupt request lines o f lower priority. Interrupt (INT) This output goes directly to the CPU interrupt input. The VOH level on this line is designed to be fully compatible withthe 8080, 8085, 8086/88, 80C86/88, 80286 , and 80C286 input levels. Interrupt Acknowledge (INTA) INTA pulses will cause the 82C59A to release vectoring information onto the data bus. The Format of this datadepends on the system mode (mPM) of the 82C59A. Data Bus Buffer This 3-state, bidirectional 8-bit buffer is used to interface the 82C59A to the System Data Bus. Control words and status information are transferred through th e Data Bus Buffer. Read/Write Control Logic The function of this block is to accept output commands from the CPU. It contain s the Initialization Command Word (lCW) registers and Operation Command Word (OC W) registers which store the various control formats for device operation. This function block also allows the status of the 82C59A to be transferred onto the D ata Bus. Chip Select (CS) A LOW on this input enables the 82C59A. No reading or writing of the device will occur unless the device is selected. Write (WR) A LOW on this input enables the CPU to write control words(lCWs and OCWs) to the 82C59A. Read (RD) A LOW on this input enables the 82C59A to send the statusof the Interrupt Reques t Register (lRR), In-Service Register(lSR), the Interrupt Mask Register (lMR), o r the interruptlevel (in the poll mode) onto the Data Bus. A0 This input signal is used in conjunction with WR and RD signalsto write commands into the various command registers, as well as to read the various status regis ters of the chip.This line can be tied directly to one of the system address l i nes. The Cascade Buffer/Comparator This function block stores and compares the IDs of all 82C59As used in the syste m. The Associated three I/O pins (CAS0 - 2) are outputs when the 82C59A is used as a masterand are inputs when th e 82C59A is used as a slave. As amaster, the 82C59A sends the ID of the interrup ting slavedevice onto the CAS0 - 2 lines. The slave, thus selected willsend its preprogrammed subroutine address onto the DataBus during the next one or two con secutive INTA pulses. Interrupt Sequence The powerful features of the 82C59A in a micro computer system are its programma bility and the interrupt routine addressing capability. The latter allows direct or indirect jumping to the specified interrupt routine requested without any po lling of the interrupting devices. The normal sequence of events during an inter

rupt depend on the type of CPU being used. These events occur in an 8080/8085 system: 1. One or more of the INTERRUPT REQUEST lines(IR0 - IR7) are raised high, settin g the corresponding IRR bit(s). 2. The 82C59A evaluates those requests in the priority resolver and sends an int errupt (INT) to the CPU, if appropriate. 3. The CPU acknowledges the lNT and responds with an INTA pulse. 4. Upon receiving an lNTA from the CPU group, the highest priority lSR bit is se t, and the corresponding lRR bit is reset. The 82C59A will also release a CALL i nstruction code (11001101) onto the 8-bit data bus through D0 - D7. 5. This CALL instruction will initiate two additional INTApulses to be sent to 8 2C59A from the CPU group. 6. These two INTA pulses allow the 82C59A to release its preprogrammed subroutin e address onto the data bus.The lower 8-bit address is released at the first INT A pulseand the higher 8-bit address is released at the second INTA pulse. 7. This completes the 3-byte CALL instruction released bythe 82C59A. In the AEOI mode, the lSR bit is reset at theend of the third INTA pulse. Otherwise, the l SR bit remains set until an appropriate EOI command is issued at the end of the interrupt sequence.The events occurring in an 80C86/88/286 system are the same u ntil step 4. 4. The 82C59A does not drive the data bus during the first INTA pulse. 5. The 80C86/88/286 CPU will initiate a second INTA pulse.During this INTA pulse , the appropriate ISR bit is set and the corresponding bit in the IRR is reset. The 82C59Aoutputs the 8-bit pointer o nto the data bus to be read by the CPU. 6. This completes the interrupt cycle. In the AEOI mode, theISR bit is reset at the end of the Second INTA pulse. Otherwise,the ISR bit remains set until an app ropriate EOIcommand is issued at the end of the interrupt subroutine. Interrupt Sequence Outputs 8080, 8085 Interrupt Response Mode This sequence is timed by three INTA pulses. During the firstINTA pulse, the CAL L opcode is enabled onto the data bus.First Interrupt Vector Byte Data: Hex CDDu ring the second INTA pulse, the lower address of theappropriate service routine is enabled onto the data bus.When interval = 4 bits, A5 - A7 are programmed, whi leA0 - A4 are automatically inserted by the 82C59A. Wheninterval = 8, only A6 an d A7 are programmed, while A0 - A5are automatically inserted Programming the 82C59A The 82C59A accepts two types of command words generated by the CPU: 1. Initialization Command Words (ICWs): Before normaloperation can begin, each 8 2C59A in the system must be brought to a starting point - by a sequence of 2 to 4 bytestimed by WR pulses. 2. Operation Command Words (OCWs): These are thecommand words which command the 82C59A to operatein various interrupt modes. Among these modes are: a. Fully nested mode. b. Rotating priority mode. c. Special mask mode. d. Polled mode. The OCWs can be written into the 82C59A anytime after initialization. Initialization Command Words (lCWs) General Whenever a command is issued with A0 = 0 and D4 = 1, thisis interpreted as Initi alization Command Word 1 (lCW1). lCW1 starts the initialization sequence during which the followingautomatically occur: a. The edge sense circuit is reset, which means that followinginitialization, an interrupt request (IR) input must make a low-to-high transition to generate an interrupt.

b. c. d. e.

The Interrupt Mask Register is cleared. lR7 input is assigned priority 7. Special Mask Mode is cleared and Status Read is set tolRR. If lC4 = 0, then all functions selected in lCW4 are set to

. Initialization Command Word 3 (ICW3) This word is read only when there is more than one 82C59A in the system and casc ading is used, in which case SNGL = 0. It will load the 8-bit slave register. Th e functions of this register are: a. In the master mode (either when SP = 1, or in buffered mode when M/S = 1 in l CW4) a 1 is set for each slave in the bit corresponding to the appropriate IR line for the slave. The master then will release byte 1 of the call sequence (for 80 80/85 system) and will enable the corresponding slave to release bytes 2 and 3 ( for 80C86/88/286, only byte 2) through the cascade lines. b. In the slave mode (either when SP = 0, or if BUF = 1 and M/S = 0 in lCW4), bi ts 2 - 0 identify the slave. The slave compares its cascade input with these bit s and if they are equal, bytes 2 and 3 of the call sequence are released by it on the Data Bus. Initialization Command Word 4 (ICW4) SFNM: If SFNM = 1, the special fully nested mode is programmed.BUF: If BUF = 1, the buffered mode is programmed. Inbuffered mode, SP/EN becomes an enable output and the master/slave determination is by M/S. If buffered mode is selected: M/S = 1 means the82C59A is programmed to be a master, M/S = 0means the 82C59A is pro grammed to be a slave. If BUF = 0, M/S has no function. AEOI: If AEOI = 1, the a utomatic end of interrupt mode is programmed. mPM: Microprocessor mode: mPM = 0 sets the 82C59A for8080/85 system operation, mPM = 1 sets the82C59A for 80C86/88 /286 system operation. Operation Command Words (OCWs) After the Initialization Command Words (lCWs) are programmed into the 82C59A, th e device is ready to accept interrupt requests at its input lines. However, duri ng the82C59A operation, a selection of algorithms can command the 82C59A to operate in various modes through the Operation Command Words (OCWs ). Operation Command Word 1 (OCW1) OCW1 sets and clears the mask bits in the Interrupt Mask Register (lMR) M7 - M0 represent the eight mask bits. M = 1 indicates the channel is masked (inhibited) , M = 0 indicates the channel is enabled. Operation Command Word 2 (OCW2) R, SL, EOI - These three bits control the Rotate and End of Interrupt modes and combinations of the two. A chart ofthese combinations can be found on the Operat ion Command Word Format. L2, L1, L0 - These bits determine the interrupt level acted upon when the SL bit is active. Operation Command Word 3 (OCW3) ESMM - Enable Special Mask Mode. When this bit is set to 1 it enables the SMM bi t to set or reset the Special Mask Mode. When ESMM = 0, the SMM bit becomes a dont care.SMM - Special Mask Mode. If ESMM = 1 and SMM = 1, the82C59A will enter Speci al Mask Mode. If ESMM = 1 and SMM = 0, the 82C59A will revert to normal mask mod e.When ESMM = 0, SMM has no effect. Fully Nested Mode This mode is entered after initialization unless another mode is programmed. The interrupt requests are ordered in priority from 0 through 7 (0 highest). When a n interrupt is acknowledged the highest priority request is determined and its v ector placed on the bus. Additionally, a bit of the Interrupt Service register ( IS0 - 7) is set. This bit remains set until the microprocessor issues an End of Interrupt (EOI) command immediately before returning from the service routine, o r ifthe AEOI (Automatic End of Interrupt) bit is set, until the trailing edge of the last INTA. While the IS bit is set, all further interrupts of the same or l ower priority are inhibited, while higher levels will generate an interrupt (whi

ch will be acknowledged only if the microprocessor internal interrupt enable fli p-flop has been re-enabled through software). After the initialization sequence, IR0 has the highest priority and IR7 the lowest. Priorities can be changed, as will be explained in the rotating priority mode or via the set priority command.

The Special Fully Nested Mode This mode will be used in the case of a big system where cascading is used, and the priority has to be conserved within each slave. In this case the special ful ly nested mode will be programmed to the master (using lCW4). This mode is simil ar to the normal nested mode with the following Exceptions: a. When an interrupt request from a certain slave is in service, this slave is n ot locked out from the masters priority logic and further interrupt requests from higher priority IRs within the slave will be recognized by the master and will initiate interrupts to the processor. b. When exiting the Interrupt Service routine the software has to check whether the interrupt serviced was the only one from that slave. This is done by sending a non-specific End of Interrupt (EOI) command to the slave and then reading its In-Service register and checking for zero. If it is empty, a non-specified EOI can be sent to the master, too. If not, no EOI should be sent. Buffered Mode When the 82C59A is used in a large system where bus driving buffers are required on the data bus and the cascading mode is used, there exists the problem of ena bling buffers The buffered mode will structure the 82C59A to send an enable sign al on SP/EN to enable the buffers. In this mode, whenever the 82C59As data bus ou tputs are enabled, the SP/EN output becomes active. This modification forces the use of software programming to determine whether the 82C59A is a master or a sl ave. Bit 3in ICW4 programs the buffered mode, and bit 2 in lCW4determines whethe r it is a master or a slave. Cascade Mode The 82C59A can be easily interconnected in a system of one master with up to eig ht slaves to handle up to 64 priority levels. The master controls the slaves thr ough the 3 line cascade bus (CAS2 - 0). The cascade bus acts like chip selects t o the slaves during the INTA sequence. In a cascade configuration, the slave int errupt outputs (INT)are connected to the master interrupt request inputs. When a slave request line is activated and afterwards acknowledged, the master will en able the corresponding slave to release the device routine address during bytes 2 and 3 of INTA. (Byte 2 only for 80C86/88/286).The cascade bus lines are normal ly low and will contain the slave address code from the leading edge of the firs t INTA pulse to the trailing edge of the last INTA pulse. Each 82C59A in the sys tem must follow a separate initialization sequence and can be programmed to work in a different mode. An EOI command must be issued twice: once

The INTEL 8279 is specially developed for interfacing keyboard and display devic es to 8085/8086/8088 microprocessor based system. The important features of 8279 are, 1. Simultaneous keyboard and display operations. 2. Scanned keyboard mode. 3. Scanned sensor mode. 4. 8-character keyboard FIFO. 5. 1 6-character display.

6. Right or left entry 1 6-byte display RAM. 7. Programmable scan timing. Keyboard section: The keyboard section consists of eight return lines RL0 - RL7 that can be used t o form the columns of a keyboard matrix. It has two additional input: shift and control/strobe. The keys are automaticall y debounced. The two operating modes of keyboard section are 2-key lockout and N-key rollover . In the 2-key lockout mode, if two keys are pressed simultaneously, only the firs t key is recognized. In the N-key rollover mode simultaneous keys are recognized and their codes are stored in FIFO. The keyboard sections also have an 8 x 8 FIFO (First In First Out) RAM. The FIFO can store eight key codes in the scan keyboard mode. The status of the shift key and control key are also stored along with key code. The 8279 generate an interrupt signal when there is an eFIFO. Block diagram of 8279: The functional block diagram of 8279 is shown.

In sensor matrix mode the condition (i.e., open/close status) of 64 switches is stored in FIFO RAM. If the condition of any of the switches changes then the 827 9 asserts IRQ as high to interrupt the processor. Display section: The display section has eight output lines divided into two groups A0-A3 and B0B3. The output lines can be used either as a single group of eight lines or as two g roups of four lines, in conjunction with the scan lines for a multiplexed displa y. The output lines are connected to the anodes through driver transistor in case o f common cathode 7-segment LEDs. The cathodes are connected to scan lines through driver transistors. The display can be blanked by BD (low) line. The display section consists of 16 x 8 display RAM. The CPU can read from or wri te into any location of the display RAM. Scan section: The scan section has a scan counter and four scan lines, SL0 to SL3. In decoded scan mode, the output of scan lines will be similar to a 2-to-4 decod er. In encoded scan mode, the output of scan lines will be binary count, and so an e xternal decoder should be used to convert the binary count to decoded output. The scan lines are common for keyboard and display. The scan lines are used to form the rows of a matrix keyboard and also connected to digit drivers of a multiplexed display, to turn ON/OFF. CPU interface section: The CPU interface section takes care of data transfer between 8279 and the proce ssor. This section has eight bidirectional data lines DB0 to DB7 for data transfer bet ween 8279 and CPU. It requires two internal address A =0 for selecting data buffer and A = 1 for se lecting control register of8279. The control signals WR (low), RD (low), CS (low) and A0 are used for read/write to 8279. It has an interrupt request line IRQ, for interrupt driven data transfer with pr ocessor. The 8279 require an internal clock frequency of 100 kHz. This can be obtained by

dividing the input clock by an internal prescaler. The RESET signal sets the 8279 in 16-character display with two -key lockout key board modes.

UNIT V 8086 INTERRUPTS Normal program flow can be interrupted because of a variety of reasons When the i nterrupt occurs and is recognized, the values of the Flag register, CS and IP re gisters are saved on the stack and the control is transferred from the executing program to an associated Interrupt Service Routine (ISR). After completing the IS R control returns to the interrupted program. Thus, this mechanism is similar to yet different from Far Call. CALL is always an instruction in the program. The mechanism of calling & returning from ISR is somewhat different from normal CALL mechanism. Interrupt can be because of: an external interrupt signal at the pins nmi or intr . these are called hardware i nterrupts (studied in a later session). a software interrupt instruction. internal causes resulting from execution of other instructions etc, like interrupt On divide error. (sometimes called exceptions) Whatever be the source of interrupt: an interrupt instruction has an associated numeric operand called interrupt type code;a number in the range of 0 to 255 (00h to ffh). (thus we can have a total of 256 type codes) The interrupt type code: is provided by external hardware like interrupt controller (in the case of externa l interrupts). is specified as part of instruction in the case of software interrupts. is implicit in the case exceptions like divide error. Whatever be the source of interrupt & what ever be the type code: for an isr, both cs and ip are specified. to this extent, an isr is like a far procedure. cs and ip of an isr together constitute the interrupt vector. thus an interrupt vector is 2 + 2 = 4 bytes long. one interrupt vector is required for each interrupt type code. we have 256 poss ible interrupt type codes and thus 256 possible interrupt vectors. consequently , to specify all these interrupt vectors, we need 256 x 4 = 1024 bytes of memory. interrupt vector table: a table of 1024 bytes containing the 256 interrupt vecto rs. address range is 00000h (0:0) to 003ffh (0:03ffh). this is a memory block of 1kb starting from 00000h interrupt vector corresponding to interrupt type code n starts at location 4 x n . Example: interrupt type code = 20h corresponding interrupt vector starts at 20h x 4 = 80h. (in locations 80h, 81h, we have ip and in locations 82h, 83h, we have cs)

 another example: interrupt type code = 00h corresponding interrupt vector starts Whatever be the source of interrupt: An interrupt instruction has an associated numeric operand called interrupt type code; a number in the range of 0 to 255 (00H to FFH). (Thus we can have a total of 256 type codes) The interrupt type code: Is provided by external hardware like Interrupt Controller (in the case of externa l Interrupts). Is specified as part of instruction in the case of Software Interrupts. Is implicit in the case exceptions like Divide Error. Whatever be the source of interrupt & whatever be the type code: For an ISR, both CS and IP are specified. To this extent, an ISR is like a far procedure. CS and IP of an ISR together constitute the Interrupt Vector. Thus an interrupt vector is 2 + 2 = 4 bytes long. One interrupt vector is required for each interrupt type code. We have 256 Possibl e interrupt type codes and thus 256 possible interrupt vectors.Consequently, to specify all these interrupt vectors, we need 256 x 4 = 1024 bytesof memory. Interrupt Vector Table: A table of 1024 bytes containing the 256 interrupt vecto rs. Address range is 00000H (0:0) to 003FFH (0:03FFH). This is a memory block o f 1KB starting from 00000H Interrupt vector corresponding to interrupt type code n starts at location 4 x n . Example: Interrupt type code = 20H Corresponding interrupt vector starts at 20H x 4 = 80H. (In locations 80H, 81H, we have IP and in locations 82H, 83H, we have CS) Another Example: Interrupt type code = 00H Corresponding interrupt vector starts a t 00H x 4 = 00H. (00H, 01H: IP ; 02H, 03H: CS) Interrupt type codes: Some have predefined meaning; Some are reserved for future use; and Remaining interrupt type codes are free for user definitions. This scheme is shown in the following Interrupt Vector Table: Interrupt Processing: When an interrupt is to be processed: Flags, CS and IP are pushed on to the stack. (Note that no automatic pushing of Flags occurs with far Call!) T and I flags are cleared (disabling Single Step and External Interrupts) Control is transferred to the new CS : IP specified in the Interrupt Vector. (IS R begins execution.) Return from ISR: To return from the ISR, the interrupt return (IRET) instruction is used. Executing IRET pops IP, CS and Flags from the stack. In particular, the status of T and I flags is restored. Now, control returns to the interrupted program. I Flag: I flag is cleared disabling recognition of external interrupts. To enable them w ithin the ISR, programmer can enable them using STI (Set Interrupt Flag) instruction. CLI (Clear Interrupt Flag) instruction also clears the I flag disabling recognit ion of Interrupts from INTR pin. T Flag: Setting the T flag enables Single Step. The, after the execution of every instru ction, an interrupt of type 1 is generated. This feature is quite useful for debugging. Ev

idently, within the ISR, Single Step should not be in effect! So T is cleared. O n return from ISR, the value of T is restored. Software Interrupt Instructions (INT n): These instructions appear as regular instructions in the program code. INT 3 is 1 Byte long. (The only special case). Rest of INT n instructions are all 2 Byte long.These instructions are commonly used to access system procedures. Ex ample: INT 21H to access DOS services. A software interrupt instruction is more convenient than far call. It occupies l ess memoryas it needs only 1 or 2 bytes as against the 5 bytes required for a fa r Call. Further, there isno need to remember the CS:IP values. These values are obtained from the InterruptVector Table. INT 3 Instruction: Only INT n instruction that is 1 Byte long! Rest are 2 Byte long. This is often used to effect a breakpoint in the program. The breakpoint service r outine can provide Register values and other information useful for debugging. Any INT n can be used for implement a breakpoint. However, as INT 3 is only 1-byte long, it is comparatively easier to insert this instruction into the program. INTO Instruction: This instruction causes an Interrupt on Overflow. Thus if the O flag = 1, an int errupt is generated as Interrupt Vector 4. And if the O flag = 0 , this instruct ion results in no operation. This instruction is placed in the program usually after arithmetic instructions that may lead to overflow condition. (Recall that JO instruction also detects ov erflow condition.) Interrupts in PC: Type codes 0 to 4 are used in the standard way. Several interrupt type codes are dedicated to interrupts from hardware devices l ike keyboard, mouse etc. Examples: 9 for Keyboard; 17H for Parallel Port. Software interrupt instructions commonly used in Assembly Language Programs are: INT 21H : DOS Services INT 27H : Terminate and Stay Resident (TSR) INT 1AH : Clock Service etc.

UNIT VI The Intel 80286[1] (also called iAPX 286), introduced on 1 February 1982, was a 16-bit x86 microprocessor with 134,000 transistors. Like its contemporary simple r cousin, the 80186, it could correctly execute most software written for the ea rlier Intel 8086 and 8088.[2] It was employed for the IBM PC/AT, introduced in 1 984, and then widely used in most PC/AT compatible computers until the early 199 0s. The 80286 is the first member of the family of advanced microprocessors with memory management and wide protection abilities. ARCHITECTURE he 80286 was designed for multi-user systems with multitasking applications, inc luding communications (such as automated PBXs) and real-time process control. It had 134,000 transistors and consisted of four independent units: address unit, bus unit, instruction unit and execution unit, which formed a pipeline significa ntly increasing the performance.[6] It was produced in a 68-pin package includin g PLCC (Plastic Leaded Chip Carrier), LCC (Leadless chip carrier) and PGA (Pin G rid Array) packages.[7] The performance of the 80286 per clock cycle exceeded that of the Intel 8086 and Intel 8088 by more than two times. This increase of the 80286 s performance ove

r its immediate predecessors may be the largest among the generations of x86 pro cessors. Calculations of the addresses (such as base+index) were less expensive because they were performed by a special unit in the 286. The 8086 had to do eff ective address computation using its general ALU, which led to a significant clo ck penalty. Also, the 80286 was more efficient in complex mathematical operation s (such asMUL/DIV) than its predecessor.[6] The intel 80286 had a 24-bit address bus and was able to address up to 16 MB of RAM, compared to 1 MB for its predecessor. However cost and initial rarity of so ftware using the memory above 1 MB meant that 80286 computers were rarely shippe d with more than one megabyte of RAM.[6] Additionally, there was a performance p enalty involved in accessing extended memory from real mode, as noted below Protected mode An interesting feature of this processor is that it was the first x86 processor with protected mode. Protected mode enabled up to 16 MB of memory to be addresse d by the on-chip linear memory management unit (MMU) with 1 GB logical address s pace. The MMU also provided protection from (crashed or ill-behaved) application s writing outside their allocated memory zones. The MMU and protection mechanism s are enabled only in case of protected mode (except for the segment overrun pro tection) keeping them disabled in real mode of operation. Several additional ins tructions were introduced in protected mode of 80286, which are helpful for mult itasking operating systems. Another important feature of 80286 is Prevention of Unauthorised Access. This is achieved by: Forming different segments for data, code, and stack, and preventing their overl apping Assigning Privilege levels to each segment. Segment with lower privilege level c annot access the segment with higher privilege level. The 80286 provided built in memory protection mechanisms which had been almost e xclusive to mainframes and minicomputers (CPUs like the NS320xx and M68000 neede d additional components in order to implement MMU functions) and the large perfo rmance enhancements represented by the 80286 and many of its successors would pa ve the way for the x86 and the IBM PC architecture to extend from low performanc e personal computers all the way to high-end workstations and servers and even d rive the market for other architectures. In 80286 (and in its co-processor Intel 80287), arithmetic operations can be per formed on the following different types of numbers: unsigned packed decimal, unsigned binary, unsigned unpacked decimal, signed binary, and floating point numbers. By design, the 286 could not revert from protected mode to the basic 8086-compat ible "real mode" without a hardware-initiated reset. In the PC/AT introduced in 1984, IBM added external circuitry as well as specialized code in the ROM BIOS t o enable special series of program instructions to cause the reset, allowing rea l-mode reentry (while retaining active memory and control). Though it worked cor rectly, the method imposed a huge performance penalty. In theory, real-mode applications could be directly executed in 16-bit protected mode if certain rules were followed; however, as many DOS programs broke those rules, protected mode was not widely used until the appearance of its successor, the 32-bit Intel 80386, which was designed to go back and forth between modes e asily. When Intel designed the 286, it was not designed to be able to multitask real-mode applications; real mode was intended to be a simple way for a bootstra p loader to prepare the system and then switch to protected mode

80386 The 80386 microprocessor is an enhanced version of the 80286 microprocessor and includes a memory-management unit is enhanced to provide memory pagingThe 80386 also includ es 32-bit extended registers and a 32-bit address and data bus The 80386 has a physical memory size of 4GBytes that can be addressed as a virtu al memory with up to 64TBytes The 80386 is operated in the pipelined mode, it sends the address of the next in struction or memory data to the memory system prior to completing the execution of the current instruction This allows the memory system to begin fetching the next instruction or data bef ore the current is completed This increases access time, thus reducing the speed of the memoryThe I/O structu re of the 80386 is almost identical to the 80286, except that I/O can be inhibit ed when the 80386 is operated in the protected mode through the I/O bit protecti on map The register set of the 80386 contains extended versions of the registers introd uced on the 80286 microprocessor. These extended registers include EAX, EBX, ECX, EDX, EBP, ESP, E DI, ESI, EIP and EFLAGS The instruction set of the 80386 is enhanced to include instructions that addres s the 32-bit extended register set Interrupts, in the 80386 microprocessor, have been expanded to include additiona l predefined interrupts in the interrupt vector table The 80386 memory manager is similar to the 80286, except the physical addresses generated by the MMU are 32 bits wide instead of 24-bitsThe 80386 is also capabl e of paging The 80386 is operated in the real mode (i.e. 8086 mode) when it is resetThe rea l mode allows the microprocessor to address data in the first 1MByte of memory In the protected mode, 80386 addresses any location in its 4G bytes of physical address space

UNIT VII SERIAL COMMUNICATION. DCE AND DTE devices DTE stands for data terminal equipment, and DCE stands for data communications e quipment. These terms are used to indicate the pin-out for the connectors on a d evice and the direction of the signals on the pins. Your computer is a DTE devic e, while most other devices such as modem and other serial devices are usually d ce devices. Rs-232 has been around as a standard for decades as an electrical in terface between data terminal equipment (dte) and data circuit-terminating equip ment (DCE) such as modems. It appears under different incarnations such as rs-23 2c, rs-232d, v.24, v.28 or v.10. Rs-232 is used for asynchronous data transfer a s well as synchronous links such as sdlc, hdlc, frame relay and x.25 Synchronous data transfer In program-to-program communication, synchronous communication requires that eac h end of an exchange of communication respond in turn without initiating a new c ommunication. A typical activity that might use a synchronous protocol would be a transmission of files from one point to another. As each transmission is recei ved, a response is returned indicating success or the need to resend. Asynchronous data transfer The term asynchronous is usually used to describe communications in which data c an be transmitted intermittently rather than in a steady stream. For example, a telephone conversation is asynchronous because both parties can talk whenever th ey like. If the communication were synchronous, each party would be required to wait a specified interval before speaking. The difficulty with asynchronous comm unications is that the receiver must have a way to distinguish between valid dat a and noise. In computer communications, this is usually accomplished through a special start bit and stop bit at the beginning and end of each piece of data. F or this reason, asynchronous communication is sometimes called start-stop transm ission. RS232 RS-232 (Recommended standard-232) is a standard interface approved by the Electr onic Industries Association (EIA) for connecting serial devices. In other words, RS-232 is a long established standard that describes the physical interface and protocol for relatively low-speed serial data communication between computers a nd related devices. for teletypewriter devices. In 1987, the EIA released a new version of the standard and changedthe name to EIA-232-D. Many people, however, still refer to the standard as RS-232C, or just RS-232.RS-232 is the interface t hat your computer uses to talk to and exchange data with your modem and other se rial devices. The serial ports on most computers use a subset of the RS-232C sta ndard. 2.1. RS232 on DB9 (9-pin D-type connector) There is a standardized pin out for RS-232 on a DB9 connector, as shown below RS232 on DB25 (25-pin D-type connector) In DB-25 connector most of the pins are not needed for normal PC communications, and indeed, most new PCs are equipped with male D type connectors having only 9 pins. Using a 25- pin DB-25 or 9-pin DB-9 connector, its normal cable limitatio n of 50 feet can be extended to several hundred feet with high-quality cable. RS -232 defines the purpose and signal timing for each of the 25 lines; however, ma

ny applications use less than a dozen. There is a standardized pin out for RS-23 2 on a DB25 connector, as shown below. 2.4. Signal Description TxD: - This pin carries data from the computer to the serial device RXD: - This pin carries data from the serial device to the computer DTR signals: - DTR is used by the computer to signal that it is ready to communi cate with the Serial device like modem. In other words, DTR indicates to the Dataset that the DTE is ON. DSR: - Similarly to DTR, Data set ready (DSR) is an indication from the Dataset that it is ON. DCD: - Data Carrier Detect (DCD) indicates that carrier for the transmit data is ON. RTS: - This pin is used to request clearance to send data to a modem CTS: - This pin is used by the serial device to acknowledge the computer s RTS S ignal. In most situations, RTS and CTS are constantly on throughout the communic ation session. Clock signals (TC, RC, and XTC): - The clock signals are only used for synchrono us communications. The modem or DSU extracts the clock from the data stream and provides asteady clock signal to the DTE. Note that the transmit and receive clo ck signals do not have to be the same, or even at the same baud rate. CD: - CD stands for Carrier Detect. Carrier Detect is used by a modem to signal that it has a made a connection with another modem, or has detected a carrier to ne. In other words, this issued by the modem to signal that a carrier signal has been received from a remote modem. RI: - RI stands for Ring Indicator. A modem toggles (keystroke) the state of thi s line when an incoming call rings your phone. In other words, this is used by a n auto answer modem to signal the receipt of a telephone ring signal The Carrier Detect (CD) and the Ring Indicator (RI) lines are only available in connections to a modem. Because most modems transmit status information to a PC when either a car rier signal is detected (i.e. when a connection is made to another modem) or whe n the line is ringing, these two lines are rarely used. Limitations of RS-232 RS-232 has some serious shortcomings as an electrical interface. Firstly, the in terface presupposes a common ground between the DTE and DCE. This is a reasonabl e assumption where a short cable connects a DTE and DCE in the same room, but wi th longer lines and connections between devices that may be on different electri cal busses, this may not be true. We have seen some spectacular electrical event s causes by "uncommon grounds" .Secondly, a signal on a single line is impossibl e to screen effectively for noise. By screening the entire cable one can reduce the influence of outside noise, but internally generated noise remains a problem . As the baud rate and line length increase, the effect of capacitance between t he cables introduces serious crosstalk until a point is reached where the data i tself is unreadable. Using low capacitance cable can reduce crosstalk. Also, as it is the higher frequencies that are the problem, control of slew rate in the s ignal (i.e., making the signal more rounded, rather than square) also decreases the crosstalk. The original specifications for RS-232 had no specification for m aximum slew rate. Voltage levels with respect to ground represent the RS 232 sig nals. There is a wire for each signal, together with the ground signal (referenc e for voltage levels). This interface is useful for point-to-point communication at slow speeds. For example, port COM1 in a PC can be used for a mouse, port CO M2 for a modem, etc. This is an example of point-to-point communication: one por t, one device. Due to the way the signals are connected, a common ground is requ ired. This implies limited cable length - about 30 to 60 meters maximum. (Main p roblems are interference and resistance of the cable.) Shortly, RS 232 was desig ned for communication of local devices, and supports one transmitter and one rec

eiver. RS422 and RS485 When communicating at high data rates, or over long distances in real world envi ronments, single-ended methods are often inadequate. Differential data transmiss ion offers superior performance in most applications. EIA has recently released new serial interface, RS-422 and RS-485. These standards were designed for high speed communication. RS422 Serial Communication RS422 is a Standard interfaces approved by the Electronic Industries Association (EIA), and designed for greater distances and higher Baud rates than RS232. In its simplest form, a pair of converters from RS232 to RS422 (and back again) can be used to form an "RS232 extension cord." Data rates of up to 100K bits / seco nd and distances up to 4000 Ft. can be accommodated with RS422. RS422 is also sp ecified for multi-drop (party-line) applications where only one driver is connec ted to, and transmits on, a "bus" of up to 10 receivers.RS422 devices cannot be used to construct a truly multi-point network. A true multi-point network consis ts of multiple drivers and receivers connected on a single bus, where any node c an transmit or receive data. RS485 Serial Communication RS485 is an Electronics Industry Association (EIA) standard for multipoint commu nications. It supports several types of connectors, including DB-9 and DB-37. RS -485 is similar to RS-422 but can support more nodes per lineRS485 meets the req uirements for a truly multi-point communications network, and the standard speci fies up to 32 drivers and 32 receivers on a single (2-wire) bus. With the introd uction of "automatic" repeaters and high-impedance drivers / receivers this "lim itation" can be extended to hundreds (or even thousands) of nodes on a network. The RS-485 and RS-422 standards have much in common, and are often confused for that reason. RS-485, which specifies bi-directional, half-duplex data transmissi on, is the only EIA/TIA standard that allows multiple receivers and drivers in " bus" configurations. RS-422, on the other hand, specifies a single, unidirection al driver with multiple receivers. 8251 UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER (USART) The 8251 is a USART (Universal Synchronous Asynchronous Receiver Transmitter) fo r serial data communication. As a peripheral device of a microcomputer system, t he 8251 receives parallel data from the CPU and transmits serial data after conv ersion. This device also receives serial data from the outside and transmits par allel data to the CPU after conversion. The intel 8251a is the industry standard universal synchronous/asynchronou s receiver/transmitter (usart), designed for data communications with intel s mi croprocessor families such as mcs-48, 80, 85, and iapx-86, 88. the 8251a is used as a peripheral device and is programmed by the cpu to operate using virtually any serial data transmission technique presently in use (including ibm "bi-sync" ). the USART accepts data characters from the cpu in parallel format and then co nverts them into a continuous serial data stream for transmission. simultaneousl y, it can receive serial data streams and convert them into parallel data charac ters for the cpu. the usart will signal the cpu whenever it can accept a new cha racter for transmission or whenever it has received a character for the cpu. the cpu can read the complete status of the usart at any time. these include data t ransmission errors and control signals such as syndet, tx empty.

UNIT VIII 8051 Microcontroller Salient Features (1) 8 bit microcontroller originally developed by Intel in 1980. (2) High-performance CMOS Technology. (3) Contains Total 40 pins. (4) Address bus is of 16 bit & data bus is of 8 bit. (5) 4K bytes internal ROM (program). (6) 128 bytes internal RAM (data). (7) Four 8-bit I/O ports. (8) Two 16-bit timers. (9) Serial interface Communication. (10) 64K external code & data memory space. (11) 210 bit-addressable locations. (12) Internal memory consists of on-chip ROM and on-chip data RAM. (13) 8051 implements a separate memory space for programs (code) and data. (14) Operating frequency is 24MHz-33MHz. (15) +5V Regulated DC power supply is required to operate . (16) It has four 8 bit ports, total 32 I/O lines. (17) RAM, ROM, I/O ports, one serial port and timers are all on-chip. (18) 6-interrupts (2 are external with 2 priority levels). (19) Low-power Idle and Power-down Modes. (20) Full duplex UART. (21) 8051 has 21 special function registers (SFRs). 8051 Block diagram: Internal Architecture Oscillator Circuit:(1). The 8051 requires an external oscillator circuit. (3). The crystal generates 12M pulses in one second. (4). The pulse is used to synchronize the system operation in a controlled pace. (5). An 8051 machine cycle consists of 12 crystal pulses (clock cycle). (6). Used for synchronizing internal operations. (7). Pins XTAL1 & XTAL2 have been used. (8). The length of machine cycle depends on the frequency of the crystal oscilla tor connected to 8051. Internal memory: (1). 8051 implements a separate memory space for programs (code) and data. (2). Both code and data may be internal, however, both expand using external com ponents to a maximum of 64K code memory and 64K data memory. (3). Internal memory consists of on-chip ROM and on-chip data RAM. (4). On-chip RAM contains a rich arrangement of general purpose storage, bit add ressable storage, Register banks, and special function registers.

(5). In the 8051, the registers and input/output ports are memory mapped and acc essible like any other Memory location. (6). In the 8051, the stack resides within the internal RAM, rather than in exte rnal RAM. Registers RAM memory space allocation in the 8051 Microcontroller:

Special Function Registers: (1). ACC (2). B (3). PSW (4). SP (5). DPTR (5). IP (6). PMODE (7). PCON (8). TMODE (9). TCON etc.

Special Function Registers: 1). 8051 has 21 special function registers (SFRs) at the top of internal RAM fro m address 80H to FFH. (2). Most of the addresses from 80H to FFH are not defined, except for 21 of the m. (3). Some SFRs are both bit-addressable and byte addressable, depending on the in struction accessing the register. (4). This area consists of a series of memory-mapped ports and registers. (5). All 8051 CPU registers, I/O ports, timers and other architecture components are accessible in 8051 C through SFRs PSW (Program Status word) / Flag Register: Stack Pointer: (1). Stack pointer (SP) is an 8-bit register at address 81H. (2). It contains the address of the data item currently on top of the stack. (3). Stack operations include pushing data on the stack and popping data off the stack. (4). Pushing increments SP before writing the data (5). Popping from the stack reads the data and decrements the SP (6). 8051 stack is kept in the internal RAM (7). Depending on the initial value of the SP, stack can have different sizes (8). Example: MOV SP,#5FH (9). On 8051 this would limit the stack to 32 bytes since the uppermost address of on chip RAM is 7FH. Data pointer (DPTR): (1). Data pointer (DPTR): is used to access external data or code. (2). DPTR is a 16 bit register at addresses 82H (low byte) and 83H (high byte). (3). The data pointer is used in operations regarding external RAM and some inst ructions involving code memory. (4). Example: the following instructions write 55H into external RAM location 10 00H: MOV A,#55H MOV DPTR,#1000H MOVX @DPTR,A

I/O Ports: (1). One of the major features of a microcontroller is the versatility built int o the I/O circuits that connect the microcontroller to the outside world . (2). To be commercially viable, the 8051 had to incorporate as many I/O function s as were technically and economically possible. (3). One of the most useful features of the 8051 is four bidirectional I/O ports . (4). Each port has an 8-bit latch in the SFR space as mentioned earlier. (5). To reduce the overall package pin count, the 8051 employs multiple functio ns for each port. (6). Each port also has an output drive and an input buffer. (7). These ports can be used to general purpose I/O, as an address and data lin es. (8). The four 8-bit I/O ports P0, P1, P2 and P3 each uses 8 pins

PORT 1: (1). Port 1 is an 8-bit bidirectional I/0 port. (2). We r using pins no. from 1 to 9. (3). Port 1 have no dual functions. (4). When used as an output the pin latches are programmed to 0. (5). When used as an input the pin latches are programmed to 1. PORT 2: (1). Port 2 is an 8-bit bidirectional I/O port. (2). Port 2 emits the high-order address byte during fetches from external progr am memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). (3). When used as an output the pin latches are programmed to 0. (4). When used as an input the pin latches are programmed to 1. (5). We r using pins no. from 21 to 28. PORT 3: (1). Port 3 is an 8-bit bi-directional I/0 port. (2). We r using pins no. from 10 to 17. RXD (P3.0): Serial input port, TXD (P3.1): Serial output port, INT0 (P3.2): External interrupt, INT1 (P3.3): External interrupt, T0 T0 (P3.4): Timer 0 external input, T1 (P3.5): Timer 1 external input, WR (P3.6): External data memory write strobe, RD (P3.7): External data memory read strobe. Timers and Counters: (1). Many microcontroller applications require the counting of external events, such as frequency of a pulse train, or the generation of precise internal time d elays between actions. (2). Both of these tasks can be accomplished using software techniques. (3). The 8051 has two 16-bit registers that can be used as either timers or coun ters. (4). These two up counters are name T0 and T1 and are provided for general use o f the programmer. (5). Each counter may be programmed to count internal clock pulses, act as a tim er, or programmed to count external events as a counter. (6). The counters are divided into two 8-bit registers called the timer low (TL0 , TL1) and timer high (TH0, TH1) bytes. TMOD (Timer/Counter Control Register): SCON (Serial Port Control Register):

PCON (Power Mode Control Register): Interrupts: An interrupt is a special feature which Allows the 8051 to provide the illusion of "multitasking, although in reality the 8051 is only doing one thing at a time. The word "interrupt" can often be substituted with the word "event. An interrupt is triggered whenever corresponding event occurs. When the event oc curs, the 8051 temporarily puts "on hold" the normal execution of the program an d executes a special section of code referred to as an interrupt handler. Whenever any device needs its service, the device notifies the microcontroller b y sending it an interrupt signal. There are total 5 interrupt sources in 8051 Microprocessor as follows. (1). Timer Flag 0, (2). Timer Flag 1, (TF1 & TF2 are Timer Flag Interru pts). (3). INT 0, (4). INT 1, (INT 0 & INT 1 are external interrupts). (5). Serial Port Interrupt (RI or TI). Interrupts Priorities: Interrupt Priority (IP) SFR: Interrupt Enable (IE) SFR: 1.Assume that XTAL = 11.0592 MHz. What value do we need to load the timers regist er if we want to have a time delay of 5 ms(milliseconds)? Show the program for t imer 0 to create a pulse width of 5 ms on P2.3. Solution: Since XTAL = 11.0592 MHz, the counter counts up every 1.085 us. This means that out of many 1.085 us intervals we must make a 5 ms pulse. To get that, we divide one by the other. We need 5 ms / 1.085 us = 4608 clocks. To Achieve that we nee d to load into TL and TH the value 65536 4608 = EE00H. Therefore, we have TH = E E and TL = 00. CLR P2.3 ;CLEAR P2.3 MOV TMOD,#01 ;TIMER 0, 16-BITMODE HERE: MOV TL0,#0 ;TL0=0, THE LOW BYTE MOV TH0,#0EEH ;TH0=EE, THE HIGH BYTE SETB P2.3 ; SET HIGH P2.3 SETB TR0 ; START TIMER 0 AGAIN: JNB TF0, AGAIN ;MONITOR TIMER FLAG 0 CLR TR0 ; STOP THE TIMER 0 CLR TF0 ; CLEAR TIMER 0 FLAG 2.Assume that XTAL = 11.0592 MHz, write a program to generate asquare wave of 2 kHz frequency on pin P1.5. Solution: This is similar to Example 9-10, except that we must toggle the bit togenerate t he square wave. Look at the following steps. (a) T = 1 / f = 1 / 2 kHz = 500 us the period of square wave. (b) 1 / 2 of it for the high and low portion of the pulse is 250 us. (c) 250 us / 1.085 us = 230 and 65536 230 = 65306 which in hex is FF1AH. (d) TL = 1A and TH = FF, all in hex. The program is as follow. MOV TMOD,#01 AGAIN: MOV TL1,#1AH MOV TH1,#0FFH SETB TR1 BACK: JNB TF1, BACK ;TIMER 0, 16-BITMODE ;TL1=1A, LOW BYTE OF TIMER ;TH1=FF, THE HIGH BYTE ; START TIMER 1 ; UNTIL TIMER ROLLS OVER

CLR TR1 CLR P1.5 CLR TF1 SJMP AGAIN

; STOP THE TIMER 1 ; CLEAR TIMER FLAG 1 ; CLEAR TIMER 1 FLAG ; RELOAD TIMER

3. write a program for counter 1 in mode 2 to count the pulses and display the s tate of the TL1 count on P2, which connects to 8 LEDs. Solution: MOV TM0D,#01100000B ;counter 1, mode 2, ;C/T=1 external pulses MOV TH1,#0 ;clear TH1 SETB P3.5 ;make T1 input AGAIN: SETB TR1 ;start the counter BACK: MOV A,TL1 ;get copy of TL MOV P2,A ;display it on port 2 JNB TF1,Back ;keep doing, if TF = 0 CLR TR1 ;stop the counter 1 CLR TF1 ;make TF=0 SJMP AGAIN ;keep doing it Notice in the above program the role of the instruction SETB P3.5 4. Assume that the 8051 serial port is connected to the COM port of PC, and on t he PC, we are using the terminal.exe program to send and receive data serially. P1 and P2 of the 8051 are connected to LEDs and switches, respectively. Write an 8051 program to (a)send to PC the message We Are Ready, (b) receive any data send by PC and put it on LEDs connected to P1, and (c) get data on switches connected to P2 and send it to PC serially. The program should perform part (a) once, but parts (b) and (c) continuously, use 4800 baud rate. Solution: ORG 0 MOV P2,#0FFH ;make P2 an input port MOV TMOD,#20H ;timer 1, mode 2 MOV TH1,#0FAH ;4800 baud rate MOV SCON,#50H ;8-bit, 1 stop, REN enabled SETB TR1 ;start timer 1 MOV DPTR,#MYDATA ;load pointer for message H_1: CLR A MOV A,@A+DPTR ;get the character JZ B_1 ;if last character get out ACALL SEND ;otherwise call transfer INC DPTR ;next one SJMP H_1 ;stay in loop B_1: MOV a,P2 ;read data on P2 ACALL SEND ;transfer it serially ACALL RECV ;get the serial data MOV P1,A ;display it on LEDs SJMP B_1 ;stay in loop indefinitely ;----serial data transfer. ACC has the data-----SEND: MOV SBUF,A ;load the data H_2: JNB TI,H_2 ;stay here until last bit CLR TI ;get ready for next char RET ;return to caller RECV: JNB RI,RECV ;wait here for char MOV A,SBUF ;save it in ACC CLR RI ;get ready for next char RET ;return to caller ;-----The message--------------MYDATA: DB We Are Ready,0