LVDS-18: USER GUIDE Ver 0.

1
The LVDS-18 are designed to work with ICP JUKI-710,JUKI-740E,JUKI-745E, NOVA-600,NOVA-7896,NOVA-3710,NOVA-7895 ..etc. single board computers 50-pin LCD interface. The LVDS-18 supports the TFT LCD which equipped the 1 pixels/clock for LVDS interface.

1.

Connector description
J4: Power Connector for backlight inverter (JST:B8B-PH-K or equivalent) 1 2 3 4 5 6 7 8 +12V +12V +12V FPVEE/ENABKL NC GND GND GND

FPVEE/ENABKL: Power sequencing control for panel bias voltage FPVEE may also be configured as ENABKL JP2: LVDS CONNECTOR (Hirose DF14A-20P-1.25H) 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 PLCD PLCD GND GND TX0TX0+ GND TX1TX1+ GND TX2TX2+ GND TXCTXC+ GND TX3TX3+ GND GND

Warning!
Notice the pin order when cabling. Improper sequence might damage the LCD!

20

PLCD: Power supply from CPU board which can be configured as +5V or +3V supply. Please refer to the CPU board manual.

2.

Jumper setting
J2:
1 2

1 2

PDATA SHFCLK

J2 Open : for TFT application (default)

3.

Signal Description: 24bit color TFT a. LVDS interface

24bit color routing table of

SAMSUNG TFT-LCD Model No.: LTM150XH-L04 CHI MEI TFT-LCD Model No.:M150X3-L01
P16(R0) P17(R1) P18(R2) P19(R3) P20(R4) P21(R5) P8(G0) P9(G1) P10(G2) P11(G3) P12(G4) P13(G5) P0 (B0) P1 (B1) DCLK P2(B2) P3(B3) P4(B4) P5(B5) LP FLM M P22(R6) P23(R7) P14(G6) P15(G7) P6(B6) P7(B7) Reserved

TX0TX0+

TX2TX2+

TX1TX1+

TX3TX3+

TXCTXC+ 2

b. Reference J5: Panel Signal from CPU board (reference)

Signal Name VPCLK P34 1

Pin # 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49

Pin # 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50

Signal Name P33 P31 P32 P28 P27 P26 P21 P22 P20 P18 P14 P12 P11 P10 PLCD P8 P6 P5 P1 P0 ENABKL FLM LP GND +12V

P35 P30 P29 P25 P24 P23 P16 P17 P19 P13 P15 P7 PLCD P9 P4 50 P3 P2 M SHFCLK FPVDD FPVEE GND +12V

49

SHFCLK: Shift Clock. Pixel clock for flat panel data. FLM: First Line Marker.Flat Panel equivalent of VSYNC. LP: Latch Pulse(may also be called CL1). M: M signal for panel AC drive control (may also be called ACDCLK). Enablk: power sequencing control for enabling the backlight FPVEE: Power sequencing control for panel bias voltage VEE. May also be configured as ENABKL

Panel interface reference table(C&T65555) A

Pin# Pin Name 40 P0 38 P1 37 P2 35 P3 33 P4 36 P5 34 P6 27 P7 32 P8 31 P9 28 P10 26 P11 24 P12 23 P13 22 P14 25 P15 17 P16 19 P17 20 P18 21 P19 18 P20 14 P21 16 P22 15 P23 13 P24 11 P25 12 P26 10 P27 8 P28 9 P29 7 P30 4 P31 6 P32 2 P33 3 P34 5 P35 41 SHFCLK Pixels/Clock 8 : Mono SS 8-bit8-bit P0 P1 P2 P3 P4 P5 P6 P7 Mono DD 8 bit UD3 UD2 UD1 UD0 LD3 LD2 LD1 LD0 Mono DD 16 bit UD7 UD6 UD5 UD4 UD3 UD2 UD1 UD0 LD7 LD6 LD5 LD4 LD3 LD2 LD1 LD0 Color TFT 9/12/16 bit B0 B1 B2 B3 B4 G0 G1 G2 G3 G4 G5 R0 R1 R2 R3 R4 Color TFT 24bit 18bit B0 B1 B2 B3 B4 B5 B6 B7 G0 G1 G2 G3 G4 G5 G6 G7 R0 R1 R2 R3 R4 R5 R6 R7

B0 B1 B2 B3 B4 B5 G0 G1 G2 G3 G4 G5 R0 R1 R2 R3 R4 R5

SHFCLK 8 F: First

SHFCLK 16 S: Second

SHFCLK 1 U: Upper

SHFCLK 1 L: Lower

SHFCLK 1

R: Red G: Green B: Blue FLM : first line marker

SHFCLK: Shift Clock. Pixel clock for panel data LP : latch pulse (may also be called CL1) M: M signal for panel AC drive control (may also be called ACDCLK) Enablk: power sequencing control for enabling the backlight

Panel interface reference table(C&T65555) B

Pin# Pin Name 40 P0 38 P1 37 P2 35 P3 33 P4 36 P5 34 P6 27 P7 32 P8 31 P9 28 P10 26 P11 24 P12 23 P13 22 P14 25 P15 17 P16 19 P17 20 P18 21 P19 18 P20 14 P21 16 P22 15 P23 13 P24 11 P25 12 P26 10 P27 8 P28 9 P29 7 P30 4 P31 6 P32 2 P33 3 P34 5 P35 41 SHFCLK Pixels/Clock: Color TFT 36-bit FB0 FB1 FB2 FB3 FB4 FB5 SB0 SB1 SB2 SB3 SB4 SB5 FG0 FG1 FG2 FG3 FG4 FG5 SG0 SG1 SG2 SG3 SG4 SG5 FR0 FR1 FR2 FR3 FR4 FR5 SR0 SR1 SR2 SR3 SR4 SR5 SHFCLK 2 Color TFT HR 18/24 bit FB0 FB1 FB2 FB3 SB0 SB1 SB2 SB3 FG0 FG1 FG2 FG3 SG0 SG1 SG2 SG3 FR0 FR1 FR2 FR3 SR0 SR1 SR2 SR3 Color STN SS 8-bit (46p) R1 B1 G2 R3 B3 G4 R5 B5 Color STN SS 16-bit (46p) R1 G1 B1 R2 G2 B2 R3 G3 B3 R4 G4 B4 R5 G5 B5 R6 Color STN DD 8-bit (46p) UR1 UG1 UB1 UR2 LR1 LG1 LB1 LR2 Color STN DD 16-bit (46p) UR0 UG0 UBO UR1 LR0 LG0 LB0 LR1 UG1 UB1 UR2 UG2 LG1 LB1 LR2 LG2 Color STN DD 24-bit UR0 UG0 UB0 LR0 LG0 LB0 UR1 UG1 UB1 LR1 LG1 LB1 UR2 UG2 UB2 LR2 LG2 LB2 UR3 UG3 UB3 LR3 LG3 LB3

SHFCLK 2 F: First

SHFCLK 2-2/3

SHFCLK 5-1/3

SHFCLK 2-2/3

SHFCLK 5-1/3

SHFCLK 8

R: Red G: Green B: Blue FLM : first line marker

S: Second

U: Upper

L: Lower

SHFCLK: Shift Clock. Pixel clock for panel data LP : latch pulse (may also be called CL1) M: M signal for panel AC drive control (may also be called ACDCLK) Enablk: power sequencing control for enabling the backlight