Cng ty ng dng v pht trin sn phm cng ngh VTECH

Bi 7: Timer/Counter
1) Tng quan v Timer/Counter:
+Chc nng chnh ca cc b Timer/Counter, nh tn gi ca chng, l nh th (to ra 1 khong thi gian, m thi gian), v m s kin bn ngoi. +Ngoi ra trn cc chip AVR, cc b Timer/Counter cn c chc nng iu ch rng xung PWM(Pulse width Modulation), ng dng trong iu khin tc ng c v iu khin sng ti ca bng n +Cc b Timer c th hot ng vi tn s bn trong (ly t thch anh), cng c th hot ng vi tn s bn ngoi, a vo u vo ca b Timer. C th dng ng dng ny m sn phm, hay o rng xung. +Timer/Counter 0: y l 1 b timer 8 bit. C 4 ch hot ng c bn l: Normal, CTC, Past PWM, Phase correct PWM. + Timer/Counter 1: y l 1 b timer 16 bit. N cng c y cc ch hot ng nh ca Timer 0, tuy nhin v l b timer 16 bit nn phm vi hot ng ca n rng hn. Nu nh gi tr MAX trong Timer0 ch l 0xFF, th gi tr MAX trong Timer1 ln n 0xFFFF. Ngoi ra b Timer1 cn c th to ra 2 tn hiu PWM c lp cc chn OC1A (PORTD.5) v OC1B (PORTD.4), gip d dng khi iu khin 2 ng c cng 1 lc (2 ng c chy bnh). +Timer/Counter 2: y l 1 b Timer 8 bit. N cng c 4 ch hot ng c bn ging nh Timer0, l: Normal, CTC, Past PWM, Phase correct PWM.

2) Gii thiu cc thanh ghi trong Timer/Counter 0:

+Thanh ghi TCNT0 (Timer/Counter Register):

y l 1 thanh ghi 8 bit cha gi tr vn hnh ca Timer0. C mi ln xut hin 1 tn hiu kch th gi tr ca thanh ghi ny tng thm 1 n v. Gi tr MAX m thanh ghi ny c th t n l 255. Sau nu xut hin thm 1 xung kch na th gi tr ca thanh ghi ny c xa v 0.

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Cng ty ng dng v pht trin sn phm cng ngh VTECH

+Thanh ghi OCR0 (Output Compare Register):

y l 1 thanh ghi 8 bit. Gi tr vn hnh ca Timer TCNT0 s lin tc c so snh vi thanh ghi ny. Khi 2 gi tr ny bng nhau, th xy ra 1 s kin Compare Match. S kin ny s to ra 1 ngt (nu ngt c cho php), hay xut tn hiu ra chn OC0, ty theo ch thch\ thi ca Timer. +Thanh ghi TCCR0 (Timer/Counter Control Register):

y l thanh ghi iu khin hot ng ca Timer. -Cc bit 0,1,2 (CS00,CS01,CS02): y l cc bit quy nh xung cp cho hot ng ca Timer, nh bng di y.

-Cc bit 3,6 (WGM00,WGM01): y l cc bit chon ch trong Timer:

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Cng ty ng dng v pht trin sn phm cng ngh VTECH

-Bit 4,5 (COM00,COM01): y l 2 bit quy nh u ra trong cc php so snh Trong qu trnh Timer m, gi tr ca thanh ghi TCNT0 s lin tc c so snh vi OCR0. Khi 2 gi tr ny bng nhau, th s c s kin Compare Match xy ra. Khi gi tr u ra OC0 (PORTB.3) s c xut ra mc tn hiu nh bng di y:

u ra, ch non-PWM (Normal hoc CTC):

u ra, ch Fast-PWM

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Cng ty ng dng v pht trin sn phm cng ngh VTECH

u ra, ch Fhase Correct PWM Ch : chn OC0 phi OUT, tc DDRB.3=1; +Thanh ghi TIMSK (Timer/Counter Interrupt Mask Register):

y l thanh ghi iu khin ngt trong Timer. -Bit 0 (TOIE0-Timer/Counter0 Overflow Interrupt Enable): y l bit cho php ngt trn trong Timer0. Khi bit ny c ghi l 1 th cho php ngt trn b nh thi. Khi 1 ngt s xy ra mi khi b Timer trn. -Bit 1 (OCIE0-Timer/Counter0 Output Compare Match Interrupt Enable): y l bit cho php ngt so snh trong Timer0. Khi bit ny c ghi l 1 th cho php ngt so snh b nh thi. Khi 1 ngt s xy ra mi khi c s kin Compare Match.

3) Ch Normal:
+y l ch hot ng n gin nht ca Timer. Mi ln c 1 tn hiu clock th gi tr ca thanh ghi TCNT0 c tng ln 1, v tng n mc TOP l 255. Khi nhp tip theo th b Timer b trn, v 1 thanh ghi TCNT0 c t li mc 0, v li tip tc qu trnh m nh vy. Thi gian TCNT0 tng ln 1 n v ph thuc vo tn s ta chn, tn s cng ln th thi gian m cng nhanh +Thng s dng ch Normal m thi gian, v iu ch rng xung PWM. + m thi gian ta la chn 1 tn s ph hp, sao cho tnh ton ra thi gian p, VD: 125kHz. Sau la chn gi tr khi u cho thanh ghi TCNT0, gi tr ny
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Cng ty ng dng v pht trin sn phm cng ngh VTECH

cng chn sao cho khi tnh ton ra thi gian p. VD: TCNT0=6. Nh vy gi tr xut pht ca b m l 6, b m s m t 6 n 255, sau 1 nhp th trn, v 1 ngt trn c xy ra. Nhng ngay sau khi ngt trn c phc v th thanh ghi TCNT0 li tr v 0, ch khng phi l gi tr 6 m ta mun. Nh vy cu lnh cui cng ca chng trnh phc v ngt trn ta li t lnh TCNT0=6, lm gi tr xut pht cho ln m tip theo. Nh vy, thi gian Timer trn 1 ln s l (256-6)/125000=2ms. V sau 1 ln trn ta c 1 thi gian l 2ms, c th x l thi gian ny nh th no th ty ngi s dng. +C th dng ch Normal iu ch rng xung, v xut xung ra 1 chn bt k. Ci ny th cn bit c 2 ch PWM hot ng nh th no.

4) Ch CTC (Clear Timer on Compare Match):

+y l ch m gi tr trong thanh ghi TCNT0 lun c so snh vi gi tr trong thanh ghi OCR0 .Khi gi tr trong thanh ghi TCNT0 bng gi tr trong thanh ghi OCR0 th gi tr trong thanh ghi TCNT0 s b xo i, v tip tc qu trnh m mi. Gi tr trong OCR0 ng vai tr l gi tr TOP cho b m. Tuy nhin trong ch ny nu gi tr mi ghi vo thanh ghi ORC m nh hn gi tr tc thi ca b m th th 1 so snh s b l, khi b m s m n gi tr ln nht sau ri xung gi tr 0 trc khi so snh tip theo xut hin.

+Ngi ta thng dng ch CTC m thi gian, v to xung vung. + m thi gian th cng ging nh ch Normal, ch khc ch l ch Normal th gi tr TOP s l 255, cn gi tr TOP ca CTC l OCR0, gi tr ny c th thay i c, v tnh ton thi gian bng cch tnh ton gi tr thanh ghi ny, thay
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Cng ty ng dng v pht trin sn phm cng ngh VTECH

i gi tr thanh ghi ny,m khng cn phi khi to gi tr ban u TCNT0 cho b m. +To xung vung ra 1 chn: c th to xung u ra ca Timer (PORTB.3), hoc to xung 1 chn bt k. Mi ln b m trn, ta o bit chn ra. Nh vy 2 ln trn s l 1 chu k ca xung vung. Tnh ton tn s hot ng ca Timer v gi tr OCR0 to ra 1 tn s mong mun. VD: mun to ra xung c tn s 1kHz chu k s l 1ms 1 ln trn Timer mt 500us. Chn tn s Timer l 125kHzgi tr OCR0 cn chn l: 500*10-6*125000+1=63.5, c th ly gn ng thnh 63.

5) Ch Fast PWM:
+Cho php to ra sng vi tn s cao. S khc bit c bn gia Fast PWM vi cc loi PWM khc l n ch s dng 1 sn dc. B m s m t BOTTOM n MAX sau khi ng li t BOTOM. Trong ch khng o (Non-inverted) u ra OC0 (PORTB.3) s bi xo khi c php ton so snh gia TCNT0 v thanh ghi OCR0 l bng nhau, v s c set ln 1 khi gi tr trn v t v Bottom. Trong ch o (inverted), u ra s c set ln 1 khi s so snh gia thanh ghi TCNT0 v gi tr thanh ghi OCR0 bng nhau v s b xo khi gi tr trn v t v Bottom. +S di y m t chu k thi gian ca ch :

6) Ch Phase Correct PWM:

+Ch ny hot ng da trn hai sn ln xung. B m s m lin tc t gi tr BOTTOM n gi tr MAX v sau t gi tr MAX n gi tr BOTTOM. Trong ch so snh khng o (Non-inverted) chn OC0 s b xa khi gi tr TCNT0 bng gi tr OCR0 trong qu trnh m ln v s c set bng 1 khi gi tr so snh xut hin trong qu trnh m xung. Ch so snh o th cc gi tr l ngc
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li. Vi hot ng hai sn xung ny th ch ny khng to ra c tn s nh nh ch mt sn xung. Nhng do tnh cn i ca hai sn xung th n tt hn cho iu khin ng c Ch phase correct PWM hot ng c nh l 8 bt. Trong ch ny b m s tng cho n khi t gi tr MAX, khi n s i chiu m. +Biu thi gian y m t hot ng ca ton b qu trnh:

<*> Quay tr li vn trn y, l xut xung ra 1 chn bt k, ch

Normal. C 2 ch iu xung Fast PWM, v Phase Correct PWM u xut xung u ra ca Timer. Tuy nhin c th xut ra 1 chn bt k (chng hn PORTA.0), bng cch s dng ch Normal (cng da vo cch hot ng ca 2 ch kia) nh sau: +Cho php ngt trn v ngt so snh. +Chng trnh phc v ngt trn, t bit PORTA.0=1; +Chng trnh phc v so snh, t bit PORTA.0=0; +Nh vy xung xut ra PORTA.0 s ging nh ch non-inverted ca Fast PWM. +Hoc cng c th iu xung nhiu chn cng lc, tuy nhin nh vy th xung ra cc chn ny lun ging nhau.

7) Bi tp:
a. To ra 1 khong thi gian bng Timer iu khin LED n, (khng dng delay) sau khong 1s th LED dch dn t tri sang phi, dch ht 8 LED th vng li. b. Dng timer qut LED 7 thanh. C sau khong 1s th s hin th li tng 1 n v. c. Dng timer qut LED 7 thanh, kt hp c nt n. 1 nt lm tng s, 1 nt lm gim s hin th.
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Cng ty ng dng v pht trin sn phm cng ngh VTECH

d. Dng Timer qut LED 7 thanh, kt hp vi iu khin LED n. Dy LED n chy dn t tri sang phi, trong khi LED 7 thanh vn hin th e. iu khin tc ng c DC bng phng php PWM, thc hnh vi ch Fast PWM, v Phase Correct PWM. C 2 nt n: 1 nt lm tng tc , v 1 nt lm gim tc . f. iu khin tc ng c DC bng phng php PWM, thc hnh vi ch Normal. Cng dng 2 nt tng, gim tc . g. iu khin sng ca dy LED n bng phng php PWM, c 2 nt tng gim sng.

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