ThietkeIC Baigiang

B mn K thut My tnh Vin Cng ngh thng tin v Truyn thng, HBKHN
IC
Msc. Nguyn c Tin tiennd@soict.hut.edu.vn +84-91-313-7399
Nm bt c kin thc c bn v ng dng ca cc IC lp trnh m t phn cng c. Nm bt c cc nguyn l lp trnh m t phn cng v cc cu trc lp trnh c bn, minh ha bng ngn ng VHDL.. C kin thc v k nng thit k mch s Hiu bit v nguyn l hot ng phn cng ca b vi iu khin v c kh nng thit k b vi iu khin.
http://dce.hut.edu.vn 2
http://dce.hut.edu.vn
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Cng ha cc ng dng mm, to sn phm u vit v tc . Hiu r nguyn tc hot ng ca b x l, lm cn bn gip vic lp trnh phn mm, lp trnh h thng tr nn hp l, logic hn.
>> NVIDIA Tegra INTEL Core i7 ha(Tnh ton vector)
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D dng thit k cc bo mch x l s. Nhanh chng to ra cc b x l mi, mch s chuyn dng da trn m ngun m v ty bin theo nhu cu. Khuynh hng to ra cc gii php tng th hardware/soft ware (Oracle & Sun, Google& Motorola Mobility), v cc khi x l tng tc.
QuadPort H/I HDMI2SDI
Chipset chuyn dng
Card tng tc chuyn dng
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Nguyn l mch tch hp. Tng Vn On. NXB Lao ng x hi. 2007. Thit k mch s vi VHDL & Verilog. Tng Vn On. NXB Lao ng x hi. 2007. Digital VLSI Systems Design. Dr. S. Ramachandran. Springer. 2007. Digital Integrated Circuits - A Design Perspective. Jan M. Rabaey, Anantha Chandrakasan, Borivoje Nikolic. Mc Graw Hill.
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Analysis and Design of Digital IC. David A.Hodges, Horace G.jackson, Resve A.Saleh. Mc Graw Hill. The Design Warriors Guide to FPGA. Clive Max Maxfield. 2004. Circuit Design with VHDL. Volnei A. Pedroni. MIT Press. 2006. Fundamentals Of Digital Logic With VHDL Design 2nd Edition. Stephen Brown, Zvonko Vranesic. McGraw Hill. 2005.
FPGA4U, kit, usb-powered, altera, niosII & linux, http://fpga4u.epfl.ch/wiki/Main_Page SecretBlaze, b x l RISC 32bit da trn MicroBlaze, Xilinx, m m VHDL, 5 cng on, cache, ngt. http://www.lirmm.fr/~barthe/index.php/page/Secret Blaze.html Cc project v module m ngun m http://www.opencores.org/ Cc th thut trn VHDL http://vhdlguru.blogspot.com/
Phn I:
Cc linh kin thit k IC (3) Cc qui trnh sn xut IC (1)
IC, Integrated Circuit, l mt mch in t m tt c cc thnh phn u c t trn mt bn dn, khng th tch ri nhau c.
Vi iu khin Intel 8742: CPU 12MHz, RAM 128B, EPROM 2KB.

http://dce.hut.edu.vn/ 10
Thc hin mt / vi chc nng in t c th.
Chc nng c th lp trnh c. Thit k = IC chun + custom IC (glue logic)

Tt c cc thnh phn ca IC c sn xut ng thi v hng lot, ch khng phi tng IC n l. t tn linh kin. c ti u v khng gian, 1 triu transitor/mm2 Module ha qu trnh thit k mch in t.
Gim chi ph nghin cu, trin khai, nng cp... Gim gi thnh thit b, chc nng.
Tiu th t nng lng. c ti u ha v tc ... ng b v tin cy. c kim th bi nh sn xut. Tui th cao.
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Die: khun, chip sillicon. Leadframe: khung dn, cha cc chn ni ra ngoi rp rp ln board d hn Wire: ni cc chn IO trn die ra cc chn tng ng trn leadframe. V: ph kn, ng gi leadframe & die bng ceramic, plastic bo v, tn nhit.
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Lin kt khung dn
Lin kt khung dn (2)
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V - package - c nhiu hnh dng khc nhau.

Dual Inline Package Ball Grid Array Plastic Leader Chip Carrier Tham kho mt s dng v
Zigzag Inline Package
Small Outline Package
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di mi cnh chng vi mm.

Kch thc IC c o bng s cng logic/transistor (cng l n v o tng ng vi cng NAND 2 u vo).
Xilinx Spartan II XC2S200, 540k , 200k cng. Intel Core i7, 6.6m , >1 t cng.
Cu thnh bi cc transistor CMOS. Mt cng NAND c 4 transistor.

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Quy trnh x l N nm s cho transistor nh nht c chiu di N nm. V d, qui trnh 28 nm.
Kch thc c trng nh nht chiu di transistor nh nht. Cc b phn chc nng cu thnh IC c phn vng r rng. (FGPA h tr).
Intel Quad Core
Intel Core i7
Intel Pentium 5
AMD Quad Core
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S dng cc transistor lng cc, Bipolar
NPN
PNP
S dng cc transistor c cc cng kim loi, Metal Oxide Semiconductor
nMOS
Knh N
Knh P
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CMOS, Complementary MOS

Cc lp lin kt ni
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Transistor lng cc
Transistor MOSFET
base emitor
collector
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Mt tch hp: tng vi tc nhanh chng

C nh (Small Scale Integration) C trung bnh (Medium Scale Integration) C ln (Large Scale Integration) C rt ln (Very Large Scale Integration)
Hiu nng:
Tn s xung clock nhn i sau mi 3 nm
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Nhu cu
Nhu cu t thc t, t cc d on trong tng lai. V d, cn RAM gp i.

c t
ng dng
c t cc nhu cu trn phng din k thut. V d, cn tng rng bus a chi.

Thit k
Kim th
ASIC
Sn xut
Thit k: mc nh logic, thit k mc RTL, Register Transfer Level
Kim th prototype
Ti u: v tc , khng gian, nng lng, v cng ngh sn xut ns.

ng dng: Release To Menufacturer
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Ti u
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To thi silicon Ct thnh wafer Mi bng wafer

Oxi ha wafer Ph cn quang
In lit Ra b mt Ph kim loi Kim th
ng gi
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Wafer thnh phm

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To ct mi wafer
Nh my
Ct v siliicon
Bi dch tham kho
Phn II:
Field Programmable Gate Array Application Specific Integrated Circuit Tng quan (1) Kin trc (2) Qui trnh thit k FPGA, ASIC (1) Gii thiu cng c thit k v trin khai (4)
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1980s, VLSI xut hin thit k IC theo nhu cu.
phc tp tng 40% mi nm. Nhu cu thit k tng 15% mi nm
Mc tch hp ca PCB trn mi die
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Silicon, 2010
DRAM
Mt (Gb/cm2) 8.5 2.5 0.3
Tc truy xut (ns) 10 10 1.5 Xung ng h (GHz) 3
Die Area: 2.5x2.5 cm Voltage: 0.6 V Technology: 0.07 m
DRAM (logic) SRAM (cache)
Mt (Mgate/cm2) Custom 25
Nng lng (W/cm2) 54
Std. Cell
Gate Single-Mask GA FPGA
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5 2.5 0.3
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18 12.5 4.5
1.5
1 0.7 0.25
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Intel 4004 (1971) - thit k th cng
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ASIC ra i so nhu cu v cc hot ng thit k ngy cng tng.

Hi ngh cc vi mch ty bin theo khch hng ca IEEE a ra cc ti liu hng dn pht trin custom IC. Thit k = IC chun + custom IC T custom IC thut ng Application Specific IC
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ASIC, IC chuyn dng. ASIC khng ng nht vi custom IC.

IC chun: ROM, RAM, DRAM, Processor, etc. ASIC: chip cho chi bit ni, chip cho 1 v tinh, chip cho b x l di dng cell cng vi mch logic.
Qui tc ph bin: Nu mt IC xut hin trong sch tra cu, th khng phi l ASIC.
Application Specific Standard Product.
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ASIC em li c hi sn xut vi s lng ln; cc b phn c tiu chun ha nhanh chng tr thnh sn phm thng mi.
Gi thnh gim theo s lng. None Reducing Cost. Quy trnh Cost Down trong cc nh my.
Hiu qu kinh t trong thit k

Thc hin prototype nhanh vi s lng thp. Thit k theo nhu cu, chuyn su, s lng ln.
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C cng c CAD cn thit t c hiu qu trong chin lc thit k:

Thit k mc h thng: VHDL Thit k mc vt l, t VHDL ti silicon, timing closure (Monterey, Magma, Synopsys, Cadence, Avant!)
Chin lc thit k: Hierarchy - phn cp; Regularity; Modularity - m un; Locality.
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Thit k l mt qu trnh lin tc cn i cc tham s u vo, t c hiu qu mong i.

Hiu nng
chc nng, thi gian, tc , nng lng

Kch thc die chi ph sn xut
Thi gian thit k

lp lch v chi ph nghin cu Test v Stability Test lp lch, chi ph ngun lc, chi ph sn xut
tng thit k
Simulink c := a + b; if (c = 1) then cf := 1;
c t thit k Thit k h thng HDL Gi lp Thit k mc cng
Synopsys
Th vin cell
Tng hp Gi lp
Cadence
Layout Kim tra Layout Sn xut
Novelus
Kim th chip Sn phm
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Mc h thng
Mc m-un chc nng
Mc cng
Mc mch
Mc thit b
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CPLD
Cell Base IC Programable Logic Device Full Custom IC
FPGA
Cc trans to sn thnh mng, v nh thit k thc hin vic to cc lin kt ni gia chng bng cch s dng cc th vin cell v CAD.
Sn xut n l c.
~ 25M gate Phi sn xut vi s lng cc ln mi
Sn xut vi s lng 100k sn phm/ nm
Sn phm kh n gin vi khong 1K gate. Sn xut n l c
Gate Array
Thit k rt phc tp, hng trm man-year
Cc cell l Flip-Flop, gate, hoc b x l c nh ngha trc, c ti s dng li,
Da trn cng ngh ROM/PROM, cu to ch gm cc lp cng AND, OR v mt s Flip Flop.
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FPGA, PLD, CPLD c xp vo nhm cc IC lp trnh c bi ngi dng
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Pht sinh th 1: Mt khi chip ASIC cng mnh th thit k cng tinh vi, phc tp, cng tim tng nhng sai st ln. Cc phn mm h tr, gi lp cha thc s phn nh ht c hot ng thc t ca h thng. kim tra thit k, ngi k s buc phi t cc nh sn xut sn xut chip n l v kim tra trn cc ng dng, mi trng thc tn thi gian, v tin bc. cn h nn kim th phn cng nhanh chng.
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Nm 1984, Ross Freeman, Bernard Vonderschmitt, ng sng lp cng ty Xillinx. Nm 1985, Xilinx a ra dng FPGA thng mi u tin, XC2064. Nm 2006, Freeman c vinh danh ti National Inventors Hall of Fame v sng ch ny. FPGA da trn cc cng ngh nn tng nh PROM v PLD, nhng vi kin trc mi hiu qu hn. Cc thit k IC c th nghim prototype trn cc chip FPGA ngay lp tc tit kim thi gian v tin bc.
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Pht sinh th 2: Cc nh sn xut ln ch cung cp cc chip thng dng trn th trng, vi s lng ln. b qua nhu cu v cc IC chuyn dng c s lng thp, nhng tng nhu cu th rt ln. Pht sinh th 3: Ban u, cc chip lp trnh c c gi thnh kh cao v tc chm, ch s dng trong cc phng th nghim. Khi cng ngh sn xut pht trin vt bc, th cc chip lp trnh c ngy cng mnh v r ng dng i tr.
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H qu: Chn tri mi FPGA khng ch l chip prototype trong cc phng th nghim, m thc s tr thnh sn phm thng mi i chng. Th trng phn cng c cung cp mt dng sn phm c th thit k v s dng c ngay. Cc cng ty va nh, cc k s hot ng c lp, khng phi l thuc vo cc IC ca cc nh sn xut ln t do sng to.
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vs
CustomIC FPGA
Chi ph ch to ln Ti u tc , nng lng Sn xut ln
Chi ph ch to thp Ti u tnh nng Sn xut nh
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Nguyn nhn s dng chip ASIC prototyping
Easiest to use 4% Quality, Reliability 9% Complete Solution 18% Other 3%
Flexibility & Expandability 31%
Lowest Power 3%
Lowest Cost 17%
Best Performance (thoughput speed) 15%

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1/2 Hard IP Hard IP Soft IP Soft IP Others

Soft IP Hard IP Others
EDA Tools
System On Chip
EDA Tools
IP-based
EDA Integrator
... ...
EDA Tools
Platform-based
Application specific integration platform
Derivative
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Intel Core i7 die

RCC, Reconfigurable Computing. V d: RAM, ROM, PLA, PAL.

Input: a ch Output: Gi tr Gi tr = f(a ch) y = f(x)
FPGA vi tnh cht lp trnh c cao, u vit, l i din ca RCC.
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Programable Array Logic (a) Programable ROM (b)

PAL thng mi
Lp trnh
A
Yu cu: F = AB = ABC + ABC

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Programable Logic Array, c ma trn AND v OR u lp trnh c.

Tit kim dung lng ma trn. B hn ch bi s lng cc cng AND khi s u vo ca cng OR ln hn s cng AND. Tr truyn lan ln hn v mt tch hp nh.
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Generic Array Logic nng cp t PAL, gm mt ma trn AND lp trnh c (cu to t EEPROM) v ma trn OR c nh. Tuy nhin, cc cng OR nm trong cc macrocell c ni vi flip-flop v cc b dn knh c th chn tn hiu ra. Tn gi chung ca cc thit b nh PAL, PLA, GAL l Programable Logic Device
V d: Dng GAL iu khin n giao thng:
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FPGA gm 3 thnh phn chnh

Khi logic Logic Block (LB): n v x l. Khi Vo ra IO cell: giao tip vi bn ngoi. Lin kt ni Interconnection: lin kt cc n v x l.
Configurable Logic Block
Thnh phn khc

Buffer ClockDll
I/O Block
Connect Connec t
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C 3 thnh phn: khi logic, khi vo ra, lin kt ni, u lp trnh c. Lp trnh cho khi logic l hnh ng: c kt ni hay khng phn t logic A vi phn t logic B? Lp trnh cho khi vo ra l hnh ng: c kt ni hay khng u ra logic A vi chun ngoi vi B? Lp trnh cho lin kt ni l hnh ng: c kt ni hay khng khi logic A vi khi logic/vo ra B?
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Vi FPGA, lp trnh l qu trnh nh tuyn gia cc phn t logic, flipflop c ch to c nh sn, thc thi mt tc v no . Mt tuyn u c ch to sn, v nh km mt kha ng m. Tuyn c thit lp hoc hy, tng ng vi trng thi kha ng hay m. Mi trng thi ca kha ng/m ng vi mt bit nh trng thi 0/1 tng ng. Tp hp cc bt nh to thnh b nh cu hnh cho FPGA. Bng nh tuyn c lu tr trong b nh. Cng c EDA s dch HDL thnh bng nh tuyn.
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Phn tch
HDL
c := a + b; if (c == 1) then cf := 1;
nh x vo FPGA c th
BIT file
01000100 11010101 10001001
RTL
B nh cu hnh
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LB
Tt c ASIC lp trnh c, bao gm FPGA, u cha cc khi logic (cell logic) c bn ging nhau to thnh di.
C 4 loi khi logic: Da vo bng tm kim (LUT Lookup Table) Xilinx Da vo b ghp knh (Multiplexers) Actel Da vo PAL/PLA Altera Transistor Pairs
I/O Cell I/O Cell I/O Cell I/O Cell I/O Cell I/O Cell LB LB LB I/O Cell I/O Cell I/O Cell
LB
LB
LB
LB
LB
LB
I/O Cell I/O Cell I/O Cell
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A0
0 MUX 1 S
A1
SA
Mux 2x1 c th thc hin c cc hm bn
Biu din mc transistor
Cu trc cell logic ACT 1 (n module)
Cell ACT 1 ch c mt module logic. Cell ACT 2, 3 c nhiu module logic hn v c Flip Flop ring. Cu to Flip Flop
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Bng tm kim, LUT, Look-Up Table, l mt SRAM c K u vo vi 2K bit nh, thc hin c mi hm logic c K bin. Thng thng, K = 4.
RAM 16bit
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 0 0 1 1 1 1 1 0 0 1 0 0 0 0 1
WE G4 G3 G2 G1
G4 G3 G2 G1
G Func. Gen.
1
G4 G3 G2 G1
Tn hiu ra ca mt LUT c th quay tr li, thnh u vo ca chnh LUT , hoc LUT khc. Trong mt LB, thng c 3 LUT v c gi l b thc hin hm F, G v H.
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Cc LUT F v G tng ng v c lp vi nhau, thc thi cc hm 4 bin v a kt qu tnh ton ra ngoi CLB, hoc nh vo FF. Nu php ton c nhiu hn 4 bin th LUT F, G s a kt qu ti LUT H m rng thm. Flip-Flop ng vai tr: Bit nh hoc Cht d liu Hai FF c th set/reset ng b/khng ng b, tch cc theo sn m/dng
Cu trc c bn ca LB dng LUT
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S liu a vo LB c th c x l bi cc hm 4 u vo, c th c cht thanh ghi, c th c chn knh, hoc bi c 3 thao tc trn.
Khi logic lp trnh c, CLB, ca XC4000 E/X
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LE(LB) ca Altera Cyclone II
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Cn c gi l CrossPoint FPGA. S lng cng t, ~ 4000
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FPGA k tha nhiu tng thit k ca cc sn phm trc s quen thuc trong kin trc. Nhng s chc nng, mc tch hp, kh nng tnh ton ca tng n v x l trong FPGA c khc nhau, gm Coarse /k:s/ , v Fine. Coarse-grained: n v x l l mt tp hp ca cc PLD, cc khi cu hnh c CLB, thc thi c hm phc tp, c yu cu tnh ton ln. V d: Actel Mux, Xilinx LUT. Fine-grained: n v x l ch gm cc khi cu hnh c CLB nh, thc thi cc hm logic n gin. V d Transistor Pairs.
LB
LB
LB
Ma trn i xng Symmetrical Array
LB
LB
LB
LB
LB
LB
LB
LB
LB
LB
LB
LB
LB
LB
LB
LB
Cu trc dng Row-based
LB
LB
LB
LB
LB
Sea-of-Gates
PLD PLD
PLD PLD PLD PLD
PLD phn cp Hierarchical (CPLD)
PLD PLD
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Kt ni a nng
Kt ni di
Kt ni trc tip
LB
LB
SM
SM
SM
Ma trn chuyn mch
Lin kt ni di, tn hiu clk lin thng ton b di. Lin kt ni trc tip gia 2 khi LB. Lin kt ni a nng gm nhiu kt ni v cc chuyn mch.
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Kt ni di
Kt ni trc tip
Kt ni a nng
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Phn ln cc kt ni to thnh cc li kt ni theo hng v theo ct. Giao ct gia cc kt ni theo hng v theo ct s tp trung cc im cn lp trnh kt ni, to thnh ma trn chuyn mch (Switching Matrix), nm phn tn trong FPGA.
SM
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Kt ni di
LB
LB
LB
LB
LB
LB
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Spartan low end
Arrix middle end
Virtex high end
Cyclone low end
Arria middle end
Stratix high end
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QuickLogic Cypress Lucent 2% 2% Lattice 6% 6% Vantis 7% Actel 10%
Xilinx 36%
Altera 31%
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Ngn ng HDL ph hp. B cng c CAD, EDA ph hp. c lng c s lng cc CLB cn thit D kin s lng cc chn I/O cn thit. in p hot ng. Cc FPGA mi s dng mc in p thp LVTTL, LVCMOS, i hi phi chuyn i in p tng thch vi in p TTL, cung cp mt hoc nhiu vng s dng ng thi a mc in p. Tc FPGA. Kh nng ti chnh.
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Thit k h thng (System Design)
Tch hp vo ra (I/O integration) c t thit k (Design Specification) Tng hp (Synthesis)

Kim tra thit k (Design Verification)
Copyright (c) 10/2006 by NPB
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Bc 1 - Thit k h thng
Phn chc nng thc hin trn FPGA Phn chc nng ny tch hp (kt hp) vi phn cn li ca h thng nh th no
Bc 2 - Tch hp vo ra vi phn cn li ca h thng
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Bc 3 - c t thit k
M t chc nng ca thit k bng:
Cc trnh son s logic Cc ngn ng c t phn cng
Kt hp m phng
Bc 4 - Tng hp logic
Ging bc Tng hp logic trong quy trnh y Kt hp ti u:
tr nng lng hao ph
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Bc 5 - Kim tra thit k

Thc hin cc m phng, phn tch cui cng (RTL, thi gian) Xc nh cc thng s ca ASIC thit k (tn s xung nhp)
Np chip v chy th trn h thng!

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Spactan II 200
Spactan II 300 PCI 32bits RS232
Userguide.pdf
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ProASIC3 Evaluation Board
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IDE ca nh sn xut FPGA.
Atera
Xilinx
Actel
Ch c nh sn xut mi thu hiu nguyn tc hot ng ca FPGA ca h. ch c cc IDE ca nh sn xut mi routing, timing, cu hnh c cho FPGA. EDA ca bn th 3 ch x l mc logic, ri gi IDE ca nh sn xut m nhim mc vt l.
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Mt s gi chng trnh ca bn th 3:
Leonardo Spectrum, CT tng hp ca Mentor Graphics Synplify, CT tng hp ca Synplicity ModelSim , CT m phng ca Mentor Graphics. Active-HDL, CT thit k v m phng ca Aldec Active
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80
To thc th thit k bng code mu, ly t Language Assistant. To thc th thit k, bng giao din Block Diagram. Tra cu li v x l port mapping trong qu trnh thit k bng Block Diagram. Chy gi lp mc logic, Cch a gi tr vo cc tn hiu gi lp logic.
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Phn III:
Very high speed integrated circuit Hardware Description Language
Gii thiu cc ngn ng HDL (2) Cu trc m ngun VHDL (2) M hnh lp trnh VHDL Cc phng php thit k
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Hardware Description Language, ngn ng m t phn cng.

C = A and B A <= B
rising_edge(CLK)
C <= 1
5V
Mi kt cu phn cng u c th biu din di dng cc lnh phn mm, cc hm v th tc.

Full Full Adder Full Adder Adder
A := B + C
Module1(A); Module(B); A<=B;
M1 M2
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M t c kin trc x l tng tranh (c trng ring ca phn cng so vi phn mm).
C L X C <= A and B; L <= P and Q; X <= C and L; C <= A and B; B <= C;
S dng cc lnh tun t m phng x l song song ca phn cng d lm quen, d lp trnh.
+
b b b a a a
a a a
for (i=1; i<3; i++) { a[i]:= a[i] + b[i] }
thay 3 bng J?
X l tun t ca phn cng biu din th no?
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Cho php gi lp cc iu kin u vo kim th thit k phn cng -> thc hin test-driven, unitest.
001100010
Khi p dng source HDL ln 1 chip lp trnh c no th cc trnh gi lp c th tnh ton chnh xc tr truyn lan, dng sng ti mi im.
Gi : nu khng chc chn v thit k mch s t cc phn t logic, c th vit bng VHDL ri tham kho phn tch RTL.
C 2 ngn ng, c s dng rng ri v cng nhn bi IEEE:

VHDL Verilog
Cc ngn ng khc nh AHDL, JHDL, RHDL
Ngoi HDL, cn c HVL Hardware Verification Language nh OpenVera,Superlog
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L ngn ng lp trnh tru tng, i lp vi thit k mc logic, mc transistor. Ph hp vi phng php thit k top-down. Gim thi gian thit k, kim th, sn xut Gim chi ph k thut khng lp li None Recurring Enginnering. Ti s dng thit k. D debug, tnh ti nguyn.
C <= A + B
HDL
chi ph ? cell ? triger ? tc ? phn t logic

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M t phn cng bng HDL. Kim th nguyn l bng gi lp trn HDL. Kim tra chi tit bng phn tch RTL. Chn IC lp trnh c. Gn kt cc chn IO ca phn cng HDL vi IC. Bin dch phn cng HDL theo IC. Np phn cng HDL ln IC.
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Very high speed integrated circuit Hardware Description Language 1980, ngn ng HDL u tin, VHDL c ra i theo mnh lnh ca b quc phng M. VHDL dng ghi nhn cch hot ng ca cc ASIC m cc cng ty cung cp s dng trong thit b qun s ging c t c php ti liu. B QP yu cu VHDL phi k tha c php v cc nh ngha ca ngn ng Ada (m rng ca Pascal) ti s dng.
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1983, , , Intermetrics, gp kinh nghim v ngn ng bc cao v thit k top-down pht trin VHDL. 1987, b QP tuyn b: Tt c mch in t s u c m t trong VHDL. VHDL cng c cng nhn l chun IEEE 1076. Mi h thng con in t ca my bay F-22 u c t bi VHDL.
Lc ny, VHDL l mt chun cng nghip, nhng t cng c h tr.
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1996, cc cng c gi lp logic, c th hiu c php VHDL xut hin nhanh chng. Sau , cc cng c tng hp, vi u vo l VHDL, u ra l m t mch phn cng thc thi.
Chun IEEE 1164 c b sung,vi nhiu kiu logic a gi tr khc nhau (U, Z, X)
VHDL
library IEEE; IEEE.std_logic_1164.all;
(S c thng xuyn s dng trong code VHDL)
01/2009, VHDL 4.0, cn gi l VHDL 2008, l chun IEEE 1076-2008

VHDL wiki
91
1/2
C tnh nh kiu mnh. Khng phn bit ch hoa, thng. Cho php to mng vi index tng dn hoc gim dn. V d: bienx : out STD_LOGIC_VECTOR(2 downto 1) C th c/ghi file, thng dng gi lp, to s liu vo, v thm nh kt qu. Mt ngi t kinh nghim cng c th vit VHDL v gi lp thnh cng, nhng khng chc tng hp c ln mt thit b vt l, hoc vt qu kh nng thc t. Ngi dng c th dng cc VHDL IDE nh Altera Quatus, Xilinx ISE to s RTL.
2/2
C th chy gi lp xem dng sng tn hiu vi cc testbench tng ng. Khi source VHDL c dch di dng cng v kt ni, tc l c nh x ln mt thit b vt l nh CPLD, FPGA, th chnh l mt phn cng thc s. Ph hp vi thit k mc h thng, v cho php kim tra hnh vi ca h thng, gi lp m khng cn thng qua cng c tng hp ln phn cng. M t c tnh tng tranh ca phn cng concurrent system. 1 m ngun VHDL ph hp vi nhiu phn cng.
1/3
1983~1984, Phil Moorby v Prabhu Goel pht trin xong mt ngn ng HDL, v c Gateway Design Automation cng b vi tn Verilog, cng trnh m phng Verilog. 1985, ra mt bn nng cp ca ngn ng v trnh m phng Verilog XL, c th m phng thit k trn 1 triu cng, d dng debug, m phng phn cng v c tc nhn kch thch. 1987, Verilog tha mn mong i ca cc k s thit k v ngy cng ph bin. 1989, mua li Gateway.
2/3
1990, Cadence chia ngn ng Verilog v trnh m phng Verilog-XL thnh cc sn phm ring bit. cng khai Verilog thnh chun m, cnh tranh vi VHDL. Hu ht cc xng ch to ASIC u h tr Verilog v s dng Verilog-XL lm trnh m phng. 1993, 85% thit k v thm tra ASIC dng Verilog. 1995, tr thnh chun IEEE 1364, hay cn gi l Verilog-95 Cng lc, Cadence pht trin Verilog-A dnh cho mch tng t, v l mt b phn ca VerilogAMS (Analog and Mixed-Signal)
3/3
2005, l chun IEEE 1634-2005, cn gi l Verilog 2005. SystemVerilog l tp bao qut hn, gm c Verilog 2005 bn trong, vi nhiu tnh nng mi v kh nng h tr thm nh thit k, m hnh ha thit k (nh tch hp Hardware Verification Language). 2009, SystemVerilog v Verilog u c hp nht li trong IEEE 1800-2009, cn gi l SystemVerilog 2009.
96
vs
Kh nng tru tng
System Algorithm RTL Logic
Verilog
1/4
VHDL
Gate Kh nng m hnh ha
Kiu d liu
VHDL: c nhiu kiu, hm chuyn kiu, ngi dng t nh ngha kiu. Verilog: kiu n gin, gn vi phn cng, ngi dng khng t nh ngha kiu c.
vs
Ti s dng thit k
2/4
VHDL: cc procedure v function c th t trong mt package v c th c dng li trong thit k khc. Verilog: cc procedure v function phi t trong mt module, trong cc file ring r v c bao gm bng cch s dng ch dn bin dch include.
Tnh d hc
VHDL: do tnh nh kiu mnh nn c li cho ngi nhiu kinh nghim, v c nhiu cch m hnh cng mt mch s. Verilog: tng i d hc vi ngi mi bt u. Tuy nhin, cc ch nh bin dch v ngn ng PLI nh km li khng n gin.
vs
nh thi
3/4
Verilog cho kh nng lin kt thng tin gia cng c layout vi cng c tng hp/m phng tt hn VHDL,nn kh nng biu din nh thi chnh xc hn.
Th vin
VHDL: th vin l min lu tr trong mi trng my ch cc thc th (entity), kin trc (architecture), gi (package) v cu hnh (configuration) bin dch c. Verilog: khng tn ti.
Tnh d c
VHDL: ging ngn ng Ada, Pascal. Verilog: ging ngn ng C (50%C + 50%Ada)
vs
M hnh thng s ha
4/4
VHDL,Verilog u cho php. V d, mt i tng tng qut n-bit, ri c c th ha vi n = 8.
Sao chp cu trc

VHDL: pht biu generate s to ra bn sao ca cc instance ca cng mt n v thit k hoc mt phn ca thit k v kt ni mt cch thch hp. Verilog: khng c pht biu tng tng.
100
1/5
Thit k FPGA thng dng VHDL.
Thit k None FPGA thng dng Verilog hoc System Verilog
06/2011, http://blogs.mentor.com/verificationhorizons/blog/tag/vhdl/
2/5
Ngoi tr System Verilog, vic s dng cc ngn ng HDL ang gim dn.
3/5
Kim th thit k FPGA thng dng VHDL.
Thit k None FPGA thng dng System Verilog hoc Verilog
4/5
Duy nht System Verilog ang tng dn khuynh hng s dng trong thm nh thit k.
vs
5/5
S lng tm kim v VHDL nhiu hn Verilog, nhng s khc bit ang gim dn.
105
Vit trc tip m ngun bng VHDL, Verilog.
S khi, s cu trc
S trng thi
Kt hp
Thit k bng s s c sinh t ng ra ngn ng HDL, khng i hi nhiu k nng v HDL. Thit k bng s mang tnh trc quan hn, kh nng tng hp c ln phn cng cao hn.
library IEEE; use IEEE.STD_LOGIC_1164.all;
entity Mach_AND is port( a : in STD_LOGIC; b : in STD_LOGIC; o : out STD_LOGIC ); end Mach_AND;
architecture Cach_Hoat_Dong_01 of Mach_AND is begin o <= a and b; end Cach_Hoat_Dong_01;

108
109
S trng thi Thit k x l mt thut ton, t thc th con. Thit k c m t vi nhiu mnh nu.. th..
S khi Thit k khng c tnh thut ton, nhiu thc th con. Thit k mang tnh giao tip v phi php thc th.
Vit m ngun HDL Thit k nh, d kim sot hot ng; hoc thut ton, thit k c tnh tun t cao. Gi lp mi trng hot ng test. Thit k tm mc h thng (khng c kh nng tng hp), sau c thay th dn bng cc thit k kh tng hp, vi tip cn top-down. Thit k FlipFlop, Mux, ALU,
Thit k thc th iu khin, thc th trng ti, thc th iu phi, phn x.

Ph hp vi thit k CU, phn x ngt, iu phi pipeline trong CPU.
Thit k mch t hp, thc th x l ti ng vo/ra, schematic.

Ph hp vi thit k ALU, thit k thanh ghi a nng/chuyn dng, thit k tng th ton b CPU
110
111
Khai bo th vin
Phn v bn ngoi
Hot ng x l
Khai bo th vin
#include <stdio.h>
nh ngha giao din

void Mach_AND( bool a, bool b, bool & o );
Hot ng x l
void Mach_AND(..) { o = a & b; }

Nem chua (entity): Thanh Ha (archi), H Ty (archi) , Lai Vung (archi),
Kin trc hot ng th 1, do cng ty A pht trin.
library IEEE; use IEEE.STD_LOGIC_1164.all; entity Mach_AND is port( a : in STD_LOGIC; b : in STD_LOGIC; o : out STD_LOGIC ); end Mach_AND; architecture Cach_Hoat_Dong_01 of Mach_AND is begin o <= a and b; end Cach_Hoat_Dong_01;
Kin trc hot ng th 2, do cng ty B pht trin.

architecture Cach_Hoat_Dong_02 of Mach_AND is begin o <= not ( (not a) or (not b) ); end Cach_Hoat_Dong_01;
Package Gi
Generic
Architecture (Dataflow) Dng lung Lnh song song
Entity Thc th
Ports
Architecture (Structural) Dng cu trc
Architecture (Behavioral) Dng hot ng Lnh song song
Ti mua ti nhiu linh kin, trong c 6 con IC. 2 con IC c 14 chn vo ra vi 6 NOT TTL, v 4 con IC c 8 chn vo ra vi 3 NOT CMOS.
Process
nh ngha Entity nh ngha Architecture, kiu nh ngha Process
Lnh tun t
Component Th hin
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117
2.1. Cc n v c bn ca VHDL
M lnh VHDL gm 3 phn c bn sau:
Khai bo LIBRARY (th vin): gm danh sch cc th vin s dng trong thit k (VD: ieee, std, work, ) ENTITY (thc th): m t cc chn vo-ra ca mch ARCHITECTURE (kin trc): m t hot ng ca mch
LIBRARY:
Tp hp cc on lnh thng c s dng Cho php s dng li cc on m lnh v chia s vi cc ng dng khc M lnh c vit theo khun dng ca cc FUNCTION, PROCEDURE hay COMPONENT v c t bn trong cc PACKAGE.
Copyright (c) 10/2006 by NPB 118
Cc n v c bn ca VHDL (tip)
119
Ni dung chng 2
2.1. Cc n v c bn ca VHDL 2.2. Khai bo th vin (Library) 2.3. Thc th (Entity) v th hin (Component) 2.4. Kin trc (Architecture) 2.5. Cc v d
120
2.2. Khai bo th vin (Library)

C php:
LIBRARY library_name; USE library_name.package_name.package_parts;
Thng s dng cc th vin sau:

LIBRARY ieee; USE ieee.std_logic_1164.all;
LIBRARY std; USE std.standard.all; LIBRARY work; USE work.all;
121
Khai bo th vin (tip)

Cc th vin std v work ngm nh c sn, khng cn khai bo. S dng th vin ieee khi dng cc kiu d liu STD_LOGIC, STD_ULOGIC, Th vin ieee gm cc gi (package):
std_logic_1164: cc mc logic STD_LOGIC v STD_ULOGIC std_logic_arith:
Cc kiu d liu SIGNED v UNSIGNED Cc thut ton x l d liu v cc php ton so snh Cc hm chuyn i d liu
std_logic_signed: cho php x l d liu STD_LOGIC_VECTOR nh l d liu kiu SIGNED std_logic_unsigned: cho php x l d liu STD_LOGIC_VECTOR nh l d liu kiu UNSIGNED
Ni dung chng 2
123
2.3. Thc th (Entity)

Thc th l mt khai bo, c t giao din ca i tng thit k, qua , thc th ny trao i vi thc th khc trong cng mi trng.
Thc th cng, my bay, in thoi di ng
Cc thnh phn c trng ca VHDL

Ging nh ngha giao din ca class trong C++ class Mach_And { int a; int CachHoatDong(int); };
125

Mi thc th bao gm hai thnh phn
Cc thuc tnh, thng s (parameters) Cc ng kt ni vo, ra vi bn ngoi
Thc th (Entity)
C php:
ENTITY entity_name IS GENERIC ( -generic_name : generic_type := <Gi tr mc nh>; ... ); PORT ( port_name : signal_mode signal_type; port_name : signal_mode signal_type; ...); END entity_name;
Trong :
Signal mode: IN, OUT, INOUT, BUFFER Signal type: BIT, STD_LOGIC, INTEGER,
generic type: integer, time

V d 1
128
V d 2: Dng khai bo generic
entity Eight_bit_register is generic ( LENGTH : integer := 8 -- Gi tr mc nh Fmax: integer := 50 -- n v MHz ); port( CLK : in STD_LOGIC; DIN : in STD_LOGIC_VECTOR(LENGTH downto 0); DOUT : out STD_LOGIC_VECTOR(LENGTH downto 0) ); end Eight_bit_register;
V d 2: (tip)
-- Nu to component t entity vi -- rng bus mc nh, 8 bit. U1 : eight_bit_register port map( CLK => NET2342 );
-- Nu to component t entity vi -- rng bus 5 bit. U1 : eight_bit_register generic map ( LENGTH => 5 ) 130 port map( CLK => NET2342);
Th hin (Component)
Th hin l mt thc th vt l c em vo s dng, c nhng vo mt kin trc ca mt thc th khc. Ging nh khi nim th hin trong class ca C++
{
Mach_And U1, Mach_And U2; U1(a,b,tmp); U2(tmp,c,o); return o; }
V d:
U1 : Mach_And generic map ( LENGTH => 5 ) port map( CLK => NET2342);
Ni dung chng 2
132
2.4. Kin trc (Architecture)

Kin trc ca mt thc th cho bit cch hot ng ca thc th . Ging nh lp trnh cho cc method trong class ca C++.
void Mach_And.CachHoatDong(bool a, bool b, bool &o) { o = a & b; }
Mi thc th phi i km vi t nht 1 kin trc. Mi thc th c th c nhiu kin trc, ging nh hm o trong cc class ca C++. Vic kin trc no c dng, s ty vo cu hnh lc s dng Cc thnh phn c trng ca VHDL ca ngi pht trin.
2.4. Kin trc (Architecture) (tip)

C php:
ARCHITECTURE architecture_name OF entity_name IS [declarations] BEGIN (code) END architecture_name;
V d:
ARCHITECTURE myarch1 OF nand_gate IS BEGIN x <= a NAND b; END myarch1; ARCHITECTURE myarch2 OF nand_gate IS BEGIN x <= NOT ( (NOT a) OR(NOT b) ); END myarch2;
Cc kiu m t kin trc

M hnh cu trc (Structural Style): gm cc thnh phn (component) c lin kt vi nhau. M hnh lung d liu (Dataflow Style): gm cc lnh gn c thc hin ng thi. M hnh hot ng (Behavioral Style): gm cc lnh gn c thc hin tun t. Dng kt hp ca 3 kiu m hnh trn. M hnh cu trc v lung d liu gn vi hot ng thc t ca phn cng hn. M hnh hot ng d hc, d quen hn v ging phn mm.
Cc thnh phn c trng ca VHDL
135
Ni dung chng 2
2.1. Cc n v c bn ca VHDL 2.2. Khai bo th vin (Library) 2.3. Thc th (Entity) 2.4. Kin trc (Architecture) 2.5. Cc v d
136
V d 1
Trigger D xc pht sn dng c tn hiu Reset tch cc mc cao.
Nu rst = 1 th q = 0 Ngc li:
Nu clk chuyn t 0 ln 1 th q = d Cn li th h gi nguyn trng thi.
137
V d 1 (tip)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 --------------------------------------LIBRARY ieee; USE ieee.std_logic_1164.all; --------------------------------------ENTITY dff IS PORT (d, clk, rst: IN STD_LOGIC; q: OUT STD_LOGIC); END dff; --------------------------------------ARCHITECTURE behavior OF dff IS BEGIN PROCESS (rst, clk) BEGIN IF (rst='1') THEN q <= '0'; ELSIF (clk'EVENT AND clk='1') THEN q <= d; END IF; END PROCESS; END behavior; --------------------------------------Copyright (c) 10/2006 by NPB 138
V d 2
Trigger D xc pht sn dng c u vo D l u ra ca 1 cng NAND 2 u vo.
139
V d 2 (tip)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 --------------------------------------ENTITY example IS PORT ( a, b, clk: IN BIT; q:OUT BIT); END example; --------------------------------------ARCHITECTURE example OF example IS SIGNAL temp : BIT; BEGIN temp <= a NAND b; PROCESS (clk) BEGIN IF (clk'EVENT AND clk='1') THEN q<=temp; END IF; END PROCESS; END example; ---------------------------------------- C th thay dng 8 v 10 bng q <= a NAND b dng 13
141
Ni dung chng 3
3.1. Khi nim chung v tn hiu 3.2. Phn loi tn hiu 3.3. Khai bo tn hiu v phm vi s dng
3.1. Khi nim chung v tn hiu

Truyn thng l qu trnh truyn thng tin t u pht n u thu C nhiu phng thc truyn thng tin nhng u c mt thnh phn chung l
tn hiu (Signal)
V d tn hiu
Tn hiu (Signal)
Tn hiu trong cc thit b in t l tn hiu in
Tn hiu (Signal)
Tm quan trng ca tn hiu in (electrical signal) Tn hiu in ng vai tr rt quan trng trong hot ng ca cc thit b in t -> VHDL: tn hiu ng vai tr rt quan trng trong vic m t qu trnh trao i d liu gia cc mch, cc khi chc nng vi nhau
3.2. Phn loi tn hiu

Phn loi theo s ng tn hiu
n tn hiu (single signal) a tn hiu (multiple signal)
Phn loi theo chc nng ca tn hiu

Tn hiu ghp ni vi bn ngoi (External signal) Tn hiu bn trong thit b (Internal signal)
n tn hiu & a tn hiu

n tn hiu: mt ng kt ni -> bit a tn hiu (bus, vector): nhiu ng kt ni -> bit_vector
rng bus v trt t cc bit
bit_vector(7 downto 0)
bit_vector(0 to 7)
Tn hiu trong & ngoi

Tn hiu ngoi (External Signal): kt ni h thng vi th gii bn ngoi Tn hiu trong (Internal Signal): kt ni cc thnh phn bn trong h thng
Tn hiu trong & ngoi

External Signals: DATA, RESULT, EXTBUS, a, b, c Internal Signals: x, y, INTBUS
3.3. Khai bo tn hiu

V tr khai bo
ENTITY
External Signals
ARCHITECTURE
Internal Signals
Khai bo External Signals Port_name: Mode Port_Type
Khai bo Internal Signals

Signal_name: Signal_Type
Phm vi s dng
Cc tn hiu khai bo trong mt package c th s dng trong tt c cc i tng s dng package Cc tn hiu ca interface (external signals) c th s dng trong tt c cc architecture ca interface Cc tn hiu khai bo bn trong mt architecture th ch c th s dng trong architecture
V d
MUX5-1
V d
entity mux5_1 is port(u, v, w, x, y: IN std_logic_vector(2 downto 0); s: IN std_logic_vector(2 downto 0); m: OUT std_logic_vector(2 downto 0)); end mux5_1; architecture structure1 of mux5_1 is signal out1, out2, out3: std_logic_vector(2 downto 0); begin --Khai bao va noi chan cac component voi nhau mux21_1: entity work.mux2_1(behavior) port map(u, v, out1, s(0)); mux21_2: entity work.mux2_1(behavior) port map(w, x, out2, s(0)); mux21_3: entity work.mux2_1(behavior) port map(out1, out2, out3, s(1)); mux21_4: entity work.mux2_1(behavior) port map(out3, Y, m, s(2)); end structure1;
1/3
Tr truyn lan ca tn hiu l khong thi gian cn thit tn hiu i t u vo ti u ra v c trng thi n nh v hp l.
out
2ns t in out
n nh
Tr truyn lan tng khi nhit mi trng hot ng, in p ngun cp, ko ti u ra tng.
158
2/3
Dy dn di 6 inch, c tr truyn lan khong 1ns. Cng logic, ty cng ngh ch to, tr khong 10ns~1ps. Tr trn mt ng dn bng tng tr ca tng thnh phn trn ng dn . T = ti tr ca mt IC c tnh bng tr ln nht trong cc ng dn gia u vo v u ra.
15,2cm, tr ~1 ns
Tr trn ng dn AiCi+1 ln nht

159
3/3
tr ln nht ca mt IC chnh bng chu k hot ng ca IC quyt nh tn s lm vic ti a Fmax. tr thay i theo tng cch ti u ha thit k, IC vt l (FGPA, CPLD, etc). tr xc nh c c th trong qu trnh tng hp ln phn cng, khng xc nh c nu ch tng hp mc logic.
Tr trn ng dn AiCi+1 ln nht

161
Ni dung chng 4
4.1. Khai bo thc th (entity) 4.2. Khai bo cng (ports) 4.3. Khai bo thuc tnh, thng s(generic)
162
4.1. Khai bo thc th (entity)

Nn khai bo tn gi nh VHDL khng phn bit ch hoa, thng t tn ca thc th phi tun theo cc quy tc:
Khai bo trn mt dng duy nht Phi bt u bng ch ci Ch c th bao gm ch ci, ch s v du gch di Du gch di (underscores) khng c s dng u, cui hoc s dng hai du lin tip nhau Khng cho php s dng khong trng Khng c s dng cc t kha
163
Kt thc khai bo thc th

S dng cu lnh end
Cch 1: end entity; Cch 2: end entity_name; (end ExampleEnt;) Cch 3: end entity entity_name; -> Nn dng
Cch 4: end; -> Khng nn dng
164
Ch thch trong VHDL

Bt u bng hai du gch ngang - - Kt thc cui dng
165
4.2. Khai bo cng (ports)

Mi cng c khai bo s dng t kha port v cc thnh phn sau:
T kha signal (optional) Tn cng, theo sau l du hai chm : Ch hot ng ca cng (IN, OUT, INOUT) Loi cng (Kiu d liu) Khi to gi tr cho cng (optional)
166
V d khai bo cng (ports)
167
Ch hot ng ca cng (Port mode) Ch hot ng ca cng (Port mode) xc nh chiu d liu trn cng Cc ch cng thng s dng
In: ch vo, cho php c tn hiu Out: ch ra, cho php xut tn hiu Inout: ch hai chiu, c vo v ra
168
4.3. Khai bo generic

Phi khai bo trong khai bo thc th (entity) L hng s, c s dng m t mt thng s ca h thng
Kch thc ca h thng ( rng bus, ) Tn s hot ng
Khai bo generic: name:
type :=value;
Tn ca thng s, theo sau l du hai chm : Kiu d liu Gi tr mc nh (optional)
169
V d khai bo generic
170
http://dce.hut.edu.vn/
171
Ni dung chng 3
3.1. Cc kiu d liu c sn 3.2. Cc kiu d liu do ngi dng nh ngha 3.3. Cc kiu d liu dn xut 3.4. Kiu d liu mng 3.5. Kiu d liu bn ghi 3.6. Cc kiu d liu c du v khng du 3.7. Chuyn i kiu d liu 3.8. Cc v d
172
Cc kiu d liu ca VHDL

VHDL cung cp:
Mt s kiu d liu c s (kiu d liu v hng scalar) Cch to nn cc kiu d liu tng hp (composite)
Cc kiu d liu v hng:

Cc kiu s, cc i lng vt l, cc kiu lit k C rt nhiu kiu d liu c s chun c nh ngha trc. V d: enumeration, integer, physical(*), floating point(*). (*) = khng tng hp c.
Cc kiu d liu tng hp:

Kiu mng (array) Kiu bn ghi (record)
Ngoi ra VHDL cn cung cp c kiu access (pointer) v kiu file (ta khng nghin cu).
C php
type type_name is type_definition; Trong type_definition c th thuc kiu scalar, composite, access, file. V d: type Sreg0_type is (S1, S2, S3, S4); type small is range 0 to 23;
174
5.1. Cc kiu d liu c sn

Gi standard ca th vin std: kiu BIT, BOOLEAN, INTEGER v REAL Gi std_logic_1164 ca th vin ieee: kiu STD_LOGIC v STD_ULOGIC Gi std_logic_arith ca th vin ieee: nh ngha kiu SIGNED v UNSIGNED, cng thm nhiu hm chuyn i d liu, VD: conv_integer(p), conv_unsigned(p, b), conv_signed(p, b), conv_std_logic_vector(p, b) Gi std_logic_signed v std_logic_unsigned ca th vin ieee: cha cc hm cho php hat ng vi d liu STD_LOGIC_VECTOR c thc hin khi m kiu d liu l SIGNED hoc UNSIGNED
175
Kiu BIT v BIT_VECTOR

Kiu BIT v BIT_VECTOR: 2 mc logic '0' v '1' V d:
SIGNAL x: BIT; -- x c khai bo nh mt tn hiu s kiu BIT SIGNAL y: BIT_VECTOR (3 DOWNTO 0); -- y l mt vector 4 bit, vi bit tri nht l MSB SIGNAL w: BIT_VECTOR (0 TO 7); -- w l mt vector 8 bit, vi bit phi nht l MSB
Cc php gn tn hiu (dng ton t <= ) sau l hp l:

x <= -- ' y <= -- y w <= -- w '1'; ' dng cho 1 bit cn " " dng cho vector "0111"; l tn hiu 4 bit c gi tr l "0111" (MSB = '0') "01110001"; l tn hiu 8 bit c gi tr l "01110001" (MSB = '1')
176
Kiu STD_LOGIC
Kiu STD_LOGIC v STD_LOGIC_VECTOR gm 8 gi tr sau:
'X' : khng xc nh '0' : mc thp '1' : mc cao 'Z' : tr khng cao 'W' : khng xc nh yu 'L' : mc thp (yu) 'H' : mc cao (yu)
177
Kiu STD_ULOGIC
H thng logic 9 mc c gii thiu trong chun IEEE 1164 (U, X, 0, 1, Z, W, L, H, ) STD_LOGIC l subtype ca STD_ULOGIC (c thm gi tr logic 'U' Unresolved)
178
Cc kiu d liu c sn (tip)

Kiu BOOLEAN: True v False Kiu INTEGER: s nguyn 32 bit (t 2.147.483.647 n +2.147.483.647) Kiu NATURAL: s t nhin (t 0 n +2.147.483.647) Kiu REAL: s thc (t -1.0E38 n +1.0E38)
179
Cc kiu d liu c sn (tip)

Kiu d liu vt l:
Biu th mt i lng vt l no , chng hn nh l khi lng, di, thi gian hoc in p. C php khai bo mt kiu d liu vt l nh sau:
physical_type_definition ::= range_constraint units base_unit_declaration { secondary_unit_declaration } end units base_unit_declaration ::= identifier ; secondary_unit_declaration ::= identifier = physical_literal ; physical_literal ::= [ abstract_literal ] unit_name
type CAPACITY is range 0 to 1E8 units pF; -- picofarad nF = 1000 pF; -- nanofarad uF = 1000 nF; -- microfarad mF = 1000 uF; -- milifarad F = 1000 mF; -- farad end units CAPACITY; variable SomeVar : CAPACITY; SomeVar := 1mF + 23pF;
type DISTANCE is range 0 to 1E5 units um; -- micrometer mm = 1000 um; -- millimeter in_a = 25400 um; -- inch end units DISTANCE;
variable Dis1, Dis2 : DISTANCE; Dis1 := 28 mm; Dis2 := 2 in_a - 1 mm; if Dis1 < Dis2 then ...
Kiu vt l l khng th tng hp ln mch cng c.

Cc k t c biu din trong cp du nhy n, v d: 'A' '*' ''' '' Ni dung ca mt xu k t c biu din trong cp du nhy kp, v d:
"A string" "" xu rng "A string in a string: ""A string"". " xu c cha k t "
182
x0 <= '0';
-- bit, std_logic, or std_ulogic value '0'
x6 <= X"2F";
S 2F theo h c s 16.
x1 <= "00011111";
bit_vector, std_logic_vector, std_ulogic_vector, signed, or unsigned
n <= 1200;
S nguyn.
x3 <= "101111";
-- Biu din dng nh phn
m <= 1_200;
S nguyn, c php c du gch di
x4 <= B"101111";
Biu din dng nh phn
y <= 1.2E-5;
S thc
x5 <= O"57";
S 57 theo h c s 8.
q <= d after 10 ns;

physical
183
SIGNAL SIGNAL SIGNAL SIGNAL SIGNAL
a: b: c: d: e:
BIT; BIT_VECTOR(7 DOWNTO 0); STD_LOGIC; STD_LOGIC_VECTOR(7 DOWNTO 0); INTEGER RANGE 0 TO 255;
a <= c;
Khng hp l (khc kiu BIT & STD_LOGIC)
a <= b(5);
Hp l (cng kiu BIT)
b <= d;
Khng hp l (khc kiu BIT_VECTOR & STD_LOGIC_VECTOR)
b(0) <= a;
Hp l (cng kiu BIT)
e <= b;
Khng hp l (khc kiu INTEGER & BIT_VECTOR)
c <= d(5);
Hp l (cng kiu STD_LOGIC)
e <= d;
Khng hp l (khc kiu INTEGER & STD_LOGIC_VECTOR)
d(0) <= c;
Hp l (cng kiu STD_LOGIC)
184
5.2. Cc kiu d liu ngi dng n

C 2 dng d liu ngi dng c th nh ngha:
integer (kiu s nguyn) enumerated (kiu lit k)
185
Kiu s nguyn do NSD nh ngha

C php:
integer_type_definition ::= range_constraint range_constraint ::= range range range ::= simple_expression direction simple_expression direction ::= to | downto
V d:
type type type type type byte_int is range 0 to 255; signed_word_int is range 32768 to 32767; bit_index is range 31 downto 0; my_integer is range -32 to 32; student_grade is range 0 to 100;
186
Kiu lit k do NSD nh ngha

C php:
enumeration_type_definition ::= ( enumeration_literal { , enumeration_literal } ) enumeration_literal ::= identifier | character_literal
V d:
type logic_level is (unknown, low, undriven, high); type alu_function is (disable, pass, add, subtract, multiply, divide); type octal_digit is ('0', '1', '2', '3', '4', '5', '6', '7');
187
Kiu d liu lit k (tip)

Kiu character: cha c tn v k t
type character is ( NUL, SOH, STX, ETX, EOT, ENQ, ACK, BEL, BS, HT, LF, VT, FF, CR, SO, SI, DLE, DC1, DC2, DC3, DC4, NAK, SYN, ETB, CAN, EM, SUB, ESC, FSP, GSP, RSP, USP, ' ', '!', '"', '#', '$', '%', '&', ''', '(', ')', '*', '+', ',', '-', '.', '/', '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', ':', ';', '<', '=', '>', '?', '@', 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I', 'J', 'K', 'L', 'M', 'N', 'O', 'P', 'Q', 'R', 'S', 'T', 'U', 'V', 'W', 'X', 'Y', 'Z', '[', '\', ']', '^', '_', '`', 'a', 'b', 'c', 'd', 'e', 'f', 'g', 'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o', 'p', 'q', 'r', 's', 't', 'u', 'v', 'w', 'x', 'y', 'z', '{', '|', '}', '~', DEL);
5.3. Cc kiu d liu dn xut

VD 1: cc kiu Subtype c dn xut t cc kiu d liu cc phn trc
SUBTYPE natural IS INTEGER RANGE 0 TO INTEGER'HIGH; SUBTYPE my_logic IS STD_LOGIC RANGE '0' TO 'Z'; -- C STD_LOGIC = ('X','0','1','Z','W','L','H','-') -- Suy ra my_logic = ('0','1','Z') SUBTYPE small_integer IS INTEGER RANGE -32 TO 32;
189
Cc kiu d liu dn xut (tip)

VD 2: Cc php gn gia Types v Subtypes
SUBTYPE my_logic IS STD_LOGIC RANGE '0' TO '1'; SIGNAL a: BIT; SIGNAL b: STD_LOGIC; SIGNAL c: my_logic; ... b <= a; --khong hop le ( BIT vs STD_LOGIC) b <= c; --hop le (cung kieu STD_LOGIC) c <= b; --hop le (cung kieu STD_LOGIC)
190
5.4. Kiu d liu mng

Mng (Array) l tp hp cc phn t c cng kiu. Mng c th l mng 1 chiu (1D), 2 chiu (2D) hoc l mng 1 chiu ca mng 1 chiu (1Dx1D)
191
Kiu mng (tip)

nh ngha mng:
TYPE type_name IS ARRAY (specification) OF data_type;
S dng mng:
SIGNAL signal_name: type_name [:= initial_value]; SIGNAL cng c th l CONSTANT hoc VARIABLE
ng dng: m hnh cc cu trc tuyn tnh nh RAM, ROM, etc.
192
V d v khai bo mng
Mng 1Dx1D:
TYPE row IS ARRAY (7 DOWNTO 0) OF STD_LOGIC; TYPE matrix IS ARRAY (0 TO 3) OF row; SIGNAL x: matrix;
TYPE matrix IS ARRAY (0 TO 3) OF STD_LOGIC_VECTOR(7 DOWNTO 0);
Mng 2D:
TYPE matrix2D IS ARRAY (0 TO 3, 7 DOWNTO 0) OF STD_LOGIC;
Khi to mng:
... :="0001"; -- mng 1D ... :=('0','0','0','1') -- mng 1D ... :=(('0','1','1','1'), ('1','1','1','0')); -- 1Dx1D / 2D
193
V d v s dng mng
TYPE row IS ARRAY (7 TYPE array1 IS ARRAY TYPE array2 IS ARRAY TYPE array3 IS ARRAY SIGNAL x: row; SIGNAL y: array1; SIGNAL v: array2; SIGNAL w: array3; DOWNTO 0) OF STD_LOGIC; (0 TO 3) OF row; (0 TO 3) OF STD_LOGIC_VECTOR(7 DOWNTO 0); (0 TO 3, 7 DOWNTO 0) OF STD_LOGIC;
x(0) <= y(1)(2); x(1) <= v(2)(3); x(2) <= w(2,1); y(1)(1) <= x(6); y(2)(0) <= v(0)(0); y(0)(0) <= w(3,3); w(1,1) <= x(7); w(3,0) <= v(0)(3);
x <= y(0); x <= v(1); x <= w(2); x <= w(2,2 DOWNTO 0); v(0) <= w(2,2 DOWNTO 0); v(0) <= w(2); y(1) <= v(3); y(1)(7 DOWNTO 3) <= x(4 DOWNTO 0); v(1)(7 DOWNTO 3) <= v(2)(4 DOWNTO 0); w(1,5 DOWNTO 1) <= v(2)(4 DOWNTO 0); -- Lnh t m l cc php gn sai
V d v gn mng
Gi s c mt mng c khai bo l:
type a is array (1 to 4) of character;
gn gi tr cho cc phn t ca mng theo th t 'f', 'o', 'o', 'd' ta c th dng cch vit nh sau:
a := ('f', 'o', 'o', 'd'); a := (1 => 'f', 3 => 'o', 4 => 'd', 2 => 'o'); a := ('f', 4 => 'd', others => 'o');
195
V d v mng cc cng vo-ra

Khng c kiu d liu c sn nhiu chiu Mt cch m t cc chn vo-ra ca mch trong khai bo ENTITY l dng mng cc vector Khng c php dng TYPE trong khai bo ENTITY. => nh ngha kiu d liu mi trong 1 PACKAGE
196
V d mng cc cng (tip)

------- Package: --------------------------LIBRARY ieee; USE ieee.std_logic_1164.all; PACKAGE my_data_types IS CONSTANT b: INTEGER := 7; TYPE vector_array IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(b DOWNTO 0); END my_data_types; ------- Main code: ------------------------LIBRARY ieee; USE ieee.std_logic_1164.all; USE work.my_data_types.all; -- user-defined package --------------------------ENTITY mux IS PORT (inp: IN VECTOR_ARRAY (0 TO 3); ... ); END mux; ... ; -------------------------------------------Copyright (c) 10/2006 by NPB 197
5.5. Kiu d liu bn ghi

Bn ghi (Record) l kiu d liu gm cc phn t c kiu khc nhau nhng c lin kt vi nhau. C php khai bo kiu bn ghi:
record_type_definition ::= record element_declaration { element_declaration } end record element_declaration ::= identifier_list : element_subtype_definition ; identifier_list ::= identifier { , identifier ) element_subtype_definition ::= subtype_indication
ng dng: m hnh cc gi d liu.

V d v kiu bn ghi
V d 1:
TYPE birthday IS RECORD day: INTEGER RANGE 1 TO 31; month: month_name; END RECORD;
V d 2:
type instruction is record op_code : processor_op; address_mode : mode; operand1, operand2: integer range 0 to 15; end record;
truy cp vo trng f ca bn ghi r, ta s dng cch vit r.f

5.6. Kiu d liu c du v khng du

Cc kiu SIGNED v UNSIGNED c nh ngha trong gi std_logic_arith ca th vin ieee. V d:
SIGNAL x: SIGNED (7 DOWNTO 0); SIGNAL y: UNSIGNED (0 TO 3); UNSIGNED: "0101" biu din s 5, "1101" biu din s 13 SIGNED: "0101" biu din s 5, "1101" biu din s -3
Dng vi cc php ton s hc, khng dng c vi cc php ton logic.
200
V d 1
LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; ... SIGNAL a: IN SIGNED (7 DOWNTO 0); SIGNAL b: IN SIGNED (7 DOWNTO 0); SIGNAL x: OUT SIGNED (7 DOWNTO 0); ... v <= a + b; w <= a AND b;
201
V d 2
LIBRARY ieee; USE ieee.std_logic_1164.all; ... SIGNAL a: IN STD_LOGIC_VECTOR (7 DOWNTO 0); SIGNAL b: IN STD_LOGIC_VECTOR (7 DOWNTO 0); SIGNAL x: OUT STD_LOGIC_VECTOR (7 DOWNTO 0); ... v <= a + b; w <= a AND b;
202
V d 3
LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; ... SIGNAL a: IN STD_LOGIC_VECTOR (7 DOWNTO 0); SIGNAL b: IN STD_LOGIC_VECTOR (7 DOWNTO 0); SIGNAL x: OUT STD_LOGIC_VECTOR (7 DOWNTO 0); ... v <= a + b; w <= a AND b;
203
5.7. Chuyn i kiu d liu

VHDL khng cho php cc php ton trc tip ( s hc, logic, ) tc ng ln cc d liu khc kiu nhau. Gi std_logic_1164 ca th vin ieee cung cp cc hm chuyn i kiu d liu.
204
Cc hm chuyn i
conv_integer(p): chuyn i p thuc kiu INTEGER, UNSIGNED, SIGNED, hoc STD_ULOGIC thnh mt gi tr INTEGER. conv_unsigned(p, b): chuyn i p thuc kiu INTEGER, UNSIGNED, SIGNED, hoc STD_ULOGIC thnh mt gi tr UNSIGNED vi kch thc l b bit. conv_signed(p, b): chuyn i p ca kiu INTEGER, UNSIGNED, SIGNED, hoc STD_ULOGIC thnh mt gi tr SIGNED vi kch thc l b bit. conv_std_logic_vector(p, b): chuyn i p thuc kiu d liu INTEGER, UNSIGNED, SIGNED, hoc STD_LOGIC thnh mt gi tr STD_LOGIC_VECTOR vi kch thc b bit.
V d 1
TYPE long IS INTEGER RANGE -100 TO 100; TYPE short IS INTEGER RANGE -10 TO 10; SIGNAL x : short; SIGNAL y : long; ... y <= 2*x + 5; y <= long(2*x + 5);
206
V d 2
LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; ... SIGNAL a: IN UNSIGNED (7 DOWNTO 0); SIGNAL b: IN UNSIGNED (7 DOWNTO 0); SIGNAL y: OUT STD_LOGIC_VECTOR (7 DOWNTO 0); ... y <= CONV_STD_LOGIC_VECTOR ((a+b), 8); Php ton hp l: a+b c chuyn i t UNSIGNED thnh mt gi tr 8-bit STD_LOGIC_VECTOR, sau gn cho y.
207
5.8. Cc v d
V d 1: cho cc khai bo sau
TYPE byte IS ARRAY (7 DOWNTO 0) OF STD_LOGIC; TYPE mem1 IS ARRAY (0 TO 3, 7 DOWNTO 0) OF STD_LOGIC; TYPE mem2 IS ARRAY (0 TO 3) OF byte; TYPE mem3 IS ARRAY (0 TO 3) OF STD_LOGIC_VECTOR(0 TO 7); SIGNAL a: STD_LOGIC; SIGNAL b: BIT; SIGNAL x: byte; SIGNAL y: STD_LOGIC_VECTOR (7 DOWNTO 0); SIGNAL v: BIT_VECTOR (3 DOWNTO 0); SIGNAL z: STD_LOGIC_VECTOR (x'HIGH DOWNTO 0); SIGNAL w1: mem1; SIGNAL w2: mem2; SIGNAL w3: mem3;
208
V d 1 (tip)
Xt tnh hp l ca cc php gn sau:
x(2) <= a; y(0) <= x(0); z(7) <= x(5); b <= v(3); w1(0,0) <= x(3); w1(2,5) <= y(7); w2(0)(0) <= x(2); w2(2)(5) <= y(7); w1(2,5) <= w2(3)(7); b <= a; w1(0)(2) <= x(2); w2(2,0) <= a;
209
V d 1 (tip)
x <= "11111110"; x <= (OTHERS => '1'); x <= y; y <= ('1','1','1','1','1','1','0','Z'); y <= (7 =>'0', 1 =>'0', OTHERS => '1'); y(2 DOWNTO 0) <= z(6 DOWNTO 4); y(5 TO 7) <= z(6 DOWNTO 0); z <= "11111" & "000"; z <= y; z <= w3(1); z(5 DOWNTO 0) <= w3(1)(2 TO 7);
210
V d 1 (tip)
w1 <= ((OTHERS=>'Z'), "11110000" ,"11110000", (OTHERS=>'0')); w1 <= (OTHERS => '1'); w1(0, 7 DOWNTO 0) <="11111111"; w2 <= (OTHERS => 'Z'); w2(0, 7 DOWNTO 0) <= "11110000"; w2(0)(7 DOWNTO 0) <= "11110000"; w2 <= ((OTHERS=>'0'), (OTHERS=>'0'), (OTHERS=>'0'), (OTHERS=>'0')); w3(2) <= y; w3(1) <= "00000000"; w3(1) <= (OTHERS => '0'); w3 <= ("11111100", ('0','0','0','0','Z','Z','Z','Z',), (OTHERS=>'0'), (OTHERS=>'0'));
V d 2
212
V d 2 (tip)
213
214
Ni dung chng 6
6.1. Cc ton t 6.2. Cc thuc tnh 6.3. Cc thuc tnh do ngi dng nh ngha 6.4. Chng ton t 6.5. GENERIC
215
6.1. Ton t
VHDL cung cp mt s loi ton t sau:
Ton t gn Ton t logic Ton t s hc Ton t so snh Ton t dch
216
Cc ton t gn
<= dng gn gi tr cho SIGNAL := dng gn gi tr cho VARIABLE, CONSTANT, GENERIC => dng gn gi tr cho tng phn t ca kiu vector hoc dng vi t kha OTHERS
217
VD v ton t gn
SIGNAL x : STD_LOGIC; VARIABLE y : STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL w : STD_LOGIC_VECTOR(0 TO 7);
x y w w <= := <= <= '1'; "0000"; "10000000"; (0 =>'1', OTHERS =>'0');
218
Cc ton t logic
VHDL nh ngha cc ton t logic sau:
NOT, AND, OR, NAND, NOR, XOR, XNOR
D liu cho cc ton t ny phi l kiu: BIT, STD_LOGIC, STD_ULOGIC, BIT_VECTOR, STD_LOGIC_VECTOR, STD_ULOGIC_VECTOR. V d:
y <= NOT (a AND b); y <= a NAND b;
219
Cc ton t s hc
Dng cho cc kiu d liu s nh l:INTEGER, SIGNED, UNSIGNED, REAL. Bao gm:
+ Ton t cng Ton t tr * Ton t nhn / Ton t chia ** Ton t ly m MOD Php chia ly phn nguyn (Y MOD X c du ca X) REM Php chia ly phn d (Y REM X c du ca Y) ABS Php ly gi tr tuyt i
220
Ton t so snh
C cc ton t so snh sau:
= So snh bng /= So snh khc nhau < So snh nh hn > So snh ln hn <= So snh nh hn hoc bng >= So snh ln hn hoc bng
Ch tc ng ln 2 ton hng c cng kiu Kt qu l mt gi tr Boolean Cc ton hng ng vi php so snh bng v khc (= v /=) c th c kiu bt k. Vi cc kiu c cu trc, 2 gi tr c coi l bng nhau nu tt c cc thnh phn tng ng ca chng l nh nhau. Cc ton t so snh cn li phi c ton hng l kiu v hng hoc kiu mng 1 chiu ca cc kiu ri rc.
Ton t dch
C php s dng ton t dch l:
<left operand> <shift operation> <right operand>
Trong :
<left operand> : kiu l BIT_VECTOR <right operand> : kiu l INTEGER
C hai ton t dch:

Sll Rll Ton t dch tri Ton t dch phi
V d:
signal x: bit_vector(bus_width-1 downto 0); x<= x sll 2;
222
Ton t ghp ni
Ton t ghp ni (&) tc ng ln cc mng 1 chiu cho ra mt mng mi vi ni dung ca ton hng bn phi c ghp ni theo sau ni dung ca ton hng bn tri. N cng c s dng thm 1 phn t vo mng hoc hnh thnh 1 mng t 2 phn t. Ton t ny thng c s dng vi kiu xu k t.
223
Th t u tin ca cc ton t
Th t u tin gim dn t trn xung:
** * / + (sign) + = /= and or abs not mod rem (sign) & < <= nand nor
> xor
>=
224
6.2. Cc thuc tnh

Thuc tnh d liu:
dLOW Tr v gi tr nh nht ca ch s mng dHIGH Tr v ch s ln nht ca ch s mng dLEFT Tr v ch s bn tri nht ca mng dRIGHT Tr v ch s bn phi nht ca mng dLENGTH Tr v kch thc ca vector dRANGE Tr v khong ch s ca vector dREVERSE_RANGE Tr v khong ch s ca vector theo th t o ngc
225
V d
Gi s d l mt vector c khai bo nh sau:
SIGNAL d : STD_LOGIC_VECTOR(0 TO 7)
Ta s c:
d'LOW = 0, d'HIGH = 7, d'LEFT = 0, d'RIGHT = 7, d'LENGTH = 8, d'RANGE = (0 to 7), d'REVERSE_RANGE = (7 downto 0)
Cc thuc tnh ny c th dng trong cc vng lp:

FOR FOR FOR FOR i i i i IN IN IN IN RANGE (0 TO 7) LOOP ... d'RANGE LOOP ... RANGE (d'LOW TO d'HIGH) LOOP ... RANGE (0 TO d'LENGTH-1) LOOP ... v gi tr phn t ti v tr pos v v tr phn t c gi tr l val Tr v gi tr phn t lin bn tri Tr v gi tr phn t lin bn phi v gi tr ca phn t c v tr nh hn n v v gi tr ca phn t c v tr ln hn n v Tr v gi tr mt v tr c bit
Nu tn hiu c kiu lit k th:

dVAL(pos) Tr dPOS(val) Tr dLEFTOF(value) ca value dRIGHTOF(value) ca value d'PRED(value) Tr v tr ca value 1 d'SUCC(value) Tr v tr ca value 1 dVAL(row,colum)
226
Cc thuc tnh (tip)

Thuc tnh tn hiu:
Gi s s l mt SIGNAL th ta c :
sEVENT : Tr v True khi mt s kin xy ra i vi s sSTABLE: Tr v True nu khng c s kin no xy ra i vi s sACTIVE: Tr v True khi s = 1 sQUIET <time>: Tr v True khi trong khong thi gian time khng c s kin no xy ra sLAST_EVENT: Tr v thi gian tri qua k t s kin cui cng sLAST_ACTIVE: Tr v thi gian qua k t ln s = 1 cui cng sLAST_VALUE: Tr v gi tr ca s s kin trc
227
V d
4 cu lnh sau kim tra s kin xut hin sn dng ca xung clk:
IF (clk'EVENT AND clk='1')... IF (NOT clk'STABLE AND clk='1')... WAIT UNTIL (clk'EVENT AND clk='1'); IF RISING_EDGE(clk)...
228
Cc thuc tnh do NSD nh ngha

NSD c th nh ngha ra 1 thuc tnh mi theo c php:
Khai bo thuc tnh:
ATTRIBUTE attribute_name: attribute_type;
M t thuc tnh:
ATTRIBUTE attribute_name OF target_name: class IS value;
Trong :
attribute_type: kiu d liu bt k (BIT, INTEGER, STD_LOGIC_VECTOR, ...) class: TYPE, SIGNAL, FUNCTION, ... value: '0', 27, "00 11 10 01", ...
229
V d 1
ATTRIBUTE number_of_inputs: INTEGER; ATTRIBUTE number_of_inputs OF nand3: SIGNAL IS 3; ... inputs <= nand3'number_of_pins; -- kt qu = 3
230
V d 2
M ha kiu lit k:
TYPE color IS (red, green, blue, white);
Ngm nh th red = "00", green = "01", blue = "10", white = "11". thay i li ta c th dng:
ATTRIBUTE enum_encoding OF color: TYPE IS "11 00 10 01";
Thuc tnh do ngi dng nh ngha c th khai bo bt c v tr no, ngoi tr trong thn ca PACKAGE.
231
6.4. Chng ton t

NSD c th nh ngha 1 ton t mi c trng tn vi 1 ton t c nh ngha sn. VD: nh ngha php + gia 1 s INTEGER v 1 BIT.
FUNCTION "+" (a: INTEGER, b: BIT) RETURN INTEGER IS BEGIN IF (b='1') THEN RETURN a+1; ELSE RETURN a; END IF; END "+";
S dng:
SIGNAL inp1, outp: INTEGER RANGE 0 TO 15; SIGNAL inp2: BIT; (...) outp <= 3 + inp1 + inp2; (...)
232
6.5. GENERIC
GENERIC l cch to ra 1 tham s tnh dng chung cho ton b thit k. => Lm cho chng trnh mm do hn v tng tnh s dng li. GENERIC phi c khai bo trong ENTITY vi c php nh sau:
GENERIC (parameter_name : parameter_type := parameter_value);
233
V d
Tham s n sau y lun c gi tr ngm nh l 8:
ENTITY my_entity IS GENERIC (n : INTEGER := 8); PORT (...); END my_entity; ARCHITECTURE my_architecture OF my_entity IS ... END my_architecture;
C th khai bo nhiu hn 1 tham s GENERIC trong 1 ENTITY.

GENERIC (n: INTEGER := 8; vector: BIT_VECTOR := "00001111");
234
1/2
architecture FSM_ARCH of entity_name is attribute enum_encoding: string; -- Khai bo cc trng thi type Sreg_type is ( Stop, Init, Go ); -- Nu cn, ch nh r gi tr binary ca tng trng thi attribute enum_encoding of Sreg_type: type is c ounter := c ounter + 1 "00 " & -- Stop Button='1' and "01 " & -- Init c ounter < Thres hold "10" ; -- Go Res et='1' Stop /00/ StopLam p<='1' -- Bin ch trng thi hin ti signal Sreg: Sreg_type; c ounter := 0 begin process (CLK) if CLK'event and CLK = '1' then .. -- xem slide tip theo end if; end process; end architecture FSM_ARCH
Init /01/ StopLam p <='0' GoLam p<='0' c ounter := c ounter * 2 c ounter >= Thres hold
c ounter:=c ounter -1 c ounter = 0 Go /10/ GoLam p <= '1'
235
1/2
-- Qu trnh bin i trng thi case Sreg is -- Bin i t State1 thnh ?? when State1 => State Action if (condition) then Sreg <= State2; Transition Action; else if (condition) then Transition Action; else Sreg <= Default State end if -- Bin i t State2 thnh ?? when State2 => -- Bin i t trng thi cn li when others => Sreg <= Init State; // or null; end case
Khng c lnh chuyn trng thi? gi nguyn trng thi
c ounter := c ounter + 1 Button='1' and c ounter < Thres hold Res et='1' Stop /00/ c ounter := 0 StopLam p<='1'
Init /01/ StopLam p <='0' GoLam p<='0'
c ounter >= Thres hold
c ounter := c ounter * 2
c ounter:=c ounter -1 c ounter = 0 Go /10/ GoLam p <= '1'
236
Phn IV:
B dn knh / phn knh ALU RAM/Thanh ghi a nng B nh chng trnh Truy cp b nh chnh
B nh thi Thanh ghi chuyn dng B gii m lnh tun t B gii m lnh r nhnh
Process (I,S) Begin If (S='1') Then O <= I(1); Else O <=I(0); End If; End Process;
I0 I1 I2 I3 S
Phn mm: Lnh r nhnh If ~ Phn cng: Mux/Demux
238
Process (I,S) Begin If (S='1') Then O(0) <= I; Else O(1) <=I; End If; End Process;
O0 O1 O2 S O3
Phn mm: Lnh r nhnh If ~ Phn cng: Mux/Demux
239
Cc cu lnh phn mm ch c 2 dng l:

Tun t Ins 0; Ins 1; Ins 2; R nhnh If .. Then Else
Tng ng vi phn cng l:

My trng thi FSM
B ghp knh
ng thit k phn cng, phn mm. Va thit k phn cng, va thit k trnh bin dch, m phng tng ng. Code VHDL tng ng code C. Khai thc u th phn cng: song song, etc.
Software: lnh 1; lnh 2; if (S) then lnh 3 else lnh 4 end if
Hardware: mch 1 mch 2
mch 3 mch 4
Xc nh mc tiu trc Thc hin sau
Thc hin trc La chn kt qu sau

241
1/3
M t entity, biu tng CI A M t architecture
Q CO OV
architecture adder_arch of adder is signal TEMP_RESULT : std_logic_vector(7 downto 0); signal TEMP_RESULT2 : std_logic_vector(1 downto 0); begin TEMP_RESULT <= ('0' & A(6 downto 0)) + ('0' & B(6 downto 0)) + CI; TEMP_RESULT2 <= ('0' & A(7)) + ('0' & B(7)) + TEMP_RESULT(7); Q <= TEMP_RESULT2(0) & TEMP_RESULT(6 downto 0); CO <= TEMP_RESULT2(1); OV <= TEMP_RESULT2(1) xor TEMP_RESULT(7); end architecture;
2/3
A - B = - ((-A ) + B ) = - (A + 1 + B ) = - (A + B ) - 1 = A + B + 1 - 1 = A + B
Php tr bng cch dng s b 2 cn 2 ln thc hin php cng tr ln. Php tr bng cch dng s b 1 chi cn 1 php cng tr gim ~ .
CI A
0 1
B
Q CO OV
0 1
ADD/SUB
3/3
Php cng/tr 1 n v c s dng nhiu.

CI A
0 1
0 1
Q CO OV
B 1 ADD/INC
0 1
ADD/SUB
Thm mt b ghp knh chn gi tr c nh 1 cho ton hng th 2.

DO = DI1 and DI2

architecture and_arch of ander is signal tmp: std_logic_vector(7 downto 0); begin tmp <= DI1 and DI2; -- Trung gian tnh c Zero DO <= tmp; ZF <= 1' when tmp = 0 else 0'; -- Tnh c Zero end architecture;
DO = DI
architecture move_arch of mover is Begin DO <= DI; end architecture;
245
DO = DI1 shr 1
architecture shr_arch of shr is begin DO <= '0' & DI(7 downto 1) ; CF <= DI(0); end architecture;
0 MSB LSB
DO = DI1 rr 1
architecture rr_arch of rr is begin DO <= DI(6 downto 0) & D(7); CF <= DI(7); end architecture;
0 DI(7) DI(6) DI(5) DI(4) DI(3) DI(2) DI(1) DI(0)
DO(7) DO(6) DO(5) DO(4) DO(3) DO(2) DO(1) DO(0) CF
C
MSB LSB
246
1/4
ALU thng l mch t hp vi 2 thnh phn:

Cc mch thc hin php ton. Cc b ghp knh.
S nguyn l
opcode b ALU
x
+ cls << >>
opcode
0 1 2 3
00x
010 011
axb
a+b a b
10x
110 111
clear a
a << b a >> b
247
2/4
Ngoi ra, cc b ghp knh cn c s dng phi ghp trng thi c t cc php ton, theo cch tng t. Nhn xt: cho d m lnh ch yu cu thc hin 1 php ton, nhng tt c cc mch php ton u hot ng. C th tit kim nng lng bng cch ngt cc mch tnh ton v ch khi ngun cp.
Dng chnh opcode iu khin cp ngun in. iu ny v c bn khng nh hng ti tc tnh ton, v mi mach php ton u thc hin song song.
248
3/4
Opcode dng chn mch tnh ton trn ALU, chnh l opcode ca tp lnh CPU, c th vi mt cht thay i nh. Thit lp b m cho opcode (v d php + ng vi m 010) c nh hng ti hiu nng ca ALU, v s lm tng/gim hiu qu gii m opcode. Lu thit k ALU:
Mt s mch php ton c th thc hin nhiu php ton (v d b cng/tr). Khi opcode cho cc php ton ny cn sai khc bit cng t cng tt d ti thiu ha.
249
4/4
V d v 2 cch m opcode khc nhau. Cch th 2 gy kh khn cho vic t chc b cng.
Cch 1 opcode 00x 010 011 10x 110 111 ALU axb a+b a b clear a a << b a >> b 00x 010 011 10x 110 111 Cch 2 opcode ALU axb a+b clear a a b a << b a >> b
250
ALU nhm thc hin php ton PreALU nhm cung cp cc ton hng vo cho ALU Ton hng vo c th ly t tp thanh ghi, b nh chnh, etc.
Thanh ghi AX Thanh ghi BX B nh chnh
0 1 2 3
Ton hng 1
0 1 2 3
Ton hng 2
251
1/2
Thanh ghi dng lu tr thng tin bn trong CPU, c tc cao nht trong phn cp b nh. C th cha c d liu v a ch. Ch gm bit nh, khng c phn cng c th km theo.
DIN( 7:0)
DOUT(4)
DIN(4)
DOUT(5)
DIN(5)
DOUT(6)
DIN(6)
DOUT(7)
DIN(7)
DO UT ( 2:0)
U1
U2
U3
U4
D I N D OUT C LK
D I N D OUT C LK
D I N D OUT C LK
D I N D OUT C LK
C E R ESET
C E R ESET
C E R ESET
C E R ESET
DF F
DF F
DF F
DF F
CE
CLK Reset
DIN(7:0) DOUT(7:0)
DOUT(0)
DIN(0)
DOUT(1)
DIN(1)
DOUT(2)
DIN(2)
DOUT(3)
DIN(3)
U5
D I N D OUT C LK C E R ESET
U6
U7
U8
DF F
DF F
DF F
DF F
252
2/2
entity IPCore_GPR is port ( CLR : in std_logic; -- xa d liu CLK : in std_logic; -- ng h CE : in std_logic; -- cho php hot ng --! cng vo d liu, ni dung cn nh DATA : in std_logic_vector(7 downto 0); --! cng ra d liu ~ ni dung nh Q : out std_logic_vector(7 downto 0) ); end entity;
architecture GPR_arch of IPCore_GPR is begin process (CLK) begin --! ti sn dng ca ng h if rising_edge(CLK) then --! Nu c php hot ng if CE = '1' then --! xa d liu ng b if CLR = '1' then Q <= (others => '0'); else --! hoc cht d liu Q <= DATA; end if; -- CLR end if; -- CE end if; -- clk end process; end GPR_arch;
253
1/2
n v nh
0 1 2 3
a ch
D liu ra
254
2/2
architecture rom_arch of IPCore_rom is begin process(ADDRESS, OE) entity IPCore_rom is variable ADDR_TEMP: std_logic_vector(1 port ( downto 0); OE : in std_logic; -- cho php d liu begin -- ng a ch ADDR_TEMP := ADDRESS(1 downto 0); ADDRESS : in std_logic_vector(2 downto 0); if (OE = '1') then -- ng liu if (ADDRESS(2) = '0') then Q : out std_logic_vector(7 downto 0) case (ADDR_TEMP) is ); when "00" => Q <= "01100001"; end entity; when "01" => Q <= "01100010"; when "10" => Q <= "00110100"; when others => Q <= "00000000"; end case; else mi gi tr cn li trong ROM = 0 Q <= "00000000"; end if; else nu OE = 0 Q <= "ZZZZZZZZ"; -- tr khng cao end if; end process; end architecture; http://dce.hut.edu.vn/ 255
1/2
C nhiu kiu thit k khc nhau: n/a cng, chung/ring ng a ch/d liu.
D liu vo n v nh CE0
gii CE1 m a CE2 ch CE3

a ch
0 1 2 3
D liu ra
256
2/2
entity IPCore_ram is port ( WE : in std_logic; CLK : in std_logic; ADDR : in std_logic_vector(3 downto 0); DATA : in std_logic_vector(7 downto 0); Q : out std_logic_vector(7 downto 0) ); end entity; architecture ram_arch of IPCore_ram is
type IPCore_ram_mem_type is array (15 downto 0) of std_logic_vector(7 downto 0); signal IPCore_ram_mem: IPCore_ram_mem_type;
begin process (CLK) begin if rising_edge(CLK) then if (WE = '1') then IPCore_ram_mem(CONV_INTEGER(ADDR)) <= DATA; end if; end if; end process; Q <= IPCore_ram_mem(CONV_INTEGER(ADDR)); end architecture;
257
Thanh ghi lnh IR, Instruction Register, cha m lnh ang c gii m. c trng phn cng: ng d liu vo c ni trc tip vi b nh chng trnh, v d liu u ra a ti b gii m lnh.
Thanh ghi lnh
ROM
Gii m lnh
258
1/5
Thanh ghi b m chng trnh PC, Program Counter hoc Instruction Pointer, cha a ch ca lnh s c thc hin. Phn ln cc lnh trong chng trnh l tun t a ch ca lnh k tip = a ch ca lnh hin ti + lch a ch gia 2 lnh . d liu vo. Vi b x l RISC, lch ny l khng i. Thit k PC s bao gm mt b cng. Vi lnh r nhnh, PC phi ghi nh a ch mi (a ch nhy ti) bt k. d liu vo. Ngt xy ra r nhnh ti 1 chng trnh con phc v ngt a ch no d liu vo.
2/5
R nhnh do tr v t chng trnh con a ch tr v s c a vo PC t Stack d liu vo. Do c nhiu ngun d liu vo nn thit k PC phi bao gm mt b ghp knh.
a ch lnh hin ti lch a ch
a ch tr v t Stack a ch c.trnh con ngt
Thanh ghi PC
Mux
ROM
a ch
Phn x logic
a ch do lnh r nhnh Nguyn nhn r nhnh

260
3/5
B phn x nhm phn tch:

opcode ca m lnh hin ti (cha trong thanh ghi IR) mt s ng cnh hin ti nh c ngt khng, kt qu gii m lnh hin ti, etc. ra quyt nh iu khin cc thnh phn cn li.
261
4/5
STACK2
D (1 0: 0 ) C L K Q (1 0: 0 )
C EST2
CE
U2
R e set se su a xo a SP1, SP2(kh on g nh o ct c nu a ) va re se t lai bo de m
STACK1 REG11CNN
D (1 0: 0 ) C L K Q (1 0: 0 )
InterruptVectorTable
IB3 (IN SN UM: 0 )
S E L(1 :0 ) O B (IN S NU M :0 )
I B 2 (I N S N U M: 0 )
U1
I B 1 (I N S N U M: 0 ) O B (IN S NU M :0 ) I B 3 (I N S N U M: 0 ) D (1 0: 0 ) CLK I B 0 (I N S N U M: 0 )
IntSel(1:0)
ST(1 0: 0 )
C EST1
CE
IB0 (IN SN UM: 0 )
VectorTable STR(7:6) Convert INS(8:0) Reset

IN S(8: 0 ) IB0 (10 : 9 )
S E L(1 :0 )
R e se t
C (1 0: 0 ) P R E SE T CE
MUX11X04
IB0 (8: 0 ) R e se t
REG11CNN PRC(10:0)
P RL
IB0(8 dow...
BUC11CPP
Tin h ie u t ich cu c ta i cu o i ch u ki t h u nh a t cu a le n h re nh a n h d e d e n ch u ki t hu 2 ch o p h e p Bu c n a p g ia t ri mo i
CPR
PC_Logic
Re se t P C M S (1 :0 )
PWRDN RET CALL CLK ActInt PRPC

CLK
P W RDN RE T CA LL CLK A c t I nt CCE
CCE = C EST2
not PWRDN
CE S T2
C EST1
CE S T1 P re Lo ad
P RP C
pclogic
CLK
Tin hieu tich cuc khi dung hoat dong, tiet kiem nang luong
262
5/5
Lu :
Tn hiu reset gi tr trong thanh ghi PC s a a ch khi ng h thng.
263
1/2
B m thi gian, Time Counter, m s chu k xung nhp. ng dng: to xung nhp c nh vi chu k l s nguyn ln xung nhp h thng, to hm delay()
xung nhip h thng system clock C trn ca b m thi gian
Thit k:
Mt b cng m s chu k xung nhp h thng. Thanh ghi lu tr kt qu m hin ti ca b cng. Thanh ghi lu tr gi tr khi to ca b cng. Xc nh thi im trn b cng.
2/2
Thanh ghi nh thi Gi tr np
0 1
Gi tr hin thi
+1
B cng
AND / OR
C trn
Xc nh trn Ngt nh thi
Lu :
Thanh ghi nh thi l mt thnh phn ca tp thanh ghi, nhn gi tr t ALU. Ngt nh thi s c chuyn ti b gii m x l, gi chng trnh con phc v ngt tng ng.
1/2
5V qu 2.5V Regs 5V 2.5V
lnh n+1
CE
0V
t vai tr cch ly
xc lp t
0V
lnh n
Cc tn hiu ng vo ca phn t nh thay i th cng khng nh hng ti tn hiu ra ca phn t nh.
266
2/2
out
2ns t
Pipeline: thm thanh ghi ngn qu trnh qu ca lnh mi vi gi n nh ca lnh c. v tr t thanh ghi
in
R cht d liu
out cht d liu out 1.2ns t
?
0.8ns t
Rout
267
1/2
Cng on
Lnh 1 Lnh 2
Mch s trc khi c pipeline

Mch 1 ni tip mch 2, ni tip mch 5
Mch s khi tin hnh pipeline ha

Mch 1
Mch 2
Mch 3
Mch 4
Mch 5
268
2/2
B cng
B cng sau pipeline vi 3 cng on
269
1/4
Mi b x l c mt tp lnh xc nh. Tp lnh thng c hng chc n hng trm lnh. Mi lnh l mt chui s nh phn m b x l hiu c thc hin mt thao tc xc nh. Cc lnh c m t bng cc k hiu gi nh dng text chnh l cc lnh ca hp ng.
270
2/4
MIPS 150 http://inst.eecs.berkeley.edu/~cs15 0/sp11/checkpoint_1/#block-ramgeneration hoc xem offline
271
3/4
PicoBlaze
http://bleyer.org/pacoblaze/picoblaze.pdf hoc xem offline

4/4
C nhiu lnh tng ng vi nhau v ngha ca nhm cc bit nh phn.
MIPS 150 rt = temporary reg, rs = source reg, rd = destination reg, shamt = shift amount Dng lnh: <opcode><operand>n
Cc phn chia nhm bt nh vy gi l khun dng lnh.

V d: lnh c = a + b, c = a - b thng cng khun dng lnh. V d: lnh c = a + b v c = a + 1 thng khc khun dng lnh.
1/8
B gii m lnh nhm bin i cc opcode u vo thnh cc tn hiu iu khin chn ton t v chn ton hng u ra. Tn hiu iu khin chn ton t thng l chn Select ca cc b ALU Mux, cho bit php ton cn thc hin l g. Tn hiu iu khin chn ton hng l chn Chip Enable ca cc thanh ghi v b nh cho bit kt qu php ton s c lu tr vo u.
Gii m lnh
Chn ton t ca ALU CE ca Reg A CE ca Reg B CE ca b nh chnh
opcode
2/8
Opcode ca tp lnh thng bao gm:

cc sub opcode chn ton t ca ALU. v cc opcode cho cc lnh khng dng ti ALU nh r nhnh, etc.
Khun dng 1?
opcode
Gii m khun dng
Khun dng 2? Khun dng 3? ALU
Nhiu lnh trong tp lnh c th ch tng ng vi mt ton t duy nht trong ALU. V d, php rd = rs + 10 v php rd = rs + rt vi ALU l nh nhau. phi bin i opcode ca lnh mt cht, trc khi gi ti chn chn ton t ca ALU
3/8
Gii m khun dng lnh MIPS
O pcode(31:0)
O pcode(31) O pcode(30)
Load_Store
O pcode(31) O pcode(30)
I_type
O pcode(29)
O pcode(5) O pcode(4) O pcode(3) O pcode(2) O pcode(1) O pcode(28) O pcode(27) O pcode(26)
X u ly truong hop lenh JR va JA LR
Lenh JR / JA LR
Jump_B ranch
O pcode(31) O pcode(30) O pcode(29)
R_type
276
4/8
Trong mt khun dng, ngha v kch thc ca cc nhm bit l ging nhau. chung cch gii m dng chung module gii m.
Cc lnh cng khun dng th thng chung c tnh iu khin nh thay i c, r nhnh, etc.
Khun dng 1 Khun dng 2 Khun dng 3
3 bit 1 bit
2 bit
2 bit
3 bit
2 bit
3 bit
4 bit
3 bit 1 bit
277
5/8
Trong m lnh, chui bit cha thng tin v ton hng ngun s c gi ti cc b mux chn ton hng u vo cho ALU.
Thanh ghi AX Thanh ghi BX B nh chnh
opcode
112
0 1 2 3
Ton hng 1
0 1 2 3
Ton hng 2
Opcode cng c th l cha lun ton hng theo phng php a ch tc th. V d c = a + 112. Vi ton hng ngm nh th cn tin hnh gii m theo qui tc ngm nh c c t.
6/8
B gii m lnh cn thc hin cc cng vic:

iu khin cc qu trnh song song bn trong b x l. iu khin cc ngt (V ngt cng ch l mt lnh r nhnh c bit) iu khin r nhnh.
279
7/8
Lnh r nhnh cn c x l trong 2 chu k xung nhp. Cc vn pht sinh:

1. Lnh r nhnh khng s dng ti ALU. Vy ALU lm g trong lc lnh r nhnh thc hin? 2. Trong lc r nhnh, cc lnh ang tn ti d trong ng lnh pipeline s phi x tr th no? 3. ng lnh c 5 cng on. Vy khi lnh u tin sau r nhnh mi ch nm cng on u tin, cc cng on sau s lm g?
280
8/8
Nguyn tc x l r nhnh:
nh du cc chu k r nhnh c th nhn bit c CPU ang giai on no ca lnh r nhnh. Nu mt thnh phn no ca CPU khng c dng n, (v d ALU, c cng on sau) th phi chn lnh NOP vo cc thnh phn (v d NOP l lnh trung tnh).
Vi ALU: b gii m phi a tn hiu chn ton t NOP ti ALU. Vi iu khin cng on: b gii m y gi tr NOP vo cc thanh ghi iu khin cng on, bng cch reset cc thanh ghi ny. B gii m phi tnh ton s lng lnh NOP c a vo ALU v cc cng on sao cho ph hp vi s cng on b thiu trong ng khi r nhnh. Gii php: s dng thanh ghi dch.
Ph lc:
1/2
Transparent Latch: Mch cht khng ng b. Khng ng b l g?

Signal CLK 1 CLK 2
RS Latch
74HC573
283
1/2
Transparent Latch: xut hin trng thi u ra khng chu nh hng ca tn hiu vo. gn khng hon ton. Khi tng hp mch trn cc thit b ca Altera, Xilinx, u xut hin d thng c thng bo warning.
-- ! @brief Transparent Latch library ieee; use ieee.std_logic_1164.all; entity tran_latch is port (vi : in std_logic; en : std_logic; vo : out std_logic; end entity tran_latch ; architecture RTL of tran_latch is begin process(vi, en) thay bng begin CLK if en = '1' then vo <= vi; end if; -- Oh!. Khi en=0 thi sao?? end process; end architecture RTL;
284
Nn thay Transparent Latch bng FlipFlop kch hot theo sn.

Mt s lnh ch c s dng trong cc testbench, khng th c tng hp ln mt phn cng c th. Hoc cc lnh ch s dng thit k mc logic. Nu mun tng hp c, phi chuyn i thnh dng khc.
process begin CLK <= '1'; wait for 10 ns; CLK <= '0'; wait for 10 ns; end process;
285
process (a, b) khc vi process (a)

architecture processa of processa is begin process(a, b) -- c = a or b begin if (a = '1') or (b='1') then c <= '1'; else c <= '0'; end if; end process; end processa; architecture processa of processa is begin process(a) begin if (a = '1') or (b='1') then c <= '1'; else c <= '0'; end if; end process; end processa;
286
Ty theo kin trc, c th c nhng thanh ghi c nh a ch truy cp nhng:

Khng tn ti thc t v vt l. Nm bn ngoi b x l.
V d: Qui nh gi tr c bit 0 hoc 1 chnh l thanh ghi, nhm hp nht php ton a+b v a+1 (bng cch coi 1 chnh l thanh ghi c bit). V d: thanh ghi gi tr trong cache. Thanh ghi ny nm trong khi cache ri, khng cn phi to li trong tp thanh ghi na.
Phn V:
Thit k mc nh Thit k mc thnh phn Tng hp v m phng t thit k ln FPGA
B x l 8 bit, m ngun m Phin bn nng cp pT-BDC 8x c thit k dng Block Diagram trc quan.
Kin trc Harvard.

rng bus d liu, a ch: 8 bit. rng bus lnh: 13 bit.
Lnh cha 1 a ch ton hng. C ch gim tiu th nng lng Giao tip RS232, ngt H thng pipeline 4 cng on Thit k chi tit mc phn t logic c bn
290
1/2
L kin trc my tnh m trong phn bit r rng b nh d liu v b nh chng trnh.
Von Neumann
291
2/2
Ngy nay, CPU tc cao ngy ny thng kt hp hai kin trc Harvard v Von Neumann. B nh cache trn chip c phn thnh cache chng trnh v cache d liu. Kin trc Harvard c dng khi CPU truy cp vo cache. Trong trng hp khng c cache, d liu c ly t b nh chnh, m b nh chnh khng c chia thnh vng nh chng trnh v vng nh d liu. Kin trc Von Neumann dng mc truy cp b nh chnh.
Ghp ni Ngoi vi
iu khin
Thao tc vi s liu
CLK Reset ExT Int IP0 IP1 ExDB RxD ROM PP
OE RD WR Standby OP0 OP1 ExAB TxD InsAdr
Ngt
PC
text
IR ALU
UART
text
B gii m Dn knh
B nh
m/ nh thi
ROM
text RAM
RF
Entity thc th
Architecture Kin trc
B mn k thut my tnh
H thng
H thng
CLK Reset ExT Int IP0 IP1 ExDB RxD ROM PP OE RD WR Standby OP0 OP1 ExAB TxD InsAdr
B nh RAM/ROM
Vi x l
Kin trc ngoi Kin trc trong
iu khin
Thao tc vi s liu
Ngoi vi Ghp ni
PC
IR
Dn knh
Thanh ghi
Ngt
UART
B gii m
ALU
m/nh thi
B mn k thut my tnh
Tp thao tc gm 27 php thao tc, m ho bi 5 bit, iu khin ALU.
Tp lnh gm 50 lnh vi 4 nhm: lnh s hc, lnh logic, lnh chuyn d liu, lnh iu khin .
S dng 4 phng php a ch ton hng: tc th, a ch trc tip, a ch thanh ghi, a ch gin tip qua thanh ghi. Thit k tp lnh c vai tr quyt nh ti hiu qu x l.
B mn k thut my tnh
Opcode
00000 0000 0000 00000 0000 0001 00000 0000 0011 00011 1TDR RRRR 01100 0PDR RRRR 10000 VVVR RRRR 10001 VVVR RRRR 1011V VVVV VVVV 11000 VVVV VVVV
Tn lnh
NOP PWRDN RET CMP CAZP CLRB SETB JC MOVI
ALU
PASN PASN PASN CMP CAZP CLRB SETB PASN PASN
ALF
S chu k
00000 00000 00000 00111
1 1 2 1
11000
11000 11001 00000
1
1 1 1(2)
00000 01111 00000
1 1 2
11011 VVVV VVVV 1110V VVVV VVVV
XORI CALL
XOR PASN
296
Tp thanh ghi khng lp trnh c: SSR, LSR, STACK Tp thanh ghi lp trnh c: SBUF, Acc
a ch
0x00 0x01 0x02 0x03
ACC TCON PCON INDIRECT TEMPLATE IMODE TLOAD
Thanh ghi ngm nh

......... ......... ......... ......... ......... ......... ......... ......... ......... .........
IP 0,1 OP 0,1
0x04
0x05 0x06 0x07 0x08. ...... 0x0F 0x10. ...... 0x1F
PP
INDEX SBUF STATUS Vng b nh khng soi gng Vng b nh khng soi gng
Vng b nh soi gng v bank 0 0x20~0x2F 0x00~0x0F

0x30. ...... 0x3F
Vng b nh soi gng v bank 0 0xE0~0xEF 0xF0~0x0F

0xF0. ...... 0xFF
Tp lnh khng c bit phn bit a ch thanh ghi v a ch nh qui nh soi gng.
B mn k thut my tnh
Vng b nh khng soi gng
.........
Vng b nh khng soi gng
Vng 0
Vng 1
Vng 7
Tp lnh khng c bit phn bit a ch thanh ghi v a ch nh. V d: lnh yu cu thao tc vi a ch 0xEF, l a ch thanh ghi hay b nh?
Qui nh mi a ch c dng xx0x.xxxx u qui v a ch 0000.xxxx Qui tc soi gng, gii m lnh nhanh trong 1 chu k lnh, tn khng gian a ch. Qui nh duy nht a 0000.xxxx l a ch thanh ghi tit kim khng gian a ch, kh gii m, c th tn nhiu chu k ng h mi xc nh c a ch.
a ch cui cng = thng tin trn m lnh (DI) [ kt hp gi tr trong thanh ghi a ch (WO) ]
Tp lnh ch l qui nh m bit, nhng c vai tr ht sc quan trng trong kin trc v hiu nng ca b x l.
a ch gin tip qua thanh ghi iu khin r nhnh
B nh (1)
Ton hng ngun
Kt qu
Cht PC a ch lnh Lnh m/nh thi ngoi m/nh thi UART TxD RxD iu khin ngt C C ROM IR Gii m SSR LSR
Chn ton hng
ALU
M thao tc
Ngt ngoi
Thanh ghi (2)
B mn k thut my tnh
Nhn lnh: PC, IR Gii m lnh:tun t, r nhnh, ngt. Thc hin lnh: nhn ton hng, thc hin. Ct ton hng: tn hiu cho php cht t b gii m lnh.
Lnh 1 Lnh 2 Lnh 3 Lnh 4 Lnh 5 Lnh 6 Lnh 7 Lnh 11 Lnh 12 1 2 3 4 5 6 7 8
FI DI FI EI DI FI WO EI DI FI WO EI DI FI DI FI EI DI FI FI DI FI EI DI WO EI WO WO WO
10
11
12
B mn k thut my tnh
External ROM ROM(12:0)
ROM PCReg
MCL K CL K
External ROM InsAdr(10:0)

PRC(1 0 :0 )
Status_Reg
STA(2 ) :0 CESTA MCL K AL :0 U(7 ) CE CL K Re s e t Re t se Re F(2:0 ) Re :0 F(2 ) Re tI Re tI STAT : 0 US(7 )
STA(2:0 ) STATUS(7:0 )
STATUS(7 :6 )
Co tra ng tha i m oi
STATUS(3:0 ) MCL K Ce OP0
OP0Reg
D(7 ) :0 CL K CE PR
OP0Reg
D(7:0)
Q(7 CLK :0 )
CE
Q(7:0)
IRReg
D(1 :0 2 ) CL K Re s e t Q(1 :0 2 ) RST End Cy c CE MCL K
REG13CRN
INS(8:0 ) INS(8 ) :0 PWRDN PW RDN Re s e t Re t se STATUS(7:6 ) STR(7 ) :6 PRPC PRPC PRC(1 :0 0 ) CALL INS CAL L RETINS RET In tSo rc e ( :0 ) u 1 In l (1 ) tSe :0 Ac tIn t ActIn t
Sel_SpecialRegs
STATUS(7:0 ) IB7 :0 (7 ) IP_DB(7:0 ) IB6(7:0 ) IB6 :0 (7 ) STATUS(3:0 ) STATUS(3)
OP0(7:0) PR
reg_cpn OP1Reg
MCL K Ce Op 1 D(7 ) :0 CL K CE PR
Re s e t reg_cpn
Out Space
Q(7 ) :0
statusreg
INDEX(7:0 ) TL o a d ( :0 ) 7 IM(7:0 )
From ALU (7:0 ) D(7 ) :0 MCL K CL Q(7 ) K :0 CEIDX CE CETL MCL K CE CL K D(7 ) :0 Re s e t IP_DB(7:0 ) RST Q(7 ) :0
Index_Reg
A rithmeticLogicUnit
IB5 :0 (7 ) IB3 :0 (7 ) OB(7 ) :0 IB2 :0 (7 ) IB1 :0 (7 ) IB4 :0 (7 ) SEL :0 (2 ) RAM(7:0 )
SEL_FirstOpr
IB4 :0 (7 ) IB3 :0 (7 ) IB2 :0 (7 ) OB(7 ) :0 (7 ) INS2(7:0 ) IB1 :0 SEL :0 (2 ) IB0 :0 (7 )
pccntr
TLoadReg
PO STATUS(2) PI STATUS(1) ZI STATUS(0) CI DI(7 ) :0
OP1(7:0)
reg_cpn
STA(2 ) :0 OSEn a INS2(2:0 ) I
Re s e t Ce Op 0 O0 O1 CEOp 1
IODemux
S(2 ) :0
IP1Reg IP1(7:0)
MCL K D(7 ) :0 CL K Q(7 ) :0 IP1DB(7:0 )
IOmux
IB0 :0 OB(7 ) (7 ) :0
AL :0 F(4 ) ALF(4:0 ) AL :0 U(7 ) MCL K Se r(7 ) Op :0 INS2(7:5 ) INS(7 ) :5 Sel SeOp r PL D1 D2 ASe t L ExAB(7:0 ) L Do u t( :0 ) 7 RAM(7:0 ) Q1 Q2 CEACC
reg_nnn IP0Reg
D(7 ) :0 CL K Q(7 ) :0
MUX08X07
IP0(7:0)
MCL K
IB1 :0 (7 ) INS2(2:0 ) S(2 ) :0 IP0DB(7:0 )
Mux08x08 In Sp ace
reg_nnn
From ALU (7:0 ) D(7 ) :0 MCL K CL Q(7 ) K :0 CETMP CE
TemplateReg
mux08x05 SEL_SecondOpr From T m p l te ( :0 ) e a 7

IB1 :0 (7 ) IB0 :0 (7 ) From A c (7 ) c :0 OB(7 ) :0 S mux08x02 Sel SeOp r
Demux08x01 A CCReg
D(7 ) :0 CL Q(7 ) K :0 CE
PT0Reg
PTIN(:0 DOUT(7 ) 7 ) :0 MCL K CEPT0 DIN(7 ) PTOUT(:0 :0 7 ) CL K CE PTOUT(7:0 )
AB(2:0 )
alu
L n RD L n WR
reg08cnn
PTOUT(7:0 ) PWRDN
L n RERAM L n WERAM EMCL K MCL K
PTIN(7:0)
INS2(7:0 ) INS(7:0 ) INS2 :0 (7 ) INS(7 ) :0 L AB(7:0 ) L AB(2:0 ) AB(2 ) :0 ADR(7 ) :0 L AB(2 ) :0 L SEL 2 :0 ) ( SEL :0 (2 ) Se (2 ) l :0 L (2 ) SEL :0 Sel SeOp r MCL K CL K L Sel SeOp r Se Se r l Op Se Se r l Op L l Se r Se Op INDEX(7:0 ) ALF(4:0 ) IDX(7 ) :0 L ALF( :0 ) 4 AL :0 F(4 ) INS(12 :0 ) AL :0 F(4 ) L F(4 ) AL :0 INS(1 :0 2 ) c lear Re t se MCL K CL K STA(2:0 ) selsignalreg Fl a (2 ) g :0 Ac tIn t
nRD nWR
PTOUT(7:0) Standby ExAB(7:0) Dout(7:0) nOE
DeM
ActIn t
SSR
n RERAM
L n RERAM
portsreg
SEL (2:0 )
AB(2:0 )
Chon kenh 4 loai so lieu toi ALU CLK

Ra wCL K
CL K AQ(7 ) :0 L AB(7:0 ) AD(7 ) u :0 :0 t(7 ) Do From ALU (7:0 ) AL :0 RR(7 ) U(7 ) :0
EMCL K
ClockGen
CL K in K CL e K xCL MCL K EMCL K MCL K IM(7:0 ) Re tI Re s e t J um p Ena
Din(7:0) AssertInterrupt
CL K Re tI Re t se Ju En mp a ActIn t Afte t rIn Ac tIn t
Di n :0 (7 )
emctrl
From ALU (7:0 )
IModeReg M(
M(6:0 ) AL :0 IM(7 ) U(6 ) :0 ActIn t In u (1 ) tSo rce :0 Ce IM Ce IM Re t se CL K
IM(7:0 )
clockdiv
Di e u k h i e c h d o I/O n e c u a c o n g Pa l l ral e
OSEn a End Cy c CALL INS PRPC RETINS
L OSEn a
Re s e t INS _ PWRDN
L CEACC CEACC L CESTA En Cyc d CES TA L n WERAM CAL INS n ERAM L W L CETL PRPC CETL L CEPT0 RETI S N CEPT0 L CESB CESB L CEIDX CEIDX L CETMP Re t se CET MP L CEIM PW RDN CEIM L Ce TM Ce TM L Ce PM Ce PM Re tI Ju En mp a Re tI J um p Ena
L OSEn a OSEn a OSEn a L CEACC CEACC CEACC L CESTA CESTA CES TA CETL CETL L CEPT0 CEPT0 CEPT0 L CESB CESB CESB L CEIDX CEIDX CEIDX L CETMP CETMP CET MP L CEIM CEIM CEIM L CETM CETM CETM L CEPM CEPM c lear CEPM Re t se MCL K CL K L CETL
LSR
IM(7 ) In u (1 ) :0 tSo rce :0
In tSo rc e ( :0 ) u 1
FStore
Afte rIn t CE Q(2 ) :0 CL K D(2 ) :0 Re F(2:0 ) MCL K STA(2:0 )
Re s e t MCL K
From ALU (7:0 )
assint
PCONReg
MCL K Ce PM D(7 ) :0 CL K CE PR Q(7 ) :0
PM(7:0) ExT
MCL K
TimerCounter
ExTC In K CL L a D(7 ) o d :0 Re t T_ se CF FCL K TCON(5 ) :0 T_ CF From ALU (7:0 ) Re s e t CESB MCL K T_ CF TL o a d ( :0 ) 7 Re s e t Ra wCL K TCTL ( :0 ) 5
SaveFlags
reg_cpn Re s e t TCONReg
Re s e t Afte rIn t MCL K c lear Ce TM D(7 ) :0 CL Q(7 ) K :0 CE R Re s e t TCTL ( :0 ) 7
Advance Modul e
UART
CL 6 K1 x Di n :0 (7 ) Re t se Rx W S MCL K Tx Do t(7 ) u :0 IB6(7:0 ) RxIn t TxIn t T_ CF RxIn t TxIn t
intreg
RxDRe d y al TxDRe d y al ExIn t
tcmodule RxD
Reset_syn ExReset
Re s e t INS _ MCL K ExtRe t se Re t se In se Re t CL K Re s e t
TxD
latchsignalreg
B mn k thut my tnh
decoder
Cac tham ghi ngam dinh, chi doc de dieu khien ngat, cong.... INT
resetsyn
Giai_ma_IMPLICIT
INS(12:0) INS(4:0)
INS(12:0)
INS(12:0)
Phan_nhom_lenh
I MPLICI T I MMEDI ATE
I NS(4:0) Reset
IMPLICIT IMMED IATE CLK
Gii m /k khc
LPWRDN
I MPLICI T PWRDN CLK Retx ReadP WriteP SxC SxP SxZ
Gii m r nhnh
IP_PC
Ju mp Enab l e CLK ActIn t
PWRDN ENDCYC JumpEnable SkipNext PRPC CLK ActI nt
Reset PW RDN RETINS EndCyc PRPC Dieu khien re nhanh CALLINS
LRETx Read P WriteP
INS(12:5)
I NS(12:5) STANDARD STANDARD
Giai_ma_BRA_IMP
PWRDN RET SC SP SZ JumpEnable SkipNext
Phn loi lnh
subgroup
BI TWI SE
BITWISE
5 nhom lenh: + IMD,IMP, STD + BRANCH
ModP ModT RetI
end_of_ins
INS(4:0)
INS(12:0)
INS(0) INS(12:9) Fl ag (2:0) ActIn t
CALL I NS0 I NS(12:9) Flag(2:0) ActI nt
implicit_decode
Operand1_is_A cc
Giai_m a_toan_tu
BITWISE IMMED IATE STANDARD
BI TWI SE I MMEDI ATE STANDARD ALF(4:0) I NS(11:7)
INS(12:7)
Dia_chi_thanh_ghi
INS(4:0) ADR(7:0) INDEX(7:0) LADR(7:0)
M OV A <= S T A NDA RD and (not I NS(11)and not I NS(10) and not I NS (9) and not I NS(8 and not I NS (7));
specialins
MOVA
INS(11:7)
alu_function
iu khin r nhnh
Chon toan tu cho ALU ALF(4:0) Chon so lieu In ADR(7:0) Sel(2:0) nRERAM
IDX(7:0)
Chon_kieu_toan_hang1
MOVA Read P WriteP IMMED IATE Imp l icit Stan d ard ISEn a OSEn a IMMED IATE Imp l icit Sel (2:0) n ReRAM
addressdecoder
Gii m a ch
Tao d ia ch i ch o th a h g h i n Ng u on va Dich
Len h IMMED IATE l u on INS(6) co toan h an g th u h ai l a Acc IMMED IATE
Stan d ard n ZeroHig h Ad r n ZeroHig h Ad r BitWise BitWise selmux
Gii m m thao tc
Cong dieu khien ngam dinh, writeonly
Mod P Mod T
SelSeOpr
Out Space Enable

WriteP
CESTA ADR(2:0) CEACC WERAM CETL CEPT0 CEI DX CESB CETMP CEI M
CESTA CEACC WERAM CETL CEPT0 CEIDX CESB CETMP CEIM
Gii m tn hiu cht

ActInt Flag(2:0) CLK CLK Bo phan kenh tin hieu chot ket qua phep toan cho ALU
INS(5) STANDARD BITWISE IMMED IATE Read P n ZeroHig h Ad r
I NS_5 STANDARD BI TWI SE I MMEDI ATE I SEna nZerohighAdr
Gii m tn hiu /k chn t/h
LatchReg
OSEna CESTA CEACC nW ERAM CETL CEPT0 CEIDX CESB CETMP CEIM
CePM CeTM
Dieu khien phuc hoi co Z,C,P va trang thai ngat trong thanh ghi IM RetI
RetI
Ju mp Enab l e JumpEna
B mn k thut my tnh
Lnh
Lnh tun t Lnh r nhnh hoc ngt CK1 CK2
SecHalf
0 0 1
EndCyc
1 0 1
FirstCyc
0 1 0
PC
Cng 1 Cht a ch Cng 1
IR
Cht lnh Khng cht Cht lnh
ENDCYC
Skip Next PWRDN
PRPC
ActIn t Ju mp Enab le
ENDCYC
FirstCyc
D C LK
CLK ActIn t SECHALF
DFF
B mn k thut my tnh
Hm logic 0 Hm logic 1
Ton hng ngun Gii m b cng
...
Hm logic 3, 4, 5, 6, 10, 11 B cng B dn knh 22 ng 8 bit Ton hng ch
...
Hm logic 25 Hm logic 27
Xc nh C,Z,P trng thi B dn knh 2 ng 1 bit C C, Z, P
M thao tc Xc nh thao tc thay i trng thi CE, ZE, PE
C trng thi trc
B mn k thut my tnh
m/nh thi: dng ngun xung nh thi bn trong hoc ngun xung m ngoi Module UART: phc v truyn, nhn tip, tc boud thay i c, khung truyn c nh Ngt: 3 vector ngt 4 c ngt: ngt ngoi, ngt m/nh thi, ngt truyn v nhn ni tip C ngt ngoi v m/inh thi xo bng phn cng, c ni tip xo bng phn mm Chng xung t iu khin vi lnh r nhnh
B mn k thut my tnh
iu khin ngt
Cho phep ngat toan cuc
7 6 5 4 3 2 1 0
LProcessin g In t
DetectPEdge
CLK
CLK PSynLevel PEdge
U8
D
IM
JumpEna
Q Set
TxF
RxF
TF
EF
SE
TE
EE
IE
CLK Reset
PEdge2Level
CLK Reset
Co ngat
Cho phep ngat
IM(7:0)
RetI
Cho php ngt

IM(0) Ch o ph ep n g at IM(6) IM(7) IM(3) IM(5) IM(2) IM(4) IM(1) CLK SPro
CLK CLK RetI S0

D
AfterActInt
D
CLK S1
CLK
AfterInt
Co mot n g at d u oc g oi S1
ActInt
LActIn t
CLK Reset
B mn k thut my tnh
IM(7:0)
TPro
S0 Cal lIn t
EPro
X l xung t iu khin
In tSou rce(0)
Phn x ngt
Reset In tSou rce(1)
IntSource(1:0)
ExABLatch
CE
CLK
CLK
Q (7 :0 )
AQ(7:0)
AD(7:0)
D (7 :0 )
reg08cnn RDLatch
CLK Q
D1 ASet
DFF
Q1
DelR
U2 CLK WRLatch
CLK Q CLK Q
Q2
DFF
D2
DFF
CLK
FWMReg
CE CLK Q (7 :0 )
LDout(7:0)
Dout(7:0)
ALU(7:0)
D (7 :0 )
reg08cnn
S
Din(7:0)
IB 1 (7:0 ) O B (7:0 ) IB 0 (7:0 )
RR(7:0)
MUX08X02
B mn k thut my tnh
Yu cu ti nguyn
FPGA XC2S100-5PQ208 XC2S30-5PQ208 XC2S50E-7TQ144 XC2S100E-6PQ208 XC2S300E-6FG456 Cng IO 89 / 144 89 / 136 89 / 102 89 / 146 89 / 329 62% 75% 82% 61% 27% LUT 712 / 2400 612 / 864 711 / 1536 712 / 2400 764 / 6144 29% 70% 46% 29% 12% Flip Flop 320 / 2400 316 / 864 318 / 1536 318 / 2400 329 / 6144 13% 36% 20% 13% 5% Fmax 26 MHz 26 MHz 34 MHz 31 MHz 31 MHz
LUT: Look-Up Table
S dng FPGA: XC2S100-5PQ208
B mn k thut my tnh
Cu hnh FPGA hot ng theo thit k thng qua cng JTAG Kim tra qu trnh cu hnh FPGA Ghp ni chip vi b nh ngoi Thit k cc jumper tng ng vi cc chn vo ra Xy dng sn mt s thit b vo ra c bn kim tra hot ng ca phn mm nh DIP, Led Bo mch pht trin thc hin tt c cc ghp ni phn cng c bn. Ngi s dng ch cn np chng trnh vo ROM s dng chip
B mn k thut my tnh
ng thit k phn cng - phn mm: vic thit k phn cng v phn mm din ra song song
S dng phn mm kim th hot ng ca chip Cc giai on pht trin phn mm
Vit chng trnh tng bit mt. S dng chng trnh dch pT-BDC Compiler
B mn k thut my tnh
Chng trnh kim tra x l ngt ngoi
B mn k thut my tnh
B x l m ngun m
312
PicoBlaze
http://www.xilinx.com/products/intellectualproperty/picoblaze.htm 100% code VHDL.
PicoBlaze Userguide
Vi iu khin nhng 8 bit c cu trc RISC. c ti u pht trin cho cc h FPGA ca Xillinx nh Spartan 3, Virtex II v Virtex II Pro. Vi iu khin PicoBlaze c ti u v mt hiu sut v chi ph pht trin thp. M ngun m VHDL, li mm. PicoBlaze FPC c h tr bi cc cng c assembler v IDE lp trnh, gi lp, etc , v bi cc cng c ca Xilinx nh System Generator hay ISE.
314
16 thanh ghi d liu chc nng chung c rng 8 bit. Lu tr c 1K lnh trong chng trnh c th lp trnh c trong chip v t ng np khi cu hnh FPGA hay khi khi ng FPGA. ALU vi cc c CARRY v ZERO. Mt bng RAM 64 byte. 256 u vo v 256 u ra d dng c th m rng thm. Stack cho php gi lng 31 ln CALL/RETURN.
315
Predictable performance, lun lun dng 2 xung nhp h thng cho mt cu lnh, c th t ti 200 MHz hoc 100 MIPS trong Virtex II Pro FPGA. p ng ngt nhanh; worst-case 5 clock cycles. c ti u cho cu truc Spartan 3, Virtex II, v Virtex II Pro FPGA ca Xilinx ch chim 96 slices v 0.5 ti 1 block RAM. H tr m phng tp lnh assembler.
316
8 8 8
T 16 ti 32 thanh ghi 8bit

8 8
iu khin a ch cng
8 PORT_ID READ_STROBE WRITE_STROBE
8
IN_PORT
OUT_PORT
8
ALU
A CH 10
B nh chng trnh ROM/RAM 1024 words
NGT
iu khin ngt
C ZERO & CARRY /k lung ctrnh

10
B nh lu c ngt Thanh ghi PC

10
10 A CH
LNH RESET CLK
18
iu khin hot ng & Gii m lnh
D LiU HNG
Stack ca PC
317
1/3
Chc nng chuyn mch Front panel v chc nng hin th trn Set Top Box. Link layer trong IEEE 1394 Interface. B vi iu khin trong Compact Flash Programming engine. DECT Radio/Repeater.
318
2/3
iu khin lp trnh cho PCI board. iu khin truyn thng. Thc hin tin x l cho cc b x l network. B iu khin ng c. iu khin cc ngun cp lp trnh c. L mt thnh phn ca Media Access Controller Vi iu khin trong cc thit b broadcast video.
319
3/3
http://youtu.be/hbtsz3m1wgQ
http://youtu.be/3hMara9qc-E
http://youtu.be/88FPBOOwSIg
320
Mt s kit ti CSLab. Hng dn pht tn hiu VGA bng FPGA.

http://www.fpga4fun.com/PongGame.html
FPGA Based VGA driver and Arcade game.

http://static.armandas.lt/res/fpga_based_vga_driver_and_arcade_gam e.pdf
Hng dn s dng Altera Quatus Hng dn s dng Altera Quatus, Xillinx ISE, Actel Libero Hng dn s dng kit Spartan II LC VN
321
Group project for our FPGA class. We took 80 phototransistors which sent signals out to the DE2 board via 8-bit parallel-to-serial registers (165) and then sent the signals out to an 8x10 array of LEDs via 8-bit serial-toparallel shift registers (595). http://youtu.be/LCIjWp7LDl8
Guild to build. http://youtu.be/no2_M_b059g http://www.elektroda.pl/rtvforum/t opic944484.html
322
Create your own 8x8x8 LED Cube 3dimensional display. Guide to build. http://youtu.be/6mXM-oGggrM http://youtu.be/ea8aG2aQ5FY http://www.instructables.com/id/LedCube-8x8x8/?ALLSTEPS
323
B mn K thut My tnh Vin Cng ngh thng tin v Truyn thng, HBKHN
The End
Msc. Nguyn c Tin tiennd@soict.hut.edu.vn +84-91-313-7399

ThietkeIC Baigiang

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B mn K thut My tnh Vin Cng ngh thng tin v Truyn thng, HBKHN

>> NVIDIA Tegra INTEL Core i7 ha(Tnh ton vector)

QuadPort H/I HDMI2SDI

Chipset chuyn dng

Card tng tc chuyn dng

Cc linh kin thit k IC (3) Cc qui trnh sn xut IC (1)

Vi iu khin Intel 8742: CPU 12MHz, RAM 128B, EPROM 2KB.

Thc hin mt / vi chc nng in t c th.

Chc nng c th lp trnh c. Thit k = IC chun + custom IC (glue logic)

Lin kt khung dn (2)

V - package - c nhiu hnh dng khc nhau.

Zigzag Inline Package

Small Outline Package

di mi cnh chng vi mm.

Cu thnh bi cc transistor CMOS. Mt cng NAND c 4 transistor.

Intel Quad Core

AMD Quad Core

S dng cc transistor lng cc, Bipolar

S dng cc transistor c cc cng kim loi, Metal Oxide Semiconductor

CMOS, Complementary MOS

Mt tch hp: tng vi tc nhanh chng

Nhu cu t thc t, t cc d on trong tng lai. V d, cn RAM gp i.

c t cc nhu cu trn phng din k thut. V d, cn tng rng bus a chi.

Thit k: mc nh logic, thit k mc RTL, Register Transfer Level

Ti u: v tc , khng gian, nng lng, v cng ngh sn xut ns.

To thi silicon Ct thnh wafer Mi bng wafer

In lit Ra b mt Ph kim loi Kim th

Wafer thnh phm

Bi dch tham kho

1980s, VLSI xut hin thit k IC theo nhu cu.

phc tp tng 40% mi nm. Nhu cu thit k tng 15% mi nm

Mc tch hp ca PCB trn mi die

Mt (Gb/cm2) 8.5 2.5 0.3

Tc truy xut (ns) 10 10 1.5 Xung ng h (GHz) 3

Die Area: 2.5x2.5 cm Voltage: 0.6 V Technology: 0.07 m

DRAM (logic) SRAM (cache)

Nng lng (W/cm2) 54

ASIC ra i so nhu cu v cc hot ng thit k ngy cng tng.

ASIC, IC chuyn dng. ASIC khng ng nht vi custom IC.

Application Specific Standard Product.

Hiu qu kinh t trong thit k

C cng c CAD cn thit t c hiu qu trong chin lc thit k:

Chin lc thit k: Hierarchy - phn cp; Regularity; Modularity - m un; Locality.

Thit k l mt qu trnh lin tc cn i cc tham s u vo, t c hiu qu mong i.

chc nng, thi gian, tc , nng lng

Thi gian thit k

c t thit k Thit k h thng HDL Gi lp Thit k mc cng

Layout Kim tra Layout Sn xut

Kim th chip Sn phm

~ 25M gate Phi sn xut vi s lng cc ln mi

Sn xut vi s lng 100k sn phm/ nm

Sn phm kh n gin vi khong 1K gate. Sn xut n l c

Thit k rt phc tp, hng trm man-year

Cc cell l Flip-Flop, gate, hoc b x l c nh ngha trc, c ti s dng li,

Da trn cng ngh ROM/PROM, cu to ch gm cc lp cng AND, OR v mt s Flip Flop.

FPGA, PLD, CPLD c xp vo nhm cc IC lp trnh c bi ngi dng

Chi ph ch to ln Ti u tc , nng lng Sn xut ln

Chi ph ch to thp Ti u tnh nng Sn xut nh

Flexibility & Expandability 31%

Lowest Cost 17%

Best Performance (thoughput speed) 15%

1/2 Hard IP Hard IP Soft IP Soft IP Others

Application specific integration platform