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Design Summary:
The main goal of this project was to successfully simulate and implement a low noise- amplifier. There were five specifications that the Low Noise Amplifier needed to meet at a given design frequency and bandwidth. These considerations were gain, maximum noise figure, input return loss, output return loss, and unconditional stability. The following table delineates the specific requirements for this project:
The design process involved three stages: the preliminary design stage, the critical design stage, and the final design stage. In the preliminary design stage, an LNA was implemented in ADS with Infineon BFP420 NPN BJT and ideal passive components. Following this stage, the critical design stage required adding in parasitic models of passive Modelithics parts, microstrip lines, discontinuities, and VIA holes. After passing the first two stages, the LNA was realized in hardware in the final design stage and its results compared with simulation data.
Stability Analysis:
Stability was achieved in two ways. The first involved using the ADS design guide utility to find a bias point that would yield an acceptable transistor stability. As seen in Figure 1, the stability that would be achieved was 0.931, while considering a low noise figure and gain. This stability value was unsatisfactory for unconditional stability. In order to make up for the insufficiency, stability was further improved by adding a shunt resistor at the output. By choosing the right resistance, the stability circle shown in Figure 1 could be driven out of the Smith chart. The final stability value is shown in Figure 2 and Figure 3, for the preliminary and critical design stages respectively.
Figure1:InputMatchingNetworkofPreliminaryDesign
Figure2:OutputMatchingNetworkofPreliminaryDesign
Bias Network
Figure3:BiasNetworkofPreliminaryDesign
Complete Schematic
Simulated Performance
Compliance Matrix
Specification Gain (dB) Max Noise Figure (dB) Input Return Loss (dB) Output Return Loss (dB) Stability Design #1 14+/-1 1.8 >10 >10 Unconditional Results 13.053-14.217 1.798 10.402-13.905 13.385-22.423 Unconditional Pass/Fail Pass Pass Pass Pass Pass
Figure10:StabilityFactorandMeasureofCriticalDesign
Physical Layout
Input/Output Matching Network Design The input and output matching network were adjusted as needed to reach the required gain and decrease the input and output return loss. Figures 12 and 13 show the resulting input and output matching networks.
Bias Network
Complete Schematic
Simulated Performance
Compliance Matrix
Specification Gain (dB) Max Noise Figure (dB) Input Return Loss (dB) Output Return Loss (dB) Stability Design #1 14+/-1 1.8 >10 >10 Unconditional Results 13.394-14.702 1.784 13.983-18.457 13.619-14.361 Unconditional Pass/Fail Pass Pass Pass Pass Pass
Measurement Results:
S-Parameter Comparisons The red line shows simulation results. The blue line is the measurement result at 2.70V and the pink line is measurement at 3.0V.
Figure21:S21ofFinalDesign
Figure22:S11ofFinalDesign
Figure23:S22ofFinalDesign
Summary:
The design using ADS modeling did not match the measured results. The biggest issue was with stability. Above 2.70V, instability at lower frequencies manifested in the measurement. The effects of instability included a decrease in gain and increase in input and output return loss at the design DC voltage of 3.0V. Up to 2.70V, however, when stability requirements were met, the gain seemed to rise at a rate that would represent the required gain if stability had kept up. The ADS model to implementation design process could have been improved in several ways. One way was to get better VIA models. Representing the impedances across the VIA holes could have made the design better. Another way may have been to get thinner milling boards. This would have reduced the parasitic effects across the holes.