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Mc tiu:
Sau khi c xong ti liu ny, sinh vin c th: S dng KIT MSP-EXP430FG4618 thc hin cc bi lab c bn. S dng b Debug MSP-FET430UIF np chng trnh cho chip MSP430 trn KIT MSPS dng phn mm IAR lp trnh mt chng trnh n gin. Thc hin cc bi lin quan n xut/nhp, ngt, timer.
EXP430FG4618 .
1.
Kit MSP-EXP430FG4618
1.2.1. JTAG
Hai header JTAG1 v JTAG2 lp trnh v debug mi MSP430 ring bit: JTAG1 cho MSP430FG4618 v JTAG2 cho MSP430F2013. JTAG1 cho MSP430FG4618 dng kiu kt ni JTAG chun 4 dy, cn JTAG cho MSP430F2013 dng kiu giao tip JTAG Spy-Bi-Wire (2 dy). iu ny cho php cc chn cc port c s dng trong qu trnh debug.
1.2.2. Microphone:
Microphone (MIC) c kt ni vi MSP430FG4618 qua cc chn trong hnh 3. Microphone c kch hot hay khng qua chn ca MSP430FG4618.
1.2.3. Buzzer
Buzzer c kt ni vi port I/O P3.5 ca MSP430FG4618. Buzzer c th hon ton b cch ly vi jumper JP1. Lu : trong qu trnh th nghim, sau khi th nghim thnh cng, sinh vin nn tho JP1 ny trnh lm nh hng ngi xung quanh.
1.2.4. LCD
LCD trong kit ny l loi SoftBaugh SBLCDA4, n c 4 ch : tnh, 2-mux, 3-mux v 4-mux. LCD ny c h tr khi giao tip vi MSP430FG4618 qua LCD driver c sn.
1.2.6. Cc LED n
KIT MSP430FG4618 c 4 LED: LED1, LED2, v LED4 c kt ni vi chip MSP430FG4618, LED3 c kt ni vi chip MSP430F2013. LED3 v LED4 c th c ngt khi kt ni bng Jumper tit kim nng lng cho kit (LED3 dng jumper JP2, LED4 dng JP3). LED LED1 LED2 LED3 LED4
Bng 1: Kt ni LED
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1.2.8. Jumper
Header JTAG1 JTAG2 PWR1 PWR2 BATT JP1 JP2 JP3 JP4 H1(1-2, 3-4) H1(1-2, 3-4, 56,7-8)
Chc nng khi dung Jumper kt ni B FET lp trnh-debug FG4618 B FET lp trnh-debug F2013
Khi khng dng jumper kt ni FG4618 khng c s dng F2013 khng c s dng
Yu cu X X Yu cu cn gn jumper ny s dng FG4618 Yu cu cn gn jumper ny s dng F2013 Yu cu khi cn dng pin Ty chn Ty chn/ yu cu khi dng LED3 Ty chn/ yu cu khi dng LED4 Yu cu cho giao tip bn trong processor Yu cu cho giao tip bn trong processor
Cung cp ngun cho FG4618. Ngoi ra, FG4618 khng c cung cp ngun dng o dng Cung cp ngun cho F2013. Ngoi ra, F2013 khng c cung cp ngun dng o dng Cung cp ngun cho kit bng 2 pin AAA. Ngoi ra, dung o dng tng cng ca kit s dng buzzer (ni vi chn FG4618-P3.5) Cho php LED3 hot ng (LED3 ni vi chn F2013-P1.0) Cho php LED4 hot ng (LED4 ni vi chn FG4618-P5.1) Cu hnh cho I2C 1-2: SDA-UCBOSDA 3-4: SCL-UCBOSCL Cu hnh cho SPI 1-2: SDI UCB0SIMO 3-4: SDO UCB0SOMI 5-6: P1.4 P3.0 (CS) 7-8: SCLK UCB0CLK VCC_1: 3 chn pha di. Dng cho FG4618/JTAG1. VCC_2: 3 chn pha trn. Dng cho F2013/JTAG2. LCL: cung cp Vcc n FET. FET: ngun t FET (jumper BATT khng c thit lp) Pin khng cung cp ngun cho c 2 chip MSP430 Khng dng buzzer Khng dng LED3 Khng dng LED4
Suy hao mc in p ra ca audio (69%) 98% suy hao ca ng ra audio DAC12 Ty chn Khng giao tip qua I2C Khng giao tip qua SPI
Vcc
Ngun t JTAG
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Tip theo click vo Device Manager. Bc 4: Click phi trn phn thit b m cha c ci t, ri chn Properties. Tip n chn tab Driver / Update Driver v chn ng dn n file driver c download bc 1.
Start/All Programs/IAR Systems/ IAR Embeeded Workbench Kickstart for MSP430 4.21/ IAR Embeeded Workbench.
Bc 3: chn ngn ng s dng. Trong th nghim ny, chng ta chn Empty project hoc C/main hoc Asm/asm v click OK. y, la chn Empty project c s dng, sau click vo nt
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Trong mc General Options -> chn tab Target -> chn MSP430FG4618
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Tip tc, chn cc tab khc thit lp nh sau (cc la chn cn li, xem help r hn) Trong tab Output: chn Output file: Executable Trong tab Library Configuration: chn Library: CLIB Trong mc C/C++ Compiler: (nu la chn ngn ng lp trnh l ngn ng C)
Trong tab Optimizations: chn level: None ( h tr ti a qu trnh debug) Trong tab List: chn Output list file: Assembler mnemonics Trong mc Debugger: Trong tab Setup: chn Driver: FET Debugger
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Trong FET Debugger: Trong tab Setup: chn Connection: Texas Instrument USB-IF. Xong cc chn la trn trong bc 5, click OK lu li ty chn tip tc bc 6 Bc 6: Thit lp file lp trnh
(Nu bc 3 chn ngn ng C hoc Asm th c sn mt s file mc nh trn ca s lm vic, ta c th s dng lp trnh, hoc remove chng to cc file khc, hoc add thm file vo.)
File/ New/File, ca s c giao din nh hnh sau:
Vi mn hnh son tho pha bn phi ca s lm vic, ngi lp trnh c th bin son chng trnh.
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)
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File lab1.c ny cha c a vo project lab1. a file lab1.c vo project dng, ta cn: Project/Add file, mt ca s hin ra v chn lab1.c nh giao din sau:
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Sau khi lu Workspace, qu trnh bin dch s c thc hin. Nu khng c li th s hin ra thng bo nh sau (nu c li, tra cu t help)
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Trn mch np, led xanh (Power) bo hiu ngun, led (Mode) bo hiu khi mch c np. Bc 3: S dng IAR lp trnh-debug Bc 4: Thc hin cc bi th nghim.
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Ch : o Trong hm main ta thng thy dng lnh: WDTCTL = WDTPW + WDTHOLD; Stop watchdog timer n khi reset chip. Nu khng c lnh ny (v khng c ty chn khc con WDTCTL) th mch s khng hot ng. o Trong C cho MSP430, th c cc hng s c nh ngha trc ( file header), ta rt hay dng cc hng s ny: BIT0 = 0000 0001 BIT1 = 0000 0010 BIT2 = 0000 0100 BIT7 = 1000 0000 o Mt chn ca MSP430 thng c nhiu chc nng, ta mun s dng chc nng g th nh ngha cho n. V d: P1DIR = 0xFF; // ton b port1 l Output P1DIR = 0x00; //ton b port1 l Input Nh vy nu mun mt s chn ca port1 l Output v mt s chn ca port1 l Input th lm th no? Khng ging mt s VK khc, MSP430 khng cho php ta tc ng trc tip n 1 chn no ring l, ch c th tc ng ln port (8 chn). Nh vy mun tc ng ln chn ring l no th ta dng php ton OR, AND v XOR. V d: P1DIR |= BIT1; //chn P1.1 s l chn Output, cc chn khc ko b nh hng bi lnh ny P1DIR &= ~BIT1; // chn P1.1 s l chn Input (nu ta ko nh ngha th n mc nh l Input) P2DIR |= BIT0 + BIT1 + BIT3; //chn P2.0, P2.1, P2.3 s l Output Lnh trn cng c th vit li: P2DIR |= 0x0B; // BIT0 + BIT1 + BIT3 = 11d=0Bh P2DIR &= ~(BIT4+BIT5); //P2DIR &=~0x30; //chn P2.4, P2.5 l Input o Xut ra port theo tng bit ring l. Nh vic nh ngha cc chn, MSP430 cng khng cho ta tc ng trc tip n tng chn no, mun xut ra mt bit hay nhiu bit bt k ta s dng cch nh dng vi nh ngha chn. V d mun cho P1.1=1, P1.3=1, P2.1=0 P1OUT |= BIT1+BIT3 ; //P1.1=1, P1.3=1 P2OUT &=~ BIT1 ; //P2.1=0 Hoc c th o mt bit chn bt k bng ln XOR ^ P1OUT ^= BIT4 ; //chn P1.4 o trng thi o Kim tra trng thi mt chn. Ngoi ngt ra ta c th kim tra trng thi mt chn no ang mc thp (0V) hay mc cao (1.8V n 3.6V). V d kim tra chn P1.2 if( (P1IN&BIT2)==0 ) //nu chn P1.2 bng 0 //do anything else //do anything // nu vit if( P1IN&BIT2==0 ), thiu 1 ngoc l sai
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6. Cc bi th nghim Bi 1: GPIO
1. Cc thanh ghi lin quan n GPIO: 1.1. Direction Register PxDIR (P1DIR, P2DIR):
y l cc thanh ghi 8 bit iu khin chiu ca 8 chn port. P1DIR iu khin PORT1, P2DIR iu khin PORT2. Bit = 1: Chn PORT tng ng c cu hnh thnh output Bit = 0: Chn PORT tng ng c cu hnh thnh input
y l cc thanh ghi 8 bit cha gi tr c c t cc chn PORT. Bit = 1: Chn PORT tng ng mc cao Bit = 0: Chn PORT tng ng mc thp. y l thanh ghi iu khin ng ra ca cc PORT. Bit = 1: Xut mc cao ra chn PORT tng ng. Bit = 0: Xut mc thp ra chn PORT tng ng.
2. Cc lu khi vit chng trnh cho lab ny: 2.1. Watchdog Timer
2.2. Delay:
Bi v trong chng trnh cha nh ngha clock nn CPU s s dng thch anh 32.768 kHz. c thi gian delay khong 1s, vng delay s m xung t 30.000SV c th dng cu lnh di y to delay: for(int i=30000;i>0;i++);
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Bi 1.1
Yu cu: Sinh vin vit chng trnh cho LED1 v LED2 sng tt lun phin. Thi gian gia 2 ln sng tt l khong 1s.
Cu hi 1: Cc LED c kt ni vi MCU nh hnh trn. in vo ch trng tr li cc cu hi di y. + LED1 ni vo chn no ca MCU? (Cng (Port) no?) Tr li: + LED2 ni vo chn no ca MCU? (Cng (Port) no?) Tr li: + iu khin LED, cc chn port phi l input hay output? Tr li: + LED sng, phi xut gi tr g ra chn port? Tr li: Cu hi 2: Hon chnh chng trnh bng cch in vo cc ch trng: #include <msp430xG46x.h> void main (void) { volatile unsigned int i; WDTCTL = | ; P2DIR |= .; P2OUT &= .; P2OUT |= ; while(1) { i= .; do (i--); while (i !=0);
//Stop Watchdog Timer //Configure P2.1 and P2.2 as Output // Turn off LED1, LED2 // Turn on LED 1, turn off LED 2 //Infinite loop //Delay
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Bi 1.2
Yu cu: Sinh vin vit chng trnh o trng thi LED1 mi khi SW1 c nhn.
Cu hi 1: Cc SW(switch) c kt ni vi MCU nh hnh trn. in vo ch trng tr li cc cu hi di y. + SW1 ni vo chn no ca MCU? (Cng (Port) no?) Tr li: + SW2 ni vo chn no ca MCU? (Cng (Port) no?) Tr li: + c trng thi switch, cc chn port phi l input hay output? Tr li: Cu hi 2: Hon chnh chng trnh bng cch in vo cc ch trng: #include <msp430xG46x.h> void main (void) { volatile unsigned int i; WDTCTL = .; P2DIR |= ..; P1DIR &= ........; while (1) { while ((P1IN & 0x01)); P2OUT ^= .; for(.........); while (....); for(.........); } }
//Stop Watchdog Timer //Configure P2.2 as Output (LED1) //Configure P1.0 as Input (S1) //Wait for the press of the button //Toggle Port P2.2 //Delay, button debounce //Wait for the release of the button //Delay, button debounce
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1.5.1.
Mi bit trong thanh ghi ny dng cho php/khng cho php ngt trn chn PORT tng ng. Bit = 1: Cho php ngt. Bit = 0: Cm ngt.
1.5.2.
Dng chn cnh ca tn hiu ngt Bit = 1: Ngt ti cnh xung ca tn hiu. Bit = 0: Ngt ti cnh ln ca tn hiu. Thanh ghi ny cha cc c ngt. Cc c ny c t ng bt bi phn cng, phi c xa bng phn mm. Cc c ny c th c bt bng phn mm cho php ngt. Bit = 1: Mt ngt ang ch x l. Bit = 0: Khng c ngt no ang ch.
1.5.3.
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Bi 2.1
Yu cu: Sinh vin vit chng trnh o trng thi LED1 khi Switch 1 c nhn. Trong chng trnh s dng ngt trn chn port giao tip Switch.
Cu hi 1: Cc SW(switch) c kt ni vi MCU nh hnh trn. in vo ch trng tr li cc cu hi di y. + SW1 ni vo chn Port g ca CPU? Tr li: + Khi Switch c nhn, s c chuyn trng thi nh th no trn chn PORT? + cho php ngt trn chn P1.0, ta phi ghi vo bit.ca thanh ghi .? + chn cnh xung cho ngt trn chn P1.0, ta phi ghi vo bit.ca thanh ghi ? Cu hi 2: Hon chnh chng trnh bng cch in vo cc ch trng: #include <msp430xG46x.h> #pragma vector= __interrupt void Port_1 (void) { //define an interrupt service routine at 0xFFE8 volatile unsigned int i; P2OUT ^= ; //Toggle Port P2.2 for(); //Delay, button debounce while (...); //Wait for the release of the button for(.); //Delay, button debounce P1IFG &= ~0x01; //Clean P1.0 Interrupt Flag (bit 0 of P1IFG register) } void main (void) { WDTCTL = ; //Stop Watchdog Timer P2DIR |= ; //Configure P2.2 as Output (LED1) P1DIR &= ..; //Configure P1.0 as Input (S1) P1IE |= ...; //Interrupt Enable in P1.0 P1IES |= .; //P1.0 Interrupt flag high-to-low transition _BIS_SR (..); //Low Power Mode with interrupts enabled }
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