8-Bit, 40/80/100 MSPS Dual A/D Converter AD9288

FEATURES
Dual 8-bit, 40 MSPS, 80 MSPS, and 100 MSPS ADC Low power: 90 mW at 100 MSPS per channel On-chip reference and track-and-hold 475 MHz analog bandwidth each channel SNR = 47 dB @ 41 MHz 1 V p-p analog input range each channel Single 3.0 V supply operation (2.7 V to 3.6 V) Standby mode for single-channel operation Twos complement or offset binary output mode Output data alignment mode Pin-compatible 10-bit upgrade available

FUNCTIONAL BLOCK DIAGRAM

VDD

ENCA AINA AINA REFINA REFOUT REFINB AINB AINB

TIMING

OUTPUT REGISTER

AD9288
T/H ADC 8

D7AD0A SELECT 1 SELECT 2

REF

OUTPUT REGISTER

DATA FORMAT SELECT 8 D7BD0B

T/H

ADC

APPLICATIONS
Battery-powered instruments Hand-held scopemeters Low cost digital oscilloscopes I and Q communications

ENCB

TIMING

VD

GND

VDD

Figure 1.

GENERAL DESCRIPTION
The AD9288 is a dual 8-bit monolithic sampling analog-todigital converter with on-chip track-and-hold circuits. It is optimized for low cost, low power, small size, and ease of use. The product operates at a 100 MSPS conversion rate with outstanding dynamic performance over its full operating range. Each channel can be operated independently. The ADC requires only a single 3.0 V (2.7 V to 3.6 V) power supply and an Encode clock for full-performance operation. No external reference or driver components are required for many applications. The digital outputs are TTL/CMOS-compatible, and a separate output power supply pin supports interfacing with 3.3 V or 2.5 V logic. The Encode input is TTL/CMOS-compatible, and the 8-bit digital outputs can be operated from 3.0 V (2.5 V to 3.6 V) supplies. User-selectable options offer a combination of standby modes, digital data formats, and digital data timing schemes. In standby mode, the digital outputs are driven to a high impedance state. Fabricated on an advanced CMOS process, the AD9288 is available in a 48-lead surface-mount plastic package (7 mm 7 mm, 1.4 mm LQFP) specified over the industrial temperature range (40C to +85C). The AD9288 is pin-compatible with the 10-bit AD9218, facilitating future system migrations.

Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 2004 Analog Devices, Inc. All rights reserved.

00585-001

AD9288

TABLE OF CONTENTS
Specifications..................................................................................... 3 Explanation of Test Levels ........................................................... 4 Timing Diagrams.......................................................................... 5 Absolute Maximum Ratings............................................................ 7 ESD Caution.................................................................................. 7 Pin Configuration and Function Descriptions............................. 8 Typical Performance Characteristics ............................................. 9 Test Circuits..................................................................................... 12 Terminology .................................................................................... 13 Theory of Operation ...................................................................... 14 Using the AD9288 ...................................................................... 14 Encode Input............................................................................... 14 Digital Outputs ........................................................................... 14 Analog Input ............................................................................... 14 Voltage Reference ....................................................................... 14 Timing ......................................................................................... 14 User-Selectable Options ............................................................ 14 AD9218/AD9288 Customer PCB BOM...................................... 15 Evaluation Board ............................................................................ 16 Power Connector........................................................................ 16 Analog Inputs ............................................................................. 16 Voltage Reference ....................................................................... 16 Clocking....................................................................................... 16 Data Outputs............................................................................... 16 Data Format/Gain ...................................................................... 16 Timing ......................................................................................... 16 Troubleshooting.......................................................................... 20 Outline Dimensions ....................................................................... 21 Ordering Guide .......................................................................... 21

REVISION HISTORY
12/04Rev. B to Rev. C Change to Absolute Maximum Ratings......................................... 7 Replaced Evaluation Board Section ............................................. 16 Updated Outline Dimensions ....................................................... 21 Changes to Ordering Guide .......................................................... 21 2/02Rev. A to Rev. B Edits to ABSOLUTE MAXIMUM RATINGS .............................. 3 1/01Rev. 0 to Rev. A 2/99Revision 0: Initial Version

Rev. C | Page 2 of 24

AD9288 SPECIFICATIONS
VDD = 3.0 V; VD = 3.0 V, differential input; external reference, unless otherwise noted. Table 1.
Parameter RESOLUTION DC ACCURACY Differential Nonlinearity Integral Nonlinearity No Missing Codes Gain Error1 Gain Tempco1 Gain Matching Voltage Matching ANALOG INPUT Input Voltage Range (with Respect to AIN) Common-Mode Voltage Temp Test Level Min AD9288BST-100 Typ Max 8 0.5 0.50 Guaranteed 2.5 80 1.5 15 512 0.3 VD 0.2 35 40 1.2 7 5 0.3 VD 0.3 VD +0.2 +35 +40 1.3 13 16 0.3 VD 0.2 35 40 1.2 7 5 +1.25 1.50 +1.25 1.50 +6 +8 6 8 Min AD9288BST-80 Typ Max 8 0.5 0.50 Guaranteed 2.5 80 1.5 15 512 0.3 VD 0.3 VD +0.2 +35 +40 1.3 13 16 0.3 VD 0.2 35 40 1.2 7 5 +1.25 1.50 +1.25 1.50 +6 +8 6 8 Min AD9288BST-40 Typ Max 8 0.5 0.50 Guaranteed 2.5 80 1.5 15 512 0.3 VD 0.3 VD +0.2 +35 +40 1.3 13 16 +1.25 1.50 +1.25 1.50 +6 +8 Unit Bits LSB LSB LSB LSB % FS % FS ppm/C % FS mV mV p-p V

25C Full 25C Full Full 25C Full Full 25C 25C Full Full

I VI I VI VI I VI VI V V V V

6 8

Input Offset Voltage Reference Voltage Reference Tempco Input Resistance Input Capacitance Analog Bandwidth, Full Power SWITCHING PERFORMANCE Maximum Conversion Rate Minimum Conversion Rate Encode Pulse Width High (tEH) Encode Pulse Width Low (tEL) Aperture Delay (tA) Aperture Uncertainty (Jitter) Output Valid Time (tV)2 Output Propagation Delay (tPD)2 DIGITAL INPUTS Logic 1 Voltage Logic 0 Voltage Logic 1 Current Logic 0 Current Input Capacitance DIGITAL OUTPUTS3 Logic 1 Voltage Logic 0 Voltage POWER SUPPLY Power Dissipation4 Standby Dissipation4, 5 Power Supply Rejection Ratio (PSRR)

25C Full Full Full 25C Full 25C 25C

I VI VI VI I VI V V

10 1.25 130 10 2 475

10 1.25 130 10 2 475

10 1.25 130 10 2 475

mV mV V ppm/C k pF MHz

Full 25C 25C 25C 25C 25C Full Full

VI IV IV IV V V VI VI

100 4.3 4.3 300 5 3.0 4.5 1 1000 1000

80 5.0 5.0 300 5 3.0 4.5 1 1000 1000

40 8.0 8.0 300 5 3.0 4.5 1 1000 1000

2 6.0

2 6.0

6.0

MSPS MSPS ns ns ps ps rms ns ns

Full Full Full Full 25C Full Full Full Full 25C

VI VI VI VI V VI VI VI VI I

2.0 0.8 1 1 2.0 2.45 0.05 180 6 8 218 11 20

2.0 0.8 1 1 2.0 2.45 0.05 171 6 8 207 11 20

2.0 0.8 1 1 2.0 2.45 0.05 156 6 8 189 11 20

V V A A pF V V mW mW mV/V

Rev. C | Page 3 of 24

AD9288
Parameter DYNAMIC PERFORMANCE6 Transient Response Overvoltage Recovery Time Signal-to-Noise Ratio (SNR) (without Harmonics) fIN = 10.3 MHz fIN = 26 MHz fIN = 41 MHz Signal-to-Noise Ratio (SINAD) (with Harmonics) fIN = 10.3 MHz fIN = 26 MHz fIN = 41 MHz Effective Number of Bits fIN = 10.3 MHz fIN = 26 MHz fIN = 41 MHz Second Harmonic Distortion fIN = 10.3 MHz fIN = 26 MHz fIN = 41 MHz Third Harmonic Distortion fIN = 10.3 MHz fIN = 26 MHz fIN = 41 MHz Two-Tone Intermod Distortion (IMD) fIN = 10.3 MHz Temp 25C 25C Test Level V V Min AD9288BST-100 Typ Max 2 2 Min AD9288BST-80 Typ Max 2 2 Min AD9288BST-40 Typ Max 2 2 Unit ns ns

25C 25C 25C

I I I

44

47.5 47.5 47.0

44

47.5 47

44

47.5

dB dB dB

25C 25C 25C 25C 25C 25C 25C 25C 25C 25C 25C 25C

I I I I I I I I I I I I

44

47 47 47 7.5 7.5 7.5 70 70 70 60 60 60

44

47 47 47 7.5 7.5 7.5 70 70 70 60 60 60

44

47

dB dB dB Bits Bits Bits dBc dBc dBc dBc dBc dBc

7.0

7.5

7.0

7.0

55

70

55

55

55

60

55

52

25C

60

60

60

dBc

1 2

Gain error and gain temperature coefficient are based on the ADC only (with a fixed 1.25 V external reference). tV and tPD are measured from the 1.5 V level of the Encode input to the 10%/90% levels of the digital outputs swing. The digital output load during test is not to exceed an ac load of 10 pF or a dc current of 40 A. 3 Digital supply current based on VDD = 3.0 V output drive with < 10 pF loading under dynamic test conditions. 4 Power dissipation measured under the following conditions: fS = 100 MSPS, analog input is 0.7 dBFS, both channels in operation. 5 Standby dissipation calculated with Encode clock in operation. 6 SNR/harmonics based on an analog input voltage of 0.7 dBFS referenced to a 1.024 V full-scale input range.

EXPLANATION OF TEST LEVELS

Level I II III IV V VI Description 100% production tested. 100% production tested at 25C and sample tested at specified temperatures. Sample tested only. Parameter is guaranteed by design and characterization testing. Parameter is a typical value only. 100% production tested at 25C; guaranteed by design and characterization testing for industrial temperature range; 100% production tested at temperature extremes for military devices.

Rev. C | Page 4 of 24

AD9288
TIMING DIAGRAMS

SAMPLE N

SAMPLE N + 1

SAMPLE N + 5

AINA, AINB

tA tEH
ENCODE A, B

SAMPLE N + 2

SAMPLE N + 3

SAMPLE N + 4

tEL

1/fs

tPD
D7AD0A

tV

DATA N 4

DATA N 3

DATA N 2

DATA N 1

DATA N

DATA N + 1

D7BD0B

DATA N 4

DATA N 3

DATA N 2

DATA N 1

DATA N

DATA N + 1

Figure 2. Normal Operation, Same Clock (S1 = 1, S2 = 0) Channel Timing

SAMPLE SAMPLE N N+1

SAMPLE N+2

SAMPLE N+3

SAMPLE N+4

AINA, AINB

tA tEH tEL 1/fs

ENCODE A

tPD tV
ENCODE B

D7AD0A

DATA N 8

DATA N 6

DATA N 4

DATA N 2

DATA N

DATA N + 2

D7BD0B

DATA N 7

DATA N 5

DATA N 3

DATA N 1

DATA N + 1

DATA N + 3

Figure 3. Normal Operation with Two Clock Sources (S1 = 1, S2 = 0) Channel Timing

Rev. C | Page 5 of 24

00585-004

00585-003

AD9288
SAMPLE SAMPLE N N+1 SAMPLE N+2 SAMPLE N+3 SAMPLE N+4

AINA, AINB

tA tEH tEL 1/fs

ENCODE A

tPD tV
ENCODE B

D7AD0A

DATA N 8

DATA N 6

DATA N 4

DATA N 2

DATA N

DATA N + 2

D7BD0B

DATA N 9

DATA N 7

DATA N 5

DATA N 3

DATA N 1

DATA N + 1

Figure 4. Data Align with Two Clock Sources (S1 = 1, S2 = 1) Channel Timing

Rev. C | Page 6 of 24

00585-005

AD9288 ABSOLUTE MAXIMUM RATINGS

Table 2.
Parameter VD, VDD Analog Inputs Digital Inputs VREF IN Digital Output Current Operating Temperature Storage Temperature Maximum Junction Temperature Maximum Case Temperature Thermal Impedance ja Rating 4V 0.5 V to VD + 0.5 V 0.5 V to VDD + 0.5 V 0.5 V to VD + 0.5 V 20 mA 55C to +125C 65C to +150C 150C 150C 57C/W

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions outside of those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability.

ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Rev. C | Page 7 of 24

AD9288 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

GND D7A (MSB) ENCA D6A D5A D4A D3A D2A D1A
48 47 46 45 44 43 42 41 40 39 38 37

GND 1 AINA 2 AINA 3 DFS 4 REFINA 5 REFOUT 6 REFINB 7 S1 8 S2 9 AINB 10 AINB 11 GND 12

D0A
36 35 34

VDD

VD

PIN 1 IDENTIFIER

NC NC

GND 33 VDD
32

AD9288
TOP VIEW (Not to Scale)

31 30 29

GND VD VD

GND 28 VDD
27 26 25 13 14 15 16 17 18 19 20 21 22 23 24

GND NC NC

GND (MSB) D7B

VD

ENCB

D6B

D5B

D4B

D3B

D2B

D1B

D0B

VDD

NC = NO CONNECT

Figure 5. Pin Configuration

Table 3.
Pin No. 1, 12, 16, 27, 29, 32, 34, 45 2 3 4 5 6 7 8 9 10 11 13, 30, 31, 48 14 15, 28, 33, 46 1724 25, 26, 35, 36 3744 47 Name GND AINA AINA DFS REFINA REFOUT REFINB S1 S2 AINB AINB VD ENCB VDD D7BD0 B NC D0AD7 A ENC A Description Ground Analog Input for Channel A. Analog Input for Channel A (Complementary). Data Format Select. Offset binary output available if set low. Twos complement output available if set high. Reference Voltage Input for Channel A. Internal Reference Voltage. Reference Voltage Input for Channel B. User Select 1. Refer to Table 4. Tied with respect to VD. User Select 2. Refer to Table 4. Tied with respect to VD. Analog Input for Channel B (Complementary). Analog Input for Channel B. Analog Supply (3 V). Clock Input for Channel B. Digital Supply (3 V). Digital Output for Channel B. Do Not Connect. Digital Output for Channel A. Clock Input for Channel A.

Rev. C | Page 8 of 24

00585-002

AD9288 TYPICAL PERFORMANCE CHARACTERISTICS

0 10 20 30
60 72

ENCODE = 100MSPS AIN = 10.3MHz SNR = 48.52dB SINAD = 48.08dB SECOND HARMONIC = 62.54dBc THIRD HARMONIC = 63.56dBc

ENCODE RATE = 100MSPS 68 64 2ND

40
dB dB
56 52 3RD

50 60 70 80 90 SAMPLE
00585-006

48
00585-009

44 40

10

20

30

40 MHz

50

60

70

80

90

Figure 6. Spectrum: fS = 100 MSPS, fIN = 10 MHz, Single-Ended Input

0 10 20 30 40
dB dB
0

Figure 9. Harmonic Distortion vs. AIN Frequency

ENCODE = 100MSPS AIN = 41MHz SNR = 47.87dB SINAD = 46.27dB SECOND HARMONIC = 54.10dBc THIRD HARMONIC = 55.46dBc

10 20 30 40 50 60 70
00585-007

ENCODE = 100MSPS AIN1 = 9.3MHz AIN2 = 10.3MHz IMD = 60.0dBc

50 60 70 80 90 SAMPLE

80 90 SAMPLE

Figure 7. Spectrum: fS = 100 MSPS, fIN = 41 MHz, Single-Ended Input

0 10 20 30 40
dB
50

Figure 10. Two-Tone Intermodulation Distortion

ENCODE = 100MSPS AIN = 76MHz SNR = 47.1dB SINAD = 43.2dB SECOND HARMONIC = 52.2dBc THIRD HARMONIC = 51.5dBc

ENCODE RATE = 100MSPS 48 SNR 46 SINAD 44

50 60

dB

42

40

70 80 90 SAMPLE
00585-008 00585-011

38

36

10

20

30

40 MHz

50

60

70

80

90

Figure 8. Spectrum: fS = 100 MSPS, fIN = 76 MHz, Single-Ended Input

Figure 11. SINAD/SNR vs. AIN Frequency

Rev. C | Page 9 of 24

00585-010

AD9288
49 AIN = 10.3MHz SINAD 48 175 SNR 185 180 190 AIN = 10.3MHz

POWER (mW)
00585-012

170 165 160 155

dB

47

46 150 145 140 0 10 20 30 40 50 MSPS 60 70 80 90

00585-015

45

30

40

50

60

70 MSPS

80

90

100

110

100

Figure 12. SINAD/SNR vs. Encode Rate

50 SNR 48.0 47.5 46 SINAD 47.0 46.5 42 46.0

Figure 15. Analog Power Dissipation vs. Encode Rate

AIN = 10.3MHz

ENCODE RATE = 100MSPS AIN = 10.3MHz

SNR SINAD

dB

dB
45.5 38 45.0 34
00585-013

44.5 44.0 43.5

00585-016

30

7.0

6.5

6.0

5.5

5.0

4.5

4.0

3.5

3.0

40

25 TEMPERATURE (C)

85

ENCODE HIGH PULSE WIDTH (ns)

Figure 13. SINAD/SNR vs. Encode Pulse Width High

0.5 ENCODE RATE = 100MSPS 0 0.4 0.5 1.0 1.5 0 0.2 0.6

Figure 16. SINAD/SNR vs. Temperature

ENCODE RATE = 100MSPS AIN = 10.3MHz

% GAIN
00585-014

2.0

3dB

dB

2.5 3.0 3.5 4.0 4.5 5.0 5.5 0 100 200 300 400 500

0.2 0.4 0.6

00585-017

0.8 1.0

600

40

25 TEMPERATURE (C)

85

BANDWIDTH (MHz)

Figure 14. ADC Frequency Response: fS = 100 MSPS

Figure 17. ADC Gain vs. Temperature (with External 1.25 V Reference)

Rev. C | Page 10 of 24

AD9288
2.0 1.5

1.3 ENCODE = 100MSPS VD = 3.0V TA = 25C

1.2
1.0

1.1

0 0.5 1.0

VREFOUT (V)
00585-018

0.5

LSB

1.0

0.9

0.8
00585-020

1.5 2.0 CODE

0.7 0 0.25 0.50 0.75 1.00 LOAD (mA) 1.25 1.50

1.75

Figure 18. Integral Nonlinearity

1.00 0.75 0.50 0.25

Figure 20. Voltage Reference Out vs. Current Load

LSB

0 0.25 0.50
00585-019

0.75 1.00 CODE

Figure 19. Differential Nonlinearity

Rev. C | Page 11 of 24

AD9288 TEST CIRCUITS

VD 28k AIN 12k 28k
OUT VDD

AIN
00585-021

12k

Figure 21. Equivalent Analog Input Circuit

Figure 24. Equivalent Digital Output Circuit

VD

VD

VBIAS REFIN
00585-022

OUT

Figure 22. Equivalent Reference Input Circuit

VD

Figure 25. Equivalent Reference Output Circuit

ENCODE
00585-023

Figure 23. Equivalent Encode Input Circuit

Rev. C | Page 12 of 24

00585-025

00585-024

AD9288 TERMINOLOGY
Analog Bandwidth (Small Signal) The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB. Aperture Delay The delay between a 50% crossing of Encode and the instant at which the analog input is sampled. Aperture Uncertainty (Jitter) The sample-to-sample variation in aperture delay. Differential Nonlinearity The deviation of any code from an ideal 1 LSB step. Encode Pulse Width/Duty Cycle Pulse width high is the minimum amount of time that the Encode pulse should be left in Logic 1 state to achieve rated performance; pulse width low is the minimum time Encode pulse should be left in low state. At a given clock rate, these specs define an acceptable Encode duty cycle. Integral Nonlinearity The deviation of the transfer function from a reference line measured in fractions of 1 LSB using a best straight line determined by a least square curve fit. Minimum Conversion Rate The Encode rate at which the SNR of the lowest analog signal frequency drops by no more than 3 dB below the guaranteed limit. Maximum Conversion Rate The Encode rate at which parametric testing is performed. Output Propagation Delay The delay between a 50% crossing of Encode and the time when all output data bits are within valid logic levels. Power Supply Rejection Ratio The ratio of a change in input offset voltage to a change in power supply voltage. Signal-to-Noise-and-Distortion (SINAD) The ratio of the rms signal amplitude (set at 1 dB below full scale) to the rms value of the sum of all other spectral components, including harmonics but excluding dc. Signal-to-Noise Ratio (SNR) The ratio of the rms signal amplitude (set at 1 dB below full scale) to the rms value of the sum of all other spectral components, excluding the first five harmonics and dc. Spurious-Free Dynamic Range (SFDR) The ratio of the rms signal amplitude to the rms value of the peak spurious spectral component. The peak spurious component may or may not be a harmonic. May be reported in dBc (i.e., degrades as signal level is lowered), or in dBFS (always related back to converter full scale). Two-Tone Intermodulation Distortion Rejection Two-Tone SFDR The ratio of the rms value of either input tone to the rms value of the peak spurious component. The peak spurious component may or may not be an IMD product. May be reported in dBc (i.e., degrades as signal level is lowered), or in dBFS (always related back to converter full scale). Worst Harmonic The ratio of the rms value of either input tone to the rms value of the worst third order intermodulation product; reported in dBc.

Rev. C | Page 13 of 24

AD9288 THEORY OF OPERATION

The AD9288 ADC architecture is a bit-per-stage pipeline-type converter utilizing switch capacitor techniques. These stages determine the 5 MSBs and drive a 3-bit flash. Each stage provides sufficient overlap and error correction, allowing optimization of comparator accuracy. The input buffers are differential, and both sets of inputs are internally biased. This allows the most flexible use of ac or dc and differential or single-ended input modes. The output staging block aligns the data, carries out the error correction, and feeds the data to output buffers. The set of output buffers are powered from a separate supply, allowing adjustment of the output voltage swing. There is no discernible difference in performance between the two channels. the input is overdriven. The nominal input range is 1.024 V p-p centered at VD 0.3.

VOLTAGE REFERENCE
A stable and accurate 1.25 V voltage reference is built into the AD9288 (REFOUT). In normal operation, the internal reference is used by strapping Pins 5 (REFINA) and 7 (REFINB) to Pin 6 (REFOUT). The input range can be adjusted by varying the reference voltage applied to the AD9288. No appreciable degradation in performance occurs when the reference is adjusted 5%. The full-scale range of the ADC tracks reference voltage, which changes linearly.

TIMING
The AD9288 provides latched data outputs, with four pipeline delays. Data outputs are available one propagation delay (tPD) after the rising edge of the Encode command (see Figure 2, Figure 3, and Figure 4). The length of the output data lines and loads placed on them must be minimized to reduce transients within the AD9288. These transients can detract from the converters dynamic performance. The minimum guaranteed conversion rate of the AD9288 is 1 MSPS. At clock rates below 1 MSPS, dynamic performance degrades. Typical power-up recovery time after standby mode is 15 clock cycles.

USING THE AD9288

Good high speed design practices must be followed when using the AD9288. To obtain maximum benefit, decoupling capacitors should be physically as close as possible to the chip, minimizing trace and via inductance between chip pins and capacitor (0603 surface-mount capacitors are used on the AD9288/PCB evaluation board). It is recommended to place a 0.1 F capacitor at each power-ground pin pair for high frequency decoupling, and to include one 10 F capacitor for local low frequency decoupling. The VREF IN pin should also be decoupled by a 0.1 F capacitor. It is also recommended to use a split power plane and a contiguous ground plane (see the Evaluation Board section). Data output traces should be short (< 1 inch), minimizing on-chip noise at switching.

USER-SELECTABLE OPTIONS
Two pins are available for a combination of operational modes. These options allow the user to place both channels, excluding the reference, into standby mode, or just the B channel. Both modes place the output buffers and clock inputs into high impedance states. The other option allows the user to skew the B channel output data by 1/2 of a clock cycle. In other words, if two clocks are fed to the AD9288 and are 180 out of phase, enabling the data align allows Channel B output data to be available at the rising edge of Clock A. If the same Encode clock is provided to both channels and the data align pin is enabled, then output data from Channel B is 180 out of phase with respect to Channel A. If the same Encode clock is provided to both channels and the data align pin is disabled, both outputs are delivered on the same rising edge of the clock. Table 4. User-Selectable Options
S1 0 0 1 1 S2 0 1 0 1 Option Standby Both Channels A and B. Standby Channel B Only. Normal Operation (Data Align Disabled). Data Align Enabled (data from both channels available on rising edge of Clock A. Channel B data is delayed a 1/2 clock cycle).

ENCODE INPUT
Any high speed A/D converter is extremely sensitive to the quality of the sampling clock provided by the user. A track-andhold circuit is essentially a mixer. Any noise, distortion, or timing jitter on the clock is combined with the desired signal at the A/D output. For that reason, considerable care has been taken in the design of the Encode (Clock) input of the AD9288, and the user is advised to give commensurate thought to the clock source. The Encode input is fully TTL/CMOS-compatible.

DIGITAL OUTPUTS
The digital outputs are TTL/CMOS-compatible for lower power consumption. During standby, the output buffers transition to a high impedance state. A data format selection option supports either twos complement (set high) or offset binary output (set low) formats.

ANALOG INPUT
The analog input to the AD9288 is a differential buffer. For best dynamic performance, impedance at AIN and AIN should match. Special care was taken in the design of the analog input stage of the AD9288 to prevent damage and corruption of data when

Rev. C | Page 14 of 24

AD9288 AD9218/AD9288 CUSTOMER PCB BOM

Table 5. Bill of Materials
No. Qty. Reference Designator Device Package Value Comments

1 2 3 4 5 6 7 8 9 10 11

29 2 7 28 4 5 3 3 1 4 9

C1, C3-C15, C20, C21, C24, C25, C27, C30C35, C39C42 C2, C36 C16C19, C26, C37, C38 E1, E2, E3, E4, E12E30, E34E38 H1, H2, H3, H4 J1, J2, J3, J4, J5 P1, P4, P11 P1, P4, P11 P2, P31 R1, R2, R32, R34 R3, R7, R11, R14, R22, R23, R24, R30, R51 R4, R5, R8, R9, R10, R12, R13, R20, R33, R35, R36, R37, R40, R42, R43, R50, R53 R6, R38 R15, R16, R18, R26, R29, R31 R17, R25 R19, R27 R21, R28, R39, R41, R44, R46R49, R52, R54, R55 T1, T2 U1 U2, U3 U5, U6 U7, U8, U9, U10 U11, U12

Capacitor Capacitor Capacitor W-HOLE MTHOLE SMA 4-pin power connector 4-pin power connector 80-pin rt. angle male Resistor Resistor

0603 0603 TAJD W-HOLE MTHOLE SMA Post Detachable Connector

0.1 F 15 pF 10 F 8138 out

Z5.531.3425.0 25.602.5453.0 TSW-140-08L-D-RA 36 50

J2, J3, not placed Wieland Wieland Samtec R1, R2, R32, R34, not placed R11, R22, R23, R24, R30, R51 not placed R43, R50 not placed R6, R38 not placed R16, R29 not placed

0603 0603

12

17

Resistor

0603

Zero

13 14 15 16 17 18 19 20 21 22 23
1 2

2 6 2 2 12 2 1 2 2 4 2

Resistor Resistor Resistor Resistor Resistor Transformer AD92882 74LCX821 SN74VCX86 Resistor array AD8138 op amp3

0603 0603 0603 0603 0603 ADT1-1WT LQFP48

25 500 525 4 k 1 k

Minicircuits

CTS

47

768203470G

P2, P3 are implemented as one physical 80-pin connector SAMTEC TSW-140-08-L-D-RA. AD9288/PCB populated with AD9288-100. 3 To use optional amp: place R22, R23, R30, R24, R16, R29, remove R4, R36.

Rev. C | Page 15 of 24

AD9288 EVALUATION BOARD

The AD9218/AD9288 customer evaluation board offers an easy way to test the AD9218 or the AD9288. The compatible pinout of the two parts facilitates the use of one PCB for testing either part. The PCB requires power supplies, a clock source, and a filtered analog source for most ADC testing required.

CLOCKING
Each channel can be clocked by a common clock input at SMA input ENCODE A/B. The channels can also be clocked independently by a simple board modification. The clock input should be a low jitter sine source for maximum performance.

POWER CONNECTOR
Power is supplied to the board via a detachable 12-lead power strip. The minimum 3 V supplies required to run the board are VDD, VDL, and VDD. To allow the use of the optional amplifier path, 5 V supplies are required.

DATA OUTPUTS
The data outputs are latched on-board by two 10-bit latches and drive an 8-pin connector which is compatible with the dualchannel FIFO board available from Analog Devices. This board, together with ADC analyzer software, can greatly simplify ADC testing.

ANALOG INPUTS
Each channel has an independent analog path that uses a wideband transformer to drive the ADC differentially from a single-ended sine source at the input SMAs. The transformer paths can be bypassed to allow the use of a dc-coupled path by using two AD8138 op amps with a simple board modification. The analog input should be band-pass filtered to remove any harmonics in the input signal and to minimize aliasing.

DATA FORMAT/GAIN
The DFS/Gain pin can be biased for desired operation at the DFS jumper located at the S1, S2 jumpers.

TIMING
Timing on each channel can be controlled if needed on the PCB. Clock signals at the latches or the data ready signals that go to the output 80-pin connector can be inverted if required. Jumpers also allow for biasing of Pins S1 and S2 for powerdown and timing alignment control.

VOLTAGE REFERENCE
The AD9288 has an internal 1.25 V voltage reference; an external reference for each channel can be used instead by connecting two external voltage references at the power connector and setting jumpers at E18 and E19. The evaluation board is shipped configured for internal reference mode.

Rev. C | Page 16 of 24

ENCXB R53 00 GND C25 0.1F VDL E13 E12

9

ENCB **DUT CLOCK SELECTABLE** **TO BE DIRECT OR BUFFERED**

**DUT CLOCK SELECTABLE** **TO BE DIRECT OR BUFFERED** ENCA

1 2 3 4

ENCXA 1A
8

U6 74LCX86
TIEB VDL R52 1k ENCXB E35
10

R50 00 3Y 3A 3B 4Y 4A 4B VCC 1A 1 1B 2 1Y 3 2A 4 R13 00 2B 5 2Y 6 DRB E34 R48 1k CLKLATB GND 7 GND R12 00

U5 74LCX86

TIEA 1B 1Y VDL R49 1k

11 12 13

VDL 4B 13 4A 12 4Y 11 E14 E15 VDL GND VDL

14

R42 00 VCC 14 R10 00 DRA GND GND GND GND GND R46 1k VDL R50 51 R54 1k E36

ENCODE B J2 C42 0.1F

ENCODE A J3 2A 2B 2Y GND R9 00 C8 0.1F GND GND R33 00 C41 0.1F 3Y 8 CLKLATA 3A 9 R47 1k 3B 10 E3
5

C40 0.1F E4 R44 1k ENCXA

6 7

R39 1k

R43 00

E16 VDL GND E37 E38 VDL

R11 50 GND

R41 1k

VDL

GND

GND

GND

C11 0.1F

ENCA

GND

D9A (MSB)

D8A

D7A

D6A

D5A

D4A

D3A

GND GND R1 36 R4 00

C10 0.1F

VD 48

VDD 46

D8A 43 D7A 42

D6A 41

D5A 40

D4A 39

D3A 38

ENCA 47

AIN A GND E25

2

GND GND
1 3

GND 45

D9A 44

D2A 37

J4

R3 50 C9 0.1F

C14 0.1F

D2A

AMPOUTA

C7 0.1F

VD

VDD

GND

R55 1k

GND

GND D1A 36 D0A 35 GND 34 VDD 33 GND 32 VD 31 VD 30 GND 29 VDD 28 GND 27 D0B 26 D1B 25 GND D0B D1B GND C1 0.1F GND VDD GND D1A D0A GND C4 0.1F VDD GND

GND 6 5 REFOUT VREFA E18

5 6 7 8 9 10 11

AMPINA R2 36 R5 00 E27 GND GND E17 REFOUT REFINB S1 S2 AINB AINB GND E19 GND VD E28 E23 E26 R SINGLE-ENDED AMPOUTBB R38 25 GND
12

GND AINA AINA DFS/GAIN REFINA

C31 0.1F VD E2 E30 E20 E1

4

GND 4 T2 AMPOUTAB R SINGLE-ENDED GND VD E29 E24 E22 R6 25

GND

C3 0.1F VD

VD

ENCB

VDD

GND

D9B

D8B

D7B

D6B

D5B

D4B

D3B

R34 36 GND

D2B

13

14

15

16

17

18

19

20

21

22

23

2 3 T1 GND R32 36 R36 00 C39 0.1F

5 4

24

D8B

D7B

D6B

D5B

D4B

D3B

D2B

GND

AIN B AMPOUTB

VD

(MSB) D9B

J1

C13 0.1F

ENCB

GND R35 00

C15 0.1F
1 2 3 4

5V VREFB
1 2 3 4

+5V

VDD

00585-026

Figure 26. PCB Schematic

AD9218/AD9288 U1
C30 0.1F 6 R37 00 GND C5 0.1F GND C6 0.1F VD C37 10F 5V +5V GND P5 P6 P11 P7 VD VDD VDL C38 + + 10F C16 + 10F VDD C17 + 10F VDL C18 + 10F VREFA C19 + 10F VREFB C26 + 10F GND C27 0.1F GND VREFA GND GND P4

Rev. C | Page 17 of 24

GND

C12 0.1F

GND

TO TIE CLOCKS TOGETHER ENCA J5 ENCB R8 00 R20 00 TIEA R14 50 GND GND GND C24 0.1F REFINA REFINB GND R40 00 TIEB

AMPINB

GND

R7 50

H3
MTHOLE6

VDL

H1
MTHOLE6

VDD

GND

H2
MTHOLE6

VD

GND

H4
MTHOLE6

AD9288

P1

AD9288

GND C21 0.1F P3 HEADER40 D9P

40 40 38 38 36 36 34 34 32 32 30 30 28 28 26 26 24 24 22 22 20 20 18 18 16 16 14 14 12 12 10 10 8 8 6 6 4 4 2 2 35 35 33 33 31 31 29 29 27 27 25 25 23 23 21 21 19 19 17 17 15 15 13 13 11 11 9 9 7 7 5 5 3 3 1 1 37 37 39 39

OPAMP INPUT OFF PIN ONE OF TRANSFORMER U2 74LCX821 D9M

1 OE 2 X0 3 X1 4 X2 5 X3 6 X4 7 X5 8 X6 9 X7 10 X8 11 X9 12 GND CLK 13 Y9 14 Y8 15 Y7 16 Y6 17 Y5 18 Y4 19 Y3 20 Y2 21 Y1 22 Y0 23 VCC 24 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 10 10 11 11 12 12 13 13 14 14 15 15 16 16 17 17 18 18 19 19 20 20

U7 CTS20 VALUE = 50 D9A

1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 10 10 11 11 12 12 13 13 14 14 15 15 16 16 17 17 18 18 19 19 20 20

U9 CTS20 VALUE = 50 D9X D8X D8P D7P D6P D5P D4P D3P D2P D1P D0P D7X D6X D5X D4X D3X D2X D1X D0X GND DRA GND D9P D8P D7P D6P D5P D4P D3P D2P D1P D0P GND GND GND GND GND GND GND GND

GND GND D9M D9X D8X D7X D6X D5X D4X D3X D2X D1X D0X CLKLATA D8M D7M D6M D5M D4M D3M D2M D1M D0M GND R22 50 VDL R16 525 D7A D7M D6M D5M D4M D3M D2M D1M D0M +5V D5A R19 4k D4A D3A R18 500 D2A D1A D0A +5V C32 0.1F GND GND R21 1k D6A D8A D8M

AMPINA

R17 500

AD8138

+IN

IN 1

R15 500

NC

VOCM 2

5V

V+ 3

C33 0.1F

OUT

+OUT 4

U11

R23 50

C2 15pF

AMPOUTAB

AMPOUTA

GND C20 0.1F VDL

Y0 23 Y1 22 Y2 21 Y3 20 6 X4 7 X5 8 X6 Y4 19 Y5 18 Y6 17

00585-027

Figure 27. PCB Schematic (Continued)

U8 CTS20 VALUE = 50 U3 74LCX821 D0N
1 OE 2 X0 3 X1 4 X2 5 X3

Rev. C | Page 18 of 24
GND D0B
1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 10 10 11 11 12 12 13 13 14 14 15 15 16 16 17 17 18 18 19 19 20 20

U10 CTS20 VALUE = 50 D0Y D0Y D1Y D2Y D3Y D4Y D5Y D6Y D1Y D2Y D3Y D4Y D5Y D6Y D7Y
1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 20 20 19 19 18 18 17 17 16 16 15 15 14 14 13 13

P2 HEADER40 D0Q D1Q D2Q D3Q D4Q D5Q D6Q D7Q

40 40 38 38 36 36 34 34 32 32 30 30 28 28 26 26 39 39 37 37 35 35 33 33 31 31 29 29 27 27 25 25

AMPINB GND D0N D1N D2N D3N D4N D5N D6N D7N D8N D9N D9N GND R30 50 R25 525 D2B D2N D3N D4N D5N D6N D7N D8N +5V D4B R27 4k D5B D6B R26 500 D7B D8B D9B +5V C35 0.1F GND GND R28 1k D3B D1B D1N

VCC 24

GND DRB GND D9Q D8Q D7Q D6Q D5Q

R29 500

AD8138

+IN

IN 1

R31 500

NC

VOCM 2

5V

V+ 3

C34 0.1F

OUT

+OUT 4

9 X7 10 X8 11 X9 12 GND

Y7 16 Y8 15 Y9 14 CLK 13

D7Y D8Y D9Y

D8Y D9Y

9 9 10 10

12 12 11 11

D8Q D9Q

24 24 22 22 20 20

23 23 21 21 19 19

D4Q D3Q D2Q CLKLATB

18 18 16 16 14 14 12 12 10 10 8 8 6 6 4 4 2 2 17 17 15 15 13 13 11 11 9 9 7 7 5 5 3 3 1 1

U12

D1Q D0Q GND GND GND GND GND GND GND GND

R24 50

C36 15pF

AMPOUTB

AMPOUTBB

AD9288

00585-028

Figure 28. Top Silkscreen

Figure 31. Split Power Plane

00585-029

Figure 29. Top Routing

Figure 32. Bottom Routing

00585-030

Figure 33. Bottom Silkscreen

Figure 30. Ground Plane

Rev. C | Page 19 of 24

00585-033

00585-032

00585-031

AD9288
TROUBLESHOOTING
If the board does not seem to be working correctly, try the following: Verify power at the IC pins. Check that all jumpers are in the correct position for the desired mode of operation. Verify that VREF is at 1.23 V. Try running Encode clock and analog inputs at low speeds (20 MSPS/1 MHz) and monitor LCX821 outputs, DAC outputs, and ADC outputs for toggling. The AD9218/AD9288 evaluation board is provided as a design example for customers of Analog Devices, Inc. ADI makes no warranties, express, statutory, or implied, regarding merchantability or fitness for a particular purpose.

Rev. C | Page 20 of 24

AD9288 OUTLINE DIMENSIONS

0.75 0.60 0.45 1.60 MAX
48 1

9.00 BSC SQ
37 36
PIN 1

1.45 1.40 1.35

10 6 2

SEATING PLANE
0.20 0.09
7 3.5 0 0.08 MAX COPLANARITY

TOP VIEW
(PINS DOWN)

7.00 BSC SQ

VIEW A
12 13 24 25

0.15 0.05

SEATING PLANE

0.50 BSC

VIEW A
ROTATED 90 CCW COMPLIANT TO JEDEC STANDARDS MS-026BBC

0.27 0.22 0.17

Figure 34. 48-Lead Low Profile Quad Flat Package [LQFP] (ST-48) Dimensions shown in millimeters

ORDERING GUIDE
Model AD9288BST-40 AD9288BSTZ-401 AD9288BSTZRL-401 AD9288BST-80 AD9288BSTZ-801 AD9288BST-100 AD9288BSTZ-1001 AD9288/PCB
1

Temperature Range 40C to +85C 40C to +85C 40C to +85C 40C to +85C 40C to +85C 40C to +85C 40C to +85C

Package Description
48-Lead Low Profile Quad Flat Package 48-Lead Low Profile Quad Flat Package 48-Lead Low Profile Quad Flat Package 48-Lead Low Profile Quad Flat Package 48-Lead Low Profile Quad Flat Package 48-Lead Low Profile Quad Flat Package 48-Lead Low Profile Quad Flat Package

Package Options ST-48 ST-48 ST-48 ST-48 ST-48 ST-48 ST-48

Evaluation Board

Z = Pb-free part.

Rev. C | Page 21 of 24

AD9288 NOTES

Rev. C | Page 22 of 24

AD9288 NOTES

Rev. C | Page 23 of 24

AD9288 NOTES

2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C00585012/04(C)

Rev. C | Page 24 of 24