3. Thit k: 3.1.

S khi tng qut:

3.2. Cc bc thc hin 1 cu lnh:

*C 5 bc vi cc chc nng ring: + c lnh t b nh (Instruction Fetch IF) - S dng a ch lu trong thanh ghi PC gii m ra m my ca cu lnh tip theo v lu vo thanh ghi trung gian IF/ID. - Gi tr PC c cng thm 4 v lu vo thanh ghi trung gian IF/ID. + Gii m lnh v c cc thanh ghi (Instruction Decode ID) - S dng m my ca cu lnh lu trong thanh ghi IF/ID lm u vo cho khi Regfile. - Khi Control s dng phn opcode ca m my ca cu lnh gii m thnh cc tn hiu iu khin, ngoi tn hiu SignEx c s dng cho khi m rng, cc tn hiu khc c lu vo thanh ghi trung gian ID/EX. - c cc thanh ghi Rs, Rt t b thanh ghi v lu vo thanh ghi trung gian ID/EX. - Khi m rng s dng tn hiu SignEx t khi Control m rng du hay m rng zero ca 16 bit thp ca m my thnh 32 bit v lu vo thanh ghi ID/EX. - a ch ca cc thanh ghi Rs, Rt, Rd c lu vo thanh ghi ID/EX. + Tnh ton kt qu ca cu lnh hoc a ch (Execution EX) - Khi ALU s dng cc u vo c lu trong thanh ghi ID/EX tnh ton v lu kt qu vo thanh ghi trung gian EX/MEM. - Mt b mux c dng la chn thanh ghi ch t 2 thanh ghi Rt, Rd v lu a ch vo thanh ghi EX/MEM. - a ch mi ca PC sau cu lnh BNE cng c tnh ton trong khi ny. Mt s b mux c dng la chn gi tr mi cho PC t cc cu lnh r nhanh BNE, J, JR. - Cc tn hiu iu khin MemWrite, MemtoReg v RegWrite c lu tip vo thanh ghi EX/MEM. + c hoc ghi d liu trn b nh d liu (Memory access MEM) - S dng kt qu tnh ton t khi ALU v tn hiu iu khin MemWrite t thanh ghi EX/MEM thc hin c hoc ghi vo b nh d liu. Kt qu c ra c ghi vo thanh ghi trung gian MEM/WB. - Cc gi tr u ra ca ALU, a ch thanh ghi ch cng vi 2 tn hiu iu khin MemtoReg v RegWrite c ghi li vo thanh ghi MEM/WB. + Ghi kt qu vo thanh ghi (Write back WB) - S dng tn hiu MemtoReg t thanh ghi MEM/WB la chn d liu cn ghi vo thanh ghi. - S dng a ch thanh ghi ch v tn hiu cho php ghi RegWrite thc hin cng vic ghi d liu vo b thanh ghi.

3.3. Thit k cc thanh ghi pipelined:

- Ta s dng cc thanh ghi pipeline lm trung gian lu kt qu thc hin ca mi khi trong mi chu k lm u vo cho cc khi sau trong chu k tip theo

- C 4 thanh ghi trung gian gia cc khi: + IF/ID: lu cc gi tr PC + 4 M my ca cu lnh

module IFIDReg(PCIN, PCOUT, InstIN, InstOUT, IFIDWrite, IFIDFlush, clk, Reset); input [31:0] PCIN; output [31:0] PCOUT; input [31:0] InstIN; output [31:0] InstOUT; input IFIDWrite; input IFIDFlush; input clk; input Reset; reg [31:0] PCOUT; reg [31:0] InstOUT; always @(negedge clk or negedge Reset) begin if(Reset == 1'b0) begin InstOUT <= 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; PCOUT <= 32'd0; end else begin if(IFIDFlush == 1'b1) begin PCOUT <= 32'd0; InstOUT <= 32'd0; end else begin if(IFIDWrite == 1'b1) begin PCOUT <= PCIN; InstOUT <= InstIN; end else begin PCOUT <= PCOUT; InstOUT <= InstOUT; end end end end endmodule

+ ID/EX: lu cc gi tr PC + 4 a ch ca lnh Jump 2 Gi tr c ra t b thanh ghi Gi tr m rng 32bits t 16bits a ch cc thanh ghi Rs, Rt, Rd Cc tn hiu iu khin t khi Control: ALUOp, ALUSrc, RegDst, Branch, Jump, MemWrite, RegWrite, MemtoReg.

module IDEXReg(PCOUT,PCOUTex,CtrlWBIN, CtrlMIN, CtrlEXIN, RFOUT1IN, RFOUT2IN, RFOUT1OUT, RFOUT2OUT, SignExIN, SignExOUT, SignExzeroIN,SignExzeroOUT,IFIDRsIN, IFIDRsOUT, IFIDRtIN, IFIDRtOUT, IFIDRdIN, IFIDRdOUT, clk, CtrlWBOUT, CtrlMOUT, CtrlEXOUT, CtrlBrIN, CtrlBrOUT,Stall); input [1:0] CtrlWBIN; input [1:0] CtrlMIN; input [6:0] CtrlEXIN; input [31:0] RFOUT1IN; input [31:0] RFOUT2IN; input [31:0] PCOUT; output [31:0] PCOUTex; output [31:0] RFOUT1OUT; output [31:0] RFOUT2OUT; input [31:0] SignExIN; output [31:0] SignExOUT; input [31:0] SignExzeroIN; output [31:0] SignExzeroOUT; input [4:0] IFIDRsIN; output [4:0] IFIDRsOUT; input [4:0] IFIDRtIN; output [4:0] IFIDRtOUT; input [4:0] IFIDRdIN; output [4:0] IFIDRdOUT; input clk; input Stall; output [1:0] CtrlWBOUT; output [1:0] CtrlMOUT; output [6:0] CtrlEXOUT; input CtrlBrIN; output CtrlBrOUT; reg [31:0] RFOUT1OUT; reg [31:0] RFOUT2OUT; reg [31:0] SignExOUT; reg [31:0] SignExzeroOUT; reg [4:0] IFIDRsOUT; reg [4:0] IFIDRtOUT; reg [4:0] IFIDRdOUT; reg [1:0] CtrlWBOUT; reg [1:0] CtrlMOUT; reg [6:0] CtrlEXOUT; reg [31:0] PCOUTex; reg CtrlBrOUT;

always @(negedge clk) begin if(Stall==0) begin RFOUT1OUT <= RFOUT1IN; RFOUT2OUT <= RFOUT2IN; SignExOUT <= SignExIN; SignExzeroOUT <= SignExzeroIN; IFIDRsOUT <= IFIDRsIN; IFIDRtOUT <= IFIDRtIN; IFIDRdOUT <= IFIDRdIN; CtrlWBOUT <= CtrlWBIN; CtrlMOUT <= CtrlMIN; CtrlEXOUT <= CtrlEXIN; CtrlBrOUT <= CtrlBrIN; PCOUTex <=PCOUT; end else begin RFOUT1OUT <= 32'b0; RFOUT2OUT <= 32'b0; SignExOUT <= 32'b0; SignExzeroOUT <= 32'b0; IFIDRsOUT <= 5'b0; IFIDRtOUT <= 5'b0; IFIDRdOUT <= 5'b0; CtrlWBOUT <= 2'b0; CtrlMOUT <= 2'b0; CtrlEXOUT <= 5'b0; CtrlBrOUT <= 1'b0; PCOUTex <=1'b0; end end endmodule

+ EX/MEM: lu cc gi tr Kt qu tnh ton ca khi ALU Gi tr dng ghi vo b nh file thanh ghi a ch ca thanh ghi ch Cc tn hiu iu khin: MemWrite, RegWrite, MemtoReg. module EXMEMReg(CtrlWBIN, CtrlWBOUT, CtrlMIN, CtrlMOUT, ALUIN, ALUOUT, MUXRtRdIN, MUXRtRdOUT, RtDataIN, RtDataOUT, clk); input [1:0] CtrlWBIN;

output [1:0] CtrlWBOUT; input [1:0] CtrlMIN; output [1:0] CtrlMOUT; input [31:0] ALUIN; output [31:0] ALUOUT; input [4:0] MUXRtRdIN; output [4:0] MUXRtRdOUT; input [31:0] RtDataIN; output [31:0] RtDataOUT; input clk; reg [1:0] CtrlWBOUT; reg [1:0] CtrlMOUT; reg [31:0] ALUOUT; reg [4:0] MUXRtRdOUT; reg [31:0] RtDataOUT; always @(negedge clk) begin CtrlWBOUT <= CtrlWBIN; CtrlMOUT <= CtrlMIN; ALUOUT <= ALUIN; MUXRtRdOUT <= MUXRtRdIN; RtDataOUT <= RtDataIN; end endmodule + MEM/WB: lu cc gi tr Gi tr c ra t b nh d liu Kt qu ca khi ALU a ch thanh ghi ch

module MEMWBReg(CtrlWBIN, CtrlWBOUT, MemIN, MemOUT, ALUIN, ALUOUT, RtRdIN, RtRdOUT, clk); input [1:0] CtrlWBIN; output [1:0] CtrlWBOUT; input [31:0] MemIN; output [31:0] MemOUT; input [31:0] ALUIN; output [31:0] ALUOUT; input [4:0] RtRdIN; output [4:0] RtRdOUT; input clk;

reg [1:0] CtrlWBOUT; reg [31:0] MemOUT; reg [31:0] ALUOUT; reg [4:0] RtRdOUT; always @(negedge clk) begin CtrlWBOUT <= CtrlWBIN; MemOUT <= MemIN; ALUOUT <= ALUIN; RtRdOUT <= RtRdIN; end endmodule

3.4. Thit k x l Hazards:

- Nu ch s dng cc thanh ghi trung gian nh trn, trong lc thc hin chng trnh s gy ra cc Hazard do vic c ra cc thanh ghi trong khi gi tr ca n trong b thanh ghi cha kp thay i t cc cu lnh trc . - gii quyt vn ny, ta c 2 phng php: + Stalling: Mi khi c Hazard xy ra, ta tm thi cho ngng hot ng ca cc khi IF v ID, ch cho d liu c ghi xong mi tip tc. + Forwarding: Phng php Stalling ni trn c u im l n gin, tuy nhin s lm tc x l chm i. Ta c th thay th bng phng php Forwarding, nguyn tc chung ca phng php ny l tm nhng gi tr s c ghi vo thanh ghi lm i s trong bc Execution thay cho cc gi tr c ra t thanh ghi hin thi. + i vi cu lnh lw, d liu cn thit ch xut hin sau bc Memory access. Do , nu ngay sau cu lnh lw c s dng n gi tr c c ra th ta khng th c c gi tr ng bng phng php Forwarding. V vy ring vi cu lnh lw, nu xy ra Hazard, th ta phi s dng n Stalling Hazard. - Ta xy dng mt khi logic Forwarding kim tra cc tn hiu cho php ghi, ng thi so snh a ch ca 2 thanh ghi Rs, Rt ca cu lnh hin ti vi a ch ca thanh ghi ch ca cc cu lnh trc, qua a ra tn hiu iu khin cho 2 b mux la chn i s cho bc Execution.

- Code:
module Hazard(IDEXMemRead, IDEXRt, IFIDRs, IFIDRt, PCWrite, IFIDWrite, Stall, Reset); input IDEXMemRead; input [4:0] IDEXRt; input [4:0] IFIDRs; input [4:0] IFIDRt; input Reset; output PCWrite; output IFIDWrite;

output Stall; reg PCWrite; reg IFIDWrite; reg Stall; always @(IDEXMemRead or IDEXRt or IFIDRs or IFIDRt or Reset) begin if(Reset == 1'b0) begin Stall = 1'b0; PCWrite = 1'b1; IFIDWrite = 1'b1; end else begin if((IDEXMemRead == 1'b1) && ((IDEXRt == IFIDRs) || (IDEXRt == IFIDRt))) begin Stall = 1'b1; PCWrite = 1'b0; IFIDWrite = 1'b0; end else begin Stall = 1'b0; PCWrite = 1'b1; IFIDWrite = 1'b1; end end end endmodule

3.5. Thit k Forwarding:

+ Forwarding: Phng php Stalling ni trn c u im l n gin, tuy nhin s lm tc x l chm i. Ta c th thay th bng phng php Forwarding, nguyn tc chung l tm nhng gi tr s c ghi vo thanh ghi lm i s trong bc Execution thay cho cc gi tr c ra t thanh ghi hin thi. - Ta xy dng mt khi logic Forwarding kim tra cc tn hiu cho php ghi, ng thi so snh a ch ca 2 thanh ghi Rs, Rt ca cu lnh hin ti vi a ch ca thanh ghi ch ca cc cu lnh trc, qua a ra tn hiu iu khin cho 2 b mux la chn i s cho bc Execution.

Code:

module Forwarding(IDEXRs, IDEXRt, EXMEMRd, MEMWBRd, EXMEMRegWrite, MEMWBRegWrite, ForwardA, ForwardB, Reset); input [4:0] IDEXRs; input [4:0] IDEXRt; input [4:0] EXMEMRd; input [4:0] MEMWBRd; input EXMEMRegWrite; input MEMWBRegWrite; input Reset; output [1:0] ForwardA; output [1:0] ForwardB; reg [1:0] ForwardA; reg [1:0] ForwardB; always @(IDEXRs or IDEXRt or EXMEMRd or MEMWBRd or EXMEMRegWrite or MEMWBRegWrite or Reset) begin if(Reset == 1'b0) begin ForwardA = 2'b00; ForwardB = 2'b00; end else begin if((EXMEMRegWrite == 1'b1) && (EXMEMRd != 5'b0) && (EXMEMRd == IDEXRs) ) begin ForwardA = 2'b01; if(EXMEMRd == IDEXRt) begin ForwardB = 2'b01; end else if ((MEMWBRd != IDEXRt)||(MEMWBRegWrite == 1'b0)) begin ForwardB = 2'b00; end else begin ForwardB = 2'b10; end end else if((EXMEMRegWrite == 1'b1) && (EXMEMRd != 5'b0) && (EXMEMRd == IDEXRt)) begin

ForwardB = 2'b01; if ((MEMWBRd != IDEXRs)||(MEMWBRegWrite == 1'b0)) begin ForwardA = 2'b00; end else begin ForwardA = 2'b10; end end else if((MEMWBRegWrite == 1'b1) && (MEMWBRd != 5'b0) && (EXMEMRd != IDEXRs) &&(MEMWBRd == IDEXRs)) begin ForwardA = 2'b10; if (MEMWBRd == IDEXRt) ForwardB = 2'b10; else ForwardB = 2'b00; end else if((MEMWBRegWrite == 1'b1) && (MEMWBRd != 5'b0) && (EXMEMRd != IDEXRt) && (MEMWBRd == IDEXRt)) begin ForwardA = 2'b00; ForwardB = 2'b10; end else begin ForwardA = 2'b00; ForwardB = 2'b00; end end end endmodule

3.6.Thit k khi la chn a ch cho cc lnh nhy - Muxflush:

+Mi lnh sau khi thc hin s cho mt gi tr PC mi v cc lnh nhy th cch tnh gi tr PC mi (a ch nhy ti) khc vi cc lnh khc. V vy la chn chnh xc gi tr PC mi cc cu lnh thc hin ng trnh t th ta phi thit k thm khi iu khin vic la chn ny. Khi ny c t tn l muxflush.

Code:

module muxflush(cbr,cjr,cj,brs,jr,j,IFIDFlush,IDEXFlush);

input cbr; input cjr; input cj; output brs; output jr; output j; output IFIDFlush; output IDEXFlush; reg IFIDFlush; reg IDEXFlush; reg brs; reg jr; reg j; always @(cbr or cjr or cj) begin //mux br choose if(cbr==1'b1) begin assign brs=1'b1; assign IFIDFlush = 1'b1; assign IDEXFlush = 1'b1; end else if(cjr==1'b1) begin assign jr=1'b1; assign IFIDFlush = 1'b1; assign IDEXFlush = 1'b1; end else if(cj==1'b1) begin assign j=1'b1; assign IFIDFlush = 1'b1; assign IDEXFlush = 1'b0; end else begin assign jr=1'b0;

assign brs =1'b0; assign j=1'b0; assign IFIDFlush = 1'b0; assign IDEXFlush = 1'b0; end end

endmodule

3.7. Tnh ton xung clk:

Khi c thi gian thc hin di nht l Execution, vi thi gian cn cho khi ALU l khong 5000ps, ngoi ra cn 1 s b mux, add, shiftleft2. Do ta chn rng ca xung clk l 7000ps, hay chu k xung clk l 14000ps.

3.8. Thit k Module chnh:

+Kt hp cc khi c thit k pha trn v ni cc ng i ca cc tn hiu c nh hnh pha trn ta c b MIPS nh yu cu. Code:
timescale 1 ps / 100 fs module MIPS(clk,Reset); input clk; input Reset;

// PC and Instruction Memory wire [31:0] PC, PCin; wire [31:0] PC4; // PC4 = PC+4 wire [31:0] instruction; // Code here //STAGE 1 // PC4 = PC + 4 Add Add1(PC,{29'b0,3'b100},PC4); // InstructionMem InstructionMem InstructionMem1(instruction, PC); //mux branch wire [31:0] PCbranch; mux2x32to32 mux2x32to32branch(PC4,BranchResult,br,PCbranch); //mUX jump register wire [31:0] PCjr; mux2x32to32 mux2x32to32jr(PCbranch,ALUin1,jr,PCjr); //MUx jump wire [31:0] PCj; mux2x32to32 muxJump(PCjr, //DataIn0 {PCOUT[31:28],JumpAddress_28[27:0]}, j, //Sel

//DataIn1

PCj); //DataOut // PC Block PC_Block PC_Block1(PCj,PC,PCWrite,clk,Reset); /////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// IFIDReg IFIDReg1(PC4, PCOUT, instruction, instruction_2, IFIDWrite, IFIDFlush, clk, Reset); [31:0] PCOUT,instruction_2; wire IFIDWrite; // (PCIN, PCOUT, InstIN, InstOUT, IFIDWrite, IFIDFlush, clk, Reset); ///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////

wire

//Before jump wire [31:0] JumpAddress_28; shift_left_2 shift_left_2_jump({6'b0,instruction_2[25:0]}, //In32 ~ 26-bit offset of jump instruction JumpAddress_28); //Out32 ~ 28-bit after shifting left 2 bits //Hazard wire PCWrite,IFIDWite; Hazard Hazard1(CtrlMOUT_3[1], IFIDRtOUT_3, instruction_2[25:21], instruction_2[20:16], PCWrite, IFIDWrite, Stall, Reset); // Main Control wire RegDst, Jump, Branch, MemRead, MemtoReg, MemWrite, ALUSrc, RegWrite, Xori; Control Control1(instruction_2[31:26], RegDst, Jump, Branch, MemRead, MemtoReg, ALUOp, Xori, MemWrite, ALUSrc, RegWrite); wire [1:0] CtrlWBINb,CtrlMINb; wire [6:0] CtrlEXINb; assign CtrlWBINb={RegWrite,MemtoReg}; assign CtrlMINb={MemRead,MemWrite}; assign CtrlEXINb={Jump,Branch,Xori,RegDst,ALUOp,ALUSrc}; //Mux CONTROL~0 in STALLING mux2x11to11 mux2x11to11_stall({CtrlWBINb,CtrlMINb,CtrlEXINb},11'b0,Stall,{CtrlWBIN,CtrlMIN,CtrlEXIN}); // Regfile wire [4:0] WriteRegister; //STAGE 2 wire [31:0] WriteData, ReadData1, ReadData2; regfile regfile1( instruction_2[25:21], instruction_2[20:16], WriteRegister_5, WriteData, CtrlWBOUT_5[1], ReadData1, ReadData2, clk); // Sign-extend wire [31:0] Sign_extend_Out; sign_extend sign_extend1(instruction_2[15:0],Sign_extend_Out); // Sign-extend Zero wire [31:0] Sign_extendzero_Out; sign_extendzero sign_extendzero1(instruction_2[15:0],Sign_extendzero_Out); wire nop; or (nop,Stall,IDEXFlush); //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// // IDEXReg wire [31:0] ReadData1_3, ReadData2_3, Sign_extend_Out_3 ,Sign_extendzero_Out_3,PCOUTex; wire [4:0] IFIDRsOUT_3, IFIDRtOUT_3, IFIDRdOUT_3; wire [1:0] CtrlWBIN, CtrlWBOUT_3, CtrlMIN, CtrlMOUT_3; wire [6:0] CtrlEXOUT_3, CtrlEXIN; wire CtrlBrOUT; IDEXReg IDEXReg1(PCOUT,PCOUTex,CtrlWBIN, CtrlMIN, CtrlEXIN, ReadData1, ReadData2, ReadData1_3, ReadData2_3,Sign_extend_Out, Sign_extend_Out_3,Sign_extendzero_Out,Sign_extendzero_Out_3,

instruction_2[25:21], IFIDRsOUT_3, instruction_2[20:16], IFIDRtOUT_3, instruction_2[15:11], IFIDRdOUT_3, clk, CtrlWBOUT_3, CtrlMOUT_3, CtrlEXOUT_3, CtrlBrIN, CtrlBrOUT_3,nop); ///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// // Select WriteRegister mux2x5to5 mux2x5to5_1(IFIDRtOUT_3, IFIDRdOUT_3, CtrlEXOUT_3[3], WriteRegister); // Select Bus B for ALU of (format I) wire [31:0] BusB_of_ALUbefore; mux2x32to32 mux2x32to32_1(ALUin2, Sign_extend_Out_3, CtrlEXOUT_3[0], BusB_of_ALUbefore); // Select Bus B for ALU after of Xori mux2x32to32 mux2x32to32_12(BusB_of_ALUbefore, Sign_extendzero_Out_3, CtrlEXOUT_3[4], BusB_of_ALUafter); // ALU control wire [1:0] ALUOp; //STAGE 3 ALUcontrol_Block ALUcontrol1(CtrlEXOUT_3[2:1], Sign_extend_Out_3[5:0], ALUcontrol); // Addtion Of forwarding MUX32Bit3Ch MUX32Bit3Ch_fw1(ForwardA,ReadData1_3,ALUOUT_4,WriteData,ALUin1); MUX32Bit3Ch MUX32Bit3Ch_fw2(ForwardB,ReadData2_3,ALUOUT_4,WriteData,ALUin2);

// ALU Block wire [31:0] BusB_of_ALUafter, ALUresult,ALUin1,ALUin2; wire [2:0] ALUcontrol; ALU ALU1(ALUin1, BusB_of_ALUafter, ALUcontrol, ALUresult, ZeroFlag); //Block shift 2 wire [31:0] Sign_extend_Out_3af; shift_left_2 shift_left_2branch(Sign_extend_Out_3, Sign_extend_Out_3af); //Add branch wire [31:0] BranchResult; Add Addbranch(Sign_extend_Out_3af,PCOUTex,BranchResult); wire bradd; and andbranch(bradd,CtrlEXOUT_3[5],~ZeroFlag); //mux flush wire jr,j,IFIDFlush,IDEXFlush; muxflush muxflush(bradd,ALUcontrol[2],Jump,br,jr,j,IFIDFlush,IDEXFlush); //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// // EXMEMReg wire [31:0] ReadData2_4, ALUOUT_4; wire [4:0] WriteRegister_4; wire [1:0] CtrlWBOUT_4, CtrlMOUT_4; EXMEMReg EXMEMReg1(CtrlWBOUT_3, CtrlWBOUT_4, CtrlMOUT_3, CtrlMOUT_4, ALUresult, ALUOUT_4, WriteRegister, WriteRegister_4, ALUin2, ReadData2_4, clk); ///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// // Data Memory wire [31:0] ReadData_of_Mem; datamem DataMem1(ReadData_of_Mem, //data ALUOUT_4, //address ReadData2_4, //writedata //STAGE 4 CtrlMOUT_4[0], //writeenable CtrlMOUT_4[1], //readenable clk);

// Forwarding Block wire [1:0] ForwardA, ForwardB; Forwarding Forwarding1(IFIDRsOUT_3, IFIDRtOUT_3, CtrlWBOUT_4[1], CtrlWBOUT_5[1],ForwardA, ForwardB, Reset);

WriteRegister_4,

WriteRegister_5,

///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// // MEMWBReg wire [1:0] CtrlWBOUT_5; wire [31:0] MemOUT_5, ALUOUT_5; wire [4:0] WriteRegister_5; MEMWBReg MEMWBReg1(CtrlWBOUT_4, CtrlWBOUT_5, ReadData_of_Mem, MemOUT_5, ALUOUT_4, ALUOUT_5, WriteRegister_4, WriteRegister_5, clk); ///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// // Select Data to WriteData for regfile mux2x32to32 mux2x32to32_2(ALUOUT_5,

//DataIn0 MemOUT_5, //DataIn1 //STAGE 5 CtrlWBOUT_5[0], //Sel WriteData); //DataOut //-------------------------------------------------------------------------------------------------------------------------//END--STAGE--------------------------------------------------------------------------------------------------------Endmodule

4. Kt lun
+B x l MIPS Pipelined CPU c pht trin t nhu cu to ra b x l c kh nng x l d liu nhanh thay th cho b x l Mips Single-Cycle (vi tc x l kh chm). +Vi thit k trn b x l MIPS Pipelined CPU c tc x l nhanh hn nhiu ln so vi b x l Mips SingleCycle nhng b li ta phi gii quyt vn xung t d liu, sai d liu sau khi x l do vic nng cao hn na tc x l theo phng php Pipelined rt kh c th thc hin c. +Hin ti y l phng php thit k cho ta tc x l ti u hn v kh nng thc hin to ra sn phm c hiu qu hn.

Code:
`timescale 1 ps / 100 fs // The verilog file containing your register file must // be named "MIPS.v". `include "MIPS.v" module MIPStimulus(); parameter ClockDelay = 14000; reg reset, clk; wire [31:0] PC; wire [31:0] instruction integer i; MIPS MIPS1(clk, reset); initial begin $dumpfile("single.vcd"); $dumpvars(-1, MIPS1); end

initial clk = 0; initial reset=0; always #(ClockDelay/2) clk = ~clk; initial begin #(ClockDelay/2) reset=1; // Try to write the value 0xA0 into register 0. // Register 0 should begin and remain at the value of 0. end endmodule