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ASIC Verification
Hello Everyone, This is My first blog ever. I have created this blog to discuss about various topics in the field of ASIC. You'll find lot of useful information about verification. Keep visiting this site for more updates.

Showing posts with label FIFO. Show all posts

T UES DA Y , A PR IL 8, 2008

Depth of the Asynchronous FIFO

One of the most interesting architectural decision in the design project is how to calculate the depth of a FIFO. FIFO is an intermediate logic where the data would be buffered or stored . Smaller FIFO depth can cause overflow scenario and cause a data loss. For worst case scenario, difference in the data rate between write and read should be maximum. Hence, for write operation maximum data rate should be considered and for read operation minimum data rate should be considered for calculating the depth of the FIFO. Any Asynchronous FIFO has a write frequency and a read frequency. Assume that the write frequency (Fw) is faster than read frequency (Fr). Scenario 1: Fw = 1/Tw and Fr = 1/Tr where Tw and Tr are Time periods of write and read respectively. Now Transmitter (Write side) wants to transmit "W" words of data. But FIFO can take only "N" words of data in Tw time. Time taken to transmit "W" words is (Tw/N) * W But Receiver can read "P" words in Tr time interval. So the Receiver can read ((Tw/N)*W*P)/Tr words in (Tw/N) * W time. Subtract the the data read from FIFO to the data written into the FIFO. Here the data written into the FIFO is "W" words Data read from the FIFO is ((Tw/N)*W*P)/Tr words. FIFO size = W-((Tw/N)*W*P)/Tr Where W = Maximum number of bytes that the transmitter can send N = Number of bytes that the transmitter sends per Tw Tw = Transmitter's time period P = Number of bytes that receiver receives per Tr
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About Me Suresh I did my Master of Engineering in College of Engineering, Guindy Anna University in 2001-2002 and currently working as a ASIC Verification Engineer. View my complete profile

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ASIC Verification: FIFO

Tr = Receiver's time period Scenario 2: Consider the case of a FIFO where the 'Fw' is 100 MHz and 50 words are written into the FIFO in 100 clocks while the 'Fr' is 50 MHz and one word is read out every clock. In the worst case scenario, the 50 words are written into the FIFO as a burst in 500 ns. In the same time duration, the read side can read only 25 words out of the FIFO. The remaining 25 words are read out of the FIFO in the 50 idle write clocks. So the depth of the FIFO should be at least 28. (Three clock cycles are for synchronizer latency).

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Posted by Suresh at 11:23:00 AM Labels: FIFO

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ASIC Verification: FIFO

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