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MOS Transistors as Switches

G (gate) D (drain) S (source) nMOS transistor: Closed (conducting) when Gate = 1 (VDD) Open (non-conducting) when Gate = 0 (ground, 0V)

G S D

pMOS transistor: Closed (conducting) when Gate = 0 (ground, 0V) Open (non-conducting) when Gate = 1 (VDD)

For nMOS switch, source is typically tied to ground and is used to pull-down signals: Out when Gate = 1, Out = 0, (OV) G S when Gate = 0, Out = Z (high impedance)

For pMOS switch, source is typically tied to VDD, used to pull signals up: S G Out Note: The MOS transistor is a symmetric device. This means that the drain and source terminals are interchangeable. For a conducting nMOS transistor, VDS > 0V; for the pMOS transistor, VDS < 0V (or VSD > 0V).

when Gate = 0, Out = 1 (VDD) when Gate = 1, Out = Z (high impedance)

The CMOS Inverter


Truth Table VDD I 0 1 I Out I Out Out 1 0

GND

Rin

Note: Ideally there is no static power dissipation. When "I" is fully is high or fully low, no current path between VDD and GND exists (the output is usually tied to the gate of another MOS transistor which has a very high input impedance).

Power is dissipated as "I" transistions from 01 and 10 and a momentory current path exists between Vdd and GND. Power is also dissipated in the charging and discharging of gate capacitances.

Parallel Connection of Switches


Y Y = 0, if A or B = 1 A B A+B

Y = 1 if A or B = 0 A B A+B Y

Series Connection of Switches


Y A Y = 0, if A and B = 1

A B

Y = 1, if A and B = 0

B Y

A B

NAND Gate Design


p-type transistor tree will provide "1" values of logic function n-type transistor tree will provide "0" values of logic function

Truth Table (NAND): B AB 00 01 10 11 1 1 1 0

A 0 1

0 1 1

1 1 0

K-map (NAND): NAND circuit example: Vdd

Ptree = A + B Ntree = A B Y B A B Y

NOR Gate Design


p-type transistor tree will provide "1" values of logic function n-type transistor tree will provide "0" values of logic function

Truth Table: B AB 00 01 10 11 1 0 0 0

A 0 1

0 1 0

1 0 0

K-map: NOR circuit example: Vdd A Ptree = A B Ntree = A + B B Y A B

What logic gate is this?


Vdd A Y = 1 when A B Y = 0 when A + B B Y

Answer: AND function, but poor design! Why? nMOS switches cannot pass a logic "1" without a threshold voltage (VT) drop. VDD G VDD D S VDD - VT where VT = 0.7V to 1.0V (i.e., threshold voltage will vary) output voltage = 4.3V to 4.0V, a weak "1"

The nMOS transistor will stop conducting if VGS < VT. Let VT = 0.7V,
G 5V S D 0V 5V D ? 0V ?

As source goes from 0V 5V, VGS goes from 5V 0V. When VS > 4.3V, then VGS < VT, so switch stops conducting. VD left at 5V VT = 5V 0.7V = 4.3V or VDD VT.

What about nMOS in series? 5V 5V 5V 5V

0V 5V

0V 4.3V

0V 4.3V

0V 4.3V

0V (VDDVT) 5V - 0.7V 4.3V

Only one threshold voltage drop across series of nMOS transistors

For pMOS transistor, VT is negative. pMOS transistor will conduct if |VGS| > |VTp| (VSG > |VTp|), or VGS < VTp
0V G 5V S D

VTp = 0.7V VGS = 0V 5V = 5V

conducting

VGS < VTp 5V < 0.7V

or

|VGS| > |VTp| 5V > 0.7V

How will pMOS pass a "0"?


G 0V 5V 0V S D 5V ? D ?

When |VGS| < |VTp|, stop conducting

So when |VGS| < |0.7V|, VD will go from 5V 0.7V, a weak "0"

How are both a strong "1" and a strong "0" passed? Transmission gate pass transistor configuration

When I = 1, A B B = strong 1, if A = 1; B = strong 0, if A = 0

When I = 0, non-conducting

About that AND Gate...


Vdd A No!!! Poorly designed AND (circuit designer fired) B Y

Instead use this,


A B Y Vdd

Y B

More Complex Gates


F = AB + CD
Ntree will provide 0's, Ptree will provide 1's

0's of function F is F, F = AB + CD = AB + CD

nMOS transistors need high true inputs, so it is desirable for all input variables to be high true, just as above. Y

AB + CD
B D

Likewise, a Ptree will provide 1's.

F = AB + CD,
Apply DeMorgan's Theorem:

need a form involving A, B, C, D

F = AB CD = ( A + B) (C + D)
Implementation

D Y

Can also use K-maps:

AB 1 1 1 0 1 0 0 0 0 1 1 0 1

F = AB + CD
CD

1 0 1

For Ntree, minimize 0's; for Ptree, minimize 1's AB 0 0 CD 0 0 0 0 0 Ntree = AB + CD

AB 1 1 CD 1 1 1 1

Ptree = AC + AD + BC + BD = A (C + D) + B (C + D) = (A + B) (C + D)

Introduction to Static Load Inverters


1) resistor load R O I Switching point of inverter depends on ratio of R to RON (on resistance of nMOS device. When I = 1, inverter dissipates static power.

VOH = 5V, VOL close to 0V, depends on ratio R/RON Note: output can swing from almost 0V to 5V (VDD)

2) D S I

Again, static power dissipation occurs when I = 1.

Load is enhancement-mode nMOS device. Note: output swings from nearly 0V to (VDD VTn) Using a transistor as a load tends to require much less silicon area than a resistor. VOH = VDD VTn, VOL can be close to 0V, depending on ratio of RON of two enhancement devices

Depletion-mode nMOS

nMOS device with VTn < 0V (negative threshold voltage). Device is always conducting if VGS > 0V. 3) D VGS = 0V always S I O Load device is always on, looks like a load resistor. Dissipates static power when I = 1 VOH = 5V; VOL nearly 0V, depending on ratio of RON,dep to RON,enh. Depletion-mode devices were used before it was economical to put both p-type and n-type devices on the same die. 4) pMOS device as static load

S D I

Here also the load device is always on (conducting). O

Dissipates static power when I = 1.

VOH = 5V; VOL nearly 0V, depending on ratio of RON,p to RON,n

Basic MOS Device Equations


Drain Gate Bulk (or substrate for nMOS device in n-well technology) Source

The nMOS device is a four terminal device: Gate, Drain, Source, Bulk. Bulk (substrate) terminal is normally ignored at schematic level, usually tied to ground for the nMOS case. In analog applications, however, the bulk terminal may not be ignored. Gate controls channel formation for conduction between Drain and Source. Drain at higher potential than Source Source usually tied to GND to act as pull-down (nMOS). Three regions of operations first-order (ideal) equations: Cutoff region ID = 0A Linear region VGS VTn (nMOS threshold voltage)

V ID = (VGS VTn )VDS DS 2


2

0 < VDS < VGS VTn

Note: ID is linear with respect to (VGS VTn) only when VDS Saturation region ID =

2 is small.

(VGS VTn )2 0 < VGS VTn < VDS 2

Device parameters: = transistor gain factor, dependent on process parameters and device geometry (Kn)

process dependent, constant = W tox L under control of the designer


As W/L increases, effective RON of device decreases = surface mobility of the carriers in the channel = permittivity of the gate insulator tox = thickness of the gate insulator See Figure 2.5, 2.8 concerning , , and tox SPICE represents by a factor given by K' = Cox = t = KP ox

So, ID =

K' W (VGS VTn )2 ; 2 L

saturation region

VI characteristic
ID VDS VGS

boundary between linear & saturation regions (dashed line)

|VGS - V T| = |V DS | V GS5

ID

V GS4 SATURATION V GS3 V GS2 V GS1

CUTOFF

V DS

Things to note: In the "linear" region, ID becomes less and less linear with VGS as VDS becomes large. This is because the VDS

2 term in the linear region grows large.

Higher VGS values increase channel conductance allowing for higher values of ID for a given VDS.

LINEAR

GS

*MOSFET Characteristics Vds 1 0 DC 10 Vgs 2 0 DC -.723 Vdummy 3 0 DC 0 M1 1 2 3 3 Mfet .MODEL Mfet NMOS(KP=3686U VTO=2.30 LAMBDA=0.137) .DC Vds 0 10 .2 Vgs 2.5 5 .5 .probe .end

What do W and L physically look like?


nMOSFET layout:
Source n+ diffusion Gate (polysilicon) Drain n+ diffusion

In digital logic, typically will draw all transistors with the minimum gate length and vary the width. Larger W larger transconductance (more current flow for given gate voltage), higher gate capacitance During fabrication process, the actual width and length of the channel can be reduced by diffusion from the bulk, source, and drain into the device channel. SPICE has some MOSFET model parameters to account for this effect, LD and WD, where the actual the actual length and width is calculated as Leffective = Ldrawn - 2 LD Weffective = Wdrawn - 2 WD If LD, WD parameters not specified in the model, then SPICE assumes they are 0.

Ideal Inverter

Vout VDD switching point

VDD 2

Vin

Actual Inverter Characteristics, some definitions


Vout (V) VOH

VOL VIL VIH Vth

Vin (V)

VIL represents the maximum logic 0 (LOW) input voltage that will guarantee a logic 1 (HIGH) at the output VIH represents the minimum logic 1 (HIGH) input voltage that will guarantee a logic 0 (LOW) at the output

Noise Margin
Illustration of Noise Margin:
Vin VDD Input logic 1 NMH VIH Vout VDD VOH Output logic 1

VIL Input logic 0 0V NML VOL 0V Output logic 0

Calculate noise margin using

NML = VIL - VOL

NMH = VOH - VIH

How do we determine VIL, VOL, VOH, and VIH? We must exam the inverter's transfer characteristic.

CMOS Inverter Regions of Operation


A
5 Vout 4 1.2 10 -4

E
1.5 10 -4

V out (V)

9 10 -5

I DD (A)

C
2 IDD 1 3 10 -5 6 10 -5

0 0 1 2 3 4 5

0 10 0

V in (V)

Region A: 0 Vin < VTn

pMOS nonsaturated; nMOS cutoff

nMOS is cutoff because Vin < VTn Why is the pMOS device in the linear region? Linear region VSDp < VSGp - |VTp| (5 5)V < (5 0)V |0.7|V [for VDD = 5V and VTp = 0.7V] 0V < 4.3V Note that the pMOS device can be in linear region even if IDp 0A!

Region B: VTn Vin < Vth Why is nMOS saturated?


pMOS nonsaturated, nMOS saturated

Is VDSn > VGSn - VTn?

Because (VDSn = Vout) > Vth and (VGSn = Vin) < Vth , then VDSn > VGSn - VTn Vout > Vin - VTn

[B-1]

Why is pMOS in linear region? It started out in linear and will remain in linear as long as VSDp < VSGp - |VTp| (VDD - Vout) < (VDD - Vin) - |VTp| Vin < Vout - |VTp| [B-2]

Vout in the above expression (Eqn. [B-2]) is decreasing towards Vth and Vin is increasing towards Vth. When Eqn. [B-2] no longer holds, then the pMOS device will become saturated. For the pMOS device, then regions A B C correspond to linear linear saturated, respectively.

How can you predict the output voltage for region B? The nMOS is saturated, so IDn =

n (Vin VTn ) 2 = n (VGSn VTn ) 2 2 2

The pMOS is linear, so IDp = IDp =

p 2 p 2

(2(V (2(V

SGp

| VTp |)VSDp (VSDp ) 2 ) Vin | VTp |)(VDD Vout ) (VDD Vout ) 2 )

DD

Can solve for Vout since IDn = IDp VDD


S

IDp
D D

IDn
S

GND

Equivalent circuit for region B IDn

Vout

Region C: Vin = Vth


pMOS saturated, nMOS saturated

In order for nMOS to be saturated, need VDSn > VGSn VTn Vout > Vin VTn In order for pMOS to be saturated, need VSDp > VSGp |VTp| VDD Vout > VDD Vin |VTp| Vout < Vin + |VTp| So Vout in region C, Vin VTn < Vout < Vin + |VTp| The CMOS inverter has very high gain in region C so small changes in Vin produce large changes in Vout. No closed form equation for Vout. Somewhere in this region, Vout = Vin, which is the switching point for this gate. Equivalent circuit for region C:

VDD IDp Vout IDn

What is Vin in region C? In region C, both devices in saturation so

IDp =

p 2

(VDD Vin | VTp |) 2 n (Vin VTn ) 2 2

IDn =

So, using IDn = IDp, Vin can be solved for (more on this later....) Region D: Vth < Vin VDD |VTp|
pMOS saturated, nMOS linear

Hence,

IDp =

p 2

(VDD Vin | VTp |) 2

IDn =

n 2 2(Vin VTn )Vout Vout 2

Again, since IDp = IDn, we can solve for Vout: Vout2 2(Vin VTn)Vout +

p n

(VDD Vin | VTp |) 2 = 0

using

x=

b b 2 4ac 2a

and, recognizing from above,


a = 1, b = 2(Vin VTn), c =

p n

(VDD Vin | VTp |) 2

we get

Vout = (Vin VTn)

(Vin VTn ) 2

p n

(Vin VDD | VTp |) 2 .

IDp Equivalent circuit for region D Vout

Region E: Vin > VDD |VTp|


pMOS is cutoff, nMOS is linear mode

Since VSGp = VDD Vin (< |VTp|),


Vout 0V

due to nMOS acting as pull-down while pMOS in cutoff.

CMOS Inverter Transfer Characteristic


A
5 Vout 4 1.2 10 -4

E
1.5 10 -4

V out (V)

9 10 -5

I DD (A)

2 IDD 1

6 10 -5

3 10 -5

0 0 1 2 3 4 5

0 10 0

Analysis:
VOH:

V in (V)

Vin < VTn, the nMOS transistor is in cutoff while the pMOS transistor is turned-on (inversion layer established). The result is VOH VDD.

VOL:

(VDD Vin) < |VTp|, the pMOS is in cutoff while the nMOS is on and providing a conduction channel to ground. Hence, VOL 0V.

VIL:

Input low voltage, here the nMOS transistor is saturated and the pMOS is nonsaturated. Equating the currents provides

n (VIL VTn ) 2 = p (2(VDD VIL | VTp |)(VDD Vout ) (VDD Vout ) 2 ) . 2 2

VIL:

(continued) Since two unknowns exist, Vin = VIL and Vout, a second equation is needed. Use the unity-gain condition to obtain this second equation,

dVout (I Dn /Vin ) (I Dp /Vin ) = = 1, dVin (I Dp /Vout )


provides VIL 1 +

n = 2Vout + p

n VTn VDD |VTp|. p

Now the two equations needed to solve for VIL and Vout exist.
VIH:

Input high voltage, here the nMOS is nonsaturated and the pMOS is saturated. Equating the drain currents yields

p n 2 2(VIH VTn )Vout Vout = (VDD VIH | VTp |) 2 , 2 2 the first of two equations needed to solve two unknowns, Vin = VIH and Vout. Use the unity-gain condition to get the second,

dVout (I Dp /Vin ) (I Dn /Vin ) = = 1. dVin (I Dn /Vout )


This provides VIH 1 +

p = 2Vout + VTn + p (VDD | VTp |) , n n

the second equation needed to solve for the two unknowns.

Vth:

At the CMOS inverter's switching point, or inverter threshold, Vth = Vin = Vout and both the pMOS and nMOS transistors are saturated. Again, equating the drain currents,

n (Vth VTn ) 2 = p (VDD Vth | VTp |) 2 2 2


is obtained which can be easily solved to provide Vth,

VTn +
Vth =

p n

(VDD | VTp |)

p 1 + n

Note: switching point of gate (Vth) is

VDD 2

-if-

n = 1 and VTn = VTp. p

So, switching point of inverter is function of the ratio of the nMOS/pMOS gains and the threshold voltages of the nMOS, pMOS transistors.

n/p Ratio
The n (gain of nMOS) / p (gain of pMOS) ratio determines the switching point of the CMOS inverter.

Vout (V)
5

Equal pull-up/pull-down "strength" Strong pull-up

3 n = 10 p 2 n = 1 p n = 0.1 p

2 VDD 2

Vin (V)

Strong pull-down

Switching point = VDD/2 if n/p = 1 and VTn = |VTp|

Recall that W =t L . ox If we assume that the nMOS and pMOS transistors have equal W/L ratios, then n Wn tox Ln n electron mobility n = = = hole mobility . p p Wp p tox Lp In silicon, the ratio n/p is usually between 2 to 3. This means, that if then in order for Ln = Lp, Wp must be 2 to 3 times Wn n = p .

Vout
5

if

Wp Wn = because n > 1 Lp Ln p

0 0 1 2 VDD 2 3 4 5

Vin

Calculate the switching point of a static load inverter as function of n/p: In region C, already know nMOS device is saturated from previous analysis.

VDD

Vout Vin

For pMOS to be saturated need: VSDp > VSGp |VTp| VDD Vout > VDD 0V |VTp| Vout < |VTp| Not true!!! (If Vout in region C is about
VDD

and

VDD 2

>

2 |VTp| (typically this is true))

pMOS must be in linear region

Then

I Dn = n (VGSn VTn ) 2 = n (Vin VTn ) 2 2 2 I Dp = I Dp = p p

and

(2(VDD | VTp |)(VDD Vout ) (VDD Vout )2 ) 2

(2(V 2

SGp | VTp

|)VSDp VSDp

Equate IDn = IDp and solve for Vout.


Vout = | VTp | + (VDD | VTp |) 2 n (Vin VTn ) 2 p Can also solve for n/p,
2 2 n (VDD | VTp |) (Vout | VTp |) = p (Vin VTn ) 2

Consider again
2 2 n (VDD | VTp |) (Vout | VTp |) = p (Vin VTn ) 2

for the pseudo-nMOS inverter.


VDD 2

Let |VTp| = VTn = 0.2VDD and Vin = Vout =

. Then, for VDD = 5V,

n 6.1 !!! p
Note that this is very different result from the CMOS inverter case! If VDD = 3.3V, but the value of VTn = |VTp| is unchanged (i.e., 1V in the above example), then

n 11.5 p

for a switching point equal to

VDD 2

The n/p ratio depends on the absolute value of VDD! This means that the operation of the pseudo-nMOS inverter will NOT scale with VDD (for a given CMOS technology). For the CMOS inverter, the n/p ratio for a switching point of VDD/2 is independent of VDD so its operation will scale with supply voltage. This is a another big advantage of CMOS technology. Not unusual for static CMOS circuits to operate over a very large range of power supply voltages, i.e., 2.0V to 6.0V is common.

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