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G (gate) D (drain) S (source) nMOS transistor: Closed (conducting) when Gate = 1 (VDD) Open (non-conducting) when Gate = 0 (ground, 0V)
G S D
pMOS transistor: Closed (conducting) when Gate = 0 (ground, 0V) Open (non-conducting) when Gate = 1 (VDD)
For nMOS switch, source is typically tied to ground and is used to pull-down signals: Out when Gate = 1, Out = 0, (OV) G S when Gate = 0, Out = Z (high impedance)
For pMOS switch, source is typically tied to VDD, used to pull signals up: S G Out Note: The MOS transistor is a symmetric device. This means that the drain and source terminals are interchangeable. For a conducting nMOS transistor, VDS > 0V; for the pMOS transistor, VDS < 0V (or VSD > 0V).
GND
Rin
Note: Ideally there is no static power dissipation. When "I" is fully is high or fully low, no current path between VDD and GND exists (the output is usually tied to the gate of another MOS transistor which has a very high input impedance).
Power is dissipated as "I" transistions from 01 and 10 and a momentory current path exists between Vdd and GND. Power is also dissipated in the charging and discharging of gate capacitances.
Y = 1 if A or B = 0 A B A+B Y
A B
Y = 1, if A and B = 0
B Y
A B
A 0 1
0 1 1
1 1 0
Ptree = A + B Ntree = A B Y B A B Y
Truth Table: B AB 00 01 10 11 1 0 0 0
A 0 1
0 1 0
1 0 0
Answer: AND function, but poor design! Why? nMOS switches cannot pass a logic "1" without a threshold voltage (VT) drop. VDD G VDD D S VDD - VT where VT = 0.7V to 1.0V (i.e., threshold voltage will vary) output voltage = 4.3V to 4.0V, a weak "1"
The nMOS transistor will stop conducting if VGS < VT. Let VT = 0.7V,
G 5V S D 0V 5V D ? 0V ?
As source goes from 0V 5V, VGS goes from 5V 0V. When VS > 4.3V, then VGS < VT, so switch stops conducting. VD left at 5V VT = 5V 0.7V = 4.3V or VDD VT.
0V 5V
0V 4.3V
0V 4.3V
0V 4.3V
For pMOS transistor, VT is negative. pMOS transistor will conduct if |VGS| > |VTp| (VSG > |VTp|), or VGS < VTp
0V G 5V S D
conducting
or
How are both a strong "1" and a strong "0" passed? Transmission gate pass transistor configuration
When I = 0, non-conducting
Y B
0's of function F is F, F = AB + CD = AB + CD
nMOS transistors need high true inputs, so it is desirable for all input variables to be high true, just as above. Y
AB + CD
B D
F = AB + CD,
Apply DeMorgan's Theorem:
F = AB CD = ( A + B) (C + D)
Implementation
D Y
AB 1 1 1 0 1 0 0 0 0 1 1 0 1
F = AB + CD
CD
1 0 1
AB 1 1 CD 1 1 1 1
Ptree = AC + AD + BC + BD = A (C + D) + B (C + D) = (A + B) (C + D)
VOH = 5V, VOL close to 0V, depends on ratio R/RON Note: output can swing from almost 0V to 5V (VDD)
2) D S I
Load is enhancement-mode nMOS device. Note: output swings from nearly 0V to (VDD VTn) Using a transistor as a load tends to require much less silicon area than a resistor. VOH = VDD VTn, VOL can be close to 0V, depending on ratio of RON of two enhancement devices
Depletion-mode nMOS
nMOS device with VTn < 0V (negative threshold voltage). Device is always conducting if VGS > 0V. 3) D VGS = 0V always S I O Load device is always on, looks like a load resistor. Dissipates static power when I = 1 VOH = 5V; VOL nearly 0V, depending on ratio of RON,dep to RON,enh. Depletion-mode devices were used before it was economical to put both p-type and n-type devices on the same die. 4) pMOS device as static load
S D I
The nMOS device is a four terminal device: Gate, Drain, Source, Bulk. Bulk (substrate) terminal is normally ignored at schematic level, usually tied to ground for the nMOS case. In analog applications, however, the bulk terminal may not be ignored. Gate controls channel formation for conduction between Drain and Source. Drain at higher potential than Source Source usually tied to GND to act as pull-down (nMOS). Three regions of operations first-order (ideal) equations: Cutoff region ID = 0A Linear region VGS VTn (nMOS threshold voltage)
Note: ID is linear with respect to (VGS VTn) only when VDS Saturation region ID =
2 is small.
Device parameters: = transistor gain factor, dependent on process parameters and device geometry (Kn)
So, ID =
saturation region
VI characteristic
ID VDS VGS
|VGS - V T| = |V DS | V GS5
ID
CUTOFF
V DS
Things to note: In the "linear" region, ID becomes less and less linear with VGS as VDS becomes large. This is because the VDS
Higher VGS values increase channel conductance allowing for higher values of ID for a given VDS.
LINEAR
GS
*MOSFET Characteristics Vds 1 0 DC 10 Vgs 2 0 DC -.723 Vdummy 3 0 DC 0 M1 1 2 3 3 Mfet .MODEL Mfet NMOS(KP=3686U VTO=2.30 LAMBDA=0.137) .DC Vds 0 10 .2 Vgs 2.5 5 .5 .probe .end
In digital logic, typically will draw all transistors with the minimum gate length and vary the width. Larger W larger transconductance (more current flow for given gate voltage), higher gate capacitance During fabrication process, the actual width and length of the channel can be reduced by diffusion from the bulk, source, and drain into the device channel. SPICE has some MOSFET model parameters to account for this effect, LD and WD, where the actual the actual length and width is calculated as Leffective = Ldrawn - 2 LD Weffective = Wdrawn - 2 WD If LD, WD parameters not specified in the model, then SPICE assumes they are 0.
Ideal Inverter
VDD 2
Vin
Vin (V)
VIL represents the maximum logic 0 (LOW) input voltage that will guarantee a logic 1 (HIGH) at the output VIH represents the minimum logic 1 (HIGH) input voltage that will guarantee a logic 0 (LOW) at the output
Noise Margin
Illustration of Noise Margin:
Vin VDD Input logic 1 NMH VIH Vout VDD VOH Output logic 1
How do we determine VIL, VOL, VOH, and VIH? We must exam the inverter's transfer characteristic.
E
1.5 10 -4
V out (V)
9 10 -5
I DD (A)
C
2 IDD 1 3 10 -5 6 10 -5
0 0 1 2 3 4 5
0 10 0
V in (V)
nMOS is cutoff because Vin < VTn Why is the pMOS device in the linear region? Linear region VSDp < VSGp - |VTp| (5 5)V < (5 0)V |0.7|V [for VDD = 5V and VTp = 0.7V] 0V < 4.3V Note that the pMOS device can be in linear region even if IDp 0A!
Because (VDSn = Vout) > Vth and (VGSn = Vin) < Vth , then VDSn > VGSn - VTn Vout > Vin - VTn
[B-1]
Why is pMOS in linear region? It started out in linear and will remain in linear as long as VSDp < VSGp - |VTp| (VDD - Vout) < (VDD - Vin) - |VTp| Vin < Vout - |VTp| [B-2]
Vout in the above expression (Eqn. [B-2]) is decreasing towards Vth and Vin is increasing towards Vth. When Eqn. [B-2] no longer holds, then the pMOS device will become saturated. For the pMOS device, then regions A B C correspond to linear linear saturated, respectively.
How can you predict the output voltage for region B? The nMOS is saturated, so IDn =
p 2 p 2
(2(V (2(V
SGp
DD
IDp
D D
IDn
S
GND
Vout
In order for nMOS to be saturated, need VDSn > VGSn VTn Vout > Vin VTn In order for pMOS to be saturated, need VSDp > VSGp |VTp| VDD Vout > VDD Vin |VTp| Vout < Vin + |VTp| So Vout in region C, Vin VTn < Vout < Vin + |VTp| The CMOS inverter has very high gain in region C so small changes in Vin produce large changes in Vout. No closed form equation for Vout. Somewhere in this region, Vout = Vin, which is the switching point for this gate. Equivalent circuit for region C:
IDp =
p 2
IDn =
So, using IDn = IDp, Vin can be solved for (more on this later....) Region D: Vth < Vin VDD |VTp|
pMOS saturated, nMOS linear
Hence,
IDp =
p 2
IDn =
Again, since IDp = IDn, we can solve for Vout: Vout2 2(Vin VTn)Vout +
p n
using
x=
b b 2 4ac 2a
p n
we get
(Vin VTn ) 2
p n
E
1.5 10 -4
V out (V)
9 10 -5
I DD (A)
2 IDD 1
6 10 -5
3 10 -5
0 0 1 2 3 4 5
0 10 0
Analysis:
VOH:
V in (V)
Vin < VTn, the nMOS transistor is in cutoff while the pMOS transistor is turned-on (inversion layer established). The result is VOH VDD.
VOL:
(VDD Vin) < |VTp|, the pMOS is in cutoff while the nMOS is on and providing a conduction channel to ground. Hence, VOL 0V.
VIL:
Input low voltage, here the nMOS transistor is saturated and the pMOS is nonsaturated. Equating the currents provides
VIL:
(continued) Since two unknowns exist, Vin = VIL and Vout, a second equation is needed. Use the unity-gain condition to obtain this second equation,
n = 2Vout + p
Now the two equations needed to solve for VIL and Vout exist.
VIH:
Input high voltage, here the nMOS is nonsaturated and the pMOS is saturated. Equating the drain currents yields
p n 2 2(VIH VTn )Vout Vout = (VDD VIH | VTp |) 2 , 2 2 the first of two equations needed to solve two unknowns, Vin = VIH and Vout. Use the unity-gain condition to get the second,
Vth:
At the CMOS inverter's switching point, or inverter threshold, Vth = Vin = Vout and both the pMOS and nMOS transistors are saturated. Again, equating the drain currents,
VTn +
Vth =
p n
(VDD | VTp |)
p 1 + n
VDD 2
-if-
So, switching point of inverter is function of the ratio of the nMOS/pMOS gains and the threshold voltages of the nMOS, pMOS transistors.
n/p Ratio
The n (gain of nMOS) / p (gain of pMOS) ratio determines the switching point of the CMOS inverter.
Vout (V)
5
3 n = 10 p 2 n = 1 p n = 0.1 p
2 VDD 2
Vin (V)
Strong pull-down
Recall that W =t L . ox If we assume that the nMOS and pMOS transistors have equal W/L ratios, then n Wn tox Ln n electron mobility n = = = hole mobility . p p Wp p tox Lp In silicon, the ratio n/p is usually between 2 to 3. This means, that if then in order for Ln = Lp, Wp must be 2 to 3 times Wn n = p .
Vout
5
if
Wp Wn = because n > 1 Lp Ln p
0 0 1 2 VDD 2 3 4 5
Vin
Calculate the switching point of a static load inverter as function of n/p: In region C, already know nMOS device is saturated from previous analysis.
VDD
Vout Vin
For pMOS to be saturated need: VSDp > VSGp |VTp| VDD Vout > VDD 0V |VTp| Vout < |VTp| Not true!!! (If Vout in region C is about
VDD
and
VDD 2
>
Then
and
(2(V 2
SGp | VTp
|)VSDp VSDp
Consider again
2 2 n (VDD | VTp |) (Vout | VTp |) = p (Vin VTn ) 2
n 6.1 !!! p
Note that this is very different result from the CMOS inverter case! If VDD = 3.3V, but the value of VTn = |VTp| is unchanged (i.e., 1V in the above example), then
n 11.5 p
VDD 2
The n/p ratio depends on the absolute value of VDD! This means that the operation of the pseudo-nMOS inverter will NOT scale with VDD (for a given CMOS technology). For the CMOS inverter, the n/p ratio for a switching point of VDD/2 is independent of VDD so its operation will scale with supply voltage. This is a another big advantage of CMOS technology. Not unusual for static CMOS circuits to operate over a very large range of power supply voltages, i.e., 2.0V to 6.0V is common.