Cu 1: U NHC IM CA NGN NG VHDL -VHDL l ngn ng m t phn cng c pht trin dng cho chng trnh VHSIC (Very

High Speed Intergrated Circuit) ca b quc phng M. -VHDL c pht trin nh mt ngn ng c lp khng gn vi bt k mt phng php thit k,b m phng hay cng ngh phn cng no.Ngi thit k c th t do la chn cng ngh,phng php thit k trong khi vn s dng mt ngn ng duy nht. -VHDL c mt s u im hn hn cc ngn ng m t phn cng khc l: Tnh cng cng:VHDL khng thuc s hu ca bt k c nhn hay t chc no.Do ,VHDL c h tr ca nhiu nh sn xut thit b cng nh nhiu nh cung cp cng c thit k m phng h thng Kh nng h tr nhiu cng ngh v pp thit k:VHDL cho php thit k bng nhiu PP nh PP thit k t trn xung, hay t di ln da vo cc th vin c sn =>VHDL c th phc v tt cho nhiu mc ch thit k # c lp vi cng ngh: VHDL hon ton c lp vi cng ngh ch to phn cng. N cho php ngi thit k khng cn quan tm n cng ngh phn cng khi thit k h thng, nh th khi c mt cng ngh ch to phn cng mi ra i n c th c p dng ngay cho cc h thng thit k. Kh nng m t m rng:VHDL cho php m t hot ng ca phn cng t mc h thng s (hp en) cho n mc cng.VHDL c kh nng m t hot ng ca h thng trn nhiu mc nhng ch s dng mt c php cht ch thng nht cho mi mc. Kh nng trao i kt qu:1 m hnh VHDL c th chy trn mi b m phng p ng c tiu chun VHDL v cc kt qu m t h thng c th c trao i gia cc nh thit k s dng cng c thit k khc nhau Kh nng h tr thit k mc ln v kh nng s dng li cc thit k:c th s dng thit k mt h thng ln vi s tham gia ca mt nhm nhiu ngi.Bn trong ngn ng VHDL c nhiu tnh nng h tr vic qun l,th nghim v chia s thit k.VHDL cng cho php dng li cc phn c sn.

Cu 2: CC CU TRC C BN CA NGN NG VHDL Cc thnh phn chnh xy dng trong ngn ng VHDL c chia ra thnh nm nhm c bn nh sau: - Entity - Architecture - Package - Configuration. - Library. Entity: Trong mt h thng s, thng thng c thit k theo mt s xp chng cc Modul, m mi Modul ny tng ng vi mt thc th thit k (c gi l Entity) trong VHDL. Mi mt Entity bao gm hai phn: - Khai bo thc th ( Entity). - Thn kin trc ( Architecture Bodies ) Mt khai bo Entity c dng m t giao tip bn ngoi ca mt phn t (component), n bao gm cc khai bo cc cng u vo, cc cng u ra ca phn t . Phn thn ca kin trc c dng m t s thc hin bn trong ca thc th . Packages: Cc ng gi ch ra thng tin dng chung, m cc thng tin ny c s dng bi mt vi Entity no . Configuration: nh cu hnh, n cho php gn kt cc th hin ca phn t cn dng no ca mt thit k no c dng mt cu trc v a cc th hin ny vo trong cp Entity v Architecture. N cho php ngi thit k c th th nghim thay i cc s thc thi khc nhau trong mt thit k. Mi mt thit k dng VHDL bao gm mt vi n v th vin, m mt trong cc th vin ny c dch sn v ct trong mt th vin thit k.

Cu 3: Khai bo Entity phn khai bo Entity ch a ra mt ci nhn pha bn ngoi ca mt phn t m khng cung cp thng tin v s thc hin ca phn t ntn. C php khai bo ca mt Entity nh sau: Entity tn_thc_th is [cc_lnh_khai_bo_generic] [cc_lut_ti_cng] {cc thnh phn biu thc thc th} end [tn_thc_th]; Trog :[] : Du ngoc vung ch ra cc tham s c th la chn; {} : Khai bo mt hoc nhiu cc i tng a. Khai bo Generic: Dng khai bo cc hng m chng c th c dng iu khin cu trc v s hot ng ca Entity. C php ca khai bo ny nh sau: generic ( tn_hng : kiu_con [:=gi tr khi to] {;tn_hng: kiu_con [:=gi tr khi to]}); b. Khai bo cng ( Port ): c dng khai bo cc cng vo, ra ca Entity. C php ca khai bo ny nh sau: Port ( tn_cng : [mode] kiu_con [:=gi tr khi to] {; port_name:[mode] kiu_con [:=gi tr khi to]}); c. Entity_declarative_item: c dng khai bo cc hng, kiu d liu, hoc tn hiu m n c th c s dng trong khi thc hin ca mt Entity. d. V d :V d v khai bo Entity: Entity FULL_ADDER is port ( A, B, CIN : in BIT; SUM, COUT : out BIT ); End FULL_ADDER ;

Cu 4: Cc kiu kin trc (Architecture) Mt kin trc a ra kt cu bn trong ca mt Entity. M t hot ng ca kin trc th phi khai bo cho cc thc th . Mt kin trc xc nh chc nng ca mt Entity. c php : architecture tn_kin_trc of tn_thc_th is { phn khai bo ca kin trc }; Begin {cc kt cu thc hin ng thi}; end [ tn_kin_trc ]; *Kin trc theo kiu hnh vi hot ng (Behavioral) Kin trc ny ch ra cc hot ng m mt h thng ring bit no phi thc hin trong mt chng trnh N din t cc qa trnh hot ng, nhng ko cung cp chi tit thc thi thit k. Thnh phn ch yu ca vic din t theo kiu hnh vi trong VHDL l process. *Kin trc theo kiu hot ng ca cc lung d liu (Dataflow) -Mt kin trc kiu lung d liu ch ra mt HT di dng m t ng thi ca cc lung iu khin v dch chuyn ca d liu.V chng l nhng pht biu ng thi nn th t ca nhng pht biu l ko quan trng. -Nhng pht biu gn t.hiu ng thi c thc thi bt c khi no c s kin xy ra trong t.hiu c s dng trong biu thc. -V d: Architecture behavioral of mux_21 is Begin If (s=0) then y<=A; Else y<=B; End if; End Behavioral; *Kin trc theo kiu cu trc (Structure) Mt kin trc kiu cu trc ch ra s thc thi cu trc theo dng s dng cc khai bo phn t v cc th hin ca phn t . V d :cu trc ca mt b cng FULL_ADDER.

architecture STRUCTURE of FULL_ADDER is component HALF_ADDER port (L1, L2 : in BIT; CARRY, SUM : out BIT); end component; component OR_GATE port (L1, L2 : in BIT; O: out BIT); end component; begin HA1: HALF_ADDER port map (A,B,N1,N2); HA2: HALF_ADDER port map (N2,CIN,N3,SUM); OR1 : OR_GATE port map (N1, N3,COUT); end STRUCTURE;

Cu 5: Cc ng gi (Packages) Mc ch chnh ca Package l tp hp cc phn t c th b chia s bi hai hay nhiu n v thit k .N c cha cc kiu d liu, cc hng, cc chng trnh con c th dng chung gia cc thit k. Mt Package c hai phn chnh: a.Phn khai bo Package Mt khai bo Package c dng ct gi hng lot cc khai bo dng chung. Cc khai bo ny c th nhp vo cc n v thit k khc bi vic s dng mt mnh use. V d: package EXAMPLE_PACK is type SUMMER is ( MAY, JUN, JUL, AUG, SEP); component D_FLIP_FLOP port (D, CK:in BIT; Q, QBAR: out BIT) end component; constant PIN2PIN_DELAY:TIME:=125ns; function IN2BIT_VEC(INT_VALUE:INTEGER) return BIT_VECTOR; end EXAMPLE_PACK; b.Phn khai bo thn Package S khc bit gia khai bo Package v thn Package c cng mc ch nh khai bo ca mt Entity v phn thn kin trc Architecture ca chng. C php khai bo ca Package nh sau: package tn_gi is {mc_khai_bo_ca _gi } end [tn_gi]; package body tn_gi is { mc_khai_bo_ca _gi }

end [tn_gi] Mt thn package c dng lu cc nh ngha ca mt hm v th tc, m cc hm v th tc ny chng c khai bo trong phn khai bo package tng ng. V vy phn thn package lun c kt hp vi phn khai bo ca chng, hn na mt phn khai bo package lun c t nht mt phn thn package kt hp vi chng. V d: package EX_PKG is subtype INT8 is integer range 0 to 255; constant zero : INT8:=0; procedure Incrementer (variable Count : inout INT8); end EX_PKG; package body EX_PKG is procedure Incrementer (variable Data : inout INT8) is begin if (Count >= MAX ) then Count:=ZERO; else Count:= Count +1; end if; end Incrementer; end EX_PKG;

Cu 6: nh cu hnh (Configurations) Mi mt Entity bao gm nhiu kin trc khc nhau. Trong qu trnh thit k, ngi thit k c th mun th nghim vi cc s bin i khc nhau ca thit k bng vic chn la cc kiu kin trc khc nhau. Configuration c th c s dng cung cp mt s thay th nhanh cc th hin ca cc phn t (Component) trong mt thit k dng cu trc. C php khai bo ca Configuration ny nh sau: Configuration tn_cu_hnh of tn_thc_th is {phn khai bo cu hnh} For c_ im_khi {use_cluse} {mc _cu_hnh } end for; v d: configuration FADD_CONFIG of FULL_ADDER is For STRUCTURE for HA1, HA2 : HALF_ADDER use entity burcin.HALF_ADDER(structure); for OR1: OR_GATE use Entity burcin.OR_GATE; end for; end FADD_CONFIG;

Cu 7: Cc th vin thit k Kt qu ca vic bin dch VHDL l chng c ct gi bn trong cc th vin dng cho bc m phng tip theo. Mt th vin thit k c th cha cc n v th vin nh sau: - Cc ng gi (PACKAGES) - Cc thc th Entity - Cc kiu kin trc Architectures - Cc php nh cu hnh Configurations. VHDL khng h tr cc th vin theo th bc. C php khai bo tn th vin nh sau: Library tn_th_vin : [path/directory_name]; Bn c th truy cp cc n v c bin dch t mt th vin VHDL ti ba mc nh sau: Tn_th_vin.tn_gi.tn_phn_t V d. Package my_pkg is constant delay: time:=10ns; end my_pkg;

Cu 8: CC I TNG D LIU Mt i tng d liu gi mt gi tr ca mt kiu nht nh. Trong VHDL c ba lp i tng d liu : 1. Cc hng (Constants) Mt hng n l mt tng m n c khi to ch ra mt gtr c nh v n ko b thay i. N c khai bo trong cc ng gi, cc Entity, cc kin trc, cc chng trnh con, cc khi, v trong pht biu ca cc qu trnh processes. C php khai bo chng nh sau: Constant tn_hng {,tn_hng}: kiu [:= gi_tr]; V d: constant YES : BOOLEAN:= TRUE; 2. Cc bin (Variables) Cc bin c dng lu d liu tm thi, chng ch c php khai bo trong pht biu Process hoc cc chng trnh con. C php khai bo chng nh sau: variable tn_bin {,tn_bin}: kiu [:= gi_tr]; V d: variable X,Y : BIT; 3. Cc kiu tn hiu (Signals) Tn hiu c dng kt ni cc Entity ca thit k li vi nhau v trao i cc gi tr bin i trong pht biu process. Chng c th c xem nh cc dy dn hay cc bus ni trong mch thc t. Vi cc tn hiu c khai bo trong cc package th tn hiu ny c gi l tn hiu ton cc (cc thit k c th s dng chng ), cc tn hiu c khai bo trong Entity l tn hiu ton cc trong mt Entity, tn hiu c khai bo trong mt kin trc, n l tn hiu dng chung trong mt kin trc . C php ca chng c dng nh sau: Signal tn_tn_hiu {, tn_tn_hiu }: kiu [:=gi_tr]; V d: signal BEEP : BIT:= '0';

Cu 9: CC KIU D LIU 1. Cc kiu lit k (ENUMERATION) Mt kiu lit k c ch ra bi vic lit k cc gi tr cho php ca kiu C php: Type tn_nh_danh is (gi_tr {,gi_tr_lit_k }); Trong : -gi_tr: l tn nh danh hoc l 1 k t V d: type mu is (,xanh,vng,tm); 2. Kiu nguyn Kiu nguyn l cc kiu s nguyn, chng c dng cho cc php tnh, cc ch s, cc iu khin s vng lp. C di t - 2,147,483,647 n + 2,147,483,647. C php ca chng c khai bo nh sau: type tn_kiu is range - 2,147,483,647 to + 2, 147, 483,647; V d: type INTEGER is range - 2,147,483,647 to + 2, 147, 483,647; 3. Cc kiu d liu tin nh ngha trong VHDL IEEE nh ngha hai gi d liu STANDARD v TEXTIO trong th vin STD. Mi mt gi d liu ny c cha mt lot cc kiu v cc php tnh chun . Cc kiu d liu c nh ngha trong gi STANDARD: - BOOLEAN: Mt kiu lit k vi hai gi tr True v False - BIT: Mt kiu lit k vi hai gi tr '0' v '1' - CHARACTER: Kiu lit k ca cc m ASCII. - INTEGER: c dng miu t cc s m v dng. Di hot ng ca chng c n nh t - 2,147,438,647 n 2,147,438,647. - NATURE: Cc kiu con ca kiu nguyn c dg miu t cc s kiu t nhin - POSITIVE: Cc kiu con ca kiu nguyn c dng miu t cc s dng. - BIT_VECTOR: c dng miu t mt mng cc gi tr kiu BIT. - STRING: Mt mng cc k t, mt gt kiu chui c i km bi du nhy kp. - REAL: c dg m t cc kiu s thc,di hng t -1.0E+38 => +1.0E+38. - Kiu thi gian vt l: M t cc gi tr thi gian c dng trong m phng. VD: Type BOOLEAN is ( fase, true); Type BIT is ( '0', '1' );

4. Kiu mng Kiu mng l kiu ca nhm cc phn t c cng kiu ging nhau. C 2 kiu mg: Kiu mg b gn kiu l kiu m cc ch s mg ca chg c ngha tng minh. C php: type tn_kiu_mng is array (kiu _ph) of kiu_phn_t; Kiu mng khng b gn kiu l kiu m ch s mng ca chng khng b ch ra, nhng cc kiu ch s ca chng phi c ch ra. C php: Type tn_mng is array (tn_kiu_ch_s range <>) of kiu_phn_t; V d: type A1 is array ( 0 to 31) of INTEGER; 5. Kiu Record Kiu record l mt nhm c nhiu hn mt phn t c cc kiu khc nhau. Phn t ca Record bao gm cc phn t ca bt c kiu no, n c th l cc kiu mng hoc kiu Record. V d: type DATE_TYPE is ( SUN, MON, TUE , WED , THR , FRI , SAT) ; type HOLIDAY is record DAY : INTEGER range 1 to 31; DATE : DATE_TYPE; end record ; 6. Cc kiu STD_LOGIC to mu cc ng tn hiu c nhiu hn hai gi tr ( '0' , '1' ), VHDL nh ngha chn khong trong gi chun. Chn gi tr bao gm: type STD_LOGIC is ( 'U' -- khng khi to gi tr 'X' -- Khng xc nh '0' -- Kiu mc thp '1' -- Kiu mc cao 'Z' -- Kiu tr khng cao 'W' -- Khng xc nh mc yu

'L' -- Mc thp yu 'H' -- Mc cao yu '_' -- Khng quan tm n gi tr .); VHDL cung cp mt kiu khc gi l STD_LOGIC_VECTOR. s dng cc nh ngha v cc hm trong gi chun logic, cc pht biu cn c phi khai bo nh km theo chng trnh. Library IEEE; USE IEEE.STD_LOGIC_1164.all; 7. Cc kiu d liu c du v khng du Cc kiu d liu c du v khng du chng c ch ra trong cc gi chun NUMERIC_BIT v NUMERIC_STD. Vic nh ngha ca cc kiu d liu c ch ra nh sau: type signed is array (NATURAL range <>) of BIT/STD_LOGIC; 8. Cc kiu con VHDL cung cp cc cc kiu con m cc kiu con ny chng c nh ngha trong cc nh cc tp ph trong mt kiu khc. Kiu NATURAL v kiu POSITIVE l mt kiu ph hay kiu con ca kiu nguyn v chng c th c dng vi bt k mt hm nguyn no. V d: subtype INT4 is INTEGER range 0 to 15;

Cu 10: CC TON T 1. Cc ton t Logical Cc ton hng cn phi l cng kiu v cng di. V d: signal A,B : BIT_VECTOR (6 downto 0); signal C,D,E,F,G: BIT; D <= (E xor F) and (C xor G); 2. Cc ton t quan h Cc ton t quan h cho ta kt qu c kiu Boolean, cc ton hng cn phi c cng kiu v cng di. V d: signal A,B : BIT_VECTOR (6 downto 0); signal C: BOOLEAN; C <= B <= A; 3. Cc ton t cng Cc ton t cng bao gm "+", "-" , v "&", trong ton t "&" l ton t kt ni chui v cc i tng l mng cc thanh ghi. Vi s c du v khng du c th c dng vi cc s nguyn v cc kiu BIT_VECTOR. V d: signal X: INTEGER range 0 to15; signal Y,Z : UNSIGED (3 downto 0); Z <= X + Y + Z; 4.Cc ton t dch bit: -cha 2 ton hng,ton hng trc ton t l ton hng cha d liu c dch bit,cn ton hng sau tn t l ton hng cha s bit c dch. -v d: y<= 12 srl 2;

Cu 11: CC KIU TON HNG 1. Kiu ch Cc kiu ch c th chia ra thnh hai nhm chnh : -Kiu v hng: Kiu ch k t , Kiu BIT, Kiu chun STD_LOGIC , Kiu Boolean, Kiu s thc, Kiu nguyn, Kiu thi gian , -Kiu mng: Kiu chui, Kiu BIT_VECTOR, STD_LOGIC_VECTOR 1.1. Kiu ch k t Kiu ch k t ch ra mt gi tr bng vic s dng mt k t n v km theo mt du nhy n. Kiu ch k t cn phi phn bit ch thng v ch hoa. Kiu ch k t c th c dng nh ngha bt c kiu no trong cc ng gi chun v gi tr mc nh ca chng l Null. Kiu ch k t khng phi l kiu bit k t. 1.2. Kiu chui Mt kiu chui k t thc cht l mt mng cc k t. Mt chui cc k t c nh ngha trong mt du nhy kp . V d: "A" , " hold time error ", " x " .... 1.3. Kiu BIT Kiu bit l kiu m t hai gi tr ri rc bng vic s dng cc ch k t '0' v '1'. i khi cc kiu Bit ny c dng to ra kiu ch bit mt cch tng minh dng phn bit chng vi cc kiu k t. V d: '1' , ' 0 ' , bit('1') 1.4. Kiu BIT_VECTOR Kiu bit_vector l mt mng cc bit m chng c t trong du nhy kp . V d: "01001111000" , x"00FFF0" , b"100010101" , o"277756"... 1.5. Kiu ch trong ng gi chun STD_LOGIC Kiu ch logic chun l mt trong 9 gi tr c nh ngha trong ng gi chun v c a ra di dng cc ch in hoa v t trong du ngoc n. V d: ' X ' , ' 0 ' , ' 1 ' , ' Z ' , ' W ' , ' L ' , ' H ' , ' _ '

1.6. Kiu ch STD_LOGIC_VECTOR Mt kiu ch STD_LOGIC_VECTOR thc cht l mt mng bao gm cc phn t ca kiu std_logic v c t trong du ngoc kp. V d: " 10_1Z" , " UUUUU " , signed("1011 ")..... 1.7. Kiu Boolean Kiu Boolean c dng m t hai gi tr ri rc, l kiu true v false. V d: true , false , True , TRUE, FALSE ... 1.8. Kiu s thc Kiu s thc l kiu c dng din t cc s thc nm trong khong t -1.0E+38 n +1.0E+38. 1 kiu s hc c th l kiu dg hoc m nhg chg phi c du chm thp phn. V d: -1.0 , -1.0E+10. 1.9. Kiu nguyn Mt kiu nguyn c dng din t cc s nguyn nm trong khong t -2,147,438,647 n + 2,147,438,647. V d: +1,862; - 257 ; + 123; - 456 ; 16 # 00FF #. 2. Cc kiu nh danh Kiu nh danh l mt ci tn do ngi dng nh ngha. V d: xyz = xYZ = XYZ = XyZ 3. Kiu INDEX Kiu INDEX c s dng ch ra mt phn t no trong mt mng. C php s dng ca khai bo ny nh sau: array_name (expression) V d: variable DATA_ARRAY : memory; 4. Kiu Slice v ALIAS Mt khai bo Slice c dng ch ra mt s phn t ca mng. Alias c dng to ra mt tn mi cho tt c cc phn t hoc mt s phn t no nm trong mt mng. V d: variable A1: BIT_VECTOR ( 7 downto 0 ); A2: = A1(5 downto 2) ; Alias A3: BIT_VECTOR (0 to 3) is A1(7 downto 4);

5. Kiu thuc tnh ATTRIBUTE Ly cc thuc tnh cu mt bin hay mt tn hiu ca mt kiu cho trc no v tr v mt kiu gi tr. cc kiu thuc tnh thng dng trong ngn ng VHDL: - Left: Tr v ch s ca phn t bn tri cng ca mt kiu d liu. - Right: Tr v ch s ca phn t bn phi cng ca mt kiu d liu. - High: Tr v ch s ca phn t cao nht ca mt kiu d liu. - Low: Tr v ch s ca phn t thp nht ca mt kiu d liu. - Range: c dng ly v di ca ch s. - Reverse_range: Dng xc nh di ch s ngc li. - Length: Tr v s phn t ca kiu BIT_VECTOR. - Event: M t s thay i gi tr ca tn hiu ti thi im m phng. V d: variable A1 : BIT_VECTOR ( 10 downto 0 ); A1' right -- Tr v gi tr 0. 6. Kiu tp hp Kiu tp hp c th c dng gn gi tr cho mt i tng thuc kiu mng hoc kiu Record trong khi khi to khai bo hoc trong cc pht biu gn. V d: type color_list ( red, orange, blue, white ); 7. Biu thc gn kiu Biu thc gn kiu c dng ch ra kiu ca mt ton hng no . C php ca chng nh sau: tn_kiu' ( biu_thc); V d: type mu is (,vng,xanh,trng); 8. Php chuyn i kiu tn hiu Php chuyn i kiu cho php chuyn i cc kiu c kiu d liu gn ging nhau. V d: signal X : STD_LOGIC_VECTOR ( 3 downto 0 ); signal Y : STD_ULOGIC_VECTOR ( 3 downto 0 ); Y <= STD_ULOGIC_VECTOR (X);

Cu 12: CC PHT BIU TUN T Pht biu tun t ch ra s thc hin tng bc ca mt qtrnh Cc pht biu nm trong mt pht biu qtrnh (pht biu Process) c gi l pht biu tun t. 1. Pht biu gn bin Dng thay th gi tr hin thi ca bin vi mt gi tr mi, gi tr mi ny c ch ra bi mt biu thc. Bin c th c khai bo v s dng bn trong mt pht biu qu trnh hay cn c gi l pht biu Process. C php: bin:=biu_thc; Cc bin c khai bo trg mt Process khng th chuyn gtr ra ngoi Process. Bin c to ti thi im sn sinh v duy tr gi tr ca n trong sut thi gian chy chng trnh. VD: process(A,B) variable x,y : INTEGER; begin x:=2; y:=x+A+B; end process; 2. Pht biu gn tn hiu s thay th gi tr hin ti ca tn hiu vi mt gi tr mi bi vic s dng mt biu thc. Tn hiu v kt qu ca biu thc cn c cng mt kiu d liu. Tn_hiu_ch <= [ Transport] biu_thc [after biu_thc_thi_gian] c th xut hin bn trong hoc bn ngoi mt qu trnh V d php gn tn hiu trong mt Process (Vi A,B,C,D l cc tn hiu): process (C,D) variable Av, Bv, Ev : integer :=0; begin Av := 2; Bv := Av + C; Av := D + 1; Ev := Av * 2; A <= Av; B <= Bv; C <= Cv; end process;

Khi mt pht biu gn tn hiu c thc thi, gi tr ca biu thc c tnh ton v gi tr ny c chun b gn cho tn hiu sau khi delay, C hai kiu Delay c cung cp chun b cho vic thc thi tn hiu: - Tr do truyn dn. - Tr do qun tnh 3. Pht biu IF Mt pht biu if c dng chn la nhng pht biu tun t cho vic thc thi da trn gi tr ca biu thc iu kin. Biu thc iu kin y c th l mt biu thc bt k m gi tr ca chng phi l kiu lun l. C php: If <biu_thc_iu_kin1> then {<cc lnh tun t >}; elsif <biu_thc_iu_kin2> then {<cc lnh tun t >}; else {<cc lnh tun t >}; VD: if sum <=100 then SUM:=SUM+10; end if; 4. Pht biu CASE C php: case <biu_thc> is When <la_chn> => {<cu_lnh_tun_t>;} {When <la_chn> => {<cu_lnh_tun_t>;} } {When others => {<cu_lnh_tun_t>;} } End case; Pht biu case la chn mt trong nhng nhnh cho vic thc thi da trn gi tr ca biu thc. Gi tr biu thc phi thuc kiu ri rc hoc kiu mng mt chiu. Tt c cc gi tr c th c ca biu thc phi c th hin trong pht biu case ng mt ln. Mi mt chn la phi c cng kiu vi kiu ca biu thc. V d : Case (s) is When 0 => y<=A;

When 1 => y<=B; When others => y<=x; end case; . 7. Pht biu Loop Mt pht biu lp c s dng lp li mt lot cc cu lnh tun t. C php: [<Nhn>:] [<s__lp>] loop { <lnh_tun_t >;} end loop [Nhn]; trong : -<nhn>: nhn ca vng lp thng c dng xc nh nhng vng lp lng nhau,trong mi vng lp c kt thc bi t kho end loop. -<s lp>: trong VHDL c 1 s lp vi s lp khc nhau nh for, while,vng lp ko cha s lp,... V d: for N in 1 to 10 loop S:= N* 2; End loop;

Cu 13: Cc pht biu gn ng thi: 1.Pht biu gn tn hiu c iu khin: -chnh l 1 pht biu ng thi & c ch gn nht nh. Tuy nhin php gn ny c th c nhiu hn 1 biu thc cho 1 ch. ngoi tr biu thc cui cng,cc biu thc cn li phi c 1 iu kin chc chn,cc iu kin ny c nh gi theo th t. nu 1 iu kin c nh gi l true th biu thc tng ng c s dng,ngc li cc biu thc cn li c s dng.ch 1 biu thc c s dng ti 1 thi im. -C php: <tn hiu ch> <= {<biu thc> [after <biu thc thi gian>] When <iu kin> else} <biu thc> [after <biu thc thi gian>] V d: Architecture logic of 4_1 is Begin Y<=x0 when s=00 else X1 when s=01 else X2 when s=10 else X3 when s=11 else null; end logic; 2.pht biu gn tn hiu c la chn: -C th ch c 1 ch gn & cng c th c 1 biu thc with -Gi tr ny c kim tra trc ging nh pht biu case thng thng. N s qun l bt k s thay i no xut hin ti cc tn hiu c chn la. C php: with <biu thc la chn> select <tn hiu ch> <= {<biu thc> [after <biu thc thi gian>] When <gi tr la chn>} <biu thc> [after <biu thc thi gian>] When <gi tr la chn>; -V d: with (s) select Y<= x0 when 00; X1 when 01; X2 when 10; X3 when 11; null when others;

Cu 14: M HNH CU TRC *M hnh cu trc l g?ly v d? -M hnh cu trc bao gm 1 tp cc cng c th giao tip vi cc thnh phn khc. -Thit k trong VHDL & thit k c th bc l thit k a ra cc khai bo ca cc thnh phn & cc pht biu th hin thnh phn . -Mt n v c s din t hnh vi hot ng chnh l pht biu process. Cn n v c s din t theo cu trc chnh l cc pht biu th hin ca cc n v thnh phn, c 2 loi ny u c th c mt trong thn ca 1 kin trc (architecture). - v d: M t b cng 4 bit s dng b cng full_adder:

1. Cc khai bo thnh phn Trong m t thit k, mi pht biu khai bo thnh phn phi tng ng vi mt Entity. Cc pht biu khai bo thnh phn phi ging vi cc pht biu c ch ra trong Entity . component tn_thnh_phn [ port ( local_port_declaration ) ] end component ; 2. Cc th hin ca component Mt component c nh ngha trong mt architecture c th c th hin thng qua vic s dng cc pht biu th hin ca chng. Khi th hin ch c php th hin phn giao tip ca component ,cc tn hiu bn trong chng khng c th hin. instantiation_label : component _name port map ( [ local_port_name =>] expression

{ [local_port_name =>] expression} ); 3. Cc pht biu Generate Pht biu generate l mt pht biu ng thi v n c nh ngha trong phn architecture. N c dng m t cc cu trc ging nhau, hay ti to li cc cu trc khc ging nh bn gc. instantiation _label : generation_scheme generate {concurrent_statement} end generate [instantiation _label]; C hai loi lc generation : Lc for v lc if. a. S dng lc for: Lc for c dng din t cu trc thng thng, n c dng khai bo mt tham s generate v mt di ri rc ca lc for .Cc gi tr tham s ca generate c th c c nhng khng c gn hay chuyn ra ngoi pht biu generate. V d: Gi s ta c b cng 4 bit m trong bao gm bn b cng Full_adder

Hnh 3.13: B cng 4 bit. architecture IMP of FULL_ADDER4 is signal X, Y, Z : STD_LOGIC_VECTOR ( 3 downto 0 ) ; signal Cout : STD_LOGIC ; signal TMP : STD_LOGIC_VECTOR ( 4 downto 0 ) ; component FULL_ADDER

port ( A, B, Cin : in STD_LOGIC ; Sum, Cout : out STD_LOGIC ); end component ; begin TMP (0) <= ' 0 '; G : for I in 0 to 3 generate FA: FULL_ADDER port map ( X (I), Y(I), TMP (I), Z (I),TMP ( I+1 )); end generate ; Cout <= TMP (4); end IMP; b, S dng lc if s dng lc if i vi 1t s cu trc c dng khng theo qui lut chun no. Xt vi v d trn: Chng trnh c vit nh sau: architecture IMP of FULL_ADDER4 is signal X, Y, Z : STD_LOGIC_VECTOR ( 3 downto 0 ) ; signal Cout : STD_LOGIC ; signal TMP : STD_LOGIC_VECTOR ( 4 downto 1) ; component FULL_ADDER port ( A, B, Cin : in STD_LOGIC ; Sum, Cout : out STD_LOGIC ); end component ; component HALF_ADDER port ( A, B : in STD_LOGIC ; Sum, Cout : out STD_LOGIC ); end component ; begin G0 : for I in 0 to 3 generate G1: if I = 0 generate HA: HALF_ADDER port map ( X (I), Y(I), Z (I), TMP ( I+1 )); end generate ; G2: if I >= 1 and I <= 3 generate

FA: FULL_ADDER port map ( X (I), Y(I), TMP (I), Z (I),TMP ( I+1 )); end generate ; end generate ; Cout <= TMP ( 4 ); end IMP; 4. Cc thng s ca vic nh cu hnh Trong mt Entity c th c mt vi cu trc, v vy cc chi tit ca vic nh cu hnh cho php ngi thit k chn cc Entity v kin trc ca n. C php khai bo ca chng nh sau: for instantiation _list : tn_thnh_phn use Entity tn_th_vin. tn_thc_th [( tn_kin_trc)] ; Nu ch c mt kin trc architecture th tn architecture c th b qua