S.No 1. 2. 3.

VLSI Titles A Novel Technique for Improving Hardware Trojan Detection and Reducing Trojan Activation Time. High-Speed Low-Power Viterbi Decoder Design for TCM Decoders. Area-Efficient VLSI Implementation for Parallel Linear-Phase FIR Digital Filters of Odd Length Based on Fast FIR Algorithm. A novel all-digital multichannel multimode RF Transmitter using delta-sigma modulation Highly scalable parallel arithmetic coding on Multi-core processors using LDPC codes Pipelined parallel FFT architectures via Folding transformation Robust secure scan design against scan-based Differential cryptanalysis Synchronous FPGA-based highresolution Implementations of digital pulse-width modulators The LUT-SR family of uniform random Number generators for FPGA architectures VLSI architecture of arithmetic coder Used in SPIHT PAPR reduction by linear coding techniques for MIMO-OFDM systems performance Improvement: simulation and hardware implementation Extending the effective throughput of NOCS with Distributed shared-buffer

Simulation Modelsim & Xilinx Modelsim & Xilinx Modelsim & Xilinx Modelsim & Xilinx Modelsim & Xilinx Modelsim & Xilinx Modelsim & Xilinx Modelsim & Xilinx Modelsim & Xilinx Modelsim & Xilinx Modelsim & Xilinx Modelsim &

Implementation Spartan 3E Spartan 3E Spartan 3E

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Spartan 3E Spartan 3E Spartan 3E Spartan 3E Spartan 3E Spartan 3E Spartan 3E Spartan 3E

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Spartan 3E

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routers FPGA implementation of the multilayer neural Network for the speed estimation of the Two-mass drive system BIST using genetic algorithm for error detection and correction Low-Power and Area-Efficient Carry Select Adder Optimizing Floating Point Units in Hybrid FPGAs CIARP: Crypto Instruction-Aware RISC Processor Bayesian Equalization for LDPC Channel Decoding Low-Complexity Soft Decoding of Huffman Codes and Iterative Joint Source Channel Decoding. Human Gait Modeling Using a Genetic Fuzzy Finite State Machine. Accurate Analysis of Double-Weight Optical CDMA With Power Control Optimal Channel and Relay Assignment in OFDM-Based MultiRelay Multi-Pair Two-Way Communication Networks Precision-Aware Self-Quantizing Hardware Architectures for the Discrete Wavelet Transform Parallel Searching-Based Sphere Detector for MIMO Downlink OFDM Systems

Xilinx Modelsim & Xilinx Modelsim & Xilinx Modelsim & Xilinx Modelsim & Xilinx Modelsim & Xilinx Modelsim & Xilinx Modelsim & Xilinx Modelsim & Xilinx Modelsim & Xilinx Modelsim & Xilinx Modelsim & Xilinx Modelsim & Xilinx

Spartan 3E

Spartan 3E Spartan 3E Spartan 3E Spartan 3E Spartan 3E Spartan 3E Spartan 3E Spartan 3E Spartan 3E

Spartan 3E Spartan 3E

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Nonlinear Trellis Codes for BinaryInput Binary-Output Multiple-Access Channels with Single-User Decoding Low-Complexity Iterative Channel Estimation for Turbo Receivers A Low Complexity MMSE for OFDM Systems over FrequencySelective Fading Channels A Row-Parallel 88 2-D DCT Architecture Using Algebraic IntegerBased Exact Computation A Fast Cryptography Pipelined Hardware developed in FPGA with VHDL A High Performance Video Transform Engine by Using SpaceTime Scheduling Strategy Separable Reversible Data Hiding in Encrypted Image FPGA-Based Track Circuit for Railways Using Transmission Encoding Sub W Noise Reduction for CIC Hearing Aids On Modulo 2n 1 Adder Design A Multi-Resolution Fast Filter Bank for Spectrum Sensing in Military Radio Receivers. VLSI Friendly ECG QRS Complex Detector for Body Sensor Networks. Accumulator Based 3-Weight Pattern Generation.

Modelsim & Xilinx Modelsim & Xilinx Modelsim & Xilinx Modelsim & Matlab Modelsim & Xilinx Modelsim & Matlab Modelsim & Xilinx Modelsim & Xilinx Modelsim & Xilinx Modelsim & Xilinx Modelsim & Xilinx Modelsim & Xilinx Modelsim & Xilinx

Spartan 3E Spartan 3E Spartan 3E

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Spartan 3E

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Spartan 3E Spartan 3E Spartan 3E Spartan 3E Spartan 3E Spartan 3E Spartan 3E

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High-Throughput Soft-Output MIMO Detector Based on Path-Preserving Trellis-Search Algorithm. Single Cycle Access Structure for Logic Test. Area and Power-Efficient Architecture for High-Throughput Implementation of Lifting 2-DDWT. VLSI design of memory efficient, high-speed baseline MQ coder for JPEG 2000.

Modelsim & Xilinx Modelsim & Xilinx Modelsim & Matlab Modelsim & Matlab

Spartan 3E Spartan 3E
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