Basic Semiconductor Physics

Introduction Semiconductors

Conductivity in between those of metals and insulators. Conductivity can be varied over orders of magnitude by changes in temperature, optical excitation, and impurity content (doping). Generally found in column IV and neighboring columns of the periodic table. Elemental semiconductors: Si, Ge. Compound semiconductors: Binary : GaAs, AlAs, GaP, etc. (III-V). ZnS, ZnTe, CdSe (IIVI). SiC, SiGe (IV compounds).

Ternary : GaAsP. Quaternary : InGaAsP. Si widely used for rectifiers, transistors, and ICs. III-V compounds widely used in optoelectronic and high-speed applications.

Applications

Integrated circuits (ICs) SSI, MSI, LSI, and VLSI. Fluorescent materials used in TV screens II-VI (ZnS). Light detectors InSb, CdSe, PbTe, HgCdTe. Infrared and nuclear radiation detectors Si and Ge. Gunn diode (microwave device) GaAs, InP. Semiconductor LEDs GaAs, GaP. Semiconductor LASERs GaAs, AlGaAs.

Energy Gap

Distinguishing feature among metals, insulators, and semiconductors. Determines the absorption/emission spectra, the leakage current, and the intrinsic conductivity. Unique value for each semiconductor (e.g. 1.12 eV for Si, 1.42 eV for GaAs) function of temperature.

Impurities

Can be added in precisely controlled amounts. Can change the electronic and optical properties. Used to vary conductivity over wide ranges. Can even change conduction process from conduction by negative charge carriers to positive charge carriers and vice versa. Controlled addition of impurities doping.

Crystal Lattices

Semiconductor properties can be strongly affected by crystal structure.

Types of Solids

Basically, there are three types of solids: crystalline, amorphous, and polycrystalline.

Crystalline Solids

Atoms making up the solid arranged in a periodic fashion, repeated throughout. Have long-range order. Used for IC fabrication.

Amorphous Solids

Have no periodic structure at all. Interatomic distance and bond angles are almost the same as in the crystalline material of the same substance, however, a long-range order is missing. Said to have short-range order. a-Si (alloy of amorphous Si with and other similar amorphous alloys) has found important applications in photovoltaic technology and in large-area ICs used in flat displays, printers, copiers, scanners, and imagers.

Polycrystalline Solids

Composed of many small regions of single-crystal material of irregular size, separated by grain boundaries.

Lattice

3-D periodic arrangement of atoms in a crystal. Defined by primitive basis vectors , which are three independent shortest vectors connecting lattice sites. The coordinates of all points belonging to the crystal lattice are given by vectors , where k, l, and m are integers. Properties of the periodic crystal determine the allowed energies of electrons that participate in the conduction process. Thus, the lattice not only determines the mechanical properties of the crystal, but also its electrical properties.

Unit Cell

Representative of the entire crystal and regularly repeated throughout the crystal. The crystal can be analyzed as a whole by investigating a representative volume. Can find: i) the distances between nearest atoms and next nearest atoms, ii) the fraction of the unit cell volume filled by atoms, and iii) the density of the solid (related to the atomic arrangement).

Primitive Cell

Smallest unit cell that can be repeated to form the lattice.

Cubic Lattices

Simplest 3-D lattice, where the unit cell is a cube. Three types: i) simple cubic (sc) (e.g., Ga), ii) body-centered cubic (bcc) (e.g., Na, W), and iii) face-centered cubic (fcc) (e.g., Al, Au). Lattice constant: the length of each side of the cube.

The Diamond Lattice

Two interpenetrating fcc sublattices spaced 1/4th along the body diagonal. When the constituent atoms of the two sublattices are different, then the structure is Zincblende (e.g. GaAs).

Diamond and Zincblende are the two most common crystal structures for cubic semiconductors. Each atom in diamond and zincblende lattice is surrounded by four nearest neighbors. Tetrahedral configuration. By varying the atomic compositions of these two sublattices, one can grow ternary (e.g. ) and quaternary (e.g., ) compounds.

EXAMPLE 1.1: Find the fraction of the unit cell volume filled with hard spheres for a diamond lattice. SOLUTION: Diamond lattice unit cell consists of an fcc lattice along with 4 inside atoms. The corner atoms in an fcc lattice is shared by seven nearest neighbors, thus each contributing 1/8th of a sphere, and the face atoms are shared by one nearest neighbor, thus each contribution of a sphere. Thus, Atoms/cell = 1 (corners) + 3 (faces) + 4 (inside) = 8 Nearest neighbor distance = ( Radius of each sphere = ( )/8 Volume of each sphere = )/4

Maximum fraction of cell filled = Therefore, the unit cell volume filled with hard spheres for a diamond lattice is only 34%, thus, the diamond lattice is relatively loosely packed. Planes and Directions Miller Indices

Found by taking the reciprocal of the intercepts of the plane with the coordinate axes, and converting these to integers. Define a set of parallel planes. (hkl) a particular plane. {hkl} equivalent (hkl) planes. [hkl] a particular direction, perpendicular to the (hkl) plane for cubic crystals. <hkl> equivalent [hkl] directions. Negative intercepts/directions are denoted by placing bars above the integers, e.g. . Three main indices (100), (110), and (111). Atom densities different for different planes different electronic properties.

EXAMPLE 1.2: Show a (643) plane and (643) direction in a cubic lattice. SOLUTION: (643) plane: reciprocals (1/6,1/4,1/3), converting them to smallest set of integers gives (2,3,4); thus, the plane has (x,y,z) intercepts as (2,3,4).

Practice Problems 1.1 Determine the nearest neighbor distance, and the number of the nearest and the next neighbors of sc, bcc, fcc, and diamond lattices with lattice constant a. 1.2 Determine the maximum fractions of the unit cell volume that can be filled by hard spheres in the sc, bcc, and fcc lattices. 1.3 Clearly state the equivalent {100}, {110}, and {111} planes and determine their total numbers in a cubic crystal. 1.4 Show the (211) plane and the [211] direction in a cubic crystal lattice.

1.5 Calculate the densities of Ge (diamond structure, a = 5.66

) and InP (Zincblende structure, a

= 5.87 ). The atomic weights of Ge, In, and P are 72.6, 114.8, and 31 respectively. 1.6 Determine the atom density (in number of atoms/cm2) in (100), (110), and (111) planes of Si (a = 5.43 ).

Energy Bands and Charge Carriers in Semiconductors Bonding Forces and Energy Bands in Solids

Electrons are restricted to sets of discrete energy levels within atoms, with large gaps among them where no energy state is available for the electron to occupy. Electrons in solids also are restricted to certain energies and are not allowed at other energies. Difference in the solid, the electron has a range (or band) of available energies. The discrete energy levels of the isolated atom spread into bands of energies in the solid because i) in the solid, the wave functions of electrons in neighboring atoms overlap, thus, it affects the potential energy term and the boundary conditions in the equation, and different energies are obtained in the solution, and ii) an electron is not necessarily localized at a particular atom. The influence of neighboring atoms on the energy levels of a particular atom can be treated as a small perturbation, giving rise to shifting and splitting of energy states into energy bands.

Bonding Forces in Solids Ionic Bonding

Example: NaCl. Na (Z = 11) gives up its outermost shell electron to Cl (Z=17) atom, thus the crystal is made up of ions with the electronic structures of the inert atoms Ne and Ar. Note: the ions have net electric charges after the electron exchange ion has a net positive charge, having lost an electron, and ion has a net negative charge, having acquired an electron. Thus, an electrostatic attractive force is established, and the balance is reached when this equals the net repulsive force. Note: all the electrons are tightly bound to the atom. Since there are no loosely bound electrons to participate in current flow NaCl is a good insulator.

Metallic Bonding

In metals, the outer shell is filled by no more than three electrons (loosely bound and given up easily) great chemical activity and high electrical conductivity. Outer electron(s) contributed to the crystal as a whole solid made up of ions with closed shells immersed in a sea of free electrons, which are free to move about the crystal under the influence of an electric field. Coulomb attraction force between the ions and the electrons hold the lattice together.

Covalent Bonding

Exhibited by the diamond lattice semiconductors. Each atom surrounded by four nearest neighbors, each having four electrons in the outermost orbit. Each atom shares its valence electrons with its four nearest neighbors. Bonding forces arise from a quantum mechanical interaction between the shared electrons. Both electrons belong to each bond, are indistinguishable, and have opposite spins. No free electrons available at 0 K, however, by thermal or optical excitation, electrons can be excited out of a covalent bond and can participate in current conduction important feature of semiconductors.

Mixed Bonding

Shown by III-V compounds bonding partly ionic and partly covalent. Ionic character of bonding becomes more prominent as the constituent atoms move further away in the periodic table, e.g., II-VI compounds.

Energy Bands

As isolated atoms are brought together to form a solid, the electron wave functions begin to overlap. Various interactions occur, and, at the proper interatomic spacing for the crystal, the forces of attraction and repulsion find a balance. Due to Pauli exclusion principle, the discrete energy levels of individual atoms split into bands belonging to the pair instead of to individual atoms. In a solid, due to large number of atoms, the split energy levels for essentially continuous bands of energy.

Fig.2.1 Splitting of individual energy levels to energy bands as atoms are brought closer together.

Imaginary formation of a diamond crystal from isolated carbon atoms . Each atom has two 1s states, two 2s states, six 2p states, and higher states. For N atoms, the numbers of states are 2N, 2N, and 6N of type 1s, 2s, and 2p respectively. With a reduction in the interatomic spacing, these energy levels split into bands, and the 2s and 2p bands merge into a single band having 8N available states. As the interatomic spacing approaches the equilibrium spacing of diamond crystal,

this band splits into two bands separated by an energy gap , where no allowed energy states for electrons exist forbidden gap. The upper band (called the conduction band) and the lower band (called the valence band) contain 4N states each. The lower 1s band is filled with 2N electrons, however, the 4N electrons residing in the original n = 2 state will now occupy states either in the valence band or in the conduction band. At 0 K, the electrons will occupy the lowest energy states available to them thus, the 4N states in the valence band will be completely filled, and the 4N states in the conduction band will be completely empty.

Metals, Semiconductors, and Insulators

For electrons to move under an applied electric field, there must be states available to them. A completely filled band cannot contribute to current transport; neither can a completely empty band. Thus, semiconductors at 0 K are perfect insulators. With thermal or optical excitation, some of these electrons can be excited from the valence band to the conduction band, and then they can contribute to the current transport process. At temperatures other than 0 K, the magnitude of the band gap separates an insulator from a semiconductor, e.g., at 300 K, (diamond) = 5 eV (insulator), and (Silicon) = 1.12 eV (semiconductor). Number of electrons available for conduction can be increased greatly in semiconductors by reasonable amount of thermal or optical energy. In metals, the bands are either partially filled or they overlap thus, electrons and empty states coexist great electrical conductivity.

Direct and Indirect Semiconductors

In a typical quantitative calculation of band structures, the wave function of a single electron traveling through a perfectly periodic lattice is assumed to be in the form of a plane wave moving in the x-direction (say) with propagation constant k, also called a wave vector. In quantum mechanics, the electron momentum can be given by The space dependent wave function for the electron is where the function of the lattice. (2.1) modulates the wave function according to the periodicity

Allowed values of energy, while plotted as a function of k, gives the E-k diagram. Since the periodicity of most lattices is different in various directions, the E-k diagram is a complex surface, which is to be visualized in three dimensions.

Fig.2.2 Direct and indirect transition of electrons from the conduction band to the valence band: (a) direct - with accompanying photon emission, (b) indirect via defect level.

Direct band gap semiconductor: the minima of the conduction band and the maxima of the valence band occur at the same value of k an electron making the smallest energy transition from the conduction band to the valence band can do so without a change in k (and, the momentum). Indirect band gap semiconductor: the minima of the conduction band and the maxima of the valence band occur for different values of k, thus, the smallest energy transition for an electron requires a change in momentum. Electron falling from conduction band to an empty state in valence band recombination. Recombination probability for direct band gap semiconductors is much higher than that for indirect band gap semiconductors. Direct band gap semiconductors give up the energy released during this transition (= ) in the form of light used for optoelectronic applications (e.g., LEDs and LASERs). Recombination in indirect band gap semiconductors occurs through some defect states within the band gap, and the energy is released in the form of heat given to the lattice.

Variation of Energy Bands with Alloy Composition

The band structures of III-V ternary and quaternary compounds change as their composition is varied. There are three valleys in the conduction band: (at k = 0), L, and X. In GaAs, the valley has the minimum energy (direct with = 1.43 eV) with very few electrons residing in L and X valleys (except for high field excitations). In AlAs, the X valley has minimum energy (indirect with = 2.16 eV).

Fig.2.3 The E-k diagram of (a) GaAs and (b) AlAs, showing the three valleys (L, the conduction band. Charge Carriers in Semiconductors

, and X) in

In a metal, the atoms are imbedded in a "sea" of free electrons, and these electrons can move as a group under the influence of an applied electric field. In semiconductors at 0 K, all states in the valence band are full, and all states in the conduction band are empty. At T > 0 K, electrons get thermally excited from the valence band to the conduction band, and contribute to the conduction process in the conduction band. The empty states left in the valence band can also contribute to current conduction. Also, introduction of impurities has an important effect on the availability of the charge carriers. Considerable flexibility in controlling the electrical properties of semiconductors.

Electrons and Holes

For T> 0 K, there would be some electrons in the otherwise empty conduction band, and some empty states in the otherwise filled valence band. The empty states in the valence band are referred to as holes. If the conduction band electron and the valence band hole are created by thermal excitation of a valence band electron to the conduction band, then they are called electron-hole pair (EHP). After excitation to the conduction band, an electron is surrounded by a large number of empty states, e.g., the equilibrium number of EHPs at 300 K in Si is , whereas the Si atom density is .

Energy Bands and Charge Carriers in Semiconductors

Thus, the electrons in the conduction band are free to move about via the many available empty states.

Corresponding problem of charge transport in the valence band is slightly more complex. Current transport in the valence band can be accounted for by keeping track of the holes themselves. In a filled band, all available energy states are occupied. For every electron moving with a given velocity, there is an equal and opposite electron motion somewhere else in the band. Under an applied electric field, the net current is zero, since for every electron j moving with a velocity , there is a corresponding electron - . In a unit volume, the current density J can be given by moving with a velocity

(filled band) (2.2) where N is the number of

in the band, and q is the electronic charge.

Now, if the electron is removed and a hole is created in the valence band, then the net current density

Thus, the current contribution of the empty state (hole), obtained by removing the jth electron, is equivalent to that of a positively charged particle with velocity . Note that actually this transport is accounted for by the motion of the uncompensated electron having a charge of q and moving with a velocity . Its current contribution (- q)(- ) is equivalent to that of a positively charged particle with velocity + . For simplicity, therefore, the empty states in the valence band are called holes, and they are assigned positive charge and positive mass. The electron energy increases as one moves up the conduction band, and electrons gravitate downward towards the bottom of the conduction band. On the other hand, hole energy increases as one moves down the valence band (since holes have positive charges), and holes gravitate upwards towards the top of the valence band.

Effective Mass

The "wave-particle" motion of electrons in a lattice is not the same as that for a free electron, because of the interaction with the periodic potential of the lattice. To still be able to treat these particles as "free", the rest mass has to be altered to take into account the influence of the lattice. The calculation of effective mass takes into account the shape of the energy bands in three-dimensional k-space, taking appropriate averages over the various energy bands. The effective mass of an electron in a band with a given (E,k) relation is given by (2.4)

EXAMPLE 2.1: Find the dispersion relation for a free electron, and, thus, observe the relation between its rest mass and effective mass. SOLUTION: For a free electron, the electron momentum is . Thus, . Therefore, the dispersion relation, i.e., the E-k relation is parabolic. Hence, . This is a very interesting relation, which states that for a free electron, the rest mass and the effective mass are one and the same, which is due to the parabolic band structure. Most materials have non-parabolic E-k relation, and, thus, they have quite different rest mass and effective mass for electrons. Note: for severely non-parabolic band structures, the effective mass may become a function of energy, however, near the minima of the conduction band and towards the maxima of the valence band, the band structure can be taken to be parabolic, and, thus, an effective mass, which is independent of energy, may be obtained.

Thus, the effective mass is an inverse function of the curvature of the E-k diagram: weak curvature gives large mass, and strong curvature gives small mass. Note that in general, the effective mass is a tensor quantity, however, for parabolic bands, it is a constant. Another interesting feature is that the curvature is positive at the conduction band minima, however, it is negative at the valence band maxima. Thus, the electrons near the top of the valence band have negative effective mass. Valence band electrons with negative charge and negative mass move in an electric field in the same direction as holes with positive charge and positive mass. Thus, the charge transport in the valence band can be fully accounted for by considering hole motion alone. The electron and hole effective masses are denoted by and respectively.

Intrinsic Material

A perfect semiconductor crystal with no impurities or lattice defects. No carriers at 0 K, since the valence band is completely full and the conduction band is completely empty. For T > 0 K, electrons are thermally excited from the valence band to the conduction band (EHP generation). EHP generation takes place due to breaking of covalent bonds required energy = . The excited electron becomes free and leaves behind an empty state (hole). Since these carriers are created in pairs, the electron concentration ( ) is always equal to the hole concentration ( ), and each of these is commonly referred to as the intrinsic carrier concentration ( ). Thus, for intrinsic material n = p = . These carriers are not localized in the lattice; instead they spread out over several lattice spacings, and are given by quantum mechanical probability distributions. Note: ni = f(T).

To maintain a steady-state carrier concentration, the carriers must also recombine at the same rate at which they are generated. Recombination occurs when an electron from the conduction band makes a transition (direct or indirect) to an empty state in the valence band, thus annihilating the pair. At equilibrium, = , where and are the generation and recombination rates respectively, and both of these are temperature dependent. (T) increases with temperature, and a new carrier concentration ni is established, such that the higher recombination rate (T) just balances generation. At any temperature, the rate of recombination is proportional to the equilibrium concentration of electrons and holes, and can be given by (2.5) where is a constant of proportionality (depends on the mechanism by which recombination takes place).

Extrinsic Material

In addition to thermally generated carriers, it is possible to create carriers in the semiconductor by purposely introducing impurities into the crystal doping. Most common technique for varying the conductivity of semiconductors. By doping, the crystal can be made to have predominantly electrons (n-type) or holes (p-type). When a crystal is doped such that the equilibrium concentrations of electrons (n0) and holes (p0) are different from the intrinsic carrier concentration (ni), the material is said to be extrinsic. Doping creates additional levels within the band gap. In Si, column V elements of the periodic table (e.g., P, As, Sb) introduce energy levels very near (typically 0.03-0.06 eV) the conduction band. At 0 K, these levels are filled with electrons, and very little thermal energy (50 K to 100 K) is required for these electrons to get excited to the conduction band. Since these levels donate electrons to the conduction band, they are referred to as the donor levels. Thus, Si doped with donor impurities can have a significant number of electrons in the conduction band even when the temperature is not sufficiently high enough for the intrinsic carriers to dominate, i.e., >> , n-type material, with electrons as majority carriers and holes as minority carriers. In Si, column III elements of the periodic table (e.g., B, Al, Ga, In) introduce energy levels very near (typically 0.03-0.06 eV) the valence band. At 0 K, these levels are empty, and very little thermal energy (50 K to 100 K) is required for electrons in the valence band to get excited to these levels, and leave behind holes in the valence band. Since these levels accept electrons from the valence band, they are referred to as the acceptor levels. Thus, Si doped with acceptor impurities can have a significant number of holes in the valence band even at a very low temperature, i.e., >> , p-type material, with holes as majority carriers and electrons as minority carriers. The extra electron for column V elements is loosely bound and it can be liberated very easily ionization; thus, it is free to participate in current conduction. Similarly, column III elements create holes in the valence band, and they can also participate in current conduction. Rough calculation of the ionization energy can be made based on the Bohr's model for atoms, considering the loosely bound electron orbiting around the tightly bound core electrons. Thus,

(2.6)where

is the relative permittivity of Si.

EXAMPLE 2.2: Calculate the approximate donor binding energy for Si ( r = 11.7, ).

= 1.18

SOLUTION: From Eq.(2.6), we have 1.867 x J = 0.117 eV.

Note: The effective mass used here is an average of the effective mass in different crystallographic directions, and is called the "conductivity effective mass" with values of 1.28 (at 600 K), 1.18 (at 300 K), 1.08 (at 77 K), and 1.026 (at 4.2 K).

In III-V compounds, column VI impurities (e.g., S, Se, Te) occupying column V sites act as donors. Similarly, column II impurities (e.g., Be, Zn, Cd) occupying column III sites act as acceptors. When a column IV material (e.g., Si, Ge) is used to dope III-V compounds, then they may substitute column III elements (and act as donors), or substitute column V elements (and act as acceptors) amphoteric dopants. Doping creates a large change in the electrical conductivity, e.g., with a doping of , the resistivity of Si changes from 2 x -cm to 5 -cm.

Carrier Concentrations

For the calculation of semiconductor electrical properties and analyzing device behavior, it is necessary to know the number of charge carriers/cm3 in the material. The majority carrier concentration in a heavily doped material is obvious, since for each impurity atom, one majority carrier is obtained. However, the minority carrier concentration and the dependence of carrier concentrations on temperature are not obvious. To obtain the carrier concentrations, their distribution over the available energy states is required. These distributions are calculated using statistical methods.

The Fermi Level

Electrons in solids obey Fermi-Dirac (FD) statistics. This statistics accounts for the indistinguishability of the electrons, their wave nature, and the Pauli exclusion principle. The Fermi-Dirac distribution function f(E) of electrons over a range of allowed energy levels at thermal equilibrium can be given by

(2.7)where k is Boltzmann's constant (= 8.62 x

eV/K = 1.38 x

J/K).

This gives the probability that an available energy state at E will be occupied by an electron at an absolute temperature T.

is called the Fermi level and is a measure of the average energy of the electrons in the lattice an extremely important quantity for analysis of device behavior. Note: for (E ) > 3kT (known as Boltzmann approximation), f(E) exp[ - (E)/kT] this is referred to as the Maxwell-Boltzmann (MB) distribution (followed by gas atoms). The probability that an energy state at will be occupied by an electron is 1/2 at all temperatures. At 0 K, the distribution takes a simple rectangular form, with all states below occupied, and all states above empty. At T > 0 K, there is a finite probability of states above to be occupied and states below to be empty. The F-D distribution function is highly symmetric, i.e., the probability f( + ) that a state E above is filled is the same as the probability [1- f( )] that a state E below is empty. This symmetry about EF makes the Fermi level a natural reference point for the calculation of electron and hole concentrations in the semiconductor. Note: f(E) is the probability of occupancy of an available state at energy E, thus, if there is no available state at E (e.g., within the band gap of a semiconductor), there is no possibility of finding an electron there. For intrinsic materials, the Fermi level lies close to the middle of the band gap (the difference between the effective masses of electrons and holes accounts for this small deviation from the mid gap). In n-type material, the electrons in the conduction band outnumber the holes in the valence band, thus, the Fermi level lies closer to the conduction band. Similarly, in p-type material, the holes in the valence band outnumber the electrons in the conduction band, thus, the Fermi level lies closer to the valence band. The probability of occupation f(E) in the conduction band and the probability of vacancy [1- f(E)] in the valence band are quite small, however, the densities of available states in these bands are very large, thus a small change in f(E) can cause large changes in the carrier concentrations.

Fig.2.4 The density of states N(E), the Fermi-Dirac distribution function f(E), and the carrier concentration as functions of energy for (a) intrinsic, (b) n-type, and (c) p-type semiconductors at thermal equilibrium.

Note: since the function f(E) is symmetrical about , a large electron concentration implies a small hole concentration, and vice versa. In n-type material, the electron concentration in the conduction band increases as moves closer to ; thus, ( ) gives a measure of n. Similarly, in p-type material, the hole concentration in the valence band increases as moves closer to ; thus, ( ) gives a measure of p.
1 2 3 4

Energy Bands and Charge Carriers in Semiconductors Electron and Hole Concentrations at Equilibrium

The F-D distribution function can be used to calculate the electron and hole concentrations in semiconductors, if the densities of available states in the conduction and valence bands are known. In equilibrium, the concentration of electrons in the conduction band can be given by

(2.8) where N(E)dE is the density of available states/cm3 in the energy range dE.

Note: the upper limit of is theoretically not proper, since the conduction band does not extend to infinite energies; however, since f(E) decreases rapidly with increasing E, the contribution to this integral for higher energies is negligible. Using the solution of 's wave equation under periodic boundary conditions, it can be shown that

(2.9)

Thus, N(E) increases with E, however, f(E) decreases rapidly with E, thus, the product f(E)N(E) decreases rapidly with E, and very few electrons occupy states far above the conduction band edge, i.e., most electrons occupy a narrow energy band near the conduction band edge. Similarly, the probability of finding an empty state in the valence band [1 - f(E)] decreases rapidly below , and most holes occupy states near the top of the valence band. Thus, a mathematical simplification can be made assuming that all available states in the conduction band can be represented by an effective density of states NC located at the conduction band edge and using Boltzmann approximation. Thus, (2.10)

where .

Note: as ( ) decreases, i.e., the Fermi level moves closer to the conduction band, the electron concentration increases. By similar arguments, (2.11) where is the effective density of states located at the valence band edge and .

Note: the only terms separating the expressions for

are the effective

masses of electrons ( ) and holes ( ) respectively, and since , hence, . Thus, as ( ) decreases, i.e., the Fermi level moves closer to the valence band edge, and the hole concentration increases. These equations for and are valid in equilibrium, irrespective of the material being intrinsic or doped. For intrinsic material lies at an intrinsic level (very near the middle of the band gap), and the intrinsic electron and hole concentrations are given by and (2.12) Note: At equilibrium, the product is a constant for a particular material and temperature, even though the doping is varied,

i.e.,

(2.13)

This equation gives an expression for the intrinsic carrier concentration ni as a function of , , and temperature: (2.14)

These relations are extremely important, and are frequently used for calculations. Note: if were to be equal to , then would have been exactly at mid gap (i.e., - = = /2). However, since , is displaced slightly from mid gap (more for GaAs than that for Si). Alternate expressions for and : and (2.15)

Note: the electron concentration is equal to ni when is at , and n0 increases exponentially as moves away from towards the conduction band. Similarly, the hole concentration varies from to larger values as moves from towards the valence band.

EXAMPLE 2.3: A Si sample is doped with B . What is the equilibrium electron concentration n0 at 300 K? Where is relative to ? Assume for Si at 300 K = 1.5 x SOLUTION: Since B (trivalent) is a p-type dopant in Si, hence, the material will be predominantly p-type, and since >> , therefore, will be approximately equal to , and = . . The resulting band Also, diagram is:

Temperature Dependence of Carrier Concentrations

The intrinsic carrier concentration has a strong temperature dependence, given by (2.16) Thus, explicitly, ni is proportional to T3/2 and to e 1/T, however, Eg also has a temperature dependence (decreasing with increasing temperature, since the interatomic spacing changes with temperature).

Fig.2.5 The intrinsic carrier concentration as a function of inverse temperature for Si, Ge, and GaAs. As changes with temperature, so do and . With and T given, the unknowns are the carrier concentrations and the Fermi level position with respect to one of these quantities must be given in order to calculate the other. Example: Si doped with donors ( ). At very low temperature, negligible intrinsic EHPs exist, and all the donor electrons are bound to the donor atoms. As temperature is raised, these electrons are gradually donated to the conduction band, and at about 100 K (1000/T = 10), almost all these electrons are donated this temperature range is called the ionization region. , since for each

Once all the donor atoms are ionized, the electron concentration donor atom, one electron is obtained.

Fig.2.6 Variation of carrier concentration with inverse temperature clearly showing the three regions: ionization, extrinsic, and intrinsic.

Thus, remains virtually constant with temperature for a wide range of temperature (called the extrinsic region), until the intrinsic carrier concentration ni starts to become comparable to . For high temperatures, >> , and the material loses its extrinsic property (called the intrinsic region). Note: in the intrinsic region, the device loses its usefulness => determines the maximum operable temperature range. Compensation and Space Charge Neutrality

Semiconductors can be doped with both donors ( ) and acceptors ( ) simultaneously. Assume a material doped with > predominantly n-type lies above acceptor level Ea completely full, however, with above , the hole concentration cannot be equal to . Mechanism: Electrons are donated to the conduction band from the donor level An acceptor state gets filled by a valence band electron, thus creating a hole in the valence band. o An electron from the conduction band recombines with this hole. o Extending this logic, it is expected that the resultant concentration of electrons in the conduction band would be instead of . o This process is called compensation. By compensation, an n-type material can be made intrinsic (by making = ) or even p-type (for > ). Note: a semiconductor is neutral to start with, and, even after doping, it remains neutral (since for all donated electrons, there are positively charged ions ( ); and for all accepted electrons (or holes in the valence band), there are negatively charged ions ( ). Therefore, the sum of positive charges must equal the sum of negative charges, and this governing relation, given by (2.17) is referred to as the equation for space charge
o o

neutrality.

This equation, solved simultaneously with the law of mass action (given by ) gives the information about the carrier concentrations. Note: for , .
1 2 3 4

Energy Bands and Charge Carriers in Semiconductors Drift of Carriers in Electric and Magnetic Fields

In addition to the knowledge of carrier concentrations, the collisions of the charge carriers with the lattice and with the impurity atoms (or ions) under electric and/or magnetic fields must be accounted for, in order to compute the current flow through the device. These processes will affect the ease (mobility) with which carriers move within a lattice. These collision and scattering processes depend on temperature, which affects the thermal motion of the lattice atoms and the velocity of the carriers. Conductivity and Mobility

Even at thermal equilibrium, the carriers are in a constant motion within the lattice. At room temperature, the thermal motion of an individual electron may be visualized as random scattering from lattice atoms, impurities, other electrons, and defects. There is no net motion of the group of n electrons/cm3 over any period of time, since the scattering is random, and there is no preferred direction of motion for the group of electrons and no net current flow. However, for an individual electron, this is not true the probability of an electron returning to its starting point after time t is negligibly small. Now, if an electric field is applied in the x-direction, each electron experiences a net force q from the field. This will create a net motion of group in the x-direction, even though the force may be insufficient to appreciably alter the random path of an individual electron. If is the x-component of the total momentum of the group, then the force of the field on the n is (2.18) Note: this expression indicates a constant acceleration in the x-direction, which realistically cannot happen.

In steady state, this acceleration is just balanced by the deceleration due to the collisions. Thus, while the steady field does produce a net momentum , for steady state current flow, the net rate of change of momentum must be zero when collisions are included. Note: the collision processes are totally random, thus, there is a constant probability of collision at any time for each electron. Consider a group of electrons at time t = 0, and define N(t) as the number of electrons that have not undergone a collision by time t

Fig.2.7 The random thermal motion of an individual electron, undergoing random scattering. The rate of decrease of N(t) at any time t is proportional to the number left unscattered at t, i.e.

(2.19) where

is the constant of proportionality.

The solution is an exponential function (2.20) and represents the mean time between scattering events, called the mean free time.

The probability that any electron has a collision in time interval dt is dt/ , thus, the differential change in due to collisions in time dt is (2.21)

Thus, the rate of change of (2.22)

due to the decelerating effect of collisions is

For steady state, the sum of acceleration and deceleration effects must be zero, thus, (2.23)

The average momentum per electron (averaged over the entire group of electrons) is (2.24)

Thus, as expected for steady state, the electrons would have on the average a constant net velocity in the -x-direction (2.25)

This speed is referred to as the drift speed, and, in general, it is usually much smaller than the random speed due to thermal motion .

The current density resulting from this drift

(2.26)

This is the familiar Ohm's law with

being the conductivity of the sample,

which can also be written as , with is defined as the electron mobility (in ), and it describes the ease with which electrons drift in the material.

The mobility can also be expressed as the average drift velocity per unit electric field, thus with the negative sign denoting a positive value for mobility since electrons drift opposite to the direction of the electric field. The total current density can be given by (2.27) when both electrons and holes contribute to the current conduction; on the other hand, for predominantly n-type or p-type samples, respectively the first or the second term of the above equation dominates. Note: both electron and hole drift currents are in the same direction, since holes (with positive charges) move along the direction of the electric field, and electrons (with negative charges) drift opposite to the direction of the electric field.

Since GaAs has a strong curvature of the E-k diagram at the bottom of the conduction band, the electron effective mass in GaAs is very small the electron mobility in GaAs is very high since is inversely proportional to .

The other parameter in the mobility expression, i.e., (the mean free time between collisions) is a function of temperature and the impurity concentration in the semiconductor. For a uniformly doped semiconductor bar of length L, width w, and thickness t, the resistance R of the bar can be given by where is the resistivity. Effects of Temperature and Doping on Mobility

The two main scattering events that influence electron and hole motion (and, thus, mobility) are the lattice scattering and the impurity scattering. All lattice atoms vibrate due to temperature and can scatter carriers due to collisions. These collective vibrations are called phonons, thus lattice scattering is also known as phonon scattering. With increasing temperature, lattice vibrations increase, and the mean free time between collisions decreases mobility decreases (typical dependence ). Scattering from crystal defects and ionized impurities dominate at low temperatures. Since carriers moving with low velocity (at low temperature) can get scattered more easily by ionized impurities, this kind of scattering causes a decrease in carrier mobility with decreasing temperature (typical dependence ). Note: the scattering probability is inversely proportional to the mean free time (and to mobility), hence, the mobilities due to two or more scattering events add inversely: (2.28) Thus, the mechanism causing the lowest mobility value dominates. Mobility also decreases with increasing doping, since the ionized impurities scatter

carriers more (e.g., donor doping of High Field Effects

for intrinsic Si is 1350 , n drops to 700

at 300 K, whereas with a ).

For small electric fields, the drift current increases linearly with the electric field, since is a constant. However, for large electric fields (typically > ), the current starts to show a sublinear dependence on the electric field and eventually saturates for very high fields. Thus, becomes a function of the electric field, and this is known as the hot carrier effect, when the carrier drift velocity becomes comparable to its thermal velocity. The maximum carrier drift velocity is limited to its mean thermal velocity (typically ), beyond which the added energy imparted by the electric field is absorbed by the lattice (thus generating heat) instead of a corresponding increase in the drift velocity.

2.4.4 The Hall Effect

An extremely important measurement procedure for determining the majority carrier concentration and mobility.

Fig.2.8 The experimental setup for the Hall Effect measurement.

If a magnetic field is applied perpendicular to the direction of carrier flow, the path of the carriers get deflected due to the Lorentz force experienced by the carriers, which can be given by F = q(E + v x B) (2.29) Thus, the holes will get deflected towards the -y-direction, and establish an electric field along the y-direction, such that in steady state The establishment of this electric field is known as the Hall effect, and the resulting voltage is called the Hall voltage. Using the expression for the drift current, is called the Hall coefficient. A measurement of the Hall voltage along with the information for magnetic field and current density gives the majority carrier concentration Also, the majority carrier mobility can be obtained from a measurement of the resistivity This experiment can be performed to obtain the variation of majority carrier concentration and mobility as a function of temperature.

For n-type samples, the Hall voltage and the Hall coefficient are negative common diagnostic tool for obtaining the sample type. Note: caution should be exercised for near intrinsic samples.

EXAMPLE 2.4: A sample of Si is doped with In . What will be the measured value of its resistivity? What is the expected Hall voltage in a 150 m thick sample if ? SOLUTION:

Equilibrium Condition

In equilibrium, there is no external excitation except a constant temperature, no net transfer of energy, no net carrier motion, and no net current transport. An important condition for equilibrium is that no discontinuity or gradient can arise in the equilibrium Fermi level EF. Assume two materials 1 and 2 (e.g., n- and p-type regions, dissimilar semiconductors, metal and semiconductor, two adjacent regions in a nonuniformly doped semiconductor) in intimate contact such that electron can move between them. Assume materials 1 and 2 have densities of state N1(E) and N2(E), and F-D distribution functions f1(E) and f2(E) respectively at any energy E.

The rate of electron motion from 1 to 2 can be given byrate from 1 to 2 N1(E)f1(E) . N2(E)[1 f2(E)] (2.30)and the rate of electron motion from 2 to 1 can be given byrate from 2 to 1 N2(E)f2(E) . N1(E)[1 f1(E)] (2.31)" At equilibrium, these two rates must be equal, which gives f1(E) = f2(E) => EF1 = EF2 => dEF/dx = 0; thus, the Fermi level is constant at equilibrium, or, in other words, there cannot be any discontinuity or

gradient in the Fermi level at equilibrium.

Practice Problems 2.1 Electrons move in a crystal as wave packets with a group velocity where is the angular frequency. Show that in a given electric field, these wave packets obey Newton's second law of motion, i.e., the force F = m*a, where m* is the effective mass and a is the acceleration.

2.2 Some semiconductors of interest have the dependence of its energy E with respect to the wave vector k, given by E = 0, k is the wave vector, and effective mass on energy. is the effective mass for is a constant. Calculate the dependence of the

2.3 Determine the equilibrium recombination constant r for Si and GaAs, having equilibrium thermal generation rates of respectively, and intrinsic carrier concentrations of respectively. Comment on the answers. Will change with doping at equilibrium? 2.4 The relative dielectric constant for GaP is 10.2 and the electron effective mass is Calculate the approximate ionization energy of a donor atom in GaP. above the Fermi level below is empty. to the center of the band is occupied is the

2.5 Show that the probability that a state same as the probability that a state

2.6 Derive an expression relating the intrinsic level gap Assume

and compute the magnitude of this displacement for Si and GaAs at 300 K. respectively.

2.7 Show that in order to obtain maximum resistivity in a GaAs sample has to be doped slightly p-type. Determine this doping concentration. Also, determine the ratio of the maximum resistivity to the intrinsic resistivity. 2.8 A GaAs sample (use the date given in Problem 2.7) is doped uniformly with out of which 70% occupy Ga sites, and the rest 30% occupy As sites. Assume 100% ionization and T = 300 K. a) Calculate the equilibrium electron and hole concentrations b) Clearly draw the equilibrium band diagram, showing the position of the Fermi level with respect to the intrinsic level , assuming that lies exactly at midgap. c) Calculate the percentage change in conductivity after doping as compared to the intrinsic case. 2.9 A Si sample is doped with donor atoms. Determine the minimum temperature at which the sample becomes intrinsic. Assume that at this minimum it

temperature, the free electron concentration does not exceed by more than 1% of the donor concentration (beyond its extrinsic value). For 2.10 Since the event of collision of an electron in a lattice is a truly random process, thus having a constant probability of collision at any given time, the number of particles left unscattered at time t, Hence, show that if there are a total of i number of scattering events, each with a mean free time of then the net electron mobility can be given by mobility due to the ith scattering event. where is the

2.11 A Ge sample is oriented in a magnetic field (refer to Fig.2.8). The current is 4 mA, and the sample dimensions are w = 0.25 mm, t = 50 m, and L = 2.5 mm. The following data are taken: Find the type and concentration of the majority carrier, and its mobility. Hence, compute the net relaxation time for the various scattering events, assuming 2.12 In the Hall effect experiment, there is a chance that the Hall Probes A and B (refer to Fig.2.8) are not perfectly aligned, which may give erroneous Hall voltage readings. Show that the true Hall voltage can be obtained from two measurements of with the magnetic field first in the +z-direction, and then in the z-direction.
1 2 3 4

s
EXCESS CARRIERS IN SEMICONDUCTORS

Excess carriers, essential for device operation, are created by optical excitation, electron bombardment, or injected across a forward-biased p-n junction. These excess carriers can dominate the conduction process in semiconductor materials.

Optical Absorption

This includes photons in the optical range as well as those in the infrared region. Photons of various wavelengths (frequencies) are directed at the sample, and their relative transmission is measured. Note: photons having energies greater than the band gap energy are absorbed (the sample behaves opaque for this kind of illumination), whereas those having energies less than the band gap energy are transmitted (the sample behaves transparent), this experiment gives an accurate measure of the band gap energy. When photons having energies h Eg are absorbed, they create EHPs and the probability of this absorption is very high, since there are lots of electrons in the valence band and lots of empty states in the conduction band. Electrons excited to EC may initially have energies much higher than EC, however, they lose this excess energy due to scattering with the lattice until their equilibrium energy becomes equal to EC. Note: these EHPs are called excess carriers, since they are out of balance, and, thus, would eventually recombine. However, while these excess carriers remain in the respective bands, they can contribute to the current conduction. The transmitted intensity It of a beam of photons of wavelength through a sample of

thickness t can be given by

where wavelength

is called the absorption oefficient, and varies with materials and photon

Fig.3.1 The variation of the absorption coefficient as a function of the wavelength of the incident light.

Fig.3.2 Band gaps of some common semiconductors relative to the optical spectrum.

Absorption cutoff occurs at GaAs, Si, Ge, and InSb band gaps are such that c occurs beyond the visible region (in c falling within the visible

the infrared), whereas GaP and CdS have band gaps with range.

Luminescence

When recombination occurs between a conduction band electron and a valence band hole, the energy released can be given off in the form of light (luminescence). Direct band-to-band recombination in direct band gap semiconductors have a much higher probability of light emission as compared to those in indirect materials. Broadly divided into three categories: Photoluminescence: if the recombining carriers were caused by optical excitation. Cathodoluminescence: if the recombining carriers were caused by high energy electron bombardment.

Electroluminescence: if the recombining carriers were caused by injection of excess carriers (by forward biasing a p-n junction, for example).

Photoluminescence

For steady state excitation, the recombination rate and the generation rate for EHPs are equal, and one photon is emitted for each photon absorbed. Direct band-to-band recombination is a fast process with typical lifetime of excess carriers 10 8 sec => known as fluorescence (example: fluorescent lamp). In some indirect materials, the trap states within the band gap captures carriers, and slows down the recombination process, thus, emission continues for seconds or minutes after the excitation is removed => known as phosphorescence and the materials are known as phosphors. The trap states can hold the carriers for indefinite times, and the carriers can either get reexcited to the conduction band or fall to the valence band (and, thus, recombine) => this creates the delay between excitation and recombination.

EXAMPLE 3.1: A 0.5 m thick sample of thick sample of In is illuminated with monochromatic light of The absorption coefficient The power incident on the sample is 15 mW. (a) Find the total energy absorbed by the sample per second (J/sec). (b) Find the rate of excess thermal energy given up by the electrons to the lattice before recombination (J/sec). (c) Find the number of photons per second given off from recombination events, assuming perfect quantum efficiency. SOLUTION: a. (a)The transmitted intensity Therefore, the absorbed power (15 9.1) mW = 5.9 mW = 5.9 10 3 J/sec. b. (b)Since the energy of the incident photon is greater than the band gap energy, hence, the excess energy of the excited electron will be dissipated as heat to the lattice. The fraction of energy converted to heat is given by (1.5 1.34)/1.5 = 0.107. Thus, the amount of energy converted to heat per second

c. (c) For perfect quantum efficiency, one photon is emitted for each photon absorbed. Thus, the number of photons emitter per second

or, alternately, recombination radiation accounts for 5.9 0.63 = 5.27 mW at 1.34 eV/photon. Thus,

Cathodoluminescence

Best example: cathode ray tube (CRT) basis of television sets, oscilloscopes, and other display systems. Electrons emitted from the heated cathode are accelerated towards the anode by high field, deflected by electric or magnetic fields by the horizontal and vertical plates, and made to hit the screen (coated with a phosphor) at desired locations. When electrons hit these phosphors, the energy of the electrons gets transferred to the electrons of the phosphors, and they get excited to higher states, and eventually fall to the ground state, thus causing recombination and light emission. Three phosphor dots are used for each pixel, capable of transmitting three primary colors: red, green, and blue (RGB) thus by varying the intensity and position of the electron beam, a wide range of colors and picture can be attained.

Electroluminescence

Best examples: LEDs and LASERs, where carriers are injected across a forward biased p-n junction and are made to recombine (either naturally or by carrier confinement) => called injection electroluminescence.

Carrier Lifetime and Photoconductivity

Photoconductivity: increase in the conductivity of a sample due to excess carriers created by optical excitation. With excitation turned off, the photoconductivity decreases to zero since all excess carriers eventually recombine.

Direct Recombination of Electrons and Holes

Direct recombination occurs spontaneously, i.e., the probability that an electron and a hole will recombine is constant in time, which leads to an exponential solution for the decay of the excess carriers. The net rate of change in the conduction band electron concentration at any time t

where the first term is the generation rate and the second term is the recombination rate.

Let excess EHPs n and p (with n = p, since they are created in pairs) are created at t = 0 by a short flash of light. Define n(t) and p(t) (again n = p) as the instantaneous excess carrier concentrations and n and p for their values at t = 0. Note: n(t) = n0 + n(t), and p(t) = p0 + p(t). Thus,

where ) is called the minority carrier recombination lifetime or simply the minority carrier lifetime, and it determines the rate at which the minority carriers recombine with time.

Similarly, excess holes in an n-type material recombine with a rate Note: for direct recombination, the excess majority carriers (which is equal to the excess minority carriers) decay at exactly the same rate as the minority carriers, however, there is a large percentage change in the minority carriers as compared to the majority carriers. A more general expression for carrier lifetime for near not sufficiently extrinsic samples is
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EXCESS CARRIERS IN SEMICONDUCTORS Indirect Recombination: Trapping

In indirect materials, the probability of direct band-to-band recombination is very small recombination in these materials proceed through the assistance of recombination (or trapping) centers located within the band gap, which trap carriers of one type followed by trapping carriers of the opposite type, thus annihilating the pairs.

Fig.3.3 Energy levels of common impurities in silicon, measured from the closest band edge.

The resulting energy loss is often in the form of heat given to the lattice (instead of light emission), and, thus, these materials are not well suited for optoelectronic applications. There are four probabilities associated with a recombination center: (a) hole capture: when an electron from the recombination center falls to the valence band, (b) hole emission: when an electron makes a transition from the valence band to the recombination center, (c) electron capture: when an electron falls from the conduction band to the recombination center, and (d) electron emission: when an electron makes a transition from the recombination center to the conduction band. Each of these processes has their own probabilities and time constants, and the resulting analysis is significantly complicated. This theory of recombination is known as the SHR (Shockley-Hall-Read) theory of recombination. If process (a) follows process (c) or vice versa, recombination takes place, whereas, if process (b) follows process (a) (or vice versa) or process (c) follows process (d) (or vice versa), it is known as reemission, and the recombination center behaves like a trapping center. Generally, centers that are located towards the middle of the band gap (e.g., Au in Si) behave like recombination centers, whereas centers located closer to the conduction or valence band behave as traps, for obvious reasons. Alternate definition: in a center located within the band gap, if after capturing one type of carrier, the most probable next event is the capture of opposite type of carrier, then it is a recombination center, however, if the most probable next event is reexcitation, then it is a trap. The recombination can be slow or fast, depending on the amount of time the carrier spends in the center before the capture of the opposite type of carrier happens, thus, computation of lifetime for this kind of indirect recombination is sufficiently complicated.

The decay of excess carriers can be measured by a typical photoconductive decay measurement, where light shining on a sample is suddenly switched off, and the resulting decay of current passing through the sample is measured, the rate of decay of this current gives the excess carrier lifetime. Auger Recombination

Note: the lifetime is proportional to the inverse of the doping concentration. However, at relatively high doping levels, the lifetime decreases at a faster rate with an increase in the doping concentration. This is because a different recombination mechanism, called the Auger recombination becomes dominant at high doping levels. In this recombination mechanism, the electron and hole recombine without involving trap levels, and the released energy (of the order of the energy gap) is transferred to another carrier (a hole in p-type material and an electron in n-type material). This process is somewhat the inverse of the impact ionization process, in which an energetic carrier causes EHP generation. Since two electrons (in n-type material) or two holes (in p-type material) are involved in this process, it is highly unlikely except in heavily doped material. The recombination lifetime associated with the Auger recombination process is inversely proportional to the square of the majority carrier concentration, i.e., for p-type material, , and for n-type material, with values of Surface Recombination and , where Gp and Gn are coefficients .

It is obvious that near the surface of any semiconductor device, the carrier recombination rate should be very high, due to extra defects and traps at the surface. Thus, the diffusion flux of minority carriers at the surface is determined by the surface recombination processes.

Fig.3.4 Auger recombination: (a) n-type sample, and (b) p-type sample.

For example, when minority carriers are holes, this surface recombination can be described by:

where x = 0 corresponds to the surface of the sample, and recombination rate, with being the capture cross-section for holes,

is the surface is the thermal

velocity for the holes, and is the surface density of the surface states. The capture cross-section (typically ) describes the effectiveness of the localized state in capturing a carrier. The product may be visualized as the volume swept out per unit time by a particle with cross-section If the surface state lies within this volume around the carrier, then the carrier gets captured by the surface state. Note: the dimension of S is cm/sec, and, consequently, it is termed as the surface recombination velocity, even though it has nothing to do with actual velocity. Steady State Carrier Generation: Quasi-Fermi Levels

For any temperature T, there is a thermal generation rate g(T) balanced by a recombination rate r(T). Now, if a steady light is shone on the sample, an optical generation rate will be added to g(T), and the carrier concentrations n and p would increase to their new steady state values.

Generation/recombination rate balance equation:

For steady state recombination and no trapping, approximation

; and, under low level injection

Thus, the excess carrier concentrations can be given by In general, when trapping is present, , and

and

Note: when excess carriers are present, . When excess carriers are present, the equilibrium Fermi level is no more meaningful; instead, the carrier concentrations are defined in terms of quasi-Fermi levels (also referred to as Imref, which is Fermi spelled backwards) as

Imref for the minority carriers deviates significantly from the equilibrium Fermi level, whereas, for majority carriers, the Imref stays very close to the equilibrium Fermi level, and the separation between these two Imrefs is a measure of how far the system is from equilibrium. With concentrations varying with position, the Imrefs would also vary with position, thus drawing Imrefs in band diagrams clearly shows the positional variations of the carrier concentrations.

EXAMPLE 3.2 A Si sample with is illuminated by a steady light thus creating optically. Assume no trapping, and (a) Determine the electron and hole concentrations n and p respectively, and their percentage change from the equilibrium concentrations. (b) Comment on the magnitude of the product np. (c) Determine the locations of the Imrefs equilibrium Fermi leve SOLUTION (a) The equilibrium hole concentration concentration . Hence, the equilibrium electron ,and compare their locations with the

Since there is no trapping and concentrations can be given by

,therefore, the excess electron and hole

Therefore, the net electron concentration is given by

and the net hole concentration is given by

Therefore, the percentage change in the electron concentration

And the percentage change in the hole concentration Note: with optical excitation (under the low-level injection approximation), there is a very large change in the minority carrier concentration, whereas the change in the majority carrier concentration is hardly noticeable! (b) Note: Whenever excess carriers are present, departure from equilibrium. (c) In equilibrium, , and the amount of deviation quantifies the

In the presence of excess carriers, the electron Imref and the hole Imref

Thus, the majority carrier Imref almost coincides with the equilibrium Fermi level, whereas the minority carrier Imref shows a large departure from the equilibrium value.

Photoconductive Devices

Devices which change their resistance while exposed to light. Examples: automatic night light controllers, exposure meters in cameras, moving-object counters, burglar alarms, detectors in fiber optic communication systems, etc. Considerations in choosing a photoconductor for a given application: sensitive wavelength range, time response, and optical sensitivity (responsivity) of the material. The photoconductivity change while exposed to light is

Obvious that for large changes in , the carrier mobility and lifetime should be high (e.g., in , and could be used as infrared detector with high sensitivity). Time response is limited by recombination times, degree of carrier trapping, and time required for the carriers to drift through the device in an electric field. Dark resistance (i.e., the resistance of the device without any illumination) should be as small as possible. Generally, all these requirements cannot be satisfied simultaneously, and some kind of optimization is required. Diffusion of Carriers

When excess carriers are created in a semiconductor and their concentrations vary with position, then there is a net carrier motion from regions of higher concentration to regions of lower concentration. This type of motion is called the diffusion, and it is an important charge transport mechanism in semiconductors. Diffusion and drift are the two main current transport mechanisms. Diffusion processes

Natural result of the random motion of individual electrons. Electrons move randomly and experience collisions, on the average, after each mean free time . Since the motion is truly random, an electron has equal probability of moving into or out of a volume through a boundary.

Fig.3.5 Spreading of a narrow pulse of electrons created at x = 0 at t = 0 with time

A pulse of excess electrons injected at x = 0 at time t = 0 will spread out in time due to diffusion, and eventually n(x) becomes a constant, when no more net motion takes place.
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EXCESS CARRIERS IN SEMICONDUCTORS

Fig.3.6 An arbitrary electron distribution along the x-direction: (a) each segment divided into lengths equal to the mean free path , and (b) expanded view of two segments centered at

Consider any arbitrary distribution n(x), with x divided into segments wide, with n(x) evaluated at the center of each segment.

(mean free path)

In , half of the electrons in segment (1) to the left of would move into segment (2), and in the same time, half of the electrons in segment (2) to the right of would move into segment (1). Therefore, the net number of electrons moving from segment (1) to segment (2) through within a mean free time , where A is the area perpendicular to x. Thus, the electron flux density in the +x-direction

Note: is a small differential length, thus,

where x is taken at the center of segment (1) and x = .

In the limit of small

(i.e., small mean free path

between collisions)

The quantity

is called the electron diffusion coefficient

The minus sign in the expression for implies that the diffusion proceeds from higher electron concentration to lower electron concentration. Similarly, holes diffuse from a region of higher concentration to a region of lower concentration with a diffusion coefficient Thus,

and the diffusion current density

Note: electrons and holes move together in a carrier gradient, however, the resulting currents are in opposite directions because of the opposite charges of the particles. Diffusion and Drift of Carriers: Built-in Fields

The total current density can thus be written as

and the total current density is

The total current may be due primarily to one of these two components, depending upon the carrier concentrations, their gradients, and the electric field. Thus, minority carriers can contribute to current conduction significantly through diffusion, even though they contribute very little to the drift term (due to their low concentrations). Since electrons drift opposite to the direction of the electric field (due to their negative charge), their potential energy increases in the direction of the electric field. The electrostatic potential varies in the opposite direction, and can be given by V(x) = Ei(x)/(q). Thus, the electric field can be given by

Note: electrons drift downhill in a band diagram, therefore, the electric field points uphill in a band diagram. Note: in equilibrium, no net current => any fluctuation in carrier concentration which brings about a diffusion current also sets up an electric field, which opposes the diffusive motion => thus, equilibrium is established. This field is referred to as the built-in field, and can be caused by doping gradients and/or variation in the band gap. Equating the hole current density equation to zero, we get

Now, EF does not vary with x in equilibrium, and the variation of Ei with x is given above,

thus,

This is an extremely important equation valid for both carrier types, and is called the Einstein relation gives the relation between D and , which is a function only of temperature, and allows calculation of one if the other is known.

EXAMPLE 3.3 An intrinsic Si sample is doped with acceptors from one side such that (a) Find an expression for E(x) at equilibrium from x = 0 to 5 m. (b) Evaluate E(x) at x = 0 and 5 m. (c) Sketch a band diagram and indicate the direction of E SOLUTION (a) Recall, at equilibrium, the hole current density Thus, where use has been made of the Einstein relation and 100% ionization is assumed. Thus, the electric field varies inversely with distance and has positive values throughout. (b) E(0) = 52 V/cm and E(L) = 26 V/cm (c) Note: E(x) = (1/q)(dEi/dx). Since E(x) varies inversely with x, hence Ei (and consequently, both EC and EV) will have a logarithmic (ln) dependence on x.

Diffusion and Recombination: The Continuity Equation

In the description of conduction processes, the effects of recombination must be included, since they can cause a variation in the carrier distribution. Hole conservation equation:

i.e., rate of hole buildup = increase of hole concentration in rate.

per unit time recombination

Fig.3.7 Setup to obtain particle count: current entering and leaving a volume

For

This is called the continuity equation for holes, and, similarly, for electrons, we can write

When the current is carried entirely due to diffusion (negligible drift), then we obtain the diffusion equation for electrons, given by

and, similarly for holes,

Steady State Carrier Injection: Diffusion Length

In steady state, if a distribution of excess carriers is maintained, then the diffusion equations become

where are the electron diffusion length and the hole diffusion length, which is the average distance an electron or a hole diffuses before recombining respectively.

Case study: suppose excess holes are injected into a semi-infinite n-type bar, which maintains a constant concentration (relevant problem in a forward biased diode). Obviously, the excess holes would diffuse into the n-type bar, recombine with the electrons

with a characteristic lifetime (and diffusion length ), and for large values of x, the excess hole concentration should decay to zero; thus,

and the decay profile is exponential.

The steady state distribution of excess holes causes diffusion, and therefore, a hole current in the direction of decreasing concentration, given by

(This equation would come handy in the diode analysis.) The Haynes-Shockley Experiment

Counterpart of the Hall effect experiment. Independently determines the minority carrier mobility and diffusion coefficient

. Fig.3.8 Schematic for Haynes-Shockley experiment: drift and diffusion of a hole pulse in an n-type bar: (a) sample geometry, (b) shape and position of the pulse for different times along the bar.

Basic principle a pulse of excess holes is created in an n-type bar (which has an applied electric field), as time progresses, the holes spread out by diffusion and move due to the electric field, and their motion is monitored somewhere down the bar,
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EXCESS CARRIERS IN SEMICONDUCTORS

the time required for the holes to move the distance gives a measure of their mobility, and the spreading of the pulse in a given time gives a measure of the diffusion coefficient. A pulse of excess carriers is created by a light flash at x = 0 in an n-type semiconductor bar with an electric field E. The excess holes drift down the bar and reach the point x = L after a time , thus, the drift

velocity , and the hole mobility . For measurement of diffusion coefficient, assume the pulse spreads without drift and neglect recombination; then the diffusion equation can be rewritten as

The solution to this equation is the well known Gaussian distribution, given by

where

the number of holes per unit area created over a negligibly small distance at t = 0. Note: the peak values of the pulse decreases and the pulse spreads in time. Let the peak value of the pulse be at 1/e of its peak value ; thus, and note that at directions with , is down by

and

, where oscilloscope in time.

, where t is the spread of the pulse seen in an

Fig.3.9 The profile of the excess hole concentration after time td.

EXAMPLE A p-type Si sample is used in the Haynes-Shockley experiment. The length of the sample is 2 cm and the two measurement probes are separated by 1.9 cm. The voltage applied across the two ends of the sample is 5 V. A pulse arrives at the collection point 0.608 msec after its injection at the injection point, and the spread of the pulse t at the collection point is 180 sec. Calculate the electron mobility and diffusion coefficient, and verify whether Einstein relation is satisfied. SOLUTION The electron mobility

The electron diffusion coefficient

Their ratio

Thus, Einstein relation is indeed satisfied.

Any combination of drift and diffusion implies a gradient in the steady state Imrefs. Under general case of nonequilibrium electron concentration with drift and diffusion, the total electron current can be written as

Using the expression for n(x) in terms of the electron Imref, and applying Einstein relation, it can be shown that

and, similarly, for holes,

Therefore, any drift, diffusion, or a combination of the two in a semiconductor sets up currents proportional to the gradient in the Imrefs, or, in other words, no current implies constant Imrefs.

Practice Problems 3.1 1A 100 mW laser beam with wavelength nm is focused onto an InP sample 100 thick. The absorption coefficient at this wavelength is . Find the number of photons emitter per second by radiative recombination in the sample, assuming 100% quantum efficiency (i.e., each incident photon creates one EHP, and they spontaneously recombine). What power is delivered to the sample as heat? 3.2 A photon of monochromatic light of wavelength 500 nm is absorbed in , and excites an electron from the valence band into the conduction band. Calculate the kinetic energies of the electron and the

hole. 3.3 Starting from the recombination/generation rate equation, determine the excess electrons [created in a p-type sample (with equilibrium carrier concentrations given by p0 and n0) by a high intensity pulse of light] decay profile as a function of time [i.e., ]. Assume high-level injection condition State and justify whether would decay with the same profile till it reaches zero. 3.4 A Ge sample with is optically excited at 300 K such that . What is the separation of the Imrefs Clearly draw the band diagram showing the Imrefs and the equilibrium Fermi level compute the change in the sample conductivity after illumination.

? Also,

3.5 A sample of p-type Si has a dark resistivity of at 300 K. The sample is illuminated uniformly to generate . The electron lifetime in the sample is Calculate the sample resistivity and the percent change in the conductivity after illumination due to the majority and the minority carriers. 3.6 Light is shone uniformly on a n-type Si sample for a long time to attain steadystate, and the difference between the electron and the hole Imrefs is found to be 0.55 eV. Now, the light is suddenly shut off at some arbitrary time (call that t = 0), and the excess conductivity is found to decrease to 10% of its maximum value at time . Determine the optical generation rate injection and no trapping. and the excess hole lifetime Assume low-level

3.7 A sample is doped with donors such that , where G is a constant, L is the length of the sample, and Assuming equilibrium, find the built-in electric field in order to sustain this distribution, and clearly draw the band diagram. Also, plot the potential V(x) as a function of position. 3.8 A 4.63 n-type Si sample is illuminated uniformly at t = 0 to produce EHPs. Starting from the continuity equation and assuming low-level injection and no current flow, determine the expression for the build-up of excess holes as a function of time. If the excess conductivity at ; and after sufficiently long time, it is , determine the optical generation rate trapping. and the excess hole lifetime Assume no

3.9 The following date are obtained from the Haynes-Shockley experiment on a p-type Si sample at 300 K: length of sample=2cm,length between injection and collection probes =1.2 cm,applied voltage= Calculate the mobility and diffusion coefficient of the minority carriers, and check if this data satisfies the Einstein relation. What should be the minimum values of the lifetime and the diffusion length in the original sample for authentic measurement results? 3.10 In the Haynes-Shockley experiment discussed in this chapter, the recombination of the excess carriers was neglected. However, by a simple modification, it can be made to include the effects of recombination. Assume an n-type semiconductor, the peak voltage of the pulse displayed on the CRO screen is proportional to the peak value of the hole concentration under the collector terminal at time td, and that the displayed pulse can be approximated as a Gaussian, which decays due to recombination by , where is the excess hole lifetime. The electric field is varied and the following date taken: for , the peak

is 20 mV; and for

, the peak is 80 mV. What is

1 2 3 4

PN Junction in equilibrium

PN junctions are important for the following reasons: (i) PN junction is an important semiconductor device in itself and used in a wide variety of applications such as rectifiers, Photodetectors, light emitting diodes and lasers etc (ii) PN junctions are an integral part of other important semiconductor devices such as BJTs, JFETS and MOSFETs (iii) PN junctions are used as test structures for measuring important semiconductor properties such as doping, defect density, lifetime etc

The discussion associated with the PN junctions will proceed in the following order: (i) PN junction in equilibrium (ii) dc IV characteristics in forward bias (iii) characteristics in reverse bias (iv) dynamic characteristics (v) Circuit models (vi) Design perspective Device Structure : The Figure below shows a simplified structure of a PN junction:

The structure can be fabricated by diffusing P-type impurity in the n-epilayer grown over an substrate.

While the doping in the n-epilayer can be uniform, the doping in the P-region is often either Gaussian or error-function in nature. The doping profiles and the junction are schematically illustrated below:

1-D Abstraction

Even though the doping in both N and P-regions may in general be nonuniform, for simplicity, we shall assume them to be uniform in the initial analysis because the basic device physics remains almost the same A simplified, one-dimensional abstracted view of a PN junction described by the region within the dotted lines of device schematic is shown below:

We shall assume that the thicknesses of P and N-regions are large enough so that one can ignore the presence of Ohmic contacts and the heavily doped N-region and consider only the P and N regions for analysis. Such a diode with wide N and P-regions is called a widebase diode. The PN junction that we shall study will therefore be a 1-D structure with uniformly doped P and N regions with thicknesses sufficiently large to ignore effects of contacts and other layers. It shall be represented simply as

PN junction in Equilibrium

As mentioned earlier, the characteristics of a semiconductor device is completely specified in equilibrium if the variation of potential as a function of position is specified. As a first step to obtaining this potential profile, we shall sketch the energy-band diagram of the device. The energy band diagram would provide us with (i) a qualitative variation of potential in the device

(ii) boundary conditions for solution of Poisson's equation

As usual, the energy band diagram of the PN junction will be obtained by combining the energy band diagrams of N and P-type semiconductors separately

Energy Band Diagram In Equilibrium

Energy Band diagram of N- and P-regions before equilibrium

When the N and P-regions are brought into contact, the electrons would flow from regions of higher Fermi-energy to regions of lower Fermi energy and holes would flow in the opposite direction. Because of loss of electrons, the N-region would acquire a net positive charge due to the uncovered positively charged donor atoms and P-region would acquire a negative charge due to uncovered negatively charged acceptor atoms. At equilibrium there is no net flow of either electrons or holes so that the PN junction has a single constant Fermi level. The transfer of charges will affect only the regions close to the junction so that regions which are far still have the same energy band diagram(i.e. same relative positions of conduction and valence band wrt Fermi energy) As we approach the junction from the N-side, the conduction band must bend upwards away from the Fermi energy to indicate the fact that the region is progressively getting depleted of electrons ( remember .

Similarly, as we approach the junction from the P-side, the conduction band must bend downwards towards the Fermi energy to indicate the fact that the region is getting depleted of holes Using these principles, the final energy band diagram can be sketched as

As a result of transfer of charges from N and P-regions, the region next to the junction is charged and is known as the space charge region. The charge on the N-side is positive and on the P-side negative. As a result, the space charge region will have an electric field directed from the N to the Pregion with a maximum value at the junction and zero at the edges of the space charge region. As a result of the electric field, there will be a net voltage across the space charge region known as the built-in voltage. The magnitude of the built-in voltage can be quickly estimated from the energy band diagram. We do this by performing an analog of Kirchoffs voltage law: We start from a point in the N-region(away from the space charge region) at the energy and then move to a point in the P-region(away from the space charge region)again at energy via any path other than the Fermi-energy and add up the energy gained or loss at each step of the path, then the net sum should be zero!

The built-in oltage can be expessed as:

For Non-degenerate semiconductors:

An important result that can be deduced from Eq.(2) is that built-in voltage will be higher for semiconductors with larger bandgap.

Using the relationship , the expression for built-in voltage for a PN junction having non-degenerate semiconductors can be written as

Example 1.1 Determine the built in voltage for a uniformly doped Silicon PN junction with at room temperature. Will the built-in voltage increase or decrease with increase in temperature? Substitution of the doping values in Eq. (4) gives

The built-in voltage decreases with increase in temperature due to exponential increase of intrinsic carrier concentration with temperature. The pre-factor kT/q in Eq.(4) has a much lesser influence.

There is another method by which the magnitude of built-in voltage can be obtained. In this case we start with the fact that in equilibrium, the net electron current is zero:

Use of Einstein's relation :

allows the above expression to be re-written as:

Integrating the above expression across the space charge region gives:

where

are the potentials in the bulk of N- and P- regions respectively. is the electron density in the N-region and is the elecron density in the P-

region.

Example 1.2 Can the built-in voltage of the PN junction be measured by simply connecting a voltmeter across its two terminals?

The answer is NO and this can be explained in several ways:

Although there is a net voltage across P and N-regions, the built-in voltage does not appear across the external terminals. If it did, then upon connection of a resistor across it, a current would begin to flow. This contradicts the fact that no current can flow in equilibrium. So how does the voltage across the external terminals become zero?

The built-in voltage is cancelled by voltage drop across the contacts made to N and Pregions.

The net voltage between anode and cathode terminals can be written as

The first term on the RHS represents the contact potential or barrier height for the Anode/P metal-semiconductor junction. Keeping in mind that contact potential between any two materials is simply the difference of their work-functions, we obtain

where and are the work functions of P-type, N-type, cathode and anode metals respectively. For simplicity we asume that both anode and cathode metals are same ( say aluminium ) so that Using four equations given above, it is easy to see that

Poisson's equation

The energy band diagram gives only a qualitative variation of potential across the space charge region. The detailed nature of this potential can be obtained through the solution of Poisson equation:

Analytical Solution of Poisson's equation

Because of the exponential terms in the expression for charge density, the analytical solution of the Poisson's equation becomes difficult. This difficulty is overcome through the assumption that the electron and hole density within the space charge region is negligible as compared to the ionized donor or acceptor atom density. This approximation, known as the depletion approximation, allows the Poisson equation to be simplified to:

Henceforth, we shall also assume that all donor and acceptor atoms are ionized.

The table below shows the charge density as a function of potential within the space charge region for a PN junction with same doping in N and P regions for simplicity.

The data in the table shows that over a large range of potential, the depletion approximation is valid. Only for regions close to the space charge edge, does the approximation become weak.

Simplified Charge density With the depletion approximation , the charge density can be expressed as

The space charge region is often called the depletion region

Simplified Poisson Equation

The Poisson's equation for P and N-regions of the depletion region can be written as

The boundary conditions can be written as:

The boundary conditions can be written as:

Outside the space region the charge density is zero so that

This implies that electric field outside the depletion region is constant. However, to be consistent, this electric field must be zero, otherwise it would imply a non-zero current, some applied bias etc.

The electric field at x=0 must be continuous, otherwise it would imply an infinite charge density.

Similarly, the potential at x=0 also must be continuous

The Poisson equation with these boundary conditions can be easily solved to obtain the following results. Solution: Electric field: It is max. at the junction

Potential:

The variation of potential across the depletion region is parabolic. Using the boundary condition that potential must be continuous at the junction:

Deletion widths: Using the relation

, we can obtain

The depletion widths vary inversely with the doping.

Example 1.3 Determine the total depletion width and the magnitude of maximum electric field for a symmetrical Si PN junction at equilibrium for doping densities of Using Eq.(23) and (27), we can obtain the following set of values

The depletion width increases with decrease in doping but the magnitude of maximum electric field decreases even though the space charge region gets wider. This is because while the width of the space charge region increases as , the charge density with in the

space charge region decreases as as the doping is reduced. This results in a net decrease in charge and therefore the electric field at the junction.

Example 1.4 Determine the built-in voltage for a Silicon PN junction with uniformly doped P region with and an N-region which consists of two uniformly doped regions but of different doping values as illustrated below.

The difficulty in this problem is that while it is clear that in Eq.(4), it is not clear whether the N-type doping should be or 5 x . The answer depends on where the depletion edge in N-region lies. Let us assume that it lies in the lightly doped region so that we take = .This gives a of 0.7 volts.We have to check whether our assumption is correct or not. Use of Eq.(27) shows that depletion width is 4257 thereby validating our aasumption. If assumption had been wrong, we would have to redo our calculations with =5 x .

As the PN junction is reverse biased, the depletion width increases so that eventually the depletion edge would lie in the higher doped N-region. In that case also a new value of builtin voltage would have to calculated and used in the expressions for depletion width, electric field etc.

Example 1.5 Suppose in the example above, the thickness of the lightly doped region is 2500 only. Calculate the depletion width at equilibrium. Using the previous example, we know that the depletion edge will lie in the higher doped Nregion so that

To find the depletion widths , we can adopt the methodology used for uniformly doped PN junctions except that solution of Poisson's equation is carried out in three regions, with region I being P-type , region II being N-type with doping and region III with N-type doping of The boundary conditions are similar except that two new boundary conditions describing continuity of potential and electric field will have to be used at the boundary of regions II and III. An alternative to working out the solution by beginning from Poisson's equation is to use some of the results already obtained with uniformly doped PN junctions. For example, we know that the electric field will vary linearly and can be sketched as

Using the concept of charge neutrality, meaning that net charge on the P-side must be balanced by net charge on the N-side, we can write

The slopes of electric field in each region can be written straight from Poisson equation. For example, in region II, so that

and similarly using Poisson equation on the P-side in region I

In these equation refers only to the magnitude of the maximum electric field. The area under the curve is simply the total voltage across the junction so that

Solution of the above equations will give values for width.

and therefore the total depletion

Comparison With Exact Numerical calculations

The Figure below shows a comparison of an actual charge profile computed using a 1-D device simulator and charge profile under depletion approximation for a doping of .

The Figure above shows that the transition region is about 600 , almost same as the depletion width(735 ) predicted by the depletion approximation!

The depletion approximation therefore appears to be a poor assumption. However, a careful look shows that the depletion assumption overestimates the charge in region I but underestimates the charge in region II. Since, the electric field and potential are determined by the integral of charge density, the error in electric field and potential profile is not large!

Example 1.6 Instead of approximating the charge density profile by an abrupt transition region, a better approximation would be to have a linear approximation to the transition region as illustrated below for a PN junction with same value of doping in both N and P regions.

Obtain expressions for electric field and potential Integration of Poisson's equation in regions 1 and 2 and matching the electric field at the boundary gives

The maximum electric field is given by the expression:

Integration of electric field with the condition that the net voltage across the space charge region is , gives

Example 1.7 So far we have discussed PN junctions in which both P and N-regions are made out of the same semiconductor. Let us consider next an heterojunction and sketch its band diagram at equilibrium and find its barrier height.

Figure below shows the band diagram of the two semiconductors, when they are far apart.

Using the principles described earlier, the band diagram after equilibrium can be sketched as

There exists a discontinuity in conduction band and valence band at the junction. Their magnitudes can be expressed as

where

is the difference in the bandgaps of the two semiconductors

The barrier height can be determined by performing an analog of Kirchoffs law. We start from a point at Fermi energy in the P-type GaAs far from the junction and arrive again at the Fermi energy but on the side of N-AlGaAs, again far from the junction and add up all the energy increments along the way:

The first term is the usual term that is present in the expression for built-in voltages of homojunctions also. The second term is the additional term that results from the presence of conduction-band discontinuity.

I - V characteristics in Reverse Bias

A PN Junction is said to be in Forward Bias when the P-type region (Anode) is made positive with respect to the N-type region (Cathode). A PN Junction is said to be in Reverse Bias when the P-type region (Anode) is made negative with respect to the N-type region (Cathode). Let us consider the Forward bias first and examine qualitatively the mode of operation

The holes are required to move from

and electrons from

There are plenty of holes in P-type region and would like to move to N-region via diffusion but are prevented by the electric field (or the energy barrier) at equilibrium. The drift and diffusion currents cancel each other

Similarly, there are plenty of electrons in N-type region and would like to move to P-region via diffusion but are prevented by the electric field (or the energy barrier) at equilibrium. The drift and diffusion currents again cancel each other.

The application of forward bias reduces the barrier and the electric field allowing significant electron and hole current to flow:

The fraction of electrons that are able to cross over to the P-side or the fraction of holes that are able to cross over to the N-side and contribute to current goes exponentially with the barrier height (remember, )

Current increases exponentially with the applied forward bias. Reverse Bias:

The holes are now required by the applied bias to move from as shown below:

and electrons from

Although the electric field favors the flow of holes to the P-region, there are very few holes in N-region to begin with! The number of holes in N-region is , a very small number. Further, the number of holes is fixed and unaffected by the bias. Similarly, the number of available electrons in P-region for current flow is very small and unaffected by the applied bias. The only thing that the applied reverse bias does is to increase the junction electric field or the barrier height as shown below

The increased electric field does not alter the current flow because the bottleneck is the small number of carriers available for current conduction. Current in Reverse bias is very small and almost constant Static I-V Characteristics: The dc current-voltage characteristics of the PN junction diode will be obtained using the semiconductor equations listed below:

In steady state, the continuity equation reduces to

Since for every electron lost/generated due to recombination/generation, there is a corresponding hole lost/generated also

In other words, the net current flowing through the device is the same everywhere.

Since the current is the same everywhere, one can choose the region within the device for calculation of current-voltage characteristics. Big Question : Where in the device should the current be calculated such that its computation besides being easy is also accurate ?

Let us consider some alternatives: (i) At the junction:

To appreciate the ease or difficulty of carrying out the computation in this case, let us consider a symmetric junction with

The net electron current is equal to: The drift and diffusion currents oppose each other so that

Let us try to estimate the magnitude of the drift component:

Because of symmetry n(0) = p(0) at the junction

Further :

Assumption (i) : All the voltage is dropped across the junction: with the junction Net voltage across the junction = Assumption (ii) : Depletion approximation

For a forward bias of 0.6V, the electron drift current can be calculated using the results obtained as equal to

As we shall see later, the net electron current flowing through the junction for this device at a forward bias of 0.6V is

Because the drift current( ) is five orders of magnitude larger than the net current, the drift and diffusion currents would have to be calculated to an accuracy of .001% to obtain a correct estimate of the net electron current! This makes the estimation of total current via an analysis at the junction virtually impossible!

Let us consider a region for estimation of current which is far from the junction in say N-type semiconductor. Far from the junction, on the N-side, the current is expected to be primarily an electron current. Any holes which are injected from the P-side would recombine and disappear away from the junction. The electron density being constant, the electron current would be primarily a drift current so that

It might appear that this is a very good place for estimation of current because we have just one component and only one unknown , the electric field .

However, this electric field is extremely difficult to estimate because of its very small value. The voltage applied across the diode gets dropped partially across the junction and partially outside it

where the last two terms represent the voltage dropped across the neutral N and P-regions

The bottleneck for current flow in a PN junction is the space charge region where the potential barrier exists. As a result, is almost equal to the applied voltage

While it is easy to compute the junction voltage fairly accurately, the estimation of residual

drops in the neutral regions becomes very difficult.

The two examples discussed earlier illustrate that the choice of position in the PN junction for computation of its I-V characteristics is very important. As first demonstrated by Shockley, the computation of currents in PN junction diode is best done at the edges of depletion region as explained below:

During the course of the analysis, several assumptions will be made. There are two ways of justifying these assumptions. One of them is: (i) Make the assumption (ii) Solve the resulting simplified equations to obtain the current-voltage characteristics (iii) Check that the assumptions made are consistent with the results obtained. The assumptions made will be consistent only for certain range of currents, so that the range of validity of the model will be obtained.

The other approach is to justify the assumptions in the beginning of the analysis, based on available device characteristics. These assumptions would define the range of validity of the obtained model. We shall follow a mix of these two approaches

Assumption (1): Negligible recombination within the Junction We shall justify this assumption using the first approach, namely that the assumption would be shown to be consistent with the results obtained within certain limits. All the ho;es that are injected at reach the point so that Similarly all the electrons that are injected at This allows the total current to be expressed as : The total current can be computed by computing the minority carrier currents at the edges of depletion region in N and P-regions reach the point , so that

Assumption (2) : Minority carrier current is largely diffusive We shall justify this assumption using the second approach, namely that the validity of this assumption will be demonstrated prior to analysis. This is described in Appendix A.

The assumption implies :

The task of computing the currents boils down to the computation of minority carrier profiles: p(x) in N-region and n(x) in P-region.

The minority carrier profile can be determined by solving the continuity equation with appropriate boundary conditions For hole density in N-region:

In Silicon, the dominant recombination mechanism is the Shockley-Hall-Read recombination which can be described by the relation

under low level injection conditions.

is the hole recombination lifetime in N-type material.

The hole continuity equation can be re-written as

where has the units of length and as we shall see later is appropriately called the hole diffusion length Boundary Conditions:

assuming ideal ohmic contact . Solution:

Similarly for the N-side:

where

is called the electron diffusion length.

Boundary conditions:

assuming ideal ohmic contact

There are two extreme cases: (i) Wide Base diode: For this case, the minority carrier densities can be simplified to:

The minority carrier densities decay exponentially with the distance from the junction, with a characteristics decay length of

for holes and

for electrons.

It can be shown that the average distance a hole diffuses before recombining is equal to so that it is called the diffusion length.

The other extreme case is : (ii) Narrow Base diode: The minority carrier profile can be simplified to

The carrier densities vary linearly with position now !

The total diode current for wide and narrow base diodes can be expressed as Wide base diode:

Narrow base diode:

The task of determining the I-V Characteristics now reduces to finding a relationship between the minority carrier densities at the edges of depletion region and the applied voltage. We start with the relation:

where quasi-neutrality

The low level injection assumption invoked earlier can be used here also for simplification. The first obvious consequence is that

So that the first term on the LHS of the above expression can be neglected.

The second consequence of low level injection, explained in detail in Appendix A is that

for for

in the N-region and the depletion region in the P-region and the depletion region

The quasi-Fermi level on the N-side must coincide with the Fermi level of the metal forming the ohmic contact to the N-side if an ideal contact with no voltage drop across it is assumed. Similarly, the quasi-Fermi level on the P-side must coincide with the Fermi level of the metal forming the ohmic contact to the P-side if an ideal contact with no voltage drop across it is assumed. Since a voltage V is applied between the two ohmic contacts:

This allows the minority carrier densities at the edges of depletion region to be expressed as

The total current density for the diode at a bias of V volts can now be expressed as Wide base diode:

Narrow base diode:

The current varies exponentially with applied voltage when the diode is forward biased (V > 0) The current is constant and small when the diode is reverse biased (V < 0)

Example 2.1 A uniformly doped Silicon PN junction with very thick P and N regions has the following characteristics:

For a forward bias of 0.626 Volts, calculate, excess minority carrier concentrations and minority carrier currents at the edges of depletion region. Calculate also the net current flowing through the device. Solution : The wide-base diode is model valid here. Using the expressions derived earlier:

The net current is the sum of electron and hole current = 0.56+0.44 = 1 mA.

Example 2.2 For the example above, determine expressions for (a) majority carrier currents in N and P-regions (b) majority carrier diffusion currents in N and P regions (c) majority carrier drift currents in N and P regions (d) electric field in the N-region (e) minority carrier drift currents. Confirm that they are much smaller than minority carrier diffusion currents calculated in example 2.1 Solution: We will carry out the solution for the N-region since the solution for P-region is similar. The minority hole current in N-region can be written using the results of previous example as:

The hole current is primarily diffusion current and the sum of hole and electron currents is equal to the total current. The electron current on the N-side is therefore simply:

The electron diffusion current can be written as:

Using the concept of quasi-neutrality in the N-region :

, so that

The electron diffusion current can therefore be expressed as

The term in the bracket is simply the hole diffusion current which has already been obtained earlier:

The electron drift current can be written as

The low level injection assumption holds true in this case because so that

An electron mobility of 800 was assumed. Let us calculate the hole drift current at the depletion edge where there is an electric field of 28.7 mV/cm. The hole drift current is which is much smaller than the diffusion current component.

Example 2.3 A PN junction diode has the same characteristics as that of example 2.1 except that the thickness of the N region The thickness of the P-region remains very long. Calculate the total current flowing through the diode.

Solution : This is an example of a diode that can neither be considered a fully wide-base diode nor a fully narrow-base diode. On the P-side, the diode is very thick so that we can use the expression for electron current valid for wide base diodes. Therefore as before. On the N-side so that the narrow-base model can be used

The net current will be 0.44 + 25.2 mA = 25.64 mA. The current is predominantly determined by the narrow base side of the junction.

Example 2.4 Suppose the P-side thickness is also reduced to current flowing through the diode again.

. Calculate the total

Solution: This diode can be modeled as a narrow-base diode. We have already calculated the hole current in example 2.3 which remains the same. The electron can similarly be calculated as

The net current will be 12.32+25.2 = 37.5 mA This current is significantly higher than that calculated for wide-base diode in example 2.1. This illustrates that for comparable doping values, narrow-base diodes provide higher current for the same bias or equivalently have a smaller turn-on voltage.

The expression for current was derived on the basis of two assumptions: (i) negligible recombination within the depletion region

(ii) low level injection within N and P-regions These assumptions limit the range of validity of the derived expression. The first assumption determines the lower limit, while the second assumption determines the upper limit. Lower limit: As stated earlier, this is determined by neglect of space charge recombination. If the hole continuity equation is integrated across the depletion region, we obtain the relation

where Eq.(80) implies that the correct expression for total current should be

In other words

So as long as

, the neglect of SCR recombination is justified

So what we need to do first is to get an estimate for the SCR recombination current: We shall use a simple model for the Shockley-Hall-Read recombination:

The recombination is assumed to take place via a single deep level at the midgap with equal hole and electron recombination lifetimes Within the depletion region:

where the definition Noting that either p(x) or

has been used :

Because of the exponential dependence of p and n on the voltage (which varies quadratically with x ), the function is a rapidly varying function of the form shown

below:

The recombination rate would have a peak value where the factor maximum value. Since pn = constant,this would occur when

attains a

The sharp variation of U implies that most of the recombination current comes from a small region around the peak value. This allows the following simplification to be performed:

In appendix C, this relation is derived more rigorously, where it is also shown that

where occurs.

is the magnitude of the electric field at the place where peak recombination

Let us now determine the condition under which

Substituting the expressions for condition:

and

derived earlier, we obtain the following

So as long as

recombination within the SCR can be neglected within ~10% accuracy and the ideal diode equation can be used.

For values of current

, the diode current would be determined primarily by the SCR

recombination current. If we compare this recombination current with ideal diode current, we can see two major differences: (i) The ideal diode current increases as while the recombination current increases

as The other way of stating this is that the ideality factor defined as

is unity for ideal diode current and 2 for SCR recombination current. (ii) The SCR current goes as , while the ideal current goes as and is independent of lifetime for narrow base diodes. for wide base diode

It is for this reason that the SCR current is considered as an index of material quality because the recombination lifetime is very sensitive to fabrication conditions.

The upper limit for the validity of ideal diode equation is determined by the assumption of low level injection condition. This low level injection condition will first break down for the region which has the smaller doping level. We shall assume, for the sake of discussion, that N-region is the lightly doped region.

The low level injection assumption had allowed the following simplifications to be made: (i) Minority carrier current is diffusive

(ii) The expression as (iii)

to be simplified

The major departure in I-V Characteristics is caused by the breakdown of (ii) and (iii) relations because they are associated with an exponential factor.

When , the actual minority carrier density at the depletion edge is about 10 % smaller than that predicted by the simplified expression.

The (iii) simplification amounted to neglect of the IR drop in the N-region. This drop is negligible when

The expression for current under these conditions remains valid so that for wide base diode

for wide base diode All these limits are comparable in nature so that for ca be assumed to be valid. The upper limit for the validity of the ideal equation is then: for wide base diode (95) for wide base diode (96) , the ideal diode equation

So for

, the ideal diode equation remains valid.

Example 2.5 Calculate the range of validity for ideal diode equation for a wide base diode described in Example 2.1.

Solution : For simplicity, we take

in Eq. (88) to be

at V=0.6Volts

For this example, the ideal diode equation is valid over five orders of magnitude variation of current. It is because of the wide range of validity of the final equation, that the assumptions of negligible SCR recombination and low level injection are such good assumptions!

Example 2.6 For a forward bias of 0.326 Volts, calculate the ideality factor of the current for a PN junction described in Example 2.1 Solution : In general, the current consists of two components; one kT-like ideal diode current with ideality factor 1 and another 2kT-like space charge generation/recombination current with ideality factor 2:

Using Eq. (78) and Eq. (89) we obtain I(kT) = 10 nA and I(2kT) = 11 nA n = 1.35

Example 2.7 Determine expression for current in a wide-base

junction illuminated with .

light. For simplicity assume that there is a uniform carrier generation rate Solution : For a

diode, the current would be determined primarily by hole injection into

the N-region so that under low level injection conditions:

The hole continuity equation now includes an additional term due to optical generation rate:

The hole continuity equation can be re-written as

The solution of this equation gives: As before: The net current can be written as:

Thus the current includes an additional component due to light which represents the current due to flow of carriers generated effectively within a distance of one diffusion length of the depletion edge. There would be an optical generation current due to generation within the depletion region as well which can be written as , where W is the total depletion width. Since depletion width is often much smaller than diffusion length, this component can be neglected. However, in some especially designed PIN diode structures, this component is the dominant current.

Example 2.8 In the analysis of narrow base diodes, it was assumed that the excess carrier density at the contact is zero. This however is true only if the contact can be assumed to be ideal. For practical contacts, the excess carrier density may be small but is nonzero. These contacts are characterized by a parameter called surface recombination velocity, which for holes can be defined as

(a) Derive an expression for current in a diode using the above boundary condition (b) Determine the value of SP that is needed for a contact to be considered ideal. Assume a diode with

Solution :

Using the boundary condition at the contact: current:

, we obtain the final expression for

(b) The first term represents the standard current expression, while the second term represents the modification due to finite recombination velocity. The equation above shows that as , the expression becomes identical with that derived for ideal contacts. Thus an ideal contact is one with an infinite recombination velocity. More practically when the factor , then the contact could be considered almost .

ideal. This condition for the values given translates into

Appendix A

The assumption that minority carrier current is largely diffusive can be shown to be true provided low level injection conditions prevail within the device:

Consequences of Low Level Injection: In the N-region: In the P-region: We will need another result before we can demonstrate the soundness of our assumption: The regions outside the space charge region are quasi-neutral so that: In the N-region:

Similarly, In the P-region:

We will now show that the minority carrier currents can be assumed to be diffusive provided low level injection condition prevails. Although this result is general, we shall assume that the N and P regions are of comparable doping. This implies that the electron and hole currents close to the depletion edge will also be comparable.

We have already shown that electron and hole diffusion currents are comparable and that for low level injection electron drift current is much larger than the hole drift current in the Nregion so that

Appendix B

To show that Similarly,

in the P-region and within the depletion region. in the N-region and within the depletion region.

We shall first consider the neutral P-region and show that for low level injection conditions, the hole quasi Fermi level can be considered to be almost flat.

We start with the expression: Noting that :

where the integral is over the entire length of the neutral P-region. Since

Noting that the resistance of the neutral p-region is

where A is the device crossectional area, we can obtain

Therefore, as long as the IR drop is sufficiently small, the hole quasi-Fermi level can be assumed to be constant. How much is sufficiently small ? As shown in the main text, the expression which results from making the assumption is

Therefore, as long as

, the error will be less than 10%.

What is this constraint in terms of injection level?

Since

we obtain the constraint:

This constraint would be satisfied if

: the low level injection condition!

That hole and electron quasi-Fermi levels can be assumed to be flat within the depletion region can be demonstrated as follows:

As before, we start with the expression: Noting that within the depletion region

where W is the depletion width

Since, We obtain

So as long as

, The assumption is fine

Since the depletion width is of the order assumption is very well satisfied.

and diffusion length

, the

Appendix C

Substitution of the expressions for electron and hole densities in the expression for current results in

Since most of the recombination occurs within a very narrow spatial region and electric field is a slowly varying function, it can be taken out of the integral with a value at the position of maximum recombination rate ( ).

Substitution of

in the above expression allows the integral to be re-written

The limits of integration correspond to

and

. Upon Integration , one obtains

Substitution of the limits of integration gives

Using the approximation that as

, we obtain the final expression for the integral

The required expression for current can now be obtained by substituting this expression in Eq. (C5) I - V characteristics in Forward Bias

The equation for current flowing through the diode, derived earlier, is given by the expression:

This expression was derived under the assumptions: (i) Low Level Injection (ii) Negligible recombination within the SCR Although the equation was derived in the context of forward bias, much of the derivation remains valid in reverse bias also

In reverse bias, instead of injection of minority carriers in P and N-regions, there is extraction of minority carriers from them. Holes now flow from and electrons from .

As a result, N-region gets depleted of holes and P-region gets depleted of electrons

Since

can have a maximum value of

and respectively,

These are the conditions for low level injection if "injection" is interpreted as having a negative value in this case

Similarly, for the N-side

The spatial variation of electron and hole density is shown below:

The electrons diffuse from the bulk of the P-region to the edge of the depletion region after which they are swept away by the junction field. Similarly, the holes diffuse from the bulk of

the N-region to the depletion region edge after which they are swept by the electric field to the P-region.

The source of electrons in P-region and holes in N-region is thermal generation of carriers. It was shown earlier, in the context of forward bias, that :

This expression is equally valid in reverse bias also, with the difference that the last term now represents generation of carriers within the space charge region, instead of recombination. In Forward bias, we had neglected this term but as we shall see, this term is the dominant term under reverse bias for Silicon PN junction diodes.

Since

within the space charge region:

The negative sign indicates generation ! Over a large fraction of the depletion width, the electron and hole densities are much smaller than the intrinsic carrier density so that

Approximation: This allows the generation current to be written as :

The net reverse bias current can be written as:

The first tem represents the current due to minority carrier diffusion and the second due to generation within the space charge region.

Example 3.1 Calculate the reverse leakage current for a Silicon PN Junction with

Solution : For the reverse bias of 1 Volts, depletion width W=0.26m The magnitude of the diffusion current is The magnitude of the generation current is

The generation current is several orders of magnitude larger than the diffusion current !

The above example shows that for silicon PN junction diodes,

Because the depletion width varies as slowly with increase in the reverse bias.

, the reverse bias current would increase

Example 3.2 In example 3.1 suppose a similar PN junction is made but on a semiconductor with a bandgap of 0.7 eV. Other things remaining the same, will it still be true that the reverse leakage current is dominated by generation current within the depletion region? Solution : The generation current would increase by a factor while the ideal diode saturation current would increase by a factor The two currents are now comparable. For even smaller bandgaps, the reverse leakage current will be determined entirely by the ideal diode saturation current. , .

Breakdown:

The reverse current increases slowly with increase in reverse bias till impact ionization induced breakdown begins to occur within the space charge region. Impact Ionization: An electron or a hole travelling through a region of high electric field can acquire enough energy to create another electron-hole pair. Impact ionization is characterized by a parameter called ionization coefficient: = probability that an electron causes an impact ionization within dx = probability that a hole causes an impact ionization within dx

It is natural to expect that the ionization coefficients would a function of carrier energy and therefore the electric field. There are a variety of models for impact ionization coefficient, simplest of which is : for Silicon (22)

As the reverse bias increases, the electric field within the junction also increases thereby increasing the probability of impact ionization. An electron or hole generated due to impact ionization within the depletion region can acquire enough energy again to cause another impact ionization. The new electron-hole pairs generated can in turn generate further electron-hole pairs. As a result of this process, a single carrier entering the depletion region can get multiplied many times over. This process of multiplication is known as Avalanche Multiplication.

The normal reverse current gets multiplied by the avalanche multiplication process. When avalanche multiplication becomes large, very large reverse current begins to flow and breakdown is said to occur. To obtain an expression for breakdown voltage, it has to be precisely defined. This is explained using the Figure below:

Suppose a single electron enters the depletion region at multiplication, Breakdown :

. Due to avalanche .

, number of electrons will come out at the end

The number of electrons generated within electrons and holes in this region so that

will come from impact ionization caused by the

where n(x) is the number of electrons at x travelling right to the N-region and p(x) is the number of holes travelling left towards the P-region.

Since no holes are assumed to enter the depletion region, p(x) must be due to impact ionization in the region .

An equal number of electrons also must have been generated also so that, the number of electrons that would come out of the depletion region must be:

This allows Eq. (24) to be re-written as:

On Integrating across the depletion region:

The breakdown condition for

can be now written as:

where

The computation of breakdown voltage is simpler if we take a one sided junction such as a P+N junction. For this case:

At breakdown:

The Maximum electric field at the junction when breakdown occurs can be expressed as:

The max. electric field at breakdown is a weak function of doping:

It can therefore be said that whenever the maximum electric field at the junction acquires a critical value of , breakdown would occur. Taking at breakdown allows an estimate of the breakdown voltage to be determined rapidly for any PN junction diode.

Example 2.3 Determine breakdown voltage for a PN junction shown below Assume that = 0.9 Volts

Solution : We first perform a check whether at breakdown, the depletion width still lies in the lightly doped region or not. If it does then, This shows that depletion width will extend into the higher doped N-region as well resulting in the following diagram.

The electric field at

is obtained using the expression

. . + BV so that BV = 40.7 Volts .

Using the Poisson's equation: The area under the electric field curve will be equal to

Example 2.4 Keeping in mind that electron ionization coefficient is larger than hole ionization coefficient , which diode or is likely to have a higher breakdown voltage with identical doping values.

Solution : The question can be answered by examining the electron and hole density profiles within the depletion region generated due to impact ionization. These are shown below:

In the junction, the electron density is maximum near the high field region at the junction and hole density is minimum. As a result most of impact ionization is done by

electrons, while the reverse holds true for lower breakdown voltage.

junction. Therefore

junction will have

Example 2.5 Obtain an expression for the breakdown voltage of a cylindrical PN junction. This is of interest because junctions have a curvature near the periphery which can be considered as cylindrical.

Solution : The Figure below shows the junction.

The Poisson equation in cylindrical coordinates can be written as

Integration of Poisson's equation with the boundary condition that electric field at the depletion edge is zero we obtain

Further integration gives

The expressions above can be used to find the breakdown voltage by using the fact that at breakdown, the electric field is equal to the critical field. The table below shows the breakdown voltages computed for a doping of and different radii of curvature.

As a comparison, the breakdown voltage for a planar junction turns out to be 31 Volts.

The expression for multiplication factor derived earlier suggests that multiplication can be empirically modeled as

The parameter n varies with the structure of the PN junction, with

n=6 for n=4 for

diode diode

The avalanche breakdown is the most common mechanism of breakdown in PN junction diodes. There is another mechanism called Zener breakdown that comes into play in diodes with heavily doped P and N regions. As noted earlier, in reverse bias, the holes are required to flow from the P-side to the N-side and electrons from P-side to the N-side. The reverse current is normally small because there are so few holes in N-region and electrons in P-region. However, there are plenty of electrons in valence band of P-side and plenty of empty states in the conduction band of N-side. Except via tunneling, the electrons from the valence band of P-region cannot flow to empty states in the conduction band of N-side due to presence of a potential barrier When the probability of tunneling becomes significant, large reverse current begins to flow and Zener breakdown is said to occur. The Figure below depicts the tunneling process:

The barrier that the electron sees while tunneling, can be approximated as a triangular barrier as shown below:

The tunneling property can be written as

Use of the triangular barrier approximation gives :

As expected, the transmission probability increases exponentially with the thickness of the barrier which can be expressed as

where is the electric field within the junction.

As doping increases, the electric field increases causing barrier to become narrower and tunneling probability to increase. To achieve significant tunneling, the barrier width should be only a few tens of Angstroms.

The field calculated for Avalanche breakdown was , which is lower than that required for Zener breakdown. It appears, therefore, that avalanche breakdown would always precede Zener breakdown !

However, it is not the electric field but the carrier energy that is really important for impact ionization. A very high electric field in a very narrow region may not allow a carrier to gain enough energy so that impact ionization becomes significant. As a result, Zener breakdown occurs in very heavily doped junctions only with small depletion widths. Because of the small depletion widths, the breakdown voltage, despite the high electric field, is often Volts.

Diodes which have breakdown voltages larger than 7-8 Volts break down due to Avalanche multiplication process. In the intermediate range both the processes may be active. It is possible to determine the breakdown mechanism by measuring the temperature sensitivity of the breakdown voltage. Diodes which break down via avalanche multiplication have a positive temperature coefficient, while those that breakdown via tunneling have a negative temperature coefficient. The increase in avalanche breakdown voltage with temperature occurs due to increased scattering which makes it more difficult for carriers to acquire energy from the electric field. The decrease of Zener breakdown voltage with increase in temperature occurs because of increased carrier velocity which increases the flux of carriers attempting to cross the barrier. Since transmission probability remains unchanged, the tunneling current increases with temperature. Most of the diodes that go under the name Zener diodes have a breakdown via avalanche multiplication rather than tunneling.

Dynamic Characteristics

The I-V model derived earlier is valid under steady state conditions when charges, currents

and voltages are static. To determine the behavior of the PN junction under time varying excitation, we start from the continuity equation where time explicitly comes into picture:

where A is the area of the device. Integrating this equation across the depletion region gives:

By virtue of depletion approximation, the last term is zero. The second term can also be neglected because it is much smaller than the first term while ;

The net current can be expressed as:

The first three are familiar terms. The last term can be rewritten by noting that the junction depletion charge can be expressed as:

Therefore, the net current can be expressed as:

The last term represents the current due to time variation of the junction depletion charge The current due to variation of depletion charge can be expressed as:

where the voltage across the junction

where the voltage across the junction

where is the junction depletion capacitance. An expression for junction dV capacitance can be easily obtained using the depletion approximation and will be discussed later. The net current can now be expressed as:

Let us next look at he minority carrier currents. Under low level injection approximation, they can be assumed to be diffusive so that:

As for the static case, the computation of these currents requires determination of minority carrier profiles, which in turn requires solution of continuity equation. For the computation of p(x), the hole continuity equation in N-region has to be solved:

This is where the other major difference between static and time varying characteristics comes. Unlike the static case, is no longer zero .

For low level injection condition: so that integration of hole continuity equation across the N-region for a long base diode gives:

Far away from the junction, the hole current would be zero so that:

is the diffusion charge due to excess holes stored in the N-region. The first term in the expression above is also present under static conditions and represents the current due to recombination of injected holes. The second term represents the current due to time variation of stored excess hole charge For the N-side also a similar expression can be written:

With these expressions for minority carrier currents, the total current after neglecting the SCR recombination current, can be expressed as:

This representation of the diode's behavior is known as the Charge Control model. The operation of many semiconductor devices can be conceptualized as a two step process where the applied voltage modulates the charge within the device, which then modulates the current.

Just as the term

can be expressed as

, similarly, the time variation of

diffusion charge can be expressed as:

The change in diffusion charge with the applied bias can be represented by a diffusion capacitance defined as

The total device current can now be expressed as

The first two terms represent current due to recombination in N and P-regions respectively, while the last two represent the current due to charge/discharge of junction and diffusion capacitances.

To use the above equation, a relationship between the diffusion charges (and capacitances) and the applied bias is needed. This again requires solution of the continuity equation with the boundary condition that

The continuity equation being a partial differential equation is often difficult to solve analytically. It is often assumed that the minority carrier profile under transient conditions has the same form as that under static conditions. In other words:

This assumption, known appropriately as the Quasi-static assumption is frequently invoked in analysis of other semiconductor devices as well in order to obtain a simplified solution. The range of validity of this assumption will be discussed a little later. Use of quasi-static assumption allows the diffusion charges to be expressed as

The component of current due to minority carrier diffusion and recombination has exactly the same form now as under static conditions:

The diffusion capacitance can be expressed as:

For the simplified case: The final model of current under quasi-static approx. is:

The first term is the conventional diode current, while the last two terms are due to capacitive effects.

The expression for total current shows that current under dynamic conditions is the sum of a current which is identical in form to the static current and currents due capacitances in the device. The development of a dynamic model under quasi-static conditions therefore involves only development of a capacitance model of the device. This model is developed by assuming that charge distribution has a form as under static conditions. The validity of the quasi-static assumption for the PN junction diode can be checked by revisiting the continuity equation:

The quasi-static assumption would be valid if terms on the right:

is much smaller than either of the two

Taking assumption as:

, we obtain the condition for validity of the quasi-static

Similarly, for the N-side

For the excitation

one obtains an upper limit on the excitation frequency:

If the amplitude of the sinusoidal excitation is kept less than the thermal voltage, then quasi static approximation gives reasonable result for frequencies less than

The quasi-static assumption breaks down when the voltage across the diode is abruptly switched as shown below:

The figure above shows a schematic representation of the current waveform that may be experimentally observed: For the sake of simplicity, we shall assume a wide-base diode The charge control

model gives:

The diffusion capacitance, as will be shown later, is much larger than the junction capacitance, so that the last term in the expression above can be ignored. For , when the diode is in steady state:

After the voltage is switched:

The reverse current removes the excess charge stored in the N-region and continues to flow till all charge is removed.

Even though quasi-static approx. is not strictly valid here, nevertheless let us use it to get an estimate of the reverse recovery time.

The QS approx. implies that:

Because of the exponential dependence of charge on diode voltage, the change in diode voltage as the diffusion charge falls from 100% to say 10% of its initial value is less than 60mV and can therefore be neglected. Therefore, the diode voltage and hence the reverse current can be practically assumed to be constant over the entire reverse recovery period. This allows the solution of the differential equation to be written as:

The total time for which the diode remains conducting despite the applied reverse bias can be obtained by substituting in the above expression

The expression shows that the charge storage time carrier lifetime.

is directly proportional to the minority

The accuracy of this expression is questionable because the quasi-static approx. as mentioned earlier is not valid here because of the abrupt reversal in applied voltage.

The quasi-static approx. implies that the form of minority carrier profile remains the same as under static conditions even though the junction voltage is time varying. The charge decay process is therefore modeled as shown below:

The consequence of such a profile is that it predicts almost constant reverse current throughout the transient unlike what happens in reality. Because the current is flowing in the reverse direction at the junction, the expression for diffusion current demands that the slope of the minority carrier profile at the junction be positive and not negative as under static conditions.

The actual minority carrier profile on the N-side during the transient actually looks more like that shown below: The reverse transient can be broken into two phases:

(i) Constant reverse current phase (ii) Decaying current phase

During the constant current phase, the minority carrier density at the depletion edge is non zero: >0. In this situation, the reverse current is primarily determined by the external resistor because (and therefore the diffusion current) can adjust to any value without appreciable change in the diode voltage. This phase of the transient is therefore characterized by a constant reverse current.

When

falls to zero, the minority charge does not reduce to zero as was assumed to

happen in the quasi-static case. There is still a large fraction of stored charge that has to be removed. The reverse current under these conditions is unaffected by the diode voltage because is already zero and cannot be further altered. As a result, current is now determined by the dynamics of the internal hole distribution.

The peak hole density decreases with time causing the reverse current also to decrease. This part of the transient is known as the fall time delay.

An analytical solution of the time dependent continuity equation can be obtained to determine the values of the storage and fall times but for simplicity only the results will be stated here and compared with that obtained using quasi-static assumption.

It can be seen that despite the approximation, the estimate of reverse recovery time using quasi-static approx. is quite accurate if the ratio of forward and reverse current is not too low.

Junction Capacitance

The junction capacitance in the preceding discussion was defined as

To determine an expression for junction capacitance, the incremental change response to incremental change needs to be computed.

in

As a result of the change in junction voltage, an extra charge on the N-side and an equal but opposite charge

will be created on the P-side as illustrated

in the Figure:

The incremental increase in electric field within the junction as a result of these extra charges is

The corresponding change in junction voltage is:

For a uniformly doped PN junction, the depletion approx. gives:

where is the zero bias junction capacitance. The model derived for junction capacitance is based on depletion approximation. The model works well in reverse bias but tends to overestimate the junction capacitance at high forward bias. For the junction capacitance per unit area is

Let us compare this value with the diffusion capacitance: for a wide base For , this turns out to be junction. at a current density of .

Therefore, for current densities larger than the junction capacitance can be ignored in comparison with the diffusion capacitance. Under reverse bias, there is very little diffusion charge and it hardly responds the applied reverse bias so that the diffusion capacitance is practically nonexistent and only junction capacitance matters. The measurement of junction capacitance can yield information on doping density and the built-in voltage. This can be obtained by plotting for uniformly doped junction in the Figure: against the applied bias as illustrated

If the junction is one sided then the doping on the lightly doped can be extracted through capacitance measurements. This method of extraction of doping works even when doping is non-uniform. In this case:

So what is measured in this case is the doping at the edges of depletion region.

By changing the bias on the junction, the depletion edge can be sweeped thereby yielding the doping profile in the semiconductor. The junction capacitance for non uniform doping can be modeled as

where m is known as the grading coefficient and depends on the nature of doping profile. For linearly graded junction, it can be shown to be 1/3.

Example 4.1 A

diode with

is used in a circuit shown below:

Determine the maximum frequency up to which the output voltage can be considered as reasonably well rectified?

Solution : The output voltage can be considered as rectified if the diode conducts for a very small fraction of the time during which the voltage applied is negative. We will take this condition as where is the reverse recovery time of the transistor and can be written as

For the present circuit

Example 4.2 Consider the diode with , and an area of . Which capacitance, depletion will be dominant at the forward current of 0.54mA? Assume that built-in voltage is 0.95 Volts and

Solution : The diode forward voltage required for this current can be calculated to be 0.626 Volts. The junction capacitance can then be calculated to be 1.13 nF. The diffusion capacitance is 21 nF. Hence it will play the dominant role. However, if either the current is reduced or if recombination lifetime were lower, depletion capacitance will also become important.

Example 4.3 Consider a uniformly doped junction. The Silicon out of which the diode is made has a deep donor-like energy level within the bandgap as illustrated below. When the PN junction is forward biased, there are plenty of electrons and the defects can all be assumed to be occupied and therefore, being donor-like, they would be uncharged. When the diode is reverse biased, the depletion region becomes devoid of electrons. Initially the defects remain occupied but slowly they emit electrons and become finally unoccupied and thus positively charged. The charge density within the depletion region will thus vary from an initial value of Determine the resulting change in the depletion capacitance.

Solution : The depletion capacitance be

so that capacitance at t = 0 and t = infinity will

Using these two expressions we obtain Thus by measuring the change in capacitance, the defect density can be measured. Deep Level Transient Spectroscopy (DLTS) is a powerful technique for characterizing defects using the above principle. Equivalent Circuit Device Models

Since a Model is a representation for a specific purpose, there can be two kinds of device models for Circuit analysis: (i) Models to be used with circuit simulation (ii) Models to be used for "hand analysis" of circuits

In the first case, the models have to be as accurate as possible without compromising simulation speed. They can be nonlinear and relatively complex because they are numerically evaluated. In the second case, a simple model that would allow a reasonably accurate estimate of circuit characteristics with minimum computational effort is required. These models are commonly linear and obtained through simplification of more complex models using appropriate assumptions. The models of devices used for circuit simulation are general purpose in nature so that they can be used in a wide variety of situations. This results in their complexity. On the other hand, models for "hand analysis" of circuits have limited range of validity. Due to the requirements of both simplicity as well as reasonable accuracy, several simplifying assumptions have to be used which restrict their range of application. There are a variety of models here, each catering to a specific kind of analysis problem. A model of a PN Junction diode suitable for circuit simulation can be obtained using the general expression for current derived in preceding lectures:

The model can be made more accurate by including a parameter called the ideality factor n, to model the departure of real diode behavior from the ideal diode characteristics. A series resistance can also be included to model the diode behavior more accurately at high current densities.

As mentioned earlier, the model for junction capacitance is not very accurate in forward bias especially as it begins to approach the built-in Voltage. A better capacitance model uses the conventional expression upto

For higher voltages, a different model such as the one given below may be used For

The revised model now has eight parameters which are listed below, along with their SPICE representation and default values.

The SPICE model for the diode includes several other parameters describing the reverse characteristics and breakdown. There are parameters for modeling noise also which has not been dealt with in the present treatment. In all there are at least 15 parameters in the diode model. It is obvious that this model is not suitable for "mental" simulation of circuits. As mentioned earlier, there are several models that are used for different kinds of "hand analysis" problems:

Consider first the dc model:

Even an expression of the form circuit shown below due to its nonlinear nature:

is unsuitable for analysis of a simple

The analysis of the simple diode circuit requires solution of a nonlinear equation:

In such cases the analysis is greatly simplified through use of the following simple diode model: In forward bias:

is frequently taken as between 0.6-0.7 V. The basis for this model is the weak (logarithmic) dependence of the diode voltage on current so that in comparison with other linear elements, the voltage across can be assumed to be constant. If the applied bias is such that is much larger than say about 100mV (expected deviation in diode voltage for currents which are two orders of magnitude different) then the simplified model gives fairly accurate results. The dc model can be used under transient conditions also provided the frequency of the waveform is lower than the inverse of the transit time. In reverse bias the diode can simply be modeled as an open circuit. For situations where the excitation is of the form:

where is the dc forward bias voltage and is the small sinusoidal signal riding on it, a small signal model of the diode is useful. It can be derived as follows:

where

is the net current flowing though the diode has both a dc and an ac component

Eq.(12) can be re-written as

Eq. (13), which represents the relationship between small signal diode current and small signal diode voltage is known as the low frequency small signal model of the diode. For so that the model is simply a resistor

This simplified linear model is used to a great advantage in wide variety of situations .

It is to be noted that the small signal model was obtained basically through linearization of the large signal non linear model. All that needs to be done is a Taylor series expansion of the model equations around a dc bias point. The small signal model for the high frequency case can be quickly obtained by noting that the contributions of the capacitive terms is :

Therefore, the high frequency model is simply the low frequency model along with capacitances in parallel as shown below:

The small signal model is valid only when the small signal diode voltage is much less than the thermal voltage. The table below shows the accuracy of this model for different values of small signal voltage

+0.1 -0.1 +0.5 -0.5 +1 -1

5% -4.8% 30% -21.3% 72% -37%

If the small signal voltage is a sinusoidal voltage, then the small signal model overestimates the peak value on the positive side and underestimates on the negative side. As a result, if peak-to-peak signal value is evaluated, the error even at is less than 10% Another model that is very useful particularly for large signal transient analysis is the charge control model. This model along with its application has already been discussed earlier.

Example 5.1 Can a small signal model be used for the estimation of sinusoidal current flowing through the diode in the circuit shown below. Assume low frequency case.

Solution : The dc analysis of the diode gives a forward current of (5-0.7)/20K = 0.21mA. Let us apply the small signal model and then apply a consistency check. The small signal resistance of the diode will be . The small signal circuit is shown below:

The small signal voltage drop across the 121 resistor (or the diode) will be 11.6mV. Now for the validity of small signal model, this voltage drop should be much smaller than the thermal voltage. This is roughly half the thermal voltage and accoding to the table given in the text, the errors would be of the order of 30%.

Design Perspective

PN junction diodes are used in a wide variety of applications, with each application taking advantage of a different set of diode's characteristics. A few of the applications along with the diode characteristics on which they are base are listed below: Application Switching circuits Mode of Operation Forward and Reverse bias with time varying signals Reverse bias with time Photodetectors varying signals Forward bias with constant Solar Cells excitation Forward bias with time Mixers varying excitation Principle Rectification Sensitivity of reverse current to carrier generation Sensitivity of diode current to carrier generation Nonlinear diode characteristics

Let us consider applications where rectifying characteristics of the PN junction diodes is exploited. In these cases, the following characteristics are of interest: (i) Maximum forward current that can flow through the device beyond which the forward ON voltage begins to increase linearly rather than logarithmically with current. (ii) The reverse leakage current at small reverse bias

(iii) Breakdown voltage BV (iv) Reverse recovery time The desired diode characteristics have to be obtained at the least cost (C) possible Let us consider the tradeoffs among these diode characteristics for a wide base diode Th max. forward current limited by onset of high level injection is determined by the doping in the lightly doped region :

This breakdown voltage can be expressed as

The reverse leakage current is proportional to

The reverse recovery is proportional to

Finally, the cost of diode is proportional to silicon area used so that

The equations listed above can be used to obtain the following expressions

This expression describes a very important tradeoff among the max. current rating, breakdown voltage and cost of a diode It shows that an increase in forward current can only be obtained either at the expense of a lower breakdown voltage or increased cost due to use of larger Silicon area . The expression also shows that high voltage, high current diodes are likely to be the most expensive diodes. Another expression describing another important tradeoff can be written using the equations listed earlier:

This expression shows that an improvement in switching performance can be obtained either at the expense of increased leakage current or a reduced cost. The reduced cost or smaller diode area implies either a lower forward current or a lower breakdown voltage according to Eq. (6) It is interesting to see how breakdown voltage can be traded with switching speed. A reduction in recombination lifetime through say addition of suitable impurities will also increase leakage current. This can be countered by decreasing diode area which however will lead to reduced forward current rating unless doping is increased. This will lead to a reduced breakdown voltage. The breakdown voltage and reverse recovery are also related together in more direct manner. Regions which have higher doping also have a lower recombination lifetime so that a lower breakdown voltage diode is likely to have lower lifetime and better switching speeds.

The two tradeoff expressions can also be combined to obtain another expression shown below:

The expression above shows why a single diode cannot meet the needs of diverse applications. Different applications put different demands on forward current, breakdown voltage etc which can only be obtained through separate designs.

Example 6.1 Design a wide base diode with a breakdown voltage 20 Volts and maximum current handling capacity 100mA. Solution: We shall take diode and assume that and = 1s

Taking the critical field To be on the safe side , we take

we obtain

The maximum current handling capability is determined by the onset of high level injection effects. The maximum current density is

Again to be on the safe side, we take To be considered as wide base diode, the width of N-region should be several times the diffusion length which is 28m. so we take . There is no point in taking a larger value because it would unnecessarily add to the voltage drop in the neutral N-region. The final design is shown below :

Example 6.2 Design a narrow base diode with similar specifications. Comment on the advantages of the narrow base over the wide base diode. Solution : As before, we take At breakdown the junction depletion width should be less than the thickness WN of the N-region, otherwise punch though,discussed in chapter on BJT, would reduce the reverse blocking voltage.At breakdown, the depletion width W can be calculated using the expression

From this we obtain,

W = 2.5m. To be on the safe side, we take

= 3m.

The maximum current density now is Again, to be on the safe side, we take .

Advantages: The area required is an order of magnitude better . Further the transit time of diode now is which is considerably smaller than the recombination lifetime limited transit time of 1s for wide base diode. Practice Problems 1. Electrostatics: Q.1 For a uniformly doped silicon PN junction diode with an N-type doping of P-type doping of 2 x , answer the following questions: and a

(a) Determine the built-in voltage of the junction at T=300K using the expression derived in section 1. (b) Sketch the energy-band diagram of the PN junction at equilibrium and show all the relevant energy values. (c) Determine the total depletion width and its fraction on the N and P-sides respectively at equilibrium. Where will most of the depletion width lie if the P type doping is much larger than the N-type doping? (d) Sketch the electric field within the space charge region and determine its maximum value. By what factor will the maximum electric field increase if the doping in both N and Pregions is doubled? (e) Sketch the potential within the space charge region at equilibrium. What fraction of the built-in voltage is dropped in the N-region? Where will most of the built-in voltage be dropped if the P type doping is much larger than the N-type doping? (f) Determine the magnitude of the depletion width and maximum electric field when the PN junction is forward biased by 0.6 Volts. Sketch the energy band diagram. (g) Determine the magnitude of the depletion width and maximum electric field when the PN junction is reverse biased by 2 Volts. Sketch the energy band diagram. Q.2 A uniformly doped silicon junction diode has an N-type doping of and a Ptype doping of a magnitude such that the Fermi energy in the P-type semiconductor coincides with the valence band. Sketch the band diagram and determine the value of builtin voltage from it. Q.3 For and diodes, obtain simplified expressions for electric field, depletion width and potential from the general expressions derived earlier. Q.4 The electric field within the space charge region of a PN junction is given below:

(a) Where is the junction located? (b) Assuming depletion approximation, sketch the doping profile on the N and P-sides of the junction. (c) Given that the built-in potential of the PN junction is 0.75 Volts, determine whether the diode is in forward or reverse-bias condition? Q. 5 For a uniformly doped symmetrical PN junction with a doping of , determine the following at equilibrium: (a) The position within the space charge region where electron density (n) is equal to the hole density (p). (b) The position within the space charge region where n= 100 p (c) The position within the space charge region where n= 0.01 p Q.6 (a)The doping profile in a linearly graded junction can be described by the expression For x > 0, the doping is N-type and for x < 0, the doping is P-type. Using an approach similar to the one outlined for a uniformly doped PN junction, obtain expressions for electric field within the depletion region and plot it. (b) Obtain expression relating the depletion width to the voltage across the junction. Q.7 In a expression: Silicon diode, the doping in the N region is exponential and described by the

Sketch the electric field within the junction. What is the dependence of maximum electric field on the peak value of doping on the N-side? Q.8 Sketch the electric field within the space charge region of a Silicon diode with the following characteristics: , Intrinsic region I of thickness 1mm. Q. 9 For a uniformly doped doping of and a P-type doping of 2 x heterojunction diode with an N-type , answer the following questions:

(a) Sketch the energy-band diagram of the PN junction at equilibrium and show all the relevant energy values. (b) Determine the built-in voltage of the junction at T=300K

(c) Determine the total depletion width and its fraction on the N and P-sides respectively at equilibrium. 2. DC characteristics : Forward Bias Q.1 For a uniformly doped wide-base silicon PN junction diode with the characteristics given below, answer the following questions:

(a) Determine the magnitude of forward bias voltage required for a current of 1mA to flow. Assume that space charge recombination current is negligible but check the validity of the assumption. (b) Determine the magnitudes of electron and hole currents at the edges of depletion region. (c) Determine the maximum current that can flow through the diode before the ideal diode equation breaks down. (d) Determine the ideality factor of the diode at currents of 1mA, 10A and 1nA. Q.2 A uniformly doped silicon = , junction diode has the following characteristics

, N-region thickness of 0.5m .

(a) Verify that the diode can be modeled as a narrow-base diode. (b) Determine the magnitude of current density at a forward bias of 0.6 Volts. (c) Determine the drift and diffusion components of electron and hole current density and sketch it as a function of position in the N-region. Q.3 A junction diode with same description as above except that the thickness of the Nregion is 20 m. (a) Show that the diode can be modeled neither as a wide-base nor as a narrow-base diode. (b) Using the methodology described earlier for estimation of currents in PN junctions, obtain an expression for forward bias current under low level injection condition. Verify your derivation by checking that your expression reduces to the expressions derived for wide and narrow-base diodes under the appropriate limiting conditions Q.4 (a)The current in a PN junction is a strong function of temperature. Identify the parameters responsible for this dependence and explain which ones may be more important. (b)If the current through a forward biased junction is kept constant, then the voltage across it would change with change in temperature. Show that Neglect temperature dependence of (c)Calculate the temperature coefficient for a Silicon diode at a forward bias of 0.6 volts and T=300 K. Does the sign of temperature coefficient make physical sense? Explain.

Q.5 A Silicon PN junction biased at a constant voltage of 0.65 Volts is brought from darkness into sunlight. Will the current flowing through the device increase or decrease? Give reasons for you answer. Q.6 (a)A steady state forward bias voltage of 0.5 volts was measured across a diode under open circuit conditions. Explain how the diode can be forward biased and still not carry any current. (b)Sketch the minority carrier density on the N-side as a function of position. 3. DC characteristics : Reverse Bias Q.1 The characteristics of a uniformly doped wide-base silicon PN junction diode is given below

(a) Determine the reverse saturation current as predicted by the ideal diode equation. (b) Calculate the space charge generation current at a reverse bias of 2 Volts and compare its magnitude with the value calculated in part (a). What is the net reverse current. (c) If the lifetime is reduced by a factor of 10, what impact does it have on the values of two currents calculated above. (d) How much increase in temperature is required to double the net reverse current flowing through the diode at 300 K. Q.2 (a) A Silicon PIN diode is commonly used as a radiation detector. Among the important characteristics of a Photodetector is its dark current which is simply the reverse current of the diode. Determine the generation/recombination lifetime required to obtain a dark current of about 1nA in a PIN diode of area 0.1 temperature. and i-region thickness of 100 m at room

(b) By how much should the temperature of the diode be lowered so as to reduce the current by one order of magnitude? Q.3(a) For a diode with an N-region thickness of 3 mm, determine the N-type doping required to obtain a breakdown voltage of 50 Volts. Assume that breakdown field is 4 x . (b) Determine the depletion width at breakdown and check that the entire N region does not get depleted so that the expression used is correct. Q.4 (a) A diode with a lightly doped region of thickness 2.5 m is given. Determine the breakdown voltages for the following set of doping values : (b)What is the maximum breakdown voltage obtained and why does breakdown voltage not increase after a certain point even though the doping is lowered? what is the highest doping at which a breakdown voltage which is 90% of this maximum value could be obtained? Q.5 A junction diode is required to have breakdown voltage of 500 Volts. Determine the ) necessary to obtain the

doping of the N-region and the minimum junction depth (

required breakdown voltage.

4. Dynamic Characteristics : Q.1 The depletion capacitance/Area measured for a symmetrical Silicon PN junction at different bias voltages is given below:

(a) Determine the doping of N and P-regions (b) Determine the built-in voltage (c) Determine the depletion width at zero bias Q.2 Using results obtained earlier, show that for a linearly graded junction, the depletion capacitance can be expressed as

where is the zero bias capacitance, V is the applied voltage and of the junction. Q.3 The reverse recovery waveform for a shown below:

is the built-in voltage

diode under abrupt switching condition is

(a) Determine the recombination lifetime in the N-region. (b) How much will be the storage time if the reverse current is increased by a factor of 10

while keeping the forward current same. Q.4 Figure below shows a Si PN junction diode with N-region thickness much larger than hole diffusion length and P-region thickness much smaller than electron diffusion length.

Determine the effective minority carrier lifetime in the diode defined as total minority carrier charge stored in the device divided by the total current flowing through it.

Q.5 A diode is excited with a constant current source as shown below: Obtain an expression for the diode voltage as a function of time after the switch is closed. Use the charge control model with quasi-static approximation, Q.6 The current flowing through a forward-biased diode is suddenly switched off as shown in the figure below:

obtain an expression for the diode voltage as a function of time after the switch is opened. Use the charge control model with quasi-static approximation. 5. Circuit Models Q.1 A uniformly doped wide-base silicon PN junction diode has the following characteristics :

(a) Obtain a suitable value of the cut-in voltage to be used in the simplified dc model of the diode at about a forward current of 1mA. (b) Obtain a high frequency small signal model of the diode at a forward current of 1mA. (c) Determine the admittance of the diode at frequencies of 1kHz and 1MHz. (d) Obtain a small signal model of the diode at a reverse bias of 5Volts. Q.2 Suggest a diode model that is most suitable for analysis of each of the circuits shown below:

Assume a Silicon diode with a turn-on voltage of 0.65 at 1mA and transit time of 1s. Check the validity of your answer by calculating the output voltage in each case and comparing it with the accurate results obtained using SPICE simulations. 6. Design Perspective : Q.1 Two semiconductors A and B have identical properties except that bandgap of A is larger than that of B. What will be the relative advantages/disadvantages of diodes fabricated on the two semiconductors? Q.2 Two Silicon diodes C and D are identical in all respects except that recombination lifetime in C is larger than that in D. What will be the relative advantages/disadvantages of the two diodes. Q.3 Design a diode structure that can be used as a capacitor of a constant value of 10pF1pF for voltages ranging between 0-20 Volts. Your design should be such that the capacitor has minimum area and requires values of doping not less than . Q.4 Design a Silicon diode with a breakdown voltage of 500 Volts and a maximum current handling capability of 1 A. Give the doping and thicknesses of each region of the diode along with its junction area. Bipolar Junction Transistor

Introduction A Bipolar Junction Transistor (BJT) is a prominent semiconductor device used in a wide variety of applications Our discussion of BJT characteristics will proceed in the following order: (1) Basic characteristics of a BJT (2) BJT in forward active mode of operation (3) Dynamic characteristics of BJT in active mode (4) High level injection effects (5) Breakdown in BJT (6) Circuit Models (7) Design perspective Most of our discussion will center around Silicon NPN transistor meant for high frequency applications. The Figure below shows a simplified schematic of a planar npn transistor:

The transistor is fabricated on an N-epilayer grown over a P-type substrate. The P-type base is diffused first. The base diffusion depth determines the thickness of the collector region. This is followed by + N emitter diffusion. This determines both the emitter thickness as well as the base thickness.

An + N buried layer is also used in the collector to reduce the collector series resistance. The contacts for all three layers are formed at the top.

Since several transistors have to be fabricated on the same piece of Silicon, there is a need for isolating each transistor from the other. There are several ways of doing this, one of which is junction isolation. This is done by creating a reverse biased junction between two transistors through diffusion of P-type impurity right down to the substrate.

The doping profile and the junctions are illustrated by the Figure below :

In the schematic of the transistor, three distinct regions can be identified:

(i) Region I: this is known as the intrinsic transistor region where all the interesting things occur

(ii) Region II: this is known as the extrinsic collector-base region. This region provides a contact to the base

(iii) Region III: this extrinsic collector region again serves the role of providing a contact to the collector

Since the transistor action occurs only in the intrinsic region, the other two regions are called parasitic regions. One of the goals in design of transistor is to minimize the area of the parasitic regions to a minimum through process innovation. In most of our discussions on BJT, we shall confine our attention to the intrinsictransistor region and model it simply as that shown below.

The structure of the transistor shows that there are two PN junctions within it; one at the emitterbase junction and the other at the collector-base junction.

However, characteristics unique to a BJT cannot be obtained by simply taking two PN junction diodes and externally connecting them as shown below:

In the circuit above, the two diodes do not interact with each other in the sense that their current-voltage characteristics when they are connected to each is same as that in isolation. If diode D1 is forward biased and D2 reverse biased, then all the current of D1 would flow through the base contact and D2 would be carrying only its reverse saturation current. The base current would be practically equal to the emitter current. Unlike the situation above, where the two diodes function in isolation of each other, the two PN junctions are closely coupled to each other as explained below: Consider the case where the base-emitter (EB) junction is forward biased and base collector junction (CB) junction reverse biased. This mode of operation is known as the forward active mode.

At the EB- junction holes will be injected by the P-type base into the emitter and electrons will be injected by the N-type emitter into the base. The holes injected into the emitter would diffuse and get collected at the emitter contact as expected. However, the electrons injected into the base are not collected at the base contact, which is relatively far away but most of the electrons diffuse to the much nearer CBjunction from where the junction electric field sweeps them into the collector! As a result, a large current flows into the collector despite the reverse bias This is not strange, if it is remembered that in reverse bias electrons are required to flow from PN and holes from NP and current is small not because it is difficult for carriers to move from one region to another due to any barrier but because there are so few electrons in P-region and holes in N-region. The forward biasing of the emitter base junction floods the P-region of the CB diode with electrons thereby increasing the current flow. The collector current would be determined primarily by the electrons injected into the base by the emitter, its own reverse current being extremely small. As expected, this current flowing through the reverse biased collector-base junction will be little influenced by the collector-base voltage but very sensitive to the emitter-base voltage.

The transistor in forward active mode of operation can therefore be represented by the following circuit:

Apart from the expected diodes, the Figure shows a current source F F I a , which represents the fraction of emitter-base current that is coupled into the collector-base junction. As mentioned earlier, the collector current would be very sensitive to the emitter-base voltage and insensitive to collector-base voltage . We have a very interesting situation here of a current flowing between pair of terminals being insensitive to changes in voltage across it but very sensitive to voltage applied across a different pair of terminals!

Because of the prominence of transconductance or its inverse transresistance, the device is appropriately called a Transistor!

One of the tests for any three terminal device being called a transistor is :

A rearrangement of this equation shows that a device which has much larger transconductance as compared to output conductance can exhibit voltage gain.

Just as a fraction of current of forward biased emitter-base junction gets coupled into the collector-base junction, similarly we have a complimentary situation where current of forward biased CB junction will also get coupled into reverse biased emitter-base junction in

what is known as reverse active mode of operation. The circuit representation for the reverse active mode would therefore be as shown by the Figure below :

More generally, it may be expected that a transistor can be represented as :

This is the well-known model of the BJT that can be used to understand transistor operation in different modes of operation. Although the Ebers-Moll representation is a very general one, we shall for the sake of simplicity derive it under the following assumptions: (i) 1D transistor structure with uniform doping in all the regions (ii) Narrow base width so that carrier recombination within base can be neglected (iii) Low level injection condition in all the regions (iv) SCR recombination is neglected (v) Steady state conditions

Using the results derived earlier for PN junctions, the emitter, base and collector currents can be expressed as

The emitter and collector current are composed of electron and hole currents flowing through

their respective junctions. The base current is due to holes injected into the emitter and collector regions.

The neglect of recombination within the base (assumption ii) means that the steady state electron continuity equation simply reduces to

In other words, electron current within the base is constant. All the electrons that are injected from the emitter reach the collector and viceversa.

Use of low level injection assumption means that the electron current in a uniformly doped base can be modeled as a diffusion current alone :

Substitution of Eq. (8) in Eq. (7) gives

The electron density varies linearly within the base so that :

The excess electron densities at the two ends of the base can be expressed as :

The electron current can therefore, be written as :

Without going into the details, the hole current injected into the emitter being proportional to the excess hole density in the emitter, can be written as :

The negative sign indicates that the current is in negative direction. Similarly, the hole current injected into the collector can be written as :

Using Eq. (4-18), the emitter and collector currents can be expressed as :

With these definitions, the Ebers-Moll can be expressed in terms of the following two equations :

Eq. (24-26) can be represented by an equivalent circuit shown below :

The model shows that current flowing through each junction is made of two components : (i) Normal diode current (ii) Current due to coupling of a fraction of current flowing in the neighboring diode. The Ebers-Moll Model can be used to understand transistor operation in all four modes of operation depicted below :

As shown by the diagram, there are four modes in which a BJT can be operated : (i) Forward active Mode: The emitter-base junction is forward biased and collector-base junction is reverse biased.

(ii) Saturation Mode: Both the junctions are forward biased (iii) Reverse active Mode: The collector-base junction is forward biased and emitter-base junction reverse biased.

The forward active mode of operation is the most important region of transistor operation and will be discussed in detail in the next few lectures. This would be followed by a discussion of characteristics of BJT in cutoff and then saturation.

Example 1.1 : The electron density within the base of a uniformly dopde NPN BJT is constant as shown below :

Solution : (a) It is obvious that substantial minority carrier injection has taken place from both the junctions so that both are forward biased and the transistor is in saturation.

(b) Since the electron current in the base is given by the expression N it is zero because the electron density is constant. Let us calculate the hole current IP(x1), injected into the emitter. Using the definition of forward current gain :

forward active mode. To use this expression, we have to calculate the electron current for the same emitter-base forward bias as the present case but the transistor in active mode. In that case, remains the same but so that

n the calculations above, we have used only the magnitudes of the currents into account.The emitter current being composed of hole injection into the emitter would be negative, for the convention that current entering a terminal is taken as positive. Similarly the collector current would be negative and only the base current would be positive.

Example 1.2 : Determine the collector-emitter voltage of the transistor shown below with its collector open circuited.

Using the Ebers-Moll model we obtain

Since 1mA current is flowing through the base and emitter terminals, the emitter-base junction is obviously forward biased so that Using the expression derived above, it is also clear that collector-base junction will also be forward biased so that kT This simplification along with Eq. (a1) allows the collector-emitter voltage to be expressed as Using the reciprocity relationship : as we obtain the final expression

Bipolar Junction Transistor (part II) The emitter-base junction is forward biased and collector-base junction is reverse biased.Ignoring the reverse saturation current of the collector-base diode, the transistor can be represented as:

A small change in the base current would appear in an amplified form at the collector current. In other words, the BJT exhibits current gain and is called its forward current gain.

(Henceforth the subscript F will be dropped. Unless otherwise stated, the mode of operation by default is the forward active mode). Let us look at current gain in more detail: The base current supplies the holes needed to replenish those that are lost from the base due to injection/recombination. It has four distinct components : (i) (ii) (iii) this supplies the holes lost due to recombination in the neutral base region . this supplies the holes that are injected into the emitter. this supplies the holes that recombine within the EB space charge region.

(iv) this represents the holes that flow from the CB space charge region into the base as part of the reverse generation current. The current gain can therefore be written as:

Eq. (5) shows that the component of current gain, which is the least, will determine the overall current gain. Let us try to estimate each one of the current gain components: (i) The base current due to recombination within the neutral portion of the base can be written as

This requires determination of electron density within the base. It was shown earlier that if base recombination is neglected, then electron density varies linearly as shown below:

It may seem strange that we are trying to estimate recombination within the base and using neglect of recombination within the base to find the electron density! However, it must be remembered that an assumption is good or bad depending on the context. It turns out that the profile of electron density in the base with recombination taken into account differs very slightly from the case where it is assumed to be linear, so we are justified in using this assumption.

The base current due to recombination within the base can then be expressed as :

Current gain is proportional to the recombination lifetime in the base and inversely proportional to the base width. The current gain is also independent of collector current.

There is a parameter called the base transport factor, which is closely related to the component of current gain just calculated. The base transport factor is defined as the fraction of electron current, injected by the emitter, that reaches the

collector: The fraction of electrons that do not reach the collector junction are those that get lost due to recombination so that

Example 2.1 : Determine the current gain component due to neutral base recombination for base recombination lifetimes of 1, 0.1 and 0.01 ms. Calculate also the base transport factor .

Solution : The calculated values are shown below :

Example 2.2 : Repeat the calculations for a base width of 5 mm. Solution: The calculated values are shown below :

These two examples show that for a narrow base transistor suitable for high frequency digital and analog circuit applications, the neutral base recombination does not play a role and as result the base recombination lifetime is relatively unimportant. However, transistors designed for power applications have a large base width where neutral base recombination plays an important role and thus it is crucial to obtain high recombination lifetime.

Current Gain Component due to injection of holes into the emitter For a uniformly doped emitter, the hole current can be assumed to be a diffusion current because low-level injection condition is always valid in emitter due to its heavy doping level:

The emitter region is as thin or even thinner than the base so that despite a lower recombination

lifetime, the number of holes lost due to recombination within the emitter can be assumed to be negligible.

is the intrinsic carrier concentration in the emitter. The intrinsic carrier concentration depends on the band gap:

Heavy Doping Effects For small and moderate doping levels, the bandgap is independent of doping. But at higher doping levels, the bandgap decreases with increase in doping level i . Due to different doping levels in the base and emitter, the bandgap and therefore the intrinsiccarrier concentrations will also be different. There are a variety of empirical models for this bandgap narrowing effect, the simplest of which is:

The base current due to hole injection into the emitter can then be expressed as:

Using Eq. (12) and Eq. (22) and the expressions for gain can be expressed as:

, derived earlier, the current

Using the terms to denote the band gap narrowing in emitter and base regions respectively, the current gain can be re-written as :

Use of bandgap narrowing model described by Eq. (21) allows the above equation to be simplified to :

Example 2.3 : Determine the current gain component due to hole injection into the emitter without taking band gap narrowing into account, for the following set of values:

Solution : The current gain without bandgap narrowing will be:

Example 2.4 : Calculate the bandgap narrowing in emitter and base and the resulting changes in intrinsic carrier concentrations. Re-calculate the current gain.

The actual current gain may be larger because recombination velocity at the emitter contact is not infinite. As we shall soon see, this component of current gain is by far the lowest so that the overall current gain is equal to it:

The current gain can be increased by increasing the emitter doping and reducing thebase doping level. The emitter is often doped to the maximum extent possible determined by solid solubility limits so that current gain remains a function of base doping level only. The current gain is independent of collector current if low level injection condition prevails in the base. Example 2.5 : In the example above, suppose the emitter doping is increased to will the current gain increase? By what factor

Solution : For the new emitter doping

The new current gain will

be Although the doping has increase by a factor of 5, the current gain has increased only by a factor of 1.7. The bandgap narrowing in emitter makes the dependence of current gain on emitter doping rather weak. Emitter Injection efficiency A parameter which is closely related to the current gain component efficiency, defined as The emitter injection efficiency is a measure of how efficient the emitter is in injecting electrons into the base. It is important because the entire transistor action is due to the electrons injected into the base. The holes, which are simultaneously injected into the emitter, are useless from this point of view. Eq. (27) can be re-written as : is the emitter injection

Using the expression for

derived earlier, the emitter injection efficiency can be written as,

As noted earlier, the overall current gain is determined primarily by the base current resulting from injection of holes into the emitter. As a result, the current gain can be expressed in terms of emitter injection efficiency :

A high emitter injection efficiency is therefore necessary to obtain a high current gain. The component of base current due to recombination within the emitter-base space charge region can be expressed using Eq. (89) in the chapter on PN junctions as:

It is assumed here that the space charge region lies entirely on the base side because the base doping is much smaller than the emitter doping. Using the expression for collector current given by Eq. (1), we obtain :

This component of current gain is sensitive to recombination lifetime and varies with collector current density.

Example 2.6: Determine the current gain component due to SCR recombination for current densities of Take of , base doping of and effective width of SCR recombination , effective base thickness

Solution : Using Eq. (32) we obtain

The table above shows that for current densities larger than the SCR recombination will not play much of a role. The table also shows that current gain larger than unity can be obtained for current densities as low as which for a transistor area of translates into a collector current of 100pA!. This limit of course is very sensitive to recombination lifetime in the space charge region. The last component of base current is due to holes which are generated in the collector-base space charge region. Unlike other base current components, this current is negative and can be described using the expression for reverse saturation current of PN junction diode:

Since collector is lightly doped as compared to the base, most of the space charge region would be in collector. As a result recombination lifetime for collector has been used. depletion width.

is the collector-base

A quick calculation shows that this base current component is much smaller than the rest and can be ignored. There are however, situations where this current becomes the most important base current component. For example, there are devices called phototransistors, which are basically BJTs whose excitation is optical instead of electrical.

As a result of optical excitation, electron-hole pairs are generated, mostly in the collector-base depletion region. The phototransistor is operated with its base floating so that

The optically excited holes supply the rest of the base current components so that they are nonzero. As we noted earlier, the second component will be the largest so that

The optically excited current gets multiplied by the current gain and appears in an amplified form at the collector.

Overall current Gain Taking all the components of the base current into account, we can draw the following conclusions: i. at very low collector current densities, the current gain is determined primarily by recombination within the emitter-base space charge region. In this regime the current gain increases with the collector-current density and is sensitive to the recombination lifetime in the base. At higher collector current densities, the current gain is determined primarily by injection of holes into the emitter or in other words emitter injection efficiency. The current gain limited by emitter injection efficiency is independent of collector current as long as low level injection condition prevails in the base. As we shall see later, at very high collector current densities, the current gain begins to decrease.

ii.

iii.

The variation of current gain with collector current density can be represented by the following Figure:

I - Low current density II - Medium current density III - High current density Example 2.7 (a) By using the values calculated in earlier examples, determine the overall current gain at a collector current density of (b) At what collector current density, does the current gain fall below unity? (c) If recombination lifetime reduces to the current gain will be practically constant. determine the collector current density beyond which

Solution : (a) The different current gain components are so that the current gain is primarily determined by emitter injection efficiency . ( b) This requires that the SCR limited current gain reduce almost to unity so that sensitive to material purity. This limit is also inversely proportional to and thus is very

(c) If recombination lifetime is reduced to the different components become

then for a collector current density of

If collector current density is increased to will remain constant until high level injection effects set in.

Beyond this the current gain

Most of the time, the BJT is operated in region II where the current gain is constant. In this region, the current gain is given by Eq. (26) (reproduced here again):

As mentioned earlier, the emitter doping is often kept at the maximum allowable limit so as to obtain the highest possible gain. A thin, lightly doped base region is needed to obtain a high current gain. Since emitter is much more heavily doped as compared to the base, the band gap narrowing is stronger in emitter so that Eq. (38) then shows that the current gain will decrease with decrease in temperature due to the exponential term involving band gapnarrowing terms.

Example 2.8 : Determine the injection efficiency limited current gain for the following sets of temperatures:

The table below shows the variation of current gain with temperature predicted by Eq.(38)

The current gain varies significantly with temperature and drops to less than unity at 77 K, which is the temperature of liquid nitrogen. Since liquid nitrogen is readily available at a very low cost, it is one of the most widely used methods of cooling a device. It is of interest to cool a BJT so as to remove excess heat from it. Circuits such as emitter coupled logic (ECL) consume lot of power and their scale of integration is limited by the ability to extract heat generated in the bipolar transistors. A ver simple method of overcoming this would have been to refrigerate the circuit in liquid nitrogen, but as we have seen, the current gain falls to less than unity, making the transistor useless. All the discussion regarding current gain so far has been for the dc current gain. As we shall see later, the small signal current gain is also of interest in many cases

The small signal gain is sometimes also called the ac gain because, the small signal is often a sinusoidal signal in many analysis. The small signal current gain can be expressed in terms of the dc current gain using the following general expressions for collector and base currents:

The collector and base currents have ideality factors respectively. The ideality factor may depart from unity at low or very high current densities.

Using Eq. (39-41), we obtain

The small signal current gain will be different from the dc gain if either the base or the collector ideality factor is different from unity. For example, at very low collector current densities, the base current is dominated by SCR recombination current, which has an ideality factor of 2. Since the collector current has ideality factor of unity at low or moderate currents, the small signal current gain will be twice that of the dc gain. At very high collector current densities, we shall see later, collector current has ideality factor greater than unity, while the base current has ideality factor of unity. In this case the small signal gain will be smaller than the dc gain.

For intermediate collector current densities, the dc gain equals the small signal current gain.

The collector current in active mode of operation for a uniformly doped base is given by the expression:

It appears from this equation as if the collector current is independent of the collector- base voltage. However, this is not so because the effective base width collector bias as illustrated by the Figure below: depends on the

As the collector-base voltage increases, the depletion region associated with the collector base junction widens as illustrated by the Figure above. The base width narrows to As a result of the decrease in base width, the collector current would increase. This base width modulation effect described first by James Early, is known as the Early Effect.

The change in collector current as a result of change in collector-base voltage can be evaluated using Eq. (43)

Using Eq. (44), we obtain

Using the expression for the magnitude of collector-base depletion charge, we can obtain the following results:

Defining a parameter called the Early voltage:

The expression for early voltage shows that its value depends on the collector-base bias but this dependence is weak so that for collector-base voltages not far from zero:

Representing

we obtain

Noting that and base emitter voltage in active mode being less than unity is often much smaller than the early voltage, we obtain

Eq. (54) shows that the collector current would slowly increase with the collector-emitter voltage as illustrated by the Figure below:

Through extrapolation of the characteristics in active mode, the early voltage can be measured! Impact of Early effect on Base current Ignoring the small reverse current of the collector-junction, the base current can be written as

Eq. (22) for collector-base voltage so that

show that these currents have no dependence on the

Use of Eq. (51) allows Eq. (56) to be re-written as:

Eq. (57) can be re-written in terms of the base transport factor

Because of very small value of base transport factor, the voltage so that the base current is much less affected by the applied collector bias as compared to the collector current.

Example 2.9 Determine the Early voltage for an NPN transistor having the following characteristics at Take, of and -5 Volts. base doping of collector doping of effective base thickness

Solution : The collector depletion width and junction capacitance/area can be calculated to be : The early voltage then can be calculated to be: the collector depletion width and junction capacitance become The new early voltage

Non-Uniform Doping

In all the analysis carried out so far, the doping in emitter, base and collector were all assumed to be uniform. However, in most devices, due to the nature of fabrication,

doping in emitter and base is nonuniform, approximating gaussian or error function most of the time. We will next look at the model for collector current when base doping is nonuniform.

As a result of nonuniform base doping, an electric field is present in the base so that the electron cannot be assumed to be simply diffusive. The magnitude of the electric field can be obtained through analysis of the hole current:

This hole current supplies the holes that are injected into the emitter or those that recombine in the base. If the hole current is assumed to be very small so that:

This expression for electric field can be used to write the expression for electron current or equivalently collector current as:

Eq. (62) can be re-written as

Integration of this equation across the base gives:

Since doping is nonuniform in the base, the mobility and therefore the diffusion constant would also vary in the base. This variation, however, is small and represents its average value in the base.

The electron density at the edge of reverse biased collector-base junction will be negligible so that and the electron-hole product at the edge of emitter-base junction can be written as :

Eq. (64) can now be simplified to

Eq. (66) is known as the be derived using this equation later on.

representation of the collector current. A model forBJT will

is known as the Gummel number for the base. Using quasi-neutrality condition for the base:

For low level injection:

so that

For uniformly doped base :

Substitution of Eq. (70) in Eq. (66) gives the same expression for collector current as Eq. (1) that we have used throughout the previous analysis.

Example 2.10 (a) An NPN transistor has a nonuniform doping in the base described by the expression : Assume that average diffusion constant in the base is and that effective base thickness is Determine the magnitude and direction of electric field in the base (b) Obtain an expression for electron density profile within the base (c) Determine the injection efficiency limited current gain at room temperature. Assume that

(a) Under low level injection conditions,

so that

The negative sign indicates that the field is directed towards emitter. It therefore aids in drift of electrons towards the base. (b) The electron current density within the base can be written as

Using the expression for electric field obtained earlier, we can re-write the above expression as

This equation can be expressed as

Integration of the above expression from x to WB with the boundary condition that electron density at the collector end of the base is negligible, we obtain

(c) The expression for current gain can be modified to

For calculating the band gap narrowing in the base, we find the average doping in the base and use it in the expression given in the text. With that we obtain a current gain of 116.

High Level Injection Effects

There are two high-level injection effects that we shall discuss here: (i) High Level injection in Base (ii) High level injection in Collector We shall consider high level injection in the base, also termed as Webster first: effecti,

For simplicity, we shall consider a uniformly doped base. The expression for collector current that has been used in the past discussion was based on low level injection approximation. This approximation allowed the collector current to be expressed as a purely electron diffusion current:

Neglect of recombination results in linear variation of electron density across the base so that

The second simplification that low level injection resulted in was that the expression:

With these three simplifications, the collector current can be written as:

When the injected electron density begins to become comparable to the base doping, the electron current begins to have an appreciable drift component as well. Assuming that the hole current in the base and therefore the base current is small, we can obtain the magnitude of the electric field in the base:.

With this expression, the collector current can be expressed as sum of drift and diffusion terms:

The base is quasi-neutral and uniformly doped as that:

This allows Eq. (7) to be written as

Eq. (9) shows that when injected electron density is much smaller, than the hole density in the base, the current is same as before and diffusive. At very high current densities, so that

In general, the collector current can be expressed as

where Under high-level injection conditions, the approximation made in Eq. (3) is no longer valid so that a full expression for electron density has to be used:

The electron density and therefore the collector current no longer increase as but as ,where the ideality factor is unity for small baseemitter voltages but tends to approach 2 at high biases. The collector current under high level injection can therefore be modeled as

The major impact of high level injection is that the ideality factor of the collector current departs from unity and approaches a value of 2. The base current, being due to injection of holes into the emitter, continues to have an ideality factor of unity because low level injection conditions continue to prevail in emitter due to its heavy doping level. The increase in ideality factor of collector current and a constant ideality factor of unity for base current means that the collector current does not increase as rapidly as the base current with increase in bias. As a result current gain will decrease!

Eq. (15) shows that current gain will decrease with increase in collector current density. For very high collector current densities:

This rapid decrease in current with increase in collector current density means that the device quickly becomes useless since almost all applications require at least a moderate value of current gain.

As a measure of the collector current density at which high level injection effects begin to become appreciable, we take so that

When the injected electron density becomes comparable to the background doping in the base, it begins to affect the collector-base depletion region on the base side also. The charge density given by:

would increase because electron density adds to the charge due to acceptor atoms. This increase in charge density would result in decrease in depletion width on the base side thereby increasing the effective base width.

This base pushout effect, besides decreasing collector current and therefore the current gain, will also tend to increase the base transit time. There is a counteracting effect due to the presence of electric field in the base but in general the onset of high level injection results in degradation of unity gain frequency.

Conductivity Modulation The high-level injection phenomenon is also called conductivity modulation. The conductivity of base can be expressed as

Eq. (21) shows that as the injected electron density begins to become comparable to the base doping, the base conductivity will begin to increase with increase in collector density.

Example 4.1 (a)For an NPN transistor whose description is given below, determine the collector current after which the current gain will begin to fall.

(b)Discuss how can you double the value of maximum collector current. Solution : The collector current density and collector current can be found using Eq. (17) to be and 3.62 mA respectively. (b) An obvious way of doubling the collector current would be to double the transistor area. Besides occupying more area on Silicon wafer, this approach would also double all the junction capacitances thereby adversely affecting the frequency response of the device. Another approach could be by doubling the base doping. This would however decrease the current gain also. A third method could be by reducing the base thickness. This would decrease the Early voltage and as we shall see in the next section also lower what is called the punchthrough voltage of the transistor.

Current Crowding The Figure below shows a simplified schematic of a Bipolar Transistor :

The structure has two base contacts, one on each side of the emitter. As a result of the lateral resistance of intrinsic base region ( ), there will be a voltage drop across it. This means that the potential at the edge of the emitter (point the middle (point ). Since the emitter voltage is the same everywhere, ) will be larger than the potential in

This means that a larger fraction of collector current would flow at the edges than at the center.

This phenomenon will increase as the current increases so that at very high currents, the entire collector current may flow only at the edges. This is known as current crowding. There are several adverse effects of current crowding at the emitter including (i) Since all the current is confined at the emitter periphery, all the power will also be dissipated in a very narrow region resulting in localized heating which may damage the transistor (ii) Since the current flows in a very narrow area close to the emitter edge, the collector current density will become very high resulting in early onset of high-level injection effects. The onset of current crowding effect may be taken as the base current at which the lateral voltage drop becomes comparable to the thermal voltage :

The lateral base resistance can be expressed as

where are emitter length and width respectively. Using Eq. (25) and (24) , the collector current density for the onset of current crowding can be expressed as:

Eq. (26) shows that current crowding decreases as the emitter length is reduced. It is for this reason that high power bipolar transistors are fabricated using a finger like structure with multiple emitter regions sandwiched between base contact regions as shown in the Figure below:

Eq. (26) also seems to suggest that an increase in base doping and thickness will also reduce current crowding due to decrease in base resistance. However, an increase in base doping or thickness will also reduce the current gain. If the expression for current gain derived earlier is taken, then it can be shown that and increases as . is independent of base thickness

Example 4.2 For an NPN transistor whose description is given below, determine (a) the maximum collector current limited by current crowding considerations (b) Discuss different ways by which the maximum collector current can be increased by a factor of 9.

Solution : (b)To increase collector current by a factor of 9, let us increase the transistor area by same factor to 15m x 15m. However, now = 9.55 x so that maximum collector current remains = 2.16 mA. So a simple scaling up of transistor area will not work. Suppose we decrease the emitter length while keeping the transistor area the same so that now the transistor has a rectangular (1.66m x 15m) rather than square geometry. Now the current crowding limited current density increases to = 7.74 x and = 19.44 mA, which is the desired value. However, this approach requires advanced lithography to obtain a dimension of 1.6m, which may pose problems. A third approach could be to use 9 emitter fingers, each of dimension 5m x 5m in a manner shown in the Figure on the previous page. Now remains same at 8.6 x but total collector current increases nine times. There are other ways of increasing the collector current by increasing base doping etc but each comes at a price.

High Level Injection in Collector We shall assume for the most part that collector doping is considerably smaller than the base

doping. As a result, the collector depletion region would lie mostly on the collector side as illustrated by the electric field profile shown below:

The effective doping in the collector is less than the background doping due to the storage of electrons in the depletion region required for flow of collector current.

As the collector current density increases, the effective collector doping decreases resulting in an increase of collector depletion width. This would result in increase of collector transit time and a decrease in unity gain frequency. Eq. (27) predicts an infinite depletion width for a collector current density of

However, the depletion width does not become infinite but simply touches the buried layer. The effective collector doping being zero for this case, the collector can be though of as intrinsic layer. The electric field profile for this case will be

The collector-base junction is like a PIN junction now! With further increase in collector current density, the effective collector doping becomes negative, implying a P-like semiconductor layer. The junction now shifts to the buried layer as illustrated by the Figure below:

With continued increase in collector current density, the depletion region withdraws from the base completely as illustrated by the next Figure.

With even further increase in collector current density, the effective P-like doping increases further so that the space charge region begins to withdraw even from the collector region leaving behind a quasi-neutral collector region called a current induced base! This is illustrated in the next Figure.

The formation of current-induced base further degrades the base transit time and unity gain frequency! The onset of high level injection or the Kirk effect can be taken as the collector current density given by Eq. (28). At this collector current density, the collector becomes like an intrinsic layer!

Example 4.3 For an NPN transistor whose description is given below, determine the collector current after which the high level injection will begin to occur in the collector: and thickness 0.5m followed by a thick heavily doped N-layer. (b) At what current will the current induced base begin to form. Solution : The Kirk current density is given by can then be calculated to be 3.2 mA The collector current

(b) When the current induced is about to form, the collector junction has shifted to the the N-region is like a P-type region as shown below

region and

The effective P-type doping of begins to form now is so that

The total depletion width, when current induced just

This gives which then gives a collector current density of 5.5 x translates into a collector current of 5.5 mA.

This

Cutoff Mode

In cutoff mode, none of the junctions are forward biased so that normally the current is very small and relatively constant with respect to the applied bias. We will consider several bias conditions and determine the magnitude of leakage current for each case.

The collector current is primarily due to thermal generation in the collector base depletion region The electrons generated in this region are swept by the electric field into the neutral collector region from where they flow to the contact. The holes generated are swept into the base from where they flow out of the contact. Let us call this current The current due to generation and diffusion of carriers outside the collector depletion region also contributes to current flow but is usually much smaller than the generation current in the collector junction.

However, this small current results in a non-zero current flowing through the emitter even though emitter-base junction is at zero bias..

Due to reverse bias, the electron density . As a result an electron would flow:

, but electron density at the other end is

This result can also be obtained using the Ebers-Moll model derived earlier. For , the Ebers-Moll Model can be simplified to

Since collector-base diode is reverse biased:

The expression for emitter current agrees with that estimated earlier (Eq. (1)) but the collector current is underestimated by Eq. (2) because of neglect of generation/recombination in the space charge regions during the derivation of Ebers-Moll Model.

(ii) Let us consider a situation where emitter is open junction reverse biased as usual

and collector base

Like the first case, the collector current is primarily due to thermal generation in the collector base depletion region. The generated electrons and holes flow to collector and base contacts respectively.

The emitter junction is slightly reverse biased even though emitter current is zero. This can be understood by noting that if emitter junction were zero biased, an electron current given by Eq. (1) would tend to flow, which is impossible here. To counteract this current the junction gets slightly reverse biased so that the reverse current of the junction cancels this diffusion current. This can also be understood using Ebers-Moll Model :

As usual

. Because the emitter current is zero:

The negative direction of

denotes that emitter junction is reverse biased.

(iii) Base is open, emitter grounded and collector reverse biased

Since the collector-base junction is reverse biased, electron-hole pairs will be generated. While the electrons flow to the collector contact as usual, the holes cannot flow out of the base contact because it is floating. As indicated by the Figure, the only place where the excess holes can go is into the emitter. The injection of holes into the emitter implies forward biasing of the emitter-base junction. For every hole injected into the emitter, several electrons will be injected by the emitter into the base. These electrons would travel across the base and contribute to collector current. The current flowing through the collector will therefore be the sum of the normal generation current due to the injected electrons. The net current can then be written as

The multiplication of collector-base leakage current can also be derived using the Ebers-Moll Model. A zero value for base current implies:

The expression for current gain that is appropriate for estimating the leakage current is the current gain at very low current densities limited primarily by space charge recombination in the emitter junction. The magnitude of this current gain can be significantly smaller than the current gain at moderate collector current densities.

Example 5.1 Determine the reverse leakage currents under open emitter and open base conditions for an NPN transistor whose description is given below:

Solution : The collector depletion width (

)can be calculated to be 0.42

To calculate the current under open base conditions, we need a value of current gain. Let us initially assume that collector current density of . For this value . This corresponds to a . Since this is quite small, so current gain

component will not be very high. This can be calculated using expressions developed in an earlier chapter as

The new value of current gain turns out to be 20, and

= 0.195nA.

The current flowing in the cutoff mode remains small, till impact ionization induced breakdown occurs. We shall consider two cases of breakdown: (i) Breakdown with emitter open circuited and base grounded. (ii) Breakdown with base open circuited and emitter grounded.

The breakdown voltage obtained in the first case will be represented as second case

and in the

Breakdown voltage with Emitter open

In the absence of impact ionization, the collector leakage current is due to thermal generation within the space charge region. The number of electron-hole pairs generated within a narrow region is given by the expression , where

The net current is given by the expression

With the onset of impact ionization, there is an additional source of carrier generation which will also contribute to current flow, so that

The generation rate due to impact ionization can be written as

For equal electron and hole ionization coefficients, Eq. (12) simplifies to :

Eq. (14) and Eq. (10) allow Eq. (11) to be written as:

Eq. (15) can also be written as:

Eq. (17-18) show that the normal reverse leakage current of the transistor gets multiplied by the multiplication factor M. When , avalanche breakdown would occur. The condition for this is:

This is identical to the condition for breakdown of a diode in isolation, so that breakdown of the transistor in this configuration is simply the breakdown of the collector-base diode. The multiplication factor M can be empirically modeled as

where n varies with the structure of the PN junction, whether it is Let us consider the next case of breakdown. Breakdown voltage with Base open

or

etc.

As discussed earlier, due to the requirement of zero base current, the holes generated in the collector depletion region have nowhere to flow but the emitter. This results in injection of electrons by the emitter into the base. These electrons flow into the collector. The net collector current , would therefore have three components: (i) Normal thermal generation current (ii) Current due to generation of carriers as a result of impact ionization. (iii) Current due to electrons injected by the collector Eq. (13) shows that the second current can be expressed as:

where G is given by Eq. (16)

The current injected by the emitter would be times the hole current, which is simply the sum of the first two generation current components. Therefore, the net current can be written as:

Eq. (23) can be simplified to:

where the relation M = 1/1 - G has been used. When avalanche multiplication is small, the collector current is times the current under emitter-open conditions as derived earlier also.

In this case breakdown would occur when

Using Eq. (20) for multiplication coefficient, we obtain

Eq. (26) shows that breakdown would occur earlier with base open due to extra injection of electrons by the emitter.

Example 5.2 Determine the breakdown voltage under open emitter conditions for an NPN transistor which has a collector consisting of a lightly doped region of doping followed by a very heavily doped N-type region. Determine the breakdown voltage for collector thicknesses of 1 , 0.5 and 0.2 .

Solution : Considering base doping to be much higher than the collector doping, the electric field profile in the collector can be sketched as

The breakdown voltage can then be written as

The table below shows the breakdown voltages:

1 0.5 0.2

32.2 18 7.7

It can be seen that the breakdown voltage of cylindrical junctions is lower than that for planar junctions especially for small radii of curvature.

Punchthrough

Punchthrough is another mechanism by which a large collector current can flow in the cutoff mode. Let us consider a case where emitter-base junction is biased at zero volts and collector-base junction is reverse biased. For small collector bias, the depletion regions associated with emitter and collector junctions will be far apart as illustrated below:

The variation of conduction band across the device is also shown. There is a barrier of height which prevents the numerous electrons present in the emitter from flowing into the base and collector. As collector voltage increases, the depletion region extends in the base and approaches closer to the emitter depletion region. Eventually, at a sufficiently higher collector voltage, the two depletion regions would just touch each other as illustrated below:

The collector depletion region has punched through the base and merged with the emitter depletion region. The collector-base voltage at which this phenomenon occurs is known as the punchthrough voltage .

The barrier seen by the electrons is still the built in voltage. However, if the collector voltage is further increased, then the collector depletion region will encroach over the emitter depletion region. The decrease in emitter depletion width will also be accompanied with a decrease in the barrier height.

The barrier height is reduced by an amount base-emitter junction by the same amount.

. This amounts to a forward biasing of the

As a result a large collector current begins to flow. The voltage at which punchthrough occurs can be determined using the relation:

where is the width of emitter depletion region in the base and is the metallurgical base width. The second term in the expression above represents the width of collector depletion region in the base. Using standard expressions for depletion widths, we obtain:

Punchthrough is of importance only if the punchthrough voltage turns out to be less that the breakdown voltage. As expected, this begins to happen when base thickness is reduced.

Example 5.3 : Determine the punchthrough voltage for an NPN transistor having the following characteristics:

(b) How can you increase the punch through voltage without compromising the current gain? Solution : (a) Using Eq. (29), we obtain = 7.6 Volts

(b) Increase in base width or base doping will result in decrease in current gain, so it cannot be used. The only other factor is the collector doping, whose reduction will improve the

punchthrough voltage. The drawback of this approach is that it would lower the maximum collector current density due to early onset of Kirk effect and also increase the collector transit time.

Circuit Models

We will first describe the Gummel-Poon model that is suitable for use with circuit .The model is based on an expression for electron current in the base derived in part II in the context of non uniform base doping:

Eq. (1) can be re-written as:

can be broken into five components as explained below:

Eq. (7) makes use quasi-neutrality approximation. The first term can be expressed as

The subscript 'O' refers to depletion widths at zero bias. The first term is simply The second term represents the change in emitter-base junction charge from its zero bias value, and the third term change in collector-base depletion charge . Therefore,

The second term in Eq. (7) represents charge due to electrons stored in the base. The electrons, in general, can come from either emitter or the collector. This term can therefore be written as sum of two diffusion charges:

The diffusion charges can be expressed in terms of forward and reverse time constants:

Using Eq. (7-12), we obtain

Consider the third tem in the expression above. It can be expressed as:

where as :

is the familiar Early voltage. Similarly, the second term can be written

where

is the inverse Early voltage.

The fourth term in Eq. (13) can be written as:

Similarly,

Eq. (13) can now be written as:

To summarize, the electron current in the base can be written as:

Thus the modeling of electron current requires five parameters:

The emitter current would be the sum of electron current and a hole current which itself can be modeled as sum of two components:

The first component with ideality factor unity represents the hole current injected into the emitter, while the second term can be used to represent the SCR recombination current. The hole current associated with collector-base junction can similarly be expressed as:

is the current gain in reverse active mode. Under static conditions, the emitter and collector currents are sum of electron and hole components:

Eq. (33-34) can be represented by the following circuit:

The model can be extended to dynamic conditions by adding the following capacitances to the above model:

Emitter-base junction: (i) Junction capacitance given by the expression

is the built-in voltage of the emitter-base junction and (ii) Diffusion capacitance given by the expression:

is the grading coefficient.

Collector-base junction: (i)Junction capacitance given by the expression

(ii)Diffusion capacitance given by the expression:

The effects of high level injection into the collector can be modeled using the following empirical expression:

The complete dynamic model can be represented by the following circuit:

The model can be improved by including emitter, base and collector resistances.

The main model parameters of the BJT in SPICE are described below:

Almost all the parameters listed in the table are part of the Gummel-Poon model equations described earlier. The emission coefficients (or ideality factors) for forward and reverse currents were taken as unity in the model but they could be different and are included in SPICE explicitly for this reason.

The base resistance in SPICE is modeled as a variable resistance due to effects such as current crowding. It is modeled as:

is the resistance at zero bias is the minimum base resistance that occurs at high currents. is the current where the base resistance falls halfway to its minimum value.

The parameter is already listed in the table. Two additional parameters need to be inserted to model the variation of base resistance.

Simple BJT Models

The Gummel-Poon model is unsuitable for "hand analysis" of circuits. For this case, a variety of simplified models are used. In the forward active mode of operation, a very commonly used model for dc or low frequency large signals is:

The base emitter voltage is often taken between 0.65-0.75. A model that gives better accuracy but at the expense of being nonlinear is

In saturation mode of operation, circuit analysis is often based on the following simple model:

The base emitter voltage is usually taken slightly larger as compared to the active mode. The collector-emitter voltage is assumed to be a small value around 200mV.

Small Signal Model

A small signal model for the BJT can be derived simply by linearizing the Gummel-Poon model equations around a bias point.

The small signal representation of a BJT in active mode of operation is of particular interest because of its usefulness for analyzing BJT amplifier circuits. For the active mode, the Gummel-Poon model equations in a simplified form can be written as:

Eq. (45) ignores the inverse Early effect at the emitter junction and the high level injection effects in base and collector. In Eq. (46), the term involving has been added to model the effects of base collector voltage on the base current. A small signal model from the above equations can be obtained by writing all voltages and currents as sum of a dc component and a small signal (say ac) component:

Substitution of Eq. (47-48) in Eq. (45-46) and simplification by ignoring all nonlinear second order terms yields the following set of relationships between small signal variables:

Eq. (51-58) describe the well known hybrid-pi small signal representation of the bipolar transistor. The central approximation made in obtaining these equations was

This approximation is good when small signal base emitter voltage is small compared to the thermal voltage. The errors involved in making this approximation were discussed in detail in the context of PN junctions. Eq. (51) and (55) can be represented in the form of a circuit shown below:

The model can be made more accurate by including the series base, emitter and collector resistances. The base and collector resistances can be modeled as sum of an intrinsic resistance and an extrinsic resistance corresponding to transistor area outside the intrinsic region. The junction capacitance corresponding to the reverse biased extrinsic collector-base junction can also be explicitly incorporated in the model.

The capacitance between the buried layer and the P-type substrate (see the Figure below) can also be included to improve the accuracy of the model.

Example 6.1 : Determine the hybrid-pi model parameters for a transistor whose description is given below:

refers to collector-base junction area. Substrate : P-type with doping Take total collector area as 20 times larger than the emitter area. Take base-emitter voltage to be 0.75 V , base-collector voltage as 2V. and collector current as 1mA. Solution : The following results can be obtained using the expressions derived earlier:

The emitter junction capacitance is = 32 pF The intrinsic and extrinsic collector junction capacitances are The model parameters can now be calculated to be:

The intrinsic base resistance For a reverse bias of 2 Volts the substrate capacitance between the buried layer in the collector and P-type substrate can be calculated to be The total capacitance will be

Design Perspective In this chapter, design issues associated with analog and digital circuits will be discussed in brief. To appreciate the design issues, some of the important transistor parameters and their dependence on base and collector doping and thicknesses are summarized below:

A number of important tradeoffs can be seen in the table shown above. Tradeoffs:

Eq. (1) shows that for a fixed base doping, an increase in current gain will be accompanied by an increase in base resistance as well. Similarly, Eq. (2) shows that for constant base doping, an increase in early voltage will result in decrease in current gain.

Example 7.1 Design an NPN transistor that has a current gain of 500 at

=0

Solution : What will be described here is a first pass at design. Various assumptions that are made will have to refined in the next iteration.

We take is We take ,

The corresponding bandgap narrowing in emitter

We will take small doping in the base so as to obtain this high value of gain. As a result BGN in base can be neglected. This gives . We have several choices here for base doping and the resulting

base thickness. Let us take This is the effective base width. Let us calculate the metallurgical base width. For this we will have to calculate the depletion regions within the base due to emitter-base and collectorbase junctions. For the emitter base junction we assume a forward bias of 0.7 volts and built-in voltage of 0.95 Volts. Most of the depletion region will lie in the base so that

Similarly, the depletion width due to collector junction can be calculated:

The metallurgical base width will be The punchthrough voltage for such a lightly doped and narrow-base can be calculated using the expression

This is a very small voltage meaning that transistor can only be operated close to zero collectorbase voltage. The early voltage of the transistor is also very small.Thus a large current gain is obtained only at the expense of very small punchthrough and Early voltages. The base resistance is also very large.

Eq. (1-3) also show that overall transistor characteristics can be improved by increasing the doping level in the base. The base thickness has to be simultaneously scaled to maintain a constant current gain and to improve the base transit time. The transistor area should be scaled so as to reduce the emitter and collector junction

capacitances. A general guideline for improving the performance of a BJT would therefore be: 1. 2. 3. 4. increase base doping reduce base thickness reduce device area minimize the extrinsic transistor region

These tasks have to be done such that: 1. 2. 3. 4. punchthrough does not occur in the base high-level injection does not occur in the base high-level injection does not occur in the collector collector-base breakdown voltage is adequate

In order to appreciate the design issues in more detail, let us first look at the demands imposed on the transistor by some common analog circuit blocks. The Figure below shows a common emitter amplifier(without the biasing network):

The important characteristics of a common emitter include :

Eq. (6-8) can be combined to obtain a single equation:

Since a high voltage gain , a high input resistance and a low output resistance are the desirable characteristics of a CE amplifier, we would like to have a transistor with as high a

current gain as possible.

To improve the upper cutoff frequency, the terms;

Since :

Where

its width (perpendicular to the plane of the paper)

Eq. (15-17) show that frequency performance can be improved by reducing emitter length Le , increasing base doping NA and reducing collector doping NDC. The base thickness has to be reduced even though it tends to increase the time constants described by Eq. (15-16), so as to maintain a constant current gain. Eq. (16) shows that the collector-base junction area should be made close to the base emitter junction area by reducing the extrinsic transistor region. Since collector current is dictated by the circuit, the scaling of device dimensions to improve the frequency performance will be accompanied by an increase in collector current density. Therefore, steps should be taken so as to avoid onset of high level injection effects at the operating current density. The actual design of base and collector regions would depend on the relative importance of different time constants in the expression of upper cutoff frequency. For example, if the amplifier is biased at low collector currents and voltage gain is small, then the time constant described by Eq. (15) may be the most important. If we remember that:

then using Eq. (18) and Eq. (15)

In other words, increase in base doping will have little impact on the frequency performance. The best way of improving the performance will be via scaling of emitter length. Let us consider another situation where the amplifier is biased at large collector current so

that the time constant described by Eq. (17) is the most important. For this case,

In this case, scaling will not have any impact but increase in base doping and scaling of base width will considerably improve the circuit performance. What this example shows is that different transistor characteristic and therefore different designs are required for different circuit applications. In discrete circuits, this can be handled by using different kinds of transistors for different circuits but for monolithic circuits, the same transistor has to be used in all the circuits thereby complicating the transistor design. The importance of high base doping stems largely from the reduction in base resistance that it leads to. Suppose the amplifier shown in the earlier Figure is driven by a resistance RC which is considerably larger than the base resistance as shown below:

To improve the upper cutoff frequency now, the terms; have to be minimized. From the transistors point of view, this means that the capacitances and the base transit time should be minimum. As earlier, for low collector currents and small voltage gain, the term involving emitter junction capacitance will be the most important term. Since, , a base with low doping level will be better ! Let us consider another circuit which is commonly used in analog circuits: an amplifier with an active load:

The voltage gain for the CE amplifier with an active load can be written as:

is the Early voltage, where the subscript N & P denote N and p-type transistors respectively.Similarly,

As before, so that a high current gain is desirable. But now, Eq. (21) shows that a high early voltage is also required to obtain a high voltage gain. The importance of high base doping is even larger here.

The upper cutoff frequency may be dominated by the collector junction capacitance due to very high voltage gain

As a result, the collector junction capacitance acquires the highest importance. Eq. (16) along with the expression for current gain give:

A high doping in the base and low doping in the collector are the requirements now. The base thickness needs to be only slightly scaled so as to maintain a constant current gain.

Example 7.2 Figure below shows an CE amplifier with an active load. Design a transistor for such a circuit such that it has .The transistor should be

able to handle a collector current of 1mA. Solution : As in the previous example, We take The corresponding bandgap narrowing in emitter is

We take We will take small doping in the base so as to obtain the given value of gain. As a result BGN in base can be neglected. This gives . We have several choices here for base doping and the

resulting base thickness. Let us take Suppose we take This gives =14.66Volts which is much smaller than the target value. We cant increase the base width or the base doping because that will decrease the current gain below the specified value of 100. The only option is to decrease the collector doping. If it is reduced by a factor of 10 to .This gives =43.66Volts, which is still short of the target. We could try and decrease the collector doping further but that would create problems. Even for collector doping of injection in collector would limit the collector current density to impacts the unity gain frequency: the high level

. A smaller value of collector current density directly

So far we have calculated the early voltage at zero collector-base bias. If the voltage is calculated for volts which meets the target. Thus the shortcoming of the transistor can be met through circuit techniques. We also need a base resistance less than 1K so that

where Taking

is emitter length and its width perpendicular to the plane of the paper. =280, we find that / =0.1 should be satisfactory.

The current handling capability should be better than 1mA so that . The current density is limited by Kirk effect rather than Webster effect and its value has been calculated earlier. As a result we find that Area = should be satisfactory. Since Area = x . we obtain =3 and =30

Final design: Only the effective base width is given above. With all the doping values available, the corresponding metallurgical base width can be easily determined.

amplifier, transistor characteristics will have to be optimized keeping the requirements of both the circuits in mind.

output stages where voltage swings are larger. Let us next consider the design issues associated with a BJT in a digital circuit. For this we shall take an ECL gate as an example:

For the 10K series gate these values=4mA and total power dissipation A circuit containing just 500 gates would therefore have a power dissipation of 2 W! Among the important characteristics of an ECL gate are: 1. 2. 3. 4. propagation delay power dissipation noise margin Area

The propagation delay is a complicated function of various capacitances and resistance in the transistor. It can be modeled as:

The various time constant and the multiplying factors are listed below:

Example 7.3 Consider an ECL circuit fabricated using a 6

x6

non self aligned BJT having

the following characteristic: The ECL circuit had =400 and a load capacitance of =100fF and a voltage swing =400mV ,corresponding to a collector current of 1mA.Calculate the gate delay and also give a breakup of different factors in terms of their relative contributions to the delay. Solution : The gate delay turns out to be ~316ps. The contributions of some of the important time constants is given below:

The examination of the table shows that among the capacitances, the most important one for this transistor is the extrinsic collector-base capacitance. About 44% of the delay is due to this capacitance. Similarly, terms involving the extrinsic base resistance account for about 42% of the delay. The emitter junction capacitance accounts for about 25.6% of the delay and is the next important capacitance. The forward transit time, which is basically, the base transit time accounts for about 14.4% of the overall delay.

As a result, the approach for reducing the overall delay would be to : i. ii. iii. iv. reduce the extrinsic collector-base area to reduce the extrinsic collector junction capacitance reduce the extrinsic base resistance scale the area to reduce both the collector as well as emitter junction capacitances scale the base width to reduce the base transit time

The transistor described above was a non-self-aligned structure typical of transistors used in

Through use of self-aligned techniques, both the extrinsic base resistance, as well as extrinsic base capacitance can be sharply reduced resulting in overall improvement in delay.

These self aligned structures are described below:

The oxide spacer layer shown in the self aligned structure is very narrow so that the base contact is very close to the intrinsic base region as compared to the non self aligned structure shown in the first Figure. The use of poly silicon facilitates formation of the spacer to isolate emitter and base contacts and also improves the current gain.

Note that the base contact is formed on the Poly which makes the contact with the extrinsic base region. As mentioned earlier, use of self aligned techniques will improve the transistor characteristics and ECL propagation delay through reduction in extrinsic base and collector resistances.

Example 7.4 Calculate the ECL gate delay and determine the relative contributions of different factors for a self aligned transistor described below Also shown for comparison are the characteristics of a non self-aligned transistor.

Both the transistors have dimensions of 6mm x 6mm and are quite similar to each other except for the fact that base is self aligned to the emitter in the second case. Solution : The overall ECL delay reduces to 157ps. The relative importance of different time constants becomes different now!

Examination of the table shows that emitter junction capacitance is the most important one

accounting for almost 32% of the overall delay. The extrinsic collector capacitance accounts for only 8% of the delay.

The base transit time now represents 27% of the delay. The most important resistance is the load resistance of the ECL gate accounting for almost 46% of the delay. The next important resistance is the intrinsic base resistance accounting for about 13.4% of the overall delay.

The ECL delay can now be improved through the following techniques:

void punchthrough and high level injection in the base. On the circuit side, reduction in load resistance will pay rich dividends but it would increase the supply current according to the expression.

where is the voltage swing. Increase in supply current would increase the already high power dissipation in ECL gates and would therefore be counterproductive.

The other way of avoiding an increase in current is by scaling the voltage swing along with scaling of load resistance. This would result in decrease of noise margin. Nevertheless, voltage swing has been reduced in ECL circuits over the years. An increase in supply current may not result in increased power dissipation if the supply voltage is scaled. This trend can also be seen over the years. Even if current is maintained constant, due to scaling of device size, the collector current density inside the BJT will increase so that steps to avoid high level injection in base and collector have to be taken during the design.

The table below shows the relative contributions of different time constants for an ECL circuit fabricated using a selfaligned transistor of dimensions

The overall delay is ~20ps

The base transit time is the most important factor now. It accounts for nearly 47% of the delay.

The emitter junction capacitance now accounts for less than 4% of the delay as a result of scaling. The extrinsic collector junction now accounts for about 7% of the delay and is the most importance capacitance now after the diffusion capacitance represented by base transit time. The renewed importance of extrinsic collector-base capacitance is because the extrinsic region does not scale as fast as the intrinsic region. The other important capacitance is the load capacitance. Its contribution to delay has jumped from 9.5% to 22.2%. The most important resistance is the load resistance again accounting for about 34.5% of the delay. Next to it is the intrinsic base resistance accounting for nearly 14% of the delay. The trend seen so far indicates that with continued improvement in BJT characteristics, the eventual ECL delay would be decided by the term!

The values for various resistances and capacitances for the example under discussion are given below:

These results suggest that delay can be further reduced by: 1. scaling the base thickness to reduce base transit time 2. increasing the base doping to reduce the intrinsic base resistance and avoid punchthrough and high level injection in the base.

The collector current density for the above example is ~4x10 4 A/cm 2 !. The current density for onset of high level injection in collector is ~7x10 4 A/cm 2 for a collector doping of As a result high level injection would also begin to become important now and has to be taken into account.

The scaling of transistor area may not yield much improvement in delay because of the small contributions of area dependent junction capacitances. However, as base doping is raised along with scaling of base thickness, the emitter junction capacitance will increase which can be kept in check through suitable scaling of transistor area. As a result major improvement in transistor performance will now come as a result of reduction in forward transit time through scaling of base width and simultaneously increasing the base doping to avoid punchthrough, high level injection and reducing the base resistance. The collector doping will also have to be raised to avoid high level injection in the collector and to reduce the collector transit time which becomes increasingly more important as base transit time is continually reduced. As the base doping is increased, the emitter-base junction tends to become of type. This junction begins to have a very low breakdown voltage and high leakage currents associated with tunneling. As a result of this, the base doping is limited less than about . This has very serious consequences. If base doping cannot be increased beyond a limit,

then base thickness can also not be scaled beyond a limit otherwise punchthrough would occur. The base resistance would also become constant due to limitation on base doping. This means that transistors performance cannot be improved beyond a certain point.

Example 7.5 Suppose the base doping is limited to What is the minimum base width we can have such the transistor can handle a reverse collector voltage of 5 volts? (b) Will this value of base width be useful for transistor operation? Solution : Using the expression for punchthrough voltage:

We obtain (b) Such a small base width will first of all be difficult to fabricate. But besides that let us look at other consequences. The depletion region due to emitter junction calculated to be 98.5 and that due to collector junction for a collector doping of Thus the effective base width will be This would yield a base transit time of only 0.156 ps which is good but really not necessary when for example the collector transit time for of 0.1 is itself 1.6ps. The current gain for an emitter doping of can be evaluated to be 590 which is also good. and thickness

However, the early voltage is only 16 Volts at zero collector-base bias. Further the sheet resistance of the base can be calculated to be : . For a minimum geometry transistor where is very large. the base resistance will be , which

Increase in effective base thickness to will decrease base resistance to but decrease current gain to 210 which is all right. The base transit time will also increase to about 1.2 ps. The Early voltage will improve to 45 Volts. Thus this would be a betterchoice. But of course it all depends on the application.

The source of this limitation is stemming from the emitter base junction becoming heavily doped junction on both sides. This can be avoided by making the emitter lightly doped to say a doping of around The base doping can be increased now without increasing the tunneling leakage currents. The base thickness can also be scaled now. But a lowly doped emitter and heavily doped base will have a current gain less than unity !. Such a device would be useless for all applications. The expression for current gain shows that there is a way of making a transistor with lightly doped emitter and heavily doped base and still get a high current gain:

Normally due to heavy doping in the emitter as compared to the collector, the bandgap in emitter is smaller than that in the base so that the first term is much less than unity.

However, if we now make the emitter using a material which has a larger bandgap as compared to the material used in the base then a very high current gain can be obtained despite a low emitter doping and a high base doping level. For example, if the difference in the bandgaps of emitter and base is 0.4eV, then for emitter doping of and base doping of the current gain for comparable emitter and base thicknesses turns out to be A BJT which is fabricated using different semiconductors in emitter and base is known as a heterojunction bipolar transistor or simply In an HBT the base doping can be made very high and base thickness very small so that very low intrinsic base resistance and base transit times can be obtained.

Example 7.6 Suppose the base is heavily doped to the tune of and emitter lightly doped but current gain is maintained at a reasonable value through use of wide bandgap semiconductor emitter. What will be the resulting changes in Transistors characteristics as compared to the previous example?

Solution : For a similar effective base thickness of and for the moment ignoring the reduction in mobility as a result of increased base doping, the base resistance will reduce to 260 and Early voltage will increase to 800 !. The unity gain frequency will be determined by collector transit time because the base transit time is so small.

BJT Practice Problems 1. Basic Characteristics and Ebers-Moll Model: Q.1 Figure below shows an NPN transistor which is biased in such a way that the collector current is zero. The electron density profile in the base is also shown.

Q.2 An NPN transistor is biased in such a way that and transistor operating in ? (Note : Current entering a terminal is considered positive here)

Which mode is the

Q.3 Analyze each of the transistor circuits given below and determine all the terminal currents and voltages. Assume that Q.4 Sketch the Ebers-Moll Model for a PNP transistor

2. DC characteristics : Forward Active Mode Q.1 An NPN transistor has the following characteristics

For the emitter, use the bandgap narrowing model discussed in the text but ignore bandgap narrowing for the base. (a) Determine the magnitude of forward bias voltage required for a collector current of 1mA to flow in the forward active mode. (b) Determine the different components of current gain at this current . Which base current component will determine the overall current gain? (c) At very small values of collector current, the current gain is also small. Determine the value of collector current at which the current gain drops to unity. Q.2 Repeat Q.1 for a PNP transistor having the following set of comparable characteristics:

Which transistor NPN or PNP would you prefer for obtaining a high current gain? Q.3 An NPN transistor has the following characteristics:

(a) Using the bandgap narrowing model described in the text, determine the current gain at 300 K. (b) Although the current gain is less than unity at room temperature, show that its value will increase as the temperature is lowered. Determine a temperature at which current gain larger than unity may be obtained. (c) Suppose you had a choice of changing the semiconductor material in the base while keeping emitter as Silicon. What will be the bandgap of the semiconductor needed so as to obtain a current gain of 100 at room temperature? Assume that the hypothetical semiconductor has same characteristics as silicon except for its bandgap. Q.4 On a hot summer afternoon, the following set of values for collector current and base emitter voltages were measured for a constant collector-emitter voltage:

Determine the temperature of the day. Q.5 Three students measured the dc and small signal current gains of transistors that were identical but reported the following conflicting results:

How can you explain the discrepancy? Q.6 An NPN transistor has the following characteristics:

refers to the metallurgical base width i.e separation between EB and CB junctions. The transistor is biased at a constant emitter-base voltage of 0.72 Volts.

Q.7 Without appealing to the expression for Early voltage, explain why a decrease in collector doping will result in an increase in Early voltage. Q.8 Determine the collector current for an NPN transistor with the following characteristics:

The doping in the base is non uniform and shown below:

Show that the value of collector current at 0.72 Volts is same as that obtained in Example 2.1 where the base doping was uniform. Q.9 A phototransistor is a BJT which is operated with its base open circuited. The base current is supplied by the photo-generated carriers. We shall assume that these carriers are uniformly generated in the neutral collector region which is assumed to have a thickness much larger than the hole diffusion length. The generation within emitter, base and collector depletion regions can be neglected. Calculate the collector current if Assume that in the collector region, and forward current gain is 100.

3. Dynamic Characteristics : Q.1 Determine the unity gain frequency at a collector current of 1mA for an NPN transistor whose characteristics are given below

Give a breakup of the contributions of various factors to the collector-emitter transit time. Q.2 Determine unity gain frequency for the above transistor with the change that device dimensions are scaled down by a factor of 10 so that transistors emitter area is now The ratio of collector-to-emitter areas remain the same. Explain why scaling of device area improves the unity

gain frequency? Q.3 Determine the unity gain frequency at a collector current of 1mA for a PNP transistor whose characteristics, given below, are similar to that of the NPN transistor described in

Which transistor, NPN or PNP would you in general prefer to obtain a good high frequency characteristics of a BJT amplifier? Q.4 Determine the base transit time for a transistor described in Q.7 of section 2 of the practice problems.

4. High Level Injection Effects : Q.1 For the NPN transistor described in Q.1 of the previous section, determine the maximum value for collector current before high level injection effects begin to occur. Which phenomenon determines this limit? Calculate the maximum value of unity gain frequency. Q.2 As explained in the text, the decrease in current gain due to Webster effect is also accompanied with a modulation of the base resistivity. Show that the ratio remains constant despite occurrence of high level injection in the base. is the lateral resistance of the intrinsic base region. Q.3 The collector current in the example above can be further increased by increasing the area of the transistor until current crowding begins to occur. Determine the maximum collector current that can flow before this occurs. How would you design the transistor geometry so that this maximum current limit can be increased by a factor of 10. What are the adverse consequences of your suggested changes?

5. Cutoff Mode

Assume that the collector is sufficiently thick to sustain the depletion width at breakdown.

Assume equal emitter and collector areas. The transistor is biased in such a way that base current is zero, emitter is grounded and collector connected to 5 Volts. Determine the collector current and base-emitter voltage. Do not use the Ebers-Moll model for your calculations. Q.3 Calculate the dark current for a phototransistor whose description is given in Q.2. The transistor is biased at

The collector consists of two regions; one lightly doped with a doping of thickness of and another thick heavily doped layer. Q.5 For a metallurgical base width of determine the base doping required to through voltage of 5 Volts

and

have a punch-

7. Circuit Models : Q.1 Two NPN BJTs A and B are identical in all respects except that base thickness of A is twice that of B. Both transistors are biased in forward-active mode with identical collector current and collector-base voltage. Determine which transistor has the larger value for the following parameters: Give reasons for your answer in each case. Q.2 For a PNP transistor whose description is given below, obtain the low frequency small signal model:

What is the range of base-emitter voltage and frequency for which the model is valid? Q.3 One way of representing the small-signal equivalent circuit of a BJT is through hybrid (not hybrid-pi) parameters describe below :

Determine the hybrid parameters in terms of the hybrid-pi parameters. Assume low frequency case for which the capacitances can be neglected.

8. Design Perspective : Q.1 (a) Determine the Early voltage of the NPN transistor whose characteristics are described below :

(b) The early voltage of the transistor needs to be doubled. Determine different ways in which the transistor characteristics could be modified to achieve this. Determine also the consequences of your changes on other important transistor parameters such as current gain, breakdown, punchthrough voltage, unity gain frequency etc. Q.2 Determine the lateral base resistance of the transistor described above. Determine different ways in which the base resistance can be halved and determine the consequences of your changes on other transistor parameters. Note that minimum device dimension is Q.3 Determine the base transit time of the transistor described in Q.1. Determine different ways in which the base transit time can be halved and determine the consequences of your changes on other transistor parameters. Q.4 Design a transistor that has the following characteristics:

Transistor should be able to sustain a reverse collector voltage Volts and collector current of 1mA without going into high level injection conditions. In your design, determine the doping and thicknesses of all the layers and the area of the transistor with the constraint that emitter thickness is less than or equal to base thickness .After completion of design, determine other transistor parameters such as base resistance, unity gain frequency etc. Q.5 Design a transistor, suitable for high power applications, that has the following characteristics:

In your design, determine the doping and thicknesses of all the layers and the area of the transistor with the constraint that emitter thickness is less than or equal to base thickness Note that for this design, you may not be able to neglect recombination in the base. For you calculations assume a recombination lifetime in the base of unity gain frequency of the device. .After the design is complete, determine the

Q.6 Design a suitable BJT for the CE amplifier shown below such that it can have a Input and upper cutoff Assume that the dc voltage at the base is 1.7Volts and dc collector current is 1mA.

Q.7 Design a BJT with the objective of maximizing the unity gain frequency under the constraints :

What are the important factors affecting the maximum value of unity gain frequency and what is the collector current density required to achieve it? In your design, determine the doping and thicknesses of all the layers and the area of the transistor with the constraint that emitter thickness than Q.8 In conventional BJTs such as the one designed above, the emitter doping is kept much higher than the base doping so as to obtain a reasonable current gain. If an emitter semiconductor with a bandgap higher than that of the base semiconductor is used, then the emitter can be made lightly doped and base heavily doped. Carry out the design of this Single heterojunction bipolar transistor (SHBT) so as to obtain the highest possible unity gain frequency under similar constraints of : In your design, determine the doping and thicknesses of all the layers and the area of the transistor with the constraint that emitter thickness is less than or equal to base thickness but while the base doping can be anything, the emitter doping should be less than Assume that the hypothetical emitter semiconductor has same characteristics as that of Silicon with the difference that its bandgap is 1.4eV. What are the important factors affecting the maximum value of unity gain frequency in this case and what is the collector current density required to achieve it? Compare also the value of base is less than or equal to base thickness .And base doping is less

resistance obtained with that obtained for a conventional BJT of Q.8. Q.9 Suppose that you could substitute for Silicon, a wide bandgap semiconductor in the collector as well that has a breakdown field that is double that of Silicon. Carry out the design of this Double heterojunction transistor (DHBT) with identical constraints as above. Compare the performance with a BJT and a SHBT designed earlier.

SCHOTTKY BARRIER HEIGHT Metal-semiconductor junctions can be classified into two kinds: (i) Rectifying Schottky barrier diodes (ii) Ohmic Contacts

Schottky barrier diode is an important semiconductor device in itself with applications including high speed rectifiers, Photodetectors, etc Important part of other devices such as MESFETs, HEMTs etcMetal semiconductor Schottky barrier diodes are used as test structures for measuring doping, defect properties etc. Metal-semiconductor Ohmic contacts are an essential part of all semiconductor devices. We begin our discussions with an analysis of the junction in equilibrium. As a first step,we will determine the energy band diagram of the junction.

We will first sketch energy band diagram for an ideal metal-semiconductor junction having the following characteristics: i. ii. iii. iv.

Semiconductor surface same as bulk No interfacial oxides etc Semiconductor: uniformly doped N-type Silicon Metal: Aluminum The energy band diagram of the junction is determined by first drawing the band diagrams of metal and the semiconductor separately and then suitably combining them. Energy-band diagram before equilibrium

After equilibrium, Fermi levels will align. This will be accompanied with transfer of electrons from semiconductor(higher Fermi level) to metal (lower Fermi level) Far from junction: band diagram of semiconductor same as before Metal unaffected by addition of small number of electrons: following diagram can be easily sketched. can be easily drawn. same as before so that the

Energy-band diagram after equilibrium

As we approach the junction, the semiconductor gets progressively depleted of electrons: bands must bend upwards.

Barrier Height The barrier height can be expressed as:

Whenever two materials are brought into contact, a contact potential develops upon attainment of equilibrium. The contact potential is the difference in their work functions.

Example 1.1 Determine the contact potential for the following sets of metals deposited on N-type Silicon and compare it with experimentally measured values given below:

Solution : Using Eq.(1), we obtain the following set of values: Metal Aluminium Gold Titanium Tungsten Work Function 4.28 5.1 4.33 4.55 Calculated Experimental 0.27 1.09 0.32 0.54 0.7 0.79 0.5 0.67

It can be seen from the table that the theoretically predicted barrier heights do not match well with the experimentally measured values at all. Despite change in workfunctions, the barrier heights do not change as much. Reason for lack of agreement between theory and experiment: Wrong Assumption: Surface has characteristics same as the bulk semiconductor Surface has a large number of energy levels within the bandgap unlike the bulk semiconductor. These energy levels are almost distributed in a continuous manner and are described by surface state density Simple model of a Semiconductor surface: Surface states either donor or acceptor-like, with each kind distributed within the bandgap. Assumption: States above Fermi energy are unoccupied and those below it are occupied Donor states above Fermi energy will be positively charged. Acceptor states below Fermi energy will be negatively charged. Semiconductor surface in general will be charged. The net charge at the surface can be expressed as :

Eq. (3) shows that when charged and when

is zero (at the valence band), then the surface would be positively , the surface would be negatively charged.

is equal to

Concept of a Neutral Level We can find a position for the surface Fermi-level somewhere within the bandgap such that net charge at the surface is zero.

One can define now an energy level called neutral Level N E such that if Fermi energy at the surface were equal to it, the net charge at the surface would be zero.

The first tem is zero by the definition of neutral level and the second term can be written as

Implications of Neutral Level: If the Fermi energy at the surface( surface is zero. ) coincides with the neutral level , net charge at the

Explanation: Compared to the case where between and

, there are now some additional states lying

which are occupied(shaded area)

The consequences of a large surface state density is that Fermi energy at the surface is pinned to the neutral level irrespective of other factors such as doping in the bulk etc Explanation: For simplicity, assume surface state density to be constant This charge must be balanced by charge in the bulk For an N-type semiconductor, positive depletion charge will balance the negative surface charge with energy band diagram as shown:

Example 1.2 : For an N-type semiconductor of doping for surface state densities of

, determine the difference

Solution : This can be obtained using Eq.(13) provided Vbi is known. However, Vbi itself requires knowledge of . We can get around this circularity by assuming some value of Vbi, calculate using Eq. (13) and then with the revise value of built-in voltage evaluate Eq.(13) again. The solution is obtained after a few iterations and is shown below:

The results show that for the Fermi level is almost pinned to the neutral level. It can be verified that if the doping is changed to say , the Fermi level at the surface remains pinned for high surface state densities. The table above shows that for surface state densities less than , there is virtually no band bending and Fermi level at the surface is same as that in the bulk. If surface state density is large(often taken as for most surfaces), then for all practical doping levels, Fermi energy at the surface is pinned to the neutral level. Consequences for Schottky barrier height

Pinning of surface Fermi level at the neutral level implies:

For N-type Si this is about 0.75 eV.

The value given by Eq. (14) also does not agree all the time with experimental values if neutral level is assumed to remain at 0.33 eV

A more sophisticated model i that takes into account presence of interfacial oxide(removal of second assumption) gives a better match with experimental results

All the results derived for N-type Schottky barrier also apply to Schottky barriers on P-type semiconductors as well.

Schottky barrier on P-Type Si

Example 1.3 : Determine the contact potential for the following sets of metals deposited on P-type Silicon using the ideal work function difference theory and compare it with experimentally measured values given below:

Solution : Using Eq.(15), we obtain the following set of values: Metal Aluminium Gold Titanium Tungsten Work Function(eV) 4.28 5.1 4.33 4.55 Calculated 0.85 0.03 0.8 0.58

Experimental 0.58 0.34 0.61 0.45

It can be seen that the workfunction theory does not explain the experimental results at all. According to the workfunction theory the sum of N-type Schottky barrier height and P-type Schottky barrier height should add up to the bandgap. This is roughly true for the experimentally measured values for Gold Titanium and Tungsten but not for Aluminum.

Neither the simple work function difference theory nor the simple Fermi level pinning theory adequately explains the experimental values. A more complicated model that takes into account voltage drop across interfacial oxide gives a better match. Almost all the metals form a junction with Silicon such that a barrier exists for the flow of electrons in N-type material and for holes in P-type material. A consequence of this is that semiconductor near the junction is depleted of carriers and a space charge region exists. The detailed nature of potential variation, electric field, space charge regions width etc can be obtained through the solution of Poisson Equation.

Depletion Approximation Assumptions: (i) Neglect (ii) All donors are ionized (iii) Neglect

within the space charge region

The neglect of electron and hole density within the space charge region is known as thedepletion approximation. The validity of this assumption will be discussed in detail during the study of PN junctions. Charge Profile after depletion approx.

With the depletion approximation, the Poisson equation can be easily solved to obtain the following important results:

Although derived for equilibrium, the equations remain valid for non zero values of applied voltage also, provided depletion approximation is assumed to hold. The only change that needs to be made is to substitute Vbi by Vbi - V , where V is the voltage applied between the metal and the semiconductor.

Example 1.4 : Determine the value of maximum electric field and depletion width for a Schottky barrier on N-type Silicon of doping Solution : . Assume that =0.7eV.

Static I-V Characteristics (part II)

Almost all the metals form a junction with Silicon such that a barrier exists for the flow of electrons in N-type material and for holes in P-type material.

We shall confine out attention to Schottky barriers on N-type semiconductors only

Although the barrier exists for flow of electrons in both the directions (metal-to-semiconductor or semiconductor-to-metal), the nature of the barrier is different. While the barrier to flow of electrons from metal-to-semiconductor remains fixed, the barrier

to flow of electrons from semiconductor-to-metal changes as a bias is applied across the junction. For the case when metal is made positive as compared to the N-type semiconductor, the energy band diagram is shown below:

It can be seen from the Figure that the semiconductor-to-metal barrier is reduced by qVF. In Forward bias, when metal is made positive with respect to the semiconductor, there should be a net flow of electrons towards the metal.The current in general can be expressed as:

Since the barrier to flow of electrons from the metal-to-semiconductor remains unchanged, so the component remains practically the same as at equilibrium.Due to reduction of barrier height for flow of electrons from the semiconductor-to-metal, the current increases substantially causing significant current to flow. When metal is made negative w.r.t N-type semiconductor, the barrier height is increased by qVR as shown in the Figure.

In this case, the barrier to electron flow into the metal has been increased making negligible. Since the barrier to flow of electrons from the metal into the semiconductor remains the same, remains the same at a very low value due to large barrier height. Therefore,the current is small and relatively independent of voltage. Current Path from Ohmic Contact To Schottky Contact

The flow of electrons from the backside Ohmic contact to the Schottky metal can be broken into three distinct parts: i. ii. iii. flow of electrons across the Ohmic contact and the neutral N-region flow of electrons across the depletion region flow of electrons across the Schottky metal-semiconductor interface

We shall assume throughout that any hole current is negligible as compared to the electron current. Electron Flow across Ohmic contact and neutral N-region

We normally want to keep the IR voltage drop as small as possible so that when Schottky diode is ON, the forward voltage drop is as small as possible. Current Flow across the Depletion Region The current flow involves both drift and diffusion currents. The two currents oppose each other with electrons tending to move towards the metal via diffusion and away from the metal via drift. In equilibrium, they cancel each other. As a result of forward bias, the electric field gets reduced making the diffusion current exceed the drift current and causing a net flow of electrons towards the metal.

Using the relation

and integrating after multiplying both sides by

Boundary Conditions

where V is the applied voltage and DV is the drop across the ohmic contact and neutral N-region.

It is not clear as of now what the electron density at the interface should be. The variation of voltage across the depletion region can be determined by invoking the depletion approximation as done under equilibrium:

The depletion width that

is determined by the boundary condition for potential described earlier so

With the boundary conditions listed earlier and the expression for variation of potential across the depletion region, the current can be expressed as :

For typical values of doping and voltages This allows the denominator of Eq. (31) to be simplified as

Eq.(31) can now be written as

Thermionic Emission:

The expression for current can be obtained if the value of n(0) is known. For this we shall have to look at the transport across the metal-semiconductor interface. To begin with, we shall assume that the transport mechanism is predominantly thermionic emission and not tunneling Thermionic emission is one of the dominant mechanisms of current flow across abrupt barriers as illustrated below:

There may be large number of electrons in material-1 but only a few can contribute to current flow and this number will increase as temperature is raised The electrons, which can contribute to current flow, must have the following characteristics:

If the electrons are assumed to be moving randomly, then the current due to flow of electrons from material-1 to material-2 can be written as:

is the density of all the electrons at the interface that have an energy greater than or equal to the barrier height.

VR is the average velocity of electrons in the positive x direction.

Similarly, the flux of electrons towards materla-1 can be written as: is the electron density at the interface on the right side.

The net electron current can therefore be expressed as

With this expression we can now determine the I-V characteristics of the Schottky barrier diode. There can be two extreme cases: (i) current is determined primarily by drift-diffusion flow of electrons

across the depletion region (ii) current is determined primarily by thermionic emission.

The first case implies that the bottleneck to current flow is drift diffusion across the depletion region. If this is true then the current should be much smaller than either the left or the right flux of electrons in the expression for thermionic current. Since the metal can be assumed to remain at equilibrium despite the current flow:

Since the current densities are most of the time several orders of magnitude larger than this, the first extreme case will not hold true at all.

Let us take the other extreme case. In this case, if drift-diffusion is not a bottleneck, then the net current should be much less than either of the two terms in the expression given by Eq.(33)

Substitution of typical values shows that this condition is indeed satisfied, so that it can be assumed that the current is determined primarily by thermionic emission. The above inequality along with Eq. (33) also allows us to write:

The net current density through the diode can be written as

where A* is known as the Richardson constant and has a value of for N-type Silicon. A similar expression holds for current flow in P-type Schottky barriers for which the Richardson constant is for Silicon.

Example 2.1 : For an N-type Schottky diode with barrier height of 0.7eV, determine the forward on voltage for a forward current density of . Compare your answer with a typical value of 0.6 Volts for a Silicon PN junction at a comparable current density. Solution : Using Eq. (42) and assuming negligible voltage drop across neutral P-region we obtain VON = 0. 195 Volts, which is about 300mV lower that PN junction diode,has a reverse saturation current of according to the expression just derived.The forward voltage drop for a

current density of

turns out to be ~0.45V.

Example 2.2 : Repeat Q.2.1 for a P-type Schottky barrier diode with barrier height of 0.58eV. Solution : Using Eq. (42) and assuming negligible voltage drop across neutral P-region at the low current density value, we obtain VON = 0. 195 Volts, which is about 400mV lower that PN junction diode. All nice things however, come at a price! Example 2.3 : Calculate the reverse saturation currents for N and P Schottky diodes discussed above and compare it with a typical value of for a PN junction diode. for

Using the expressions derived earlier, the reverse leakage current turns out to be N Schottky and for P Schottky diode.

Thus although Schottky barrier diodes can have a turn on voltage which is lower by 300-400mV, they also have a leakage current which is 3-4 orders of magnitude higher. The I-V characteristics of the Schottky barrier is very sensitive to the barrier height. The barrier height depends on the applied bias due to a phenomenon known as image-force-induced barrier lowering. In the representation of the energy band diagram of the metal so far, an abrupt barrier of height was shown to exist between the electrons within the metal at Fermi energy and the vacuum level outside. However, in actual practice, the potential varies gradually. When the electron comes out of the metal, it faces an attractive force due to the positive image charge induced in the metal:

As a result of this force the potential energy varies as

The variation of potential energy with distance is illustrated by the Figure below:

In the presence of a constant electric field, the net potential energy can be written as:

The potential energy has a maxima resulting in lowering of barrier height by an amount illustrated in the Figure

as

The analysis carried out for Metal-vacuum system can be extended to metal-semiconductor system as well with the difference that permittivity for Silicon should be used instead of that of vacuum. Example 2.4 : Determine the barrier height of a Schottky diode at equilibrium using image force barrier lowering into account. Assume that Solution : Taking , we obtain Vbi = 0.554Volts and

Use of Eq. (47) gives .Because of the exponential dependence of current on barrier height, this amount of reduction can have a significant impact on the I-V characteristics . For example, if barrier lowering is neglected, then the reverse leakage current will be under estimated by a factor increases. which is ~4 for the present case but will increase as the reverse bias

As a result of barrier height lowering, the reverse current is not independent of voltage but increases significantly with increase in reverse bias. As electric field increases further, avalanche multiplication begins to occur causing rapid increase in reverse current and eventually breakdown occurs. This is explained in more detail later on in the context of PN Junctions. Example 2.5 : Sketch the energy band diagram for the metal semiconductor system shown below using simple work function theory and comment on whether the junction will have rectifying characteristics or not.

In this case the electrons will transfer from the metal into the N-type semiconductor and result in an accumulation of electrons at the surface. The final band diagram is shown below: The barrier height = -0.1 eV is negative ! There is no barrier to flow of electrons either from the metal to the semiconductor or the other way around so that the contact will have ohmic properties. Dynamic Characteristics ( III ) The current-voltage characteristics discussed earlier are applicable when the excitation is constant in time, in other words dc. To determine the behavior under time varying excitation, we start with electron continuity equation:

The terms due to generation recombination have been ignored because this is a majority carrier device. Integration of this equation across the depletion region gives

The last term is zero by virtue of depletion approximation. Noting that

is the conventional thermionic emission current and the second term is due to charge/discharge of the junction capacitance. In the calculation of Thermionic emission current, it is assumed that metal is in equilibrium. However, it does take a finite amount of time for the emitted carriers to attain thermal equilibrium but since this time is very short, it is neglected. Using the expression for junction depletion charge, the junction capacitance can be determined.

The capacitance can be expressed in a form, which is general and applicable to cases,where the semiconductor is non-uniformly doped

where m, called the grading coefficient, has a value of 0.5 for uniform doping. zero bias depletion capacitance.

is the

The dependence of junction capacitance on the doping level is used to measure doping profile in semiconductors. This is described in detail during the study of PN junctions. The measurement of capacitance also allows the built-in voltage and thereby the barrier height of the Schottky diode.

Example 3.1 : Determine the junction capacitance/Area of a Schottky barrier diode on N-type Silicon of doping at a current density of . Assume that . (b) repeat for a current density of Solution: It has been estimated in an earlier example that Vbi = 0.554 Volts and that forward on voltage is equal to 0.28 Volts at estimated using Eq. (53) as (b) An increase in current by three orders of magnitude will require the forward voltage to be raised by Volts so that the new on state voltage is 0.46. The new junction capacitance turns out to be It is interesting that the capacitance increases only by 74% even though the current has increased by three orders of magnitude. Keeping in mind that diodes resistance is inversely proportional to current, this explains why increase in current results in improvement in frequency response. . The junction capacitance can then be

Circuit Models The equation for current under dynamic conditions can be expressed in the form an equivalent circuit as shown below:

The model can be made more accurate by including a parameter n to model the nonidealities in the current caused by modification of barrier height due to image force lowering, tunneling etc

The effects of voltage drop across the ohmic contact and the neutral N-region can be taken into account through a series resistance as illustrated as in the Figure:

This simple circuit model is characterized by five parameters: This model is more useful for use with circuit simulators than for hand analysis of circuits. A variety of simplified models appropriate for different situations are used for the latter. These are discussed in detail in the context of PN junctions. Among the models is the small signal representation of the device representing the response of the diode to incremental changes in applied voltage around a particular bias point: are the dc voltage and current across the is a small signal superimposed on the dc diode voltage and is the small signal and is known as the small signal

diode.

response of the diode. The relationship between model.

The small signal model can be obtained through linearization of the general large signal model described earlier. This procedure is again described in detail with respect to PN junctions and only the result is shown below:

; small signal resistance of the diode. The usefulness of the small signal model stems from its linear nature.

Example 4.1 :Determine the small signal resistance and capacitance of a Schottky diode formed on an N-type Silicon of doping Assume that density of Solution : Using expressions derived earlier in the text, the built in voltage of the diode is calculated to be 0.6 Volts and the forward On voltage to be 0.33 Volts. Assuming an ideality factor of 1, the small signal resistance is calculated to be calculated to be 17.5 pF. The junction capacitance is at a current density of Repeat your calculations for a current

The RC response time of the diode will be If the current density is increased by three orders of magnitude, then the small signal resistance will decrease by but the capacitance as seen earlier will remain relatively unchanged. As a result, the response time of the diode will decrease to a few picoseconds.

This shows that the response time of the Schottky diodes is very small and they can work upto frequencies exceeding 1Ghz !

To summarize, Schottky diodes have the advantages of small turn on voltage, fast response time but suffer from high leakage current and low breakdown voltage.

Circuit Models The equation for current under dynamic conditions can be expressed in the form an equivalent circuit as shown below:

The model can be made more accurate by including a parameter n to model the nonidealities in the current caused by modification of barrier height due to image force lowering, tunneling etc

The effects of voltage drop across the ohmic contact and the neutral N-region can be taken into account through a series resistance as illustrated as in the Figure:

This simple circuit model is characterized by five parameters: This model is more useful for use with circuit simulators than for hand analysis of circuits. A variety of simplified models appropriate for different situations are used for the latter. These are discussed in detail in the context of PN junctions. Among the models is the small signal representation of the device representing the response of the diode to incremental changes in applied voltage around a particular bias point: are the dc voltage and current across the is a small signal superimposed on the dc diode voltage and is the small signal and is known as the small signal

diode.

response of the diode. The relationship between model.

The small signal model can be obtained through linearization of the general large signal model described earlier. This procedure is again described in detail with respect to PN junctions and only the result is shown below:

; small signal resistance of the diode. The usefulness of the small signal model stems from its linear nature.

Example 4.1 :Determine the small signal resistance and capacitance of a Schottky diode formed on an N-type Silicon of doping Assume that density of Solution : Using expressions derived earlier in the text, the built in voltage of the diode is calculated to be 0.6 Volts and the forward On voltage to be 0.33 Volts. Assuming an ideality factor of 1, the small signal resistance is calculated to be calculated to be 17.5 pF. The junction capacitance is at a current density of Repeat your calculations for a current

The RC response time of the diode will be If the current density is increased by three orders of magnitude, then the small signal resistance will decrease by but the capacitance as seen earlier will remain relatively unchanged. As a result, the response time of the diode will decrease to a few picoseconds.

This shows that the response time of the Schottky diodes is very small and they can work upto frequencies exceeding 1Ghz !

To summarize, Schottky diodes have the advantages of small turn on voltage, fast response time but suffer from high leakage current and low breakdown voltage.

Practice Problems 1. Schottky Barrier Height: Q.1 Draw the energy band diagram and determine the contact potential for the following metal/semiconductor systems using the ideal Schottky diode theory.

Of these which will have rectifying and which will have ohmic characteristics. Q.2 Determine the work-function of a metal, which when deposited on an N-type semiconductor with would form a contact with zero contact potential.

Q.3 Draw the qualitative energy band diagram of the Schottky barrier for the following system:

Q.4 Determine the magnitude of doping required such that the voltage drop in the lightly doped N-region is 0.6 Volts. Assume that Schottky barrier height is 0.7 Volts

2. DC characteristics : Q.1 Determine the Schottky barrier height required so that the turn-on voltage of the diode is 0.45 Volts for a forward current of 1 A. Assume that the Richardsons constant is and the area of the diode is Q.2 Schottky barrier diodes are commonly used as gates in field effect transistors (FETs). The gate leakage current under reverse bias conditions is an important consideration in these FETs. For a gate dimension of , determine the minimum barrier height required to obtain a leakage current < 10 pA. Assume that Richardsons constant is . Q.3 Calculate the reverse leakage current of a Schottky diode for reverse voltages of 1, -5, -25, 50 Volts with and without taking Schottky barrier lowering into account. Assume that the Richardsons constant is and the area of the diode is Q.4 The barrier height of a Metal semiconductor junction is 0.3 eV. Using the approach outlined in the text, determine if the current across the diode is dominated by thermionic emission or driftdiffusion across the semiconductor. Q.5 The reverse saturation current for a Schottky barrier diode was measured as a function of temperature:

Area = Estimate the Schottky barrier height and the Richardsons constant. Q.6 Obtain an expression for the temperature coefficient of the forward turn-on voltage of a Schottky barrier diode biased at a constant current . Q.7 Schottky barrier diodes are frequently used as a Photodetector. Suppose an electron-hole pair is generated within the depletion region of the diode as a result of absorption of a photon. (a) Indicate the direction of flow of the photo-generated carriers. (b) What will be the direction of current flow? (c) In which mode, forward bias or reverse bias should the diode be operated to obtain maximum sensitivity. Q.8 Explain what will happen if the photon is absorbed outside the depletion region. Hint: Consider diffusion and recombination of photo-generated minority carriers. 3. Dynamic Characteristics : Q.1 The depletion capacitance measured for a Schottky barrier diode at different reverse bias voltages is given below:

Area = (a) Determine the doping of N region (b) Determine the barrier height (c) Determine the depletion width at zero bias 4. Circuit Models Q.1 Obtain the small signal model for a Schottky diode on Silicon biased at a current of 1mA. Assume that the Richardsons constant is: 5. Ohmic Contacts

Q.1 Determine the current at which the net voltage drop across the PN junction diode shown below becomes 1 Volts. In your calculations include the voltage drop across both the top and the bottom ohmic contacts which have a contact resistivity of The top and bottom contacts have areas of respectively. The saturation current of the diode is .

Q.2 Determine the width of the base contact required for a lateral base contact resistance of 1 Ohm in a BJT. The specific contact resistivity is and the sheet resistance of the P-type region under the base is 100 Ohm/.

THE MOS CAPACITOR

4.1 Basic Physics and Band Diagrams for MOS Capacitors

Fig.4.1 (a) The schematic of a two-terminal MIS structure. (b) Band diagram of a two-terminal MIS structure at zero gate voltage, showing accumulation of holes near the surface. VFB is the flatband voltage, Xm is the metal work function, Xi is the electron affinity of the insulator, Xs is the electron

affinity of the semiconductor, and Eg is the band gap of the semiconductor.

Two-terminal metal-insulator-semiconductor (MIS) structure: characteristic crucial to understand the operation of MOSFETs. Assumptions: -Ideal MIS structure with no charges in the insulator layer and no surface states at the semiconductor-insulator interface. -The insulator layer has infinite resistivity, thus there is no current across the insulator when a bias voltage is applied => Fermi level constant across the device. Some definitions: -Work function: energy required to remove an electron from the Fermi level to the vacuum level (free space). -Electron affinity: energy required to remove an electron from the conduction band to the vacuum level. At zero bias voltage, the band bending in the semiconductor layer is determined by the work function difference between the metal and the semiconductor, and it can be compensated by applying a voltage VFB to the gate

where VFB is called the flat-band voltage, Xm is the metal work function, and Xs is the semiconductor electron affinity.

Note: this equation for VFB is applicable for an ideal MIS structure; however, if there are charges in the insulator or at the insulator-semiconductor interface, then the gate voltage required to obtain flatband condition would change.

Fig.4.2 The band diagram of the two-terminal MIS structure under the flatband condition. Vg is the applied gate voltage.

EXAMPLE 4.1: A two-terminal Si MIS structure has a substrate doping of

(p-type). -

Calculate the flatband voltage VFB of the structure if it employs (a) Al gate (Xm =

poly gate. Assume that there is no charge in the oxide, Xs(Si) = 4.05 eV, and Eg(Si) = 1.12 eV. SOLUTION: Ei EF = kT ln(NA/ni) = 0.026 ln[1016/(1.5 1010)] = 0.35 eV Therefore, Si work function s = Xs + (Eg/2) + (Ei EF) = 4.05 + 0.56 + 0.35 = 4.96 eV (a) For Al gate, VFB = 4.1 4.96 = 0.86 V Note: all these numbers can be equivalently represented either in volts or in electron-volts, depending on whether potential or energy is represented. (b) -poly gate, hence, Xm = Xs = 4.05 eV

It is assumed here that the Fermi level of the n+-poly gate is coincident with the conduction band. Therefore, VFB = 4.05 4.96 = 0.91 V

In Fig.4.1(b), note that Ev has come closer to EF near the semiconductor-insulator interface => hole concentration is greater near the interface than that in the bulk => this is referred to as the accumulation regime. In Fig.4.2, note that after the application of a positive VFB to the gate, the bands in the semiconductor become flat => uniform concentration of holes throughout the semiconductor. If the gate voltage is further increased, the holes near the insulator-semiconductor interface are pushed back deep into the bulk, leaving behind ionized acceptors near the surface and the bands bend downwards => formation of depletion region near the surface starts => referred to as the depletion regime [Fig.4.3(a)]. For even larger positive gate voltage, the band bending near the surface becomes so large that EF becomes closer to EC than to EV => the surface behaves like an n-type material => referred to as the inversion regime [Fig.4.3(b)]. Note: the increase in the band bending leads to an exponential increase in the electron concentration near the surface, e.g., an increase in the band bending by the amount of the thermal voltage VTH (= kT/q 26 mV at room temperature), increases the electron concentration by Thus, a large change in the electron concentration near the surface can be accommodated by a small change in the surface potential Vs, and since the induced charge is proportional to the gate voltage Vg, hence, the derivative dVs/dVg becomes small in the inversion regime, whereas this derivative has a large value in the depletion regime. When the difference between EF and Ei at the interface becomes equal and opposite of the bulk potential [ =(Ei EF)bulk = VTHln(NA/ni), where NA is the substrate doping it is referred to as concentration and ni is the intrinsic carrier concentration], i.e., the onset of strong inversion. The surface potential Vs is defined as (Ei,bulk Ei,interface)/q. Operating regions: o VS < 0 => accumulation o > Vs > 0 => depletion
o

=> weak inversion

o => strong inversion. It is assumed that beyond strong inversion, the value of Vs does not change any more and it

becomes pegged at

An alternate definition has been proposed by Tsividis, which states that = |dVs/dVg| is quite large in the weak inversion regime, whereas it becomes relatively small in the strong inversion region.

Fig.4.3 The band diagram of a two-terminal MIS structure at (a) depletion and (b) inversion.

Thus, he defines Vs =

as the onset of moderate inversion, and strong inversion actually

takes place when Vs is greater than by several (3-5) VTH. In today's context, the moderate inversion region (which can extend by 0.5 V or more) is extremely important for low power device applications in analog circuits. However, for the time being, we would stick to the standard definition of strong inversion, and would discuss about moderate inversion later. The surface electron and hole concentrations are given by

where pp0 = NA, and np0 = substrate respectively.

are the equilibrium hole and electron concentrations in the

Note: at the onset of strong inversion Vs = , and also, that nsps = => consequence of zero current in the semiconductor (perpendicular to the semiconductor-insulator interface) => corresponds to constant (as a function of distance) EF in the semiconductor.

4.2 Surface Charge

The potential distribution in the semiconductor is described by the Poisson equation where the space charge density and p(x) expressed respectively as with n(x)

where V(x) (Ei,bulk Ei(x))/q.

Note: deep into the bulk, from charge neutrality condition, NA = pp0 np0. Thus,

Using the definition of the electric field F = dV(x)/dx, the above equation can be rewritten as

Integrating this equation with respect to V, one gets

Thus,

Introducing the Debye length

the equation for F become

where

THE MOS CAPACITOR EXAMPLE 4.3: Draw the low- and high-frequency C-V characteristics, clearly showing all the relevant points, including the flatband capacitance, for a twoterminal MIS structure having 30 nm thick oxide and substrate doping of 1015 cm 3 (p-type). Assume VFB = 1 V. SOLUTION: The oxide capacitance per unit area

The bulk potential = (kT/q) ln(NA/ni) = 0.026 ln[1015/(1.5 1010)] = 0.29 V The threshold voltage

The maximum width of the depletion region

The semiconductor capacitance per unit area at threshold

Therefore, the total capacitance per unit area at threshold

The Debye length

The flatband capacitance per unit area

The capacitance Csc becomes dominant in the strong inversion region, when the surface electron concentration is appreciable, since the band bending is largest at the surface.

Note: the electrons, which create the inversion region near the surface, are actually generated in the bulk due to thermal EHP generation. Due to the electric field near the surface (recall that electric field points uphill in the band diagram), the electron and hole of the generated EHP are separated; the electron moves towards the surface and the hole moves towards the bulk => thus the rate of electron build-up near the surface proceeds at a rate limited by the rate of thermal EHP generation.

Fig.4.9 (a) The exact high-frequency equivalent circuit of a two-terminal MIS structure, and (b) its simplified equivalent.

Two new components in the equivalent circuit: o where T is the thickness of the semiconductor layer, and is the hole mobility] is the resistance of the quasineutral p-region, and o Rgen (= dVs/dIgen) is a differential resistance, which is a characteristic of the EHP generation process. Igen is the generation current, given by effective generation time constant. Thus, for gate voltages smaller than the threshold voltage VT, is an

In the small-signal equivalent circuit, the parameters Ceq and Req are given by

where

and

Note: both Ceq and Req are frequency dependent: in the limiting case of + Cdep, and in the other limiting case of

Fig.4.10 The C-V characteristics for a two-terminal MIS structure at different frequencies.

4.4.1 Extraction of Parameters from the C-V Characteristic

Fig.4.11 Parameter extraction from the C-V characteristic for a two-terminal MIS structure. The parallel shift in the characteristic after the bias-temperature stress test (described later) is also shown.

The maximum measured capacitance Cmax in the accumulation region gives the dielectric thickness The minimum measured capacitance Cmin at high frequency gives the doping concentration (assumed uniform) in the substrate. Steps: o First, determine the depletion capacitance Cdep in the strong inversion region from 1/Cdep = 1/Cmin 1/Cmax. o Then, obtain the depletion region thickness from o And, finally, calculate the doping concentration from the following two equations: These two equations need to be solved by iteration: first choose a suitable value for (say, 0.3 V), obtain NA, recalculate , obtain another fine tuned value of NA, and repeat the process until the desired accuracy is achieved. It also gives the information about the flatband voltage VFB. Steps: o The device capacitance CFB under flatband condition can be given
o

by CFB = CiCs0/(Ci + Cs0) =

o o

Thus, From a knowledge of di and NA, CFB/Cmax can be obtained, and the intercept can be found on the C-V curve to yield VFB.

4.5 Non-ideality in an MIS Structure: Oxide Charges

In most of the commercially available MOS capacitors and MOSFETs, silicon (Si) is used as the semiconductor and silicon dioxide (SiO2) is used as the insulator.

Si being a crystalline material and SiO2 being an amorphous material, there is a sudden discontinuity in the lattice structure at the Si-SiO2 interface.

Fig.4.12 Different types of charges in the Si-SiO2 interface and in the SiO2 layer.

This interface has attracted considerable interest over the last few decades, and significant studies have been made on this structure, however, a detailed understanding of many of its features is still lacking. The interface and the oxide contains various types of charges, which can be broadly categorized into the following:
o o o o

Charges due to fast surface states (or interface trapped charges) located at the interface. Charges due to mobile impurity ions located in SiO2. Charges due to traps ionized by radiation within SiO2. Fixed surface state charges located at the interface.

4.5.1 Fast Surface States

These are also referred to as Tamm and Shockley states, after their inventors. These are created at the interface due to the sudden termination of the crystal periodicity, since all the bonds of the atoms at the surface are not fulfilled these unfulfilled bonds are referred to as the dangling bonds. Obviously, the density of these states is a function of the crystal orientation (since (100) planes have lower atom density than (111) planes, MOSFETs are universally fabricated on (100) oriented Si).

Roughly, one fast surface state is assigned for every surface atom, resulting in a density Proper cleaving of the surface and consequent heat treatment with H2 drastically reduces the density of these states to or so, since H2 compensates some of these dangling bond by the formation of SiH.
1 2 3 4 5

THE MOS CAPACITOR

These states behave acceptor-like or donor-like, depending on the position of the Fermi level at the surface and the amount of band bending, and these are referred to as fast states, since they capture and release the carriers at a fast rate. When the surface potential changes, the charges in the surface states change as well, and leads to a shift in VT and a change in the C-V characteristics.

Fig.4.13 The experimental C-V characteristics showing the difference between them due to the presence of fast surface states.

There is a shift of the C-V curve towards the left due to the fast surface states, which changes the flatband voltage. In the equivalent circuit of an MIS structure, the fast surface states can be represented by an additional series combination of an equivalent capacitance Css of the surface states, and an additional resistance Rss, with the time constant RssCss representing the time response of the surface states.

Fig.4.14 The overall high-frequency equivalent circuit for a two-terminal MIS structure showing the additional components Css-Rss to account for the effects of fast surface states.

Measurements of frequency-dependent MIS capacitance and conductance give information about the density of the surface states.

4.5.2 Ionic Contamination

A major difficulty with early MOS devices was the instability of the threshold voltage VT, i.e., it used to vary with bias under elevated temperatures. This happens due to the rearrangement of the mobile ions within the oxide, which are introduced into the oxide from the furnace walls during oxidation.

Fig.4.15 Shift in the C-V characteristic after the bias-temperature stress test due to ionic contamination in the oxide, and its partial recovery after annealing with gate-substrate shorted.

The initial C-V characteristic is marked by (1), while those observed after 30

minutes at 127 C with VG = +10 V applied is marked by (2), and after heating the device for 30 minutes at the same temperature with the gate shorted to the substrate yields characteristic marked by (3)- this experimental procedure is known as the bias-temperature stress test.

Fig.4.16 Charge distribution during the various stages of the bias-temperature stress test and post annealing.

Initially, all the positive ionic charges are located at the metalSiO2 interface, exerting no influence on Si; after positive gate bias at high temperature, all these ionic charges cluster near the Si-SiO2interface and induce all the image charges in Si; finally after recovery, the ions create an arbitrary distribution (x) within the oxide, inducing image charges in both the gate and the semiconductor. For any arbitrary distribution of the oxide charges (x), the shift in the flatband voltage can be given by

where di is the oxide thickness.

The menace created by mobile ions is reduced to a large extent in today's technology due to the improvements in the fabrication process.

EXAMPLE 4.4: In a two-terminal MIS structure having 40 nm thick oxide, the shift in the flatband voltage after a bias-temperature stress test was found to be 10 mV. Determine the mobile ionic contamination per unit area in the oxide in numbers per unit area. SOLUTION: The oxide capacitance per unit area

The shift in the flatband voltage due to the mobile ionic contamination after bias-

temperature stress test is given by contamination per unit area in the oxide

Thus, the mobile ionic

4.5.3 Radiation-Induced Space Charge

A positive space charge is seen to build up in SiO2 films when it is irradiated by ionizing radiation of various kinds, e.g., X-ray, gamma ray, low- and high-energy electron irradiation, etc. (potential danger during ion implantation). The physical origin of this charge is completely different from the ionic contamination. Due to irradiation, EHPs will be generated within the SiO2. In the absence of any electric field within the oxide, these carriers will immediately recombine; however, under a positive applied gate bias, due to the electric field within the SiO2, the generated electrons and holes would separate, with the electron moving towards the metal-SiO2 interface, and the hole moving towards the SiO2-Si interface. Thus, a space charge layer starts to build up within the oxide due to these charges, thus creating an electric field within the oxide, which is opposite to that of the applied field => changes VFB, and, thus, VT. These charges can be eliminated by thermal annealing.

4.5.4 Surface State Charges

A fixed charge is seen to exist within the oxide very near the SiSiO2 interface, which results in a parallel translation in the C-V characteristics along the voltage axis these charges are called the surface state charges, and the density of these charges per unit area is denoted by These surface states have the following properties: o It is fixed, i.e., its charge states cannot be changed over a wide variation in the band bending. o Unchanged under bias-temperature stress test and thermal annealing.
o o o

It is located within 200 of the Si-SiO2 interface. Its density is not significantly altered by the oxide thickness, or by the type or concentration of impurities in Si. Its density is a strong function of the oxidation and annealing conditions, and the orientation of the Si crystal.

The ratio o f in (111), (110), and (100) Si are in the ratio 3:2:1, and is a strong function of the oxidation condition.

Popular theory: originates from the excess ionic Si in the oxide, which moves into the growing SiO2 layer during the oxidation process. can be reduced by a large extent by H2 heat treatment

4.6 General Expression for the Flatband Voltage VFB

The general expression for the flatband voltage VFB can be given by

where

where m is the metal work function and

is the

semiconductor work function; is the oxide charges lumped at the SiSiO2 interface, and is any arbitrary distribution of charges within the oxide.

4.7 Some Advanced Models 4.7.1 Unified Charge Control Model (UCCM) for MIS Capacitors

The standard charge control model (SCCM) postulates that the interface inversion charge of electrons qns is proportional to the applied voltage swing VGT = VG -VT. This model is an adequate description of the strong inversion region of the MIS capacitor, but fails for applied voltages near and below VT (i.e., in the depletion and weak inversion regions). A new model has recently been proposed which has been shown to model the device behavior adequately both in the weak and strong inversion regions, and is given as:

where is the permittivity of the gate insulator, di is the thickness of the gate insulator, is an ideality factor, and is a correction to the insulator thickness related to the shift in the Fermi level in the inversion layer with respect to the bottom of the conduction band.

Note: Eq.(4.24) does not describe the mobile charge in the accumulation region, however, this region is not important for MOSFET operation. This correction is dependent on the interface electron density, however, it can be approximately taken to be a constant for typical values of the interface electron density. For Si-SiO2 MOS capacitors assumed that hence, it can usually be

The ideality factor reflects the gate voltage division between the insulator layer capacitance Ci and the depletion layer capacitance Cdep. In the subthreshold regime, At the onset of strong inversion (VGT = 0), the surface potential Vs has the value Below threshold, we have the following approximate relationship:

Note: in general, is dependent on VGT, and at low substrate doping levels, is close to unity near threshold where the gate depletion width is large (corresponding to Cdep << Ci). Usually, Cdep can be estimated as follows:

is an average width of the depletion region.

Equation (4.24) is an empirical equation, which can be justified by comparing the calculation results with experiments and more precise calculations. Intuitively, the structure of the UCCM expression [Eq.(4.24)] seems reasonable, since in the strong inversion region, it reverts to the simple charge control model [i.e., while in the subthreshold region, it predicts that the inversion charge is an exponential function of the applied voltage, as expected. Since UCCM is an empirical model, it is especially important to have a clear and unambiguous procedure for extracting model parameters from experimental data. For the MIS structure, this extraction of parameters is based on the C-V characteristics, which shows a sharp increase in the capacitance (at low frequencies) during the transition from the depletion to the strong inversion region. The voltage at which the derivative of the MIS capacitance reaches its maximum value is very close to the threshold voltage VT. The first derivative of Eq.(4.24) with respect to VGT yields the following unified expression for the metal-channel capacitance per unit area

valid for all values of applied bias voltage:

The first derivative of this capacitance

1 2 3 4 5

THE MOS CAPACITOR

reaches its maximum value for

Hence, the following sheet inversion charge density at threshold is obtained:

and the value for the unified capacitance per unit area at threshold becomes

Here, is the maximum value of Equation (4.33) serves as the basis for a very convenient and straightforward technique for determining the threshold voltage from experimental data.

Fig.4.17 Measured gate-channel capacitance as a function of gate-source voltage for an n-channel MOSFET for different values of substrate bias.

From the experimentally determined gate-channel capacitance, the inversion carrier sheet density can be calculated as

According to UCCM, this should agree with Eq.(4.29), which can be written as

Hence, from a plot of versus and a can be found. The slope of this plot gives , while the intercept with

yields a.

Fig.4.18 Inverse gate-channel capacitance plotted as a function of the inverse mobile sheet charge density (data obtained from Fig.4.17).

Fig.4.19 Measured dependence of (curves to the left) and -1 V (curves to the right). The threshold voltages determined by the two methods are also indicated.

The values of obtained from the slopes in Fig.4.18 agree very well with those determined directly from the subthreshold I-V characteristics, and the value of di calculated from a is in excellent agreement with that measured by ellipsometry. In Fig.4.19, the value of VGS corresponding to the peak value of should coincide with the value of VGS at which the gate-channel capacitance has dropped to one-third of its maximum value. In Fig.4.20, the agreement between the measured and the calculated data is excellent for the entire range of gate bias.

Fig.4.20 Measured (solid lines) and calculated (UCCM, symbols) ns versus VGS characteristics for different values of Vsub in (a) semilog scale and (b) linear scale. In (b), the results obtained from the simple charge control model (SCCM) are also shown.

The deviation in the measured curves found in the deep subthreshold region is due to two reasons: one is the C-V measurement error, and the other is the leakage current, which dominates deep subthreshold operation. At deep subthreshold, the channel offers a large series resistance compared with the reactance of the capacitance.

4.7.1.1 Analytical Unified MIS Capacitance Model

Note: the UCCM does not have an exact analytical solution for the inversion charge in terms of the applied voltage even though an accurate approximate solution can be obtained. Above threshold, the sheet density of carriers in the inversion layer can be

given as

Below threshold, the electron sheet density in the channel can be written as

From Eq.(4.37), the following expression is obtained for the subthreshold differential channel capacitance per unit area

An approximate, unified expression for the effective differential metalchannel capacitance per unit area is obtained by representing it as a series connection of the above threshold and the subthreshold capacitances, i.e.,

Hence, the unified carrier sheet charge density becomes

Equation (4.40) is similar to an interpolation formula, and calculations show that it is in excellent agreement with UCCM.

4.8 Quantum Theory of the Two Dimensional Electron Gas (2DEG)

Classically, the electrons induced at the semiconductor-insulator interface of an MIS capacitor form a classical electron gas and behave essentially in the same way as electrons in a bulk semiconductor. This assumption is only correct if the thickness of the inversion layer is much larger than the deBroglie wavelength for electrons. For the classical electron gas, this thickness d can be estimated as where Fs is the surface electric field, and using Gauss' law, this field can be approximated as In this estimate, the condition of continuity of electric displacement across the semiconductor-insulator interface is used, and it is assumed that almost all of the applied voltage drops across the insulator. Hence,

In modern day MOSFETs, di can be well below 100 , and smaller than the deBroglie wavelength, e.g., for di = 100

may become

In this case, the quantization of the energy levels in the potential well at the semiconductor-insulator interface in the direction perpendicular to the interface must be taken into account. Once quantization of energy levels take place, then the dispersion (E-k) relation in the direction parallel to the interface is given by:

where En is the electron energy, Ej is the energy level of the jth subband, and ky and kz are the wave vector components parallel to the interface.

Fig.4.21 Schematic diagram of energy subbands at the semiconductorinsulator interface (assuming constant effective field approximation).

For a relatively thick electron gas layer, the number of subbands is large and the energy difference between the bottoms of the subbands is small (<< kT). For a relatively thin electron gas layer, only the lowest few subbands are important for electron occupation, and the energy difference between the bottoms of the subbands may become large compared to the thermal energy kT. In this case, the electron gas is often referred to as a two-dimensional electron gas (2DEG). The density of states D for each subband is given by which is a constant and independent of the subband energy Ej => the overall density of states has a staircase dependence on energy for a triangular quantum well, which is characteristic for the semiconductor-insulator interface of an MIS structure.

The number of electrons occupying a given subband j can be found by multiplying the density of states D for a single subband by the F-D distribution function, and integrating from Ej to infinity:
1 2 3 4 5

THE MOS CAPACITOR

Fig.4.22 Energy levels (bottoms of subbands) and density of states for a triangular quantum well structure (j = 1, 2, , correspond to the different subbands).

After evaluating this integral and adding the contribution from all subbands, one obtains

The quantized energy levels for the subbands can be found using a numerical self-consistent solution of the dinger and Poisson's equations. However, an excellent approximation for the exact solution can be found by assuming a linear potential profile (i.e., constant effective field Feff) in the semiconductor and close to the semiconductor-insulator interface. In this case, the energy levels are given by

where is the effective mass for electron motion perpendicular to the (100) surface, and Ec(0) is the minimum conduction band energy at the Si-

SiO2 interface.

The effective field Feff is expressed through the surface field FS and the bulk field FB. For electrons, the relationship linking Feff, FB, and FS, giving the best fit to the self-consistent solution of dinger and Poisson's equation is given by and Feff = (FS + FB)/2, where ns is the interface electron sheet density, and qnB (= qNAddep(av)) is the sheet density of depletion charge. Similarly, for holes, FS = q(ps + where ps is the interface hole sheet density, and qpB (= qNDddep(av)) is the sheet density of depletion charge. In reality, it has been found that a slightly different form of the effective field Feff1 = (FS + 2FB)/3 gives a better fit to the measured data. Solving these equations iteratively, one can obtain the relation between ns and the Fermi level [EF Ec(0)].

Fig.4.23 Comparison of the interface carrier density versus EF Ec(0) characteristics for different substrate doping densities in (a) semilog plot and (b) linear plot. Symbols: calculations based on a 2DEG formulation, solid lines: charge sheet model, straight line in b): linear approximation to 2DEG formulation, the slope gives

In the calculation, it can be assumed that the maximum value of nB is given by

In the subthreshold region, the calculation agrees reasonably well with the classical charge sheet model (CCSM) given by Brews:

especially at low levels of substrate doping.

The difference between the curves at high substrate doping levels is caused by the fact that the large bulk field quantizes the energy levels even in the subthreshold region. However, at strong inversion, the difference between the charge sheet model and the 2DEG formulation is large. As can be seen from Fig.4.23, the dependence of ns on EF in the above threshold regime can be approximated by a straight line: where EF0 is the intercept of this linear approximation with ns = 0. This approximation means that a fraction of the applied voltage, equal to is accommodated by a shift in the Fermi level with respect to the bottom of the conduction band. The shift in the Fermi level with respect to the bottom of the conduction band changes the above-threshold capacitance from to where the parameter correction to the insulator thickness. can be interpreted as a is obtained,

From the straight-line approximation in Fig.4.23b),

which is much smaller than that of This difference is caused by o a much larger effective mass in the conduction band in Si, which makes quantum effects much less pronounced, and o the large difference in the dielectric constants between the insulator and the semiconductor for the MOS system.

Practice Problems 4.1 Clearly draw the band diagrams for an ideal MOS structure and

no oxide charge) on n-type Si for i) accumulation, ii) depletion, and iii) inversion. If the oxide thickness tox = 40 nm and VG= 1 V, determine the magnitude and sign of the charge density in the semiconductor. What is the status of the surface? 4.2 Show that for an MOS structure on p-type Si, the electron and hole concentrations as functions of position are given by where n0 and p0 are the equilibrium electron and hole concentrations respectively, and is defined by = [Ei(bulk) Ei(x)]/q. 4.3 Continuing with the derivation given in Section 4.2, show that the electric field E in the semiconductor in an MIS capacitor can be given by where all the notations carry their usual meanings.

4.4 Sketch the electric field and voltage distribution in an MOS structure at the threshold gate voltage. Data: substrate voltage = 0, and VFB = 0. Compute the threshold voltage VTH from the voltage distribution. 4.5 Calculate and plot the semiconductor surface charge an MIS structure as a function of the surface potential per unit area for

4.6 Starting from Eqn.(4.16), show that at flatband (i.e., when Vs = 0), the flatband capacitance per unit area compute its magnitudes for substrate dopings of Hence,

4.7 Consider the energy band diagram of a metal-SiO2-Si-SiO2-metal structure as shown in Fig.P7. Assume symmetric bands with (a) What is the flatband voltage for this structure? (b) Sketch the band diagram of the structure when the left metal plat is at 2 V and the right metal plate is grounded. Assume What is the strength of the electric field in Si? What are the positions of the Imrefs in Si? In the band diagram, all the appropriate voltage levels must be specified. Neglect induced charges in Si.

4.8 (a) Find the voltage VFB required to reduce to zero the negative charge

induced at the semiconductor surface by a sheet of positive charge located below the metal. (b) In the case of an arbitrary distribution of charge in the oxide, show that

where

= oxide capacitance per unit area =

where d = oxide thickness.

4.9 Charge density of is distributed in the oxide (d = 40 nm) in a Si MOS capacitor. Assume Find the flatband voltage required to be applied at the gate to compensate these charges if: i) the charges are uniformly distributed in the oxide, ii) the charge distribution is linear with the peak at the metal-SiO2 interface and zero at the Si-SiO2 interface, and iii) same as ii) but now with the peak at the Si-SiO2 interface and zero at the metal-SiO2 interface. Physically justify the answers. 4.10 An Al-gate where m is the Al work function to vacuum) MOS structure is made on p-type % where is electron affinity for Si) substrate. The SiO2 thickness d = 50 nm, and the effective oxide interface charge Find Wmax, VFB, and VTH. Sketch the C-V curve for this device giving all relevant details. 4.11 Find VTH for an MOS structure in Si with p-type substrate and d = 80 nm. Repeat for n-substrate with the same parameters (note: the new can be calculated from the change in EF). 4.12. Calculate and plot the maximum width of the depletion region for an ideal (i.e., VFB = 0) MIS capacitor on p-type Si with as a function of the substrate bias Vsub for -2 V < Vsub < 0.1 V. Assume that the voltage difference between the inversion layer at the interface and the gate contact is maintained constant when the substrate potential is changed (charge screening), so that the substrate voltage reverse biases the inversion layer/p-type substrate junction. Also, calculate the threshold voltage VT, and the capacitance of the structure at low and high frequencies for V >> VT for Vsub= 0. Data: ni = 4.13 Calculate and plot the surface potential as a function of the gate voltage VG in depletion and inversion for a two-terminal MIS structure. Identify the weak inversion, moderate inversion, and the strong inversion regions in the plot (as per Tsividis). Can the plot be really linearized in subthreshold? Determine an effective value of in subthreshold from the plot.

4.14 Calculate and plot the gate-to-substrate capacitance Cmis as a function of the gate voltage VG for a two-terminal MIS structure with area = The plot should show all the regions of operation (i.e., accumulation, depletion, weak inversion, and strong inversion). Mark Cso in the plot, with the magnitude shown. (Note: the externally measured capacitance includes the oxide capacitance). 4.15 Calculate and plot the temperature dependence of the surface charge per unit area for the surface potential i) in the temperature range between 150 K and 450 K. Data: effective densities of states in conduction and valence bands and respectively at 300 K (with both of them having a dependence), and the energy gap Eg = 1.12 eV (the variation of the energy gap with temperature may be neglected). 4.16 From the equivalent circuit for an MIS structure, determine the expression for the impedance across its two terminals as a function of frequency. Hence, calculate and plot the effective capacitanceof the structure as a function of the gate voltage VG (varying from -5 V to +5 V) for frequencies of

4.17 As a practice problem, draw any arbitrary C-V curve of your choice, and following the parameter extraction algorithm discussed in Section 4.4.1, obtain the i) oxide thickness, ii) threshold voltage, iii) substrate doping, iv) flatband capacitance, v) flatband voltage, and vi) fixed oxide charges. 4.18 The C-V curve of a two-terminal MIS structure shows a shift of 10 mV in the flatband voltage after a bias-temperature stress test. If the flatband voltage before the stress test is -1 V, and the surface state density is determine the oxide fixed charges. 4.19 Derive Eqn.(4.40). 4.20 Derive Eqn.(4.43). 4.21 (a) Compute and plot the surface electron concentration ns as a function of [EF - EC(0)] under the 2DEG approximation for (b) Repeat part (a) under the 3D approximation (i.e., the 3D charge sheet model as given by Brews). Data: (Note: the constant energy surface for Si consists of six ellipsoids of revolution, and ml ( ) and mt ( ) represents the lateral and transverse effective mass respectively. For {100} direction four of these ellipsoids will lye on the surface and two ellipsoids will be perpendicular. Refer to Problem 22 also.) 4.22 In the classical limit, the separation of the energy subbands in a 2D electron gas is small compared to the thermal energy kT. In this case, the

sheet density of the 2D electron gas is given by the classical charge sheet model, given by Eqn.(4.46), which is derived using a conventional 3D electron gas approach. Show that in this limit (i.e., Ej Ej 1 << kT), the equation

reduces to Eqn.(4.46). In the above equation, mpi is the parallel effective mass for the valley i, and Eji is the energy level of the jth subband in valley i. Note: the effective mass mpi is mt for two valleys, and for four valleys, where mt and ml is the transverse and lateral effective mass respectively.
1 2 3 4 5

METAL-OXIDE-SEMICONDUCTOR FIELD-EFFECT TRANSISTORS (MOSFETs)

If the inversion layer-substrate (or the source-substrate or the drainsubstrate) junction ever gets forward bias, a large leakage current would result, which would hamper normal MOSFET operation. For both n- and p-channel MOSFETs, the magnitude of the threshold voltage VT increases with an increase in |Vsub|. Physical Understanding of Saturation

A physical insight into the phenomenon of saturation may be obtained by analyzing the electric field distribution under the gate. Integrating Eq.(5.6) from 0 to x, one gets :

or

The electric field in the channel in the direction parallel to the semiconductor-insulator interface can be found from Eq.(5.5)

Solving Eqs.(5.12) and (5.13) together, the field profiles can be calculated.

Fig.5.6 The variation of the electric field along the channel for drain voltage nearly equal to the saturation voltage for gate voltages

10

METAL-OXIDE-SEMICONDUCTOR FIELD-EFFECT TRANSISTORS (MOSFETs)

If the inversion layer-substrate (or the source-substrate or the drainsubstrate) junction ever gets forward bias, a large leakage current would result, which would hamper normal MOSFET operation. For both n- and p-channel MOSFETs, the magnitude of the threshold voltage VT increases with an increase in |Vsub|. Physical Understanding of Saturation

A physical insight into the phenomenon of saturation may be obtained by analyzing the electric field distribution under the gate. Integrating Eq.(5.6) from 0 to x, one gets :

or

The electric field in the channel in the direction parallel to the semiconductor-insulator interface can be found from Eq.(5.5)

Solving Eqs.(5.12) and (5.13) together, the field profiles can be calculated.

Fig.5.6 The variation of the electric field along the channel for drain voltage nearly equal to the saturation voltage for gate voltages

10

METAL-OXIDE-SEMICONDUCTOR FIELD-EFFECT TRANSISTORS (MOSFETs)

Note: from the constancy of the drain current

throughout the device, it

can be seen that as The differential drain conductance

and the electric field F(L) diverges.

tends to zero when in the voltage region drain current

and the I-V characteristics may be extrapolated assuming a constant (independent of

may be found by substituting from Eq.(5.8) into Eq.(5.7), which results in a highly complicated expression, however, it can be simplified for gate voltages close to the threshold voltage

Note: this approach is only valid when the channel electrons do not suffer any velocity saturation due to high electric fields. Note: modern day MOSFETs have extremely small gate lengths, and the channel has high electric fields (more than the critical electric field required for velocity saturation), which creates the velocity saturation effects for the channel electrons.

Fig.5.7 The I-V characteristics of an n-channel MOSFET for different values of gate voltage . The dashed line represents the drain-to-source

saturation voltage.

Fig.5.8 The variation of the drain saturation current with gate voltage for three different values of substrate doping.

For very small the terms under the curly brackets in Eq.(5.15) can be expanded in Taylor series, leading to the following simplified expression for the I-V characteristics in the linear region:

A physical justification of Eq.(5.16) can be given as follows: At very small the charge induced in the channel is, to the first order, independent of the channel potential, thus, (5.17)

Now, for small the electric field F in the channel is nearly constant, and is given by The drain current is entirely due to drift, and is given by the electrons in transit model:

since 5.2.3 The Charge Control Model

A simplified description of the I-V characteristics of a MOSFET can be obtained by using the charge control model. In this model, it is assumed that the concentration of free carriers induced in the channel is given by

Compare Eq.(5.19) with Eq.(5.2): in Eq.(5.19), the variation of the depletion charge density The drain current with the channel potential has been neglected. can now be given by

Compare Eq.(5.20) with Eq.(5.5). Equation (5.20) can be rewritten as

Integrating Eq.(5.21) from x = 0 (source side) to x = L (drain side), which corresponds to a change in from the following expressions for the I-V characteristics are obtained:

Fig.5.9 The I-V characteristics of an n-channel MOSFET calculated using the charge control model (solid curve) and the Shockley model (dashed curve).

The differential transconductance

is defined as

From Eqs.(5.22) and (5.23),

where with

is referred to as the device transconductance parameter, is referred to as the process transconductance parameter.

Thus, in order to achieve a high value for the transconductance gm, the following steps may be taken. Higher value of low field electron mobility Thinner gate dielectric layers, which in turn gives large values for the insulator capacitance per unit area Large widths (W) and short lengths (L). Note: for short channel devices, where velocity saturation effects are important, the dependence of transconductance on the low-field electron

mobility and the gate length gets strongly affected.

EXAMPLE 5.1: An n-channel MOSFET with the process transconductance parameter the threshold voltage is biased at Determine the drain current ID, the transconductance and the drain conductance SOLUTION: i) Hence, the device is under linear mode of operation

. Note the huge change in transconductance in saturation as compared to the linear region: this is due to the square law dependence of current on the gate voltage in the saturation region (as against the linear variation in the linear region).

Drain Conductance This is due to the independence of the saturation drain current on the drain voltage. In reality, channel length modulation creates a change in drain current with respect to the drain voltage in saturation, and finite drain conductance

Effect of Source and Drain Series Resistance

The analysis so far neglects the effects of the source/drain series resistance, and the entire voltage is assumed to drop along the channel. However, for modern day MOSFETs, this effect cannot be ignored, due to smaller diffusion cross-sections and smaller drain currents. The extrinsic (measured) voltages can be related to the intrinsic (device) voltages by the following equations:

where

are the source and drain resistances respectively. is related to the intrinsic

The extrinsic transconductance transconductance

where

is the intrinsic drain conductance. is related to the

Similarly, the extrinsic drain conductance intrinsic drain conductance

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METAL-OXIDE-SEMICONDUCTOR FIELD-EFFECT TRANSISTORS (MOSFETs)

Fig.5.10 The variation of the drain saturation current as a function of the gate voltage for three different values of the series source resistance

Fig.5.11 The drain current drain-to-source voltage characteristics for different values of

The series source resistance reduces the drain current, and the series drain resistance increases the drain-to-source saturation voltage. Both series source resistance and series drain resistance reduce the drain conductance at low drain-to-source voltages. Velocity Saturation Effects in MOSFETs

In modern day MOSFETs, the channel length is very small, the electric field in the channel is very high, and the velocity saturation effects are very important. The measured electron and hole mobilities in the inversion layer may be quite different than those measured in the bulk. Note: the channel, in reality, is under a two-dimensional electric field, one directed longitudinally from the gate to the substrate, and the other directed laterally along the length of the channel. The effective inversion layer thickness is approximately given by thus, a large vertical field creates a narrow inversion layer, and vice versa.

Fig.5.12 The random path of electrons in the channel, undergoing surface scattering, which is more intense in narrow channels.

Electrons in the channel move in random directions, undergoing surface scattering, which increases for narrow channels thus their mobility drops.

Fig.5.13 The variation of the electron and hole mobilities in the channel as a function of the gate electric field.

The dependence of the electron and hole mobilities on the gate field be crudely approximated by

can

where n0 and p0 are the electron and hole mobilities for

It is very interesting to note that in highly constricted channels or at low temperatures, the carrier mobility is seen to get enhanced. This is because for these cases, the electron motion in the direction perpendicular to the interface gets quantized, and the channel electrons behave like a two-dimensional electron gas (2DEG). Thus, the surface scattering is not that important, and the impurity scattering is screened by a high density of electrons in the channel. Such enhancement of electron mobility was observed in GaAs, and is exploited in high electron mobility transistors (HEMTs) or modulationdoped field effect transistors (MODFETs). Effects of Velocity Saturation on the I-V Characteristic

For this derivation, a simple two-piece linear approximation for the electron velocity is used:

where is the electric field required for velocity saturation, and saturation limited thermal velocity.

is the

Recall: in the linear region, the I-V characteristic can be given by:

where

The saturation current can now be found by assuming that the current saturation occurs when the electric field at the drain side of the channel exceeds the critical field required for velocity saturation. This is a much more realistic assumption than the Shockley model, which assumes saturation occurs when The constant mobility model is still used for drain voltages below the saturation voltage. The absolute value of the electric field in the channel

at drain voltages below the saturation voltage can be obtained from Eq.(5.21):

Integrating Eq.(5.35) from 0 to x, the following equation for the channel potential is obtained for drain voltages below the saturation voltage:

The solution of this equation is given by

Substituting Eq.(5.37) into Eq.(5.35), the following expression for the electric field as a function of distance is obtained:

and the electric field F(L) at the drain side of the channel (where it is the largest),

From the condition as

the drain saturation current can now be found

At very large values of the term in the brackets in Eq.(5.40) may be expanded into Taylor series, which gives the following expression for the saturation drain current for long channel devices: , which does not take into account the velocity saturation effects. For long channel devices, as predicted by the constant mobility model, hence, the velocity saturation effects are not too important for long channel devices. Example: assume then for channel length velocity saturation effects on the drain saturation current may be neglected. However, for modern day MOSFETs, the typical gate length is much smaller than (recently, Intel has introduced processors using technology), where the velocity saturation effects are extremely important. In the limiting case for short channel devices, when from Eqs.(5.40) and (5.41), it is seen that Note: for short channel device, the drain saturation current is times smaller than the value predicted by the constant mobility model; and it becomes linearly dependent on instead of the familiar square law relation. while plotted as a function of for a long channel device, shows a linear behavior; however, for short channel devices, it shows a significant departure from linearity a measure of whether the device is a short-channel or a long-channel device. The drain saturation voltage is also much smaller than that predicted by the constant mobility model.

Fig.5.14 The variation of the drain saturation current as a function of the gate length for three different values of the gate voltage (3 V, 5 V, and 7 V). The drain saturation current predicted by the constant mobility model

(shown by the dashed line) is also shown for comparison.

The effects of source/drain series resistance, for these cases, can be accounted for (as done earlier for long channel devices), and the following expressions for the drain saturation current and the drain saturation voltage are obtained:

Interpolated Relation

The following interpolation formula for the MOSFET I-V characteristic has been proposed by Shur, which describes both limiting cases correctly:

This was one of the earlier formulas, and a huge amount of work has been done in this area for the last ten years or so, in order to further refine the description of the behavior of short-channel MOSFETs. In practical devices, the I-V characteristics do not completely saturate at large drain-to-source voltages, and this is related to the short channel and other nonideal effects in MOSFETs. In order to account for the finite slope of the output characteristics in saturation, the following modification to the drain current expression has been proposed:

where is referred to as the channel-length modulation parameter (an extremely important parameter for short channel device a measure of the nonidealities present in the device)

10

METAL-OXIDE-SEMICONDUCTOR FIELD-EFFECT TRANSISTORS (MOSFETs)

Short Channel and Nonideal Effects in MOSFETs

For long channel devices, the drain current becomes constant in saturation, whereas, for short channel devices, the drain current increases continuously with the drain-to-source voltage.

Fig.5.15 I-V characteristics of two n-channel MOSFETs: (i) L = 0.5 (dashed lines), and (ii) L = 0.75 (solid lines).

Fig.5.16 The variation of the threshold voltage with the effective channel length.

Another interesting feature seen in short channel devices is that the saturation current increases as the device length is reduced. Now, based on the existing model for the threshold voltage, which states that it is independent of the device length this behavior cannot be explained. In reality, it has been shown that the threshold voltage is a strong function of the channel length (for short channel devices), and it actually decreases with a decrease in the channel length, which explains the reason behind

the larger saturation current.

The Charge Sharing Model

The reduction of the threshold voltage with a reduction in the channel length can be explained by the charge sharing model.

Fig.5.17 The depletion charge profiles for (a) a long channel device, and (b) a short channel device.

For a long channel device, the depletion layer thickness at the source end of the channel and at the drain end of the channel are much less than the channel length L, and, thus, the depletion charge enclosed by these sections are much smaller than the total depletion charge under the gate. However, for a short channel device, the widths of these depletion regions are a non-negligible fraction of the total depletion charge under the gate.

Note: essentially, the depletion regions near the source and the drain are contributed by the source-substrate and the drain-substrate bias, and gate has no role to play. Under an applied drain-source bias, the depletion region thickness near the drain will obviously be larger than that at the source side. The net effect is that the gate now has to compensate for a lower depletion charge density than that for a long channel device, which qualitatively explains the reduction of the threshold voltage with a reduction in the channel length. The exact analysis of the charge sharing effects requires a twodimensional analysis, however, to the first order, it is assumed that the effect of the depletion width at the drain side of the channel is to reduce the effective channel length in the saturation region from L to where

Here, is the effective channel length, and the voltage dropped along this section is assumed to be equal to the drain saturation voltage , and is length of the pinched-off portion of the channel (related to the drain depletion width), where the excess drain voltage beyond , i.e., is dropped, where is the applied drain voltage. With an increase in the length of the pinch-off region also increases, leading to a reduction in the effective channel length . This effect is called the channel length modulation effect, and this effect leads to a higher drain saturation current, and finite output conductance in the saturation region. A very crude estimate of the pinch-off length (also referred to as the drain region length) can be obtained from the solution of the onedimensional Poisson's equation:

A more accurate and realistic expression for may be obtained by assuming that the electrons are injected from the inversion layer into the drain depletion region, and they spread uniformly, leading to the current density

Here,

is the diffusion depth of the

drain region, and

is the

thickness of the inversion layer It is also assumed that the velocity of electrons in this region is saturated, thus their volume density can be given by Now, the one-dimensional Poisson's equation can be rewritten as:

The solution of this equation leads to the following complicated expression for :

For gate lengths larger than or about 1 , and drain-to-source voltages smaller than or about 10 V, this expression may be simplified to give

In short channel devices, the depletion charge under the channel [dependent on the channel potential and has been represented by the second term within the brackets in the right-hand side of Eq.(5.7)], which has been neglected in the charge control model [Eq.(5.19)], has to be accounted for. This effect may be taken into account by introducing an additional parameter a into the equations of the charge control model, with the resulting equations given by Linear Region

Saturation Region

For Si, the (empirical and fitting) parameter a describes the influence of the bulk substrate depletion layer on the device characteristics, and can be approximated by the following expression

The threshold voltage and the parameter K can be determined from the experimentally measured data for a given device. In addition, the dependence of electron mobility on the longitudinal and transverse electric field in the channel should be included for a more realistic device modeling, however, this simple empirical model gives adequately good fit with the measured data.

Fig.5.18 The measured and calculated I-V characteristics for a Si n-channel MOSFET.

10

METAL-OXIDE-SEMICONDUCTOR FIELD-EFFECT TRANSISTORS (MOSFETs)

Similar to the short channel device, the threshold voltage of a narrow channel (along the width) device increases with a reduction in the effective device width Weff due to the fringing fields outside the gate region, and the change in the threshold voltage as a function of Weff can be given by

where

is a constant.

Fig.5.19 Variation of the threshold voltage with the channel width.

Another non-ideal effect that may be especially important for short-channel devices is the injection of electrons from the channel directly to the gate dielectric, where these electrons get trapped => hot electron effect. This phenomenon takes place because the carriers gain sufficient energy while traversing the drain depletion region, which contains a high electric field, and has been used to advantage in the FAMOS (Floating gate avalanche MOS) structures used in memories. Avalanche breakdown of the drain-substrate junction can cause a sharp increase in the drain current, and can damage the device unless it is controlled by some external means. Typically, avalanche breakdown for a heavily doped drain-moderately doped substrate junction takes place at approximately 8 to 10 V. Another very important nonideal and potentially hazardous situation may arise due to punchthrough, where the drain and source depletion regions touch each other and cause abnormally large current to flow through the device: this effect is particularly severe for short channel devices. Punchthrough effect creates a superlinear increase in the drain current with the drain voltage, even at gate voltages below the threshold voltage. Subthreshold Conduction

So far, we have considered current flow in a MOSFET only when the gate voltage exceeds the threshold voltage. However, in reality, a finite (nonzero) current does flow in a MOSFET even for gate voltages below the threshold voltage, and this effect is more marked for short channel length devices than their long channel counterparts. This current is referred to as the subthreshold current, and it flows for when the surface potential lies between the ranges of the onset of weak inversion and the onset of strong inversion. The mechanism responsible for subthreshold current is quite different for long-channel and short-channel devices. 5.6.1 Subthreshold Current in a Long Channel Device

In a long channel device, the situation is similar to a BJT, where the source plays the role of the emitter, the drain is equivalent to the collector, and the substrate is the base. The drain voltage drops almost entirely across the drain-substrate depletion region. Thus, the component of the electric field parallel to the interface is small, and the subthreshold current is contributed primarily by diffusion, just as the case for BJTs.

Fig.5.20 The depletion regions associated with a (a) long channel and (b) short channel device.

Thus, the subthreshold current can be evaluated as

where is the region where most electrons are located) is the effective cross-sectional area.

The electron density n at the surface is proportional to , and it decreases with y (perpendicular to the interface) proportionally

to where

is the vertical electric field, given by

Thus, the effective depth where most of the electrons are concentrated, can be estimated as where y = 0 corresponds to the interface. If the diffusion length of electrons in the substrate is much greater than the channel length L, then the electron density n should be a linear function of x, decreasing from the source towards the drain (just like the linear distribution of minority carriers in the base of a BJT):

where the volume concentrations for electrons drain sides of the channel are given by

at the source and the

where V(y) is the potential given by undepleted portion of the channel.

is the length of the

For long channel devices, it is assumed that the depletion widths at the source and the drain sides of the channel are small compared to the channel length L, and Also, note that since Using all the relations given above, the subthreshold current for a long channel MOSFET can be given by

The surface potential

at the source can be expressed as a function of the thus,

gate voltage by noting that

where

Note: For the subthreshold current becomes independent of the drain voltage. This is expected since in a long channel device, most of the applied drain voltage drops at the drain-substrate depletion region, and since the current is diffusive in nature, there is no change in the current with the drain voltage. Also, for large since the gradient of n is not affected by the drain voltage: a situation similar to BJTs, where the collector current in the forward active mode is independent of the collector-to-emitter voltage. Note: the subthreshold current is almost independent of the drain voltage The substrate bias shifts the threshold voltage to a more positive value, affects the surface potential, and thus the subthreshold current changes.

Fig.5.21 The subthreshold characteristics for a long channel device as a function of the gate voltage for different values of drain and substrate voltages. Subthreshold Current in a Short Channel Device

In a short channel device, the source and drain depletion widths may be a significant portion of the channel length L, and, hence, can not be neglected. To account for this effect, the term L in Eq.(5.67) is replaced by another term Leff, where where

where is the built-in voltage of the source/drain-substrate junction, and the surface potential is now found from the solution of the following

equation:

where

The curves clearly show shifts in the subthreshold current for different values of drain voltages, a characteristic typical of short channel devices. The subthreshold current is a strong function of temperature as well

Fig.5.22 The subthreshold characteristics for a short channel device as a function of gate voltage for different values of drain and substrate voltages.

Fig.5.23 The subthreshold characteristics as a function of gate voltage for two different temperatures (77 K and 300 K). MOSFET Capacitances and Equivalent Circuit

Note: in a MOSFET, the charges in the depletion region and the inversion layer depend on the gate, source, drain, and substrate potentials; and the derivatives of these charges with respect to the terminal voltages give rise to MOSFET capacitances. The small signal equivalent circuit shown in Fig.5.24 is the one used by the popular circuit simulation package called SPICE, and it contains: the drain-to-source current source IDS, two resistances (due to the quasi-neutral region resistances of the source and drain respectively)

10

METAL-OXIDE-SEMICONDUCTOR FIELD-EFFECT TRANSISTORS (MOSFETs) The gate-to-drain capacitance The gate-to-body capacitance The source-to-substrate capacitance

The drain-to-substrate capacitance

Note: in the presence of series source/drain resistances the intrinsic (internal to the device) conductance and transconductances are related to the extrinsic (measured) transconductances and conductance by the following equation:

EXAMPLE 5.3: An n-channel MOSFET has Determine SOLUTION: The intrinsic body transconductance The coefficient

Therefore, and respectively. Thus, significant degradation in the transconductances and drain conductance

may take place for large values of source/drain series resistances.

The two conductance terms appearing in the equivalent circuit shown in Fig.5.26(a) are the reverse-bias conductances of the sourcesubstrate and drain-substrate diodes, and their values are very small (tending to zero).

Fig.5.26(b) The simplified equivalent circuit of a MOSFET.

A simplified equivalent circuit is shown in Fig.5.26(b). For the circuit shown in Fig.5.26(b), the small signal voltage gain expression can be given by:

Note: at low frequencies, when the effects of the capacitances can be neglected, the voltage gain can be given by as expected. Another simplified equivalent circuit, suitable for the calculation of the current gain, is shown in Fig.5.26(c).

Fig.5.26(c) The alternate simplified equivalent circuit for a MOSFET suitable for the calculation of the short circuit current gain.

From Fig.5.26(c), the short circuit current gain can be easily found to be:

Thus, the unity gain cutoff frequency (i.e., the frequency at which the absolute value of the short circuit current gain is equal to unity) can be given by

where

Now, note that Also, the drain current Thus, Hence,

in the strong inversion region.

where

is the transit time of electrons in the channel.

This equation gives the theoretical maximum value for Assuming the characteristic switching time for a MOSFET is obtained as In reality, the measured switching times for MOSFETs are at least several times larger than that predicted above due to the parasitic and fringing capacitances that has to be added to the gate capacitance leading to the following modified expression for :

EXAMPLE 5.4: Calculate the unity-gain cutoff frequency for the MOSFET considered in Example 5.2. Compare this value with theoretical maximum value for , assuming SOLUTION: The unity-gain cutoff frequency

The theoretical maximum value for

= 7.96 GHz.

An actual device would show a cutoff frequency, which is smaller of the two, thus, the actual unity-gain cutoff for the device considered in Example 5.2 would be 2.82 GHz.

Types of MOSFETs

Broadly, MOSFETs can be categorized into two types: enhancement and depletion. Enhancement type devices are normally off, i.e., channel does not exist for and the applied must be greater than for the device to turn on. On the other hand, depletion type devices are normally on, i.e., channel does exist even for and the applied must be reduced below for the device to turn off. To put it simply, an n-channel enhancement type device has a positive , whereas an n-channel depletion type device has a negative . Similarly, a p-channel enhancement type device has a negative , whereas a p-channel depletion type device has a positive . The threshold voltage can be changed either by doping or by ion implantation, where high energy ions are made to bombard the surface and get embedded into it: since these are charged, they can change the charge state of the surface, and, hence, the threshold voltage. The shift in the threshold voltage is related to the ion density by the relation: eg., negative ions (like Boron) implanted in a pchannel (n-substrate) device will compensate some of the positive depletion charges and make the threshold voltage less negative, however, note the same ions would shift the threshold voltage to more positive for nchannel (p-substrate) device.

EXAMPLE 5.5: An n-channel MOSFET with has a threshold voltage Determine the type and dose of ion implantation required to make it a depletion mode device with SOLUTION: The oxide capacitance per unit area The dose of ion implantation required

Since the threshold voltage is shifting towards negative value, hence, obviously, the type of implant required is positive ions (e.g., P, As, Sb, etc.), which would compensate the negative depletion charge of the substrate and push the threshold voltage towards negative direction.

Some Advanced Models Unified Charge Control Model for MOSFETs

For MOSFETs, the UCCM equation for MIS capacitors [Eq.(4.24)] has to be modified to account for the channel potential, thus, the inversion charge is related to the gate-source and channel potential as follows:

where is the quasi-Fermi (electrochemical) potential measured relative to the Fermi potential at the source side of the channel, and the parameter accounts for the dependence of the threshold voltage on the channel potential in strong inversion, and, hence, on the position along the channel.

In order to get a better understanding of the term first consider the simplified version of the charge control model, given by Now, in reality, the threshold voltage depends on the depletion charge. Taking into account the dependence of this charge on the channel potential, one can write the corresponding position dependent threshold voltage as

This makes the charge control equation nonlinear and difficult to use in device modeling. However, if Eq.(5.90) is linearized with respect to V, one can write where now is the value of the threshold voltage at the source side of the channel. Thus, one obtains A generalized solution for ns is used in UCCM, given by

This equation allows the direct determination of the carrier distribution along the channel as a function of Saturation Region: The Region of the Channel with Velocity Saturation

Of late, area of considerable interest, since an accurate modeling of the pinch-off region is essential in order to obtain an exact drain current model in saturation. Important to find a solution for the longitudinal field in the channel. The model relies on the fundamental assumption that the carrier velocity in the saturated part of the channel is constant and equal to the saturation velocity, which implies that the carrier sheet density in the saturated part of the channel is also constant. Another assumption made is that the substrate is lowly doped: this assumption oversimplifies the true physics of the saturation region, however, it also leads to a manageable theory with qualitatively correct features, which gives a fairly good fit to experimental data with a judicious choice of parameters such as the saturation velocity and the effective channel thickness. The intrinsic saturation voltage can be defined as the intrinsic drainsource voltage for which the longitudinal electric field at the drain end of the channel just becomes equal to the saturation field For the location in the channel where marks the boundary between the saturated and the non-saturated regions. The boundary point moves towards the source with increasing drainsource voltage: this effect is called the channel length modulation. Another important parameter is the channel potential at the boundary point The two parameters and on the intrinsic gate-source voltage and have to be determined self-consistently using the models for the two regions with the requirement that the potential, the electric field, and the velocity be continuous at For a description of the saturated region, it is necessary to consider a twodimensional Poisson's equation of the form

10

METAL-OXIDE-SEMICONDUCTOR FIELD-EFFECT TRANSISTORS (MOSFETs)

where are the longitudinal and transverse components of the electric field respectively, is the semiconductor dielectric permittivity, and is the charge density in the semiconductor The charge density consists of a mobile charge density and a depletion charge density is the substrate doping density. Integrating Eqn.(5.92) with respect to y from the semiconductor-insulator interface through the effective channel thickness , one obtains

where over the channel thickness and electron sheet density in the channel.

is the

At low substrate doping and with the device biased in strong inversion such that the vertical electric field at will be small compared to the vertical field at the interface, in which case can be neglected in Eqn.(5.93). Making the substitution where V is the average of the potential over the cross-section of the channel, Eqn.(5.93) can be written as

The electric field at the interface is obtained by equating the electric displacement at the two sides of the semiconductor-insulator interface, leading to

From the conditions of velocity saturation and current continuity, the electron sheet density should be a constant in the saturated region, and its value can therefore be determined at the boundary point where the GCA is still valid; thus,

where

is the threshold gate voltage, given by Eqn.(5.9).

The combination of Eqns.(5.94) to (5.96) and (5.9) leads to the following second order differential equation for the channel potential in the saturated region:

where is the characteristic length in the saturation region and is given by

It should be noted that the solution of Eqn.(5.97) is very sensitive to the magnitude of the characteristic length for the saturated region. In comparisons with experimental data, it is therefore convenient to treat as a fitting parameter rather than using Eqn.(5.98), which itself is a result of rough estimates and approximations. The general solution of Eqn.(5.97) can be written in the following form:

The coefficients A and B are determined from the boundary conditions, i.e., from the requirements that with the values respectively, leading to A relationship that links to the drain-source voltage is obtained by considering Eqn.(5.99) at the drain side of the channel:

where

with L being the gate length. resulting in

Equation (5.100) can be solved with respect to

Combining Eqns.(5.99) and (5.101), we find

A self-consistent determination of is based on a model for the nonsaturated part of the channel Owing to the complexity of Eqns.(5.99) to (5.101), it is extremely difficult to

derive explicit, analytical expressions for important electrical properties, e.g., the I-V characteristics, using the present model for the saturation region. However, a numerical solution can readily be obtained which may serve as a physically based reference for simpler, more empirical models. Nonetheless, it is possible to simplify the equations somewhat in certain limiting cases. For i.e., just beyond the onset of saturation, it can be written to the first order in

For

>

i.e., in deep saturation, we have

From Eqn.(5.105), we obtain

The solutions obtained represent only an approximation of the actual potential distribution in the saturation region, however, they clearly show that the potential rises exponentially with distance inside this region. Based on this result and on numerical simulations of the potential in the saturation region, a simplified empirical expression linking the drainsource voltage to the length of the saturation region has been proposed:

where the constant is determined from the condition of continuity in the drain conductance. Subthreshold Region

Area of considerable research for the last few years due to low-voltage/lowpower analog/digital circuit operation, where most of the devices operate very near the threshold region and some may even enter subthreshold operation. In the off state of the MOSFET, a finite drain current flows through the

device, since the channel is weakly inverted, and also that there is a finite injection rate of carriers from the source into the channel. In the subthreshold regime in short channel devices, a drain voltage induces lowering of the energy barrier between the source and the channel, this effect is called the drain induced barrier lowering (DIBL) effect. DIBL causes excess injection of charge carriers from the source into the channel, and gives rise to an increased subthreshold current. This current is detrimental to both as well as digital operation. Figure 5.27 shows qualitatively the band diagram and the potential distribution at the interface in the channel, At the interface, the channel consists of three regions, the source-channel junction with length the drain-channel junction with length and the middle region of length At the interface potential in the middle of the channel can be taken to be approximately constant. A drain-source bias gives rise to a positive contribution V(x) to the channel potential => the minimum in the interface potential will be localized at the source side of the channel at Associated with the shift in the potential minimum, there will be a reduction in the interface energy barrier between the source and the channel by this is the so-called drain induced barrier lowering (DIBL) effect.

DIBL is a short channel effect, which causes a drain voltage induced shift in the threshold voltage. The expression for the drain current in the drift-diffusion form can be given as where is the potential of the channel region referred to the potential of the source.

Fig.5.27 Band diagram and potential profile at the semiconductor insulator interface of an n-channel MOSFET. The symmetrical profiles correspond to and the asymmetrical profiles to The figure indicates the origin of the Drain Induced Barrier Lowering (DIBL) effect.

It is also assumed that the longitudinal electric field in the channel is sufficiently small (except for the junction region near the drain) such that velocity saturation can be neglected. Multiplying Eq.(5.108) by the integrating factor the right hand side of this equation can be made into an exact derivative, and a subsequent integration from source to drain yields (assuming that the current density remains independent of x):

where n(L) = n(0) equals the drain and source contact doping density (neglecting degeneracy).

With the source contact as the potential reference, at the source end, and at the drain end, where is the intrinsic drain-source

voltage. When the device length is not too small, the channel potential can be taken to be independent of x over a portion of the channel length, i.e., and the integral in the denominator of Eq.(5.109) is determined by the contribution from this portion of the channel. Note: from Fig.5.27, the length of this section is approximately equal to and the current density can be expressed as

For long channel devices, and the drain current can be obtained by integrating the current density over the cross-section of the conducting channel, thus,

where is the effective channel thickness, and is the constant potential at the semiconductor-insulator interface, and is defined relative to the source electrode.

Hence, although the interface potential relative to the interior of the p-type substrate is the built-in potential between the source

contact and the substrate) is positive, will be negative for n-channel MOSFETs. At threshold, the interface potential in the channel relative to the source can be expressed as is the potential relative to the interior of the substrate at threshold For simplicity, it is assumed that the substrate is shorted to the source; the effects of a substrate-source bias are found simply by replacing of course, such a replacement is only valid for negative or small positive values of , a positive comparable to would lead to a large substrate leakage current. Below threshold, the interface potential can be written as All these equations predict that the subthreshold drain current decreases nearly exponentially with decreasing this current is practically independent of the drain-source voltage. The effective channel thickness is given by

Note: this expression in only valid when i.e., in the depletion and weak inversion regions, and this condition is fulfilled for values of the drain current that are many orders of magnitude smaller than the threshold current. For short channel length devices, L should be replaced by as discussed earlier. 5.9.4 Drain Induced Barrier Lowering (DIBL) While dealing with short channel effects, the effective gate depletion charges were distributed evenly along the channel in order to estimate the threshold voltage shift.

10

METAL-OXIDE-SEMICONDUCTOR FIELD-EFFECT TRANSISTORS (MOSFETs)

While this may be a good approximation for it will fail to accurately predict the effect on of an applied drain-source voltage. The reason is that a portion of the additional depletion charge induced by the drain-source bias will be distributed nonuniformly from source to drain.

Fig.5.28 Distribution of depletion charge induced by an applied drainsource bias, indicated by the shaded region. is the part of the induced charge located in the central channel region, and which has its counter charge on the gate electrode

Likewise, the drain-source bias will induce a nonuniform shift V(x) in the interface potential along the channel which increases from V(0) = 0 at the source to at the drain. A model for the distribution of the induced shift V(x) in the interface potential along the channel as a result of the applied drain-source bias is required. From such a model, it is possible to calculate the interface potential near its minimum, which defines the barrier for charge injection into the channel (refer to Fig.5.27). An accurate estimate of the shift in the potential minimum is especially important since the channel current is exponentially dependent on the barrier height. In principle, this involves the solution of a 2-D Poisson's equation for the

whole device, using proper boundary conditions, however, this requires extensive numerical calculations. A simplified analytical calculation is presented below. Start by considering the 2-D Poisson's equation for the depletion region under the gate, away from the source and drain contact depletion regions. In the subthreshold region, the influence of the charge carriers on the electrostatics of the channel can be neglected, and the 2-D Poisson's equation can be written as

where are the longitudinal and perpendicular components of the electric field respectively.

Integrating this equation with respect to y from the semiconductorinsulator interface through the depletion region yields

where is the average of over the thickness of the depletion region, which can be estimated approximately from a one-dimensional theory as

The vertical component of the electric field at the semiconductorchannel interface can be found by requiring the electric displacement to be continuous across the interface, i.e.,

In the presence of a drain-source bias, the interface potential can be written as: where is the constant interface potential of the middle part of the channel when and V(x) is the addition to the channel potential caused by the applied drain-source voltage. " Away from the source and drain contacts, it can be assumed that " Now, consider Eq.(5.114) with and without an applied drain-source bias and express the net effect of the drain-source bias by taking the difference, i.e.,

where

is the depletion width for V = 0.

In Eq.(5.117), is replaced by assuming that V(x) inside the gate depletion region is relatively weakly dependent on the distance from the interface The second term on the left hand side of Eq.(5.117) is equal to the difference where is the value of Since both V(x) and its x-derivatives are small outside the depletion region of the drain contact, all terms in Eq.(5.117) can be expanded to first order in V to give

where

The general solution of Eq.(5.118) can be written as

where the coefficients A and B are determined from the boundary conditions.

Without much error, one can assume that Eq.(5.120) is also valid through the source-channel junction region in which case one has the boundary condition V(x = 0) = 0, which gives such that Eq.(5.120) can be written as

Here, is a constant that remains to be determined. Note: the shift in the conduction band at the channel side of the source-channel junction is identical to the DIBL (refer to Fig.5.27). In order to find the voltage V0, one has to consider the additional charges induced in the gate electrode and in the substrate as a result of the applied drain-source voltage.

Fig.5.29 Schematic overview of the drain bias induced charges and counter charges according to the principle of charge sharing: are the induced charges in the channel and the gate, the remaining charges and counter charges are those between the drain and the substrate and between the drain and the gate

In order to be consistent with the potential variation along the channel, calculated earlier, the corresponding sheet charge distribution along the channel has to be as follows:

where GCA is invoked.

Assuming for simplicity that Eq.(5.122) is valid over the range the following expression for is obtained by requiring that the integral of over this range equals

The induced channel depletion charge now remains to be determined. The shaded region in the substrate in Fig.5.30 indicates roughly the amount of additional depletion charge induced under the gate by the drain source bias, where is the depletion width of the drain-channel junction at zero drain-source voltage. From the concept of charge sharing, can be taken to some fraction of , i.e.,

where is of the order of 0.5, however, the value of this parameter and also can be adjusted to account for the shape and doping profiles in the drain junction (e.g., lowly doped drain (LDD) MOSFETs) and substrate (e.g., ion implantation); in other words, this fitting parameter is technology dependent.

Fig.5.30 Simplified model of the drain bias induced charge in the substrate under the gate (shown as an estimate of the depletion charge under the gate between the depletion boundaries for The induced channel charge is a fraction of according to the charge sharing principle.

The parameter i.e.,

can be obtained by substituting Eq.(5.124) into Eq.(5.123),

Substituting Eq.(5.125) in Eq.(5.121) and setting the injection barrier is found to be

the lowering of

Note: The barrier lowering predicted by Eq.(5.126) decreases exponentially with increasing gate length for For sufficiently small gate lengths or sufficiently high drain-source bias

such that the DIBL diverges and Eq.(5.126) is no longer valid => this condition corresponds to severe punchthrough in the device. By assuming that the ideality factor does not change significantly with bias conditions the shift in the interface potential can be evaluated as Thus, as a consequence of the barrier lowering, there will be a drain bias induced shift in the threshold voltage, given by

where

Fig.5.31 Experimentally determined threshold voltage shift as a function of drain-source voltage for two NMOS devices with effective gate lengths of 0.21 and 0.25 . Equation (5.127) is fitted to the two data sets, yielding = 0.056 (L = 0.21 ) and = 0.038 (L = 0.25 ).

Fig.5.32 Experimental values (symbols), fitted model calculations (solid lines), and exponential approximation (dotted lines) of shift in threshold voltage as a function of effective gate length for T = 85 K (lower curve) and T = 300 K (upper curve).

Note: also varies close to exponentially with Note: an accelerated shift in the threshold voltage is observed at very small values of

10

METAL-OXIDE-SEMICONDUCTOR FIELD-EFFECT TRANSISTORS (MOSFETs)

The above estimates are simplified and partly empirical, i.e., they do not take directly into account, for example, the effect of the diffusion depth on the short channel effects, which may be important. Experimental studies show that a transition from long to short channel behavior takes place

when where are the drain-substrate and source-substrate depletion widths respectively.

This expression indicates the importance of the contact depth, however, indirectly, this behavior may also by accounted for by a judicious choice of the adjustable parameter Model for Mobility

The mobility model, which has gained wide acceptance and is used almost universally (including BSIM) is given by

where is referred to as the low-field mobility, and field-degradation coefficient for mobility.

is referred to as the

This is an extremely hot area of research, and lots of work in this area is going on around the world. There are plenty of other models also available in the literature; however, most of these are empirical and based on heuristics. Hot Electron Effects

As the device sizes are scaled down, the electric field in the channel increases, and, in the saturation region, the high field region near the drain occupies a large fraction of the channel length. This leads to the so-called hot electron effects, which manifest themselves in a superlinear increase in the drain current in the saturation region (the kink effect) and in the degradation of device parameters with time. These effects represent a major obstacle to further scaling down of MOSFET feature sizes. The physics of the hot electron effects can be described as follows. Electrons, while traveling from source to drain through the channel, experience a high field near the drain, and acquire large energy. When the energy thus acquired by an electron becomes equal to or greater than the band gap energy, then these electrons can collide with an atom and create EHPs (impact ionization EHP generation). The generated holes are pushed into the bulk due to the electric field, thus constituting the substrate current, and the electrons increase the drain current in the saturation region, thus causing the kink in the drain current characteristics. Some of these electrons may even acquire such a large energy from this field that they can surmount the barrier and get trapped in the oxide => this gives rise to instability in the device behavior, since these electrons can alter the charge states in the oxide. The process of EHP generation can be described by a generation rate G, which is an exponential function of the maximum electric field in the channel , which is reached at the drain:

where A is a constant, is the drain current, and is the characteristic field for the impact ionization, given by where is the energy required for an ionization event, and is the mean free path for the ionization process.

Typical value of is 1.7 mV/cm for Si n-channel MOSFETs. The generation rate is proportional to the drain current since it ought to be proportional to the product of the electron sheet density in the channel and the electron velocity. The maximum electric field is given by is the intrinsic drain-source voltage, is the intrinsic drain-source saturation voltage, and is the length of the pinch-off region, given by

where is the field required for velocity saturation, and is a characteristic length of the electric field variation in the high field region near the drain and is given by

The substrate current

is proportional to the generation rate, hence,

where B is a constant

Equation (5.133) can be rewritten as

where

Analysis shows that only one iteration is sufficient to accurately solve this equation by iteration if is substituted by in Eq.(5.134). Note: the measured values of Y depend linearly on the drain-source voltage in the kink region, thus, Eq.(5.134) can be used for the extraction of the saturation voltage from the experimental data. Hot electrons can also tunnel into traps in the gate oxide near the drain. The negative charge in the oxide causes partial channel depletion near the

drain, leading to an increase in the channel resistance and a decrease in the threshold voltage in this region. Hence, the device characteristics change with time when the drain voltage is high enough to cause significant electron heating (i.e., under voltage stress). The increase in the channel resistance should lead to a shift in the drainsource saturation voltage (it increases) and a reduction in the drain-source current.

Fig.5.33 Measured Y versus

curves.

Fig.5.34

Measured I-V characteristics and Y-functions for an n-channel Si MOSFET: open symbols data before stress, dark symbols data after stress

at for 104 sec. As can be seen from Fig.5.34, the Y versus parallel shift as a result of the voltage stress. This electron trapping also causes a change by

curves experience a in the drain current, given

where

is a constant.

Fig.74 Measured values of

(in percent) under stress versus time.

MOSFET Models and SPICE Parameters

A large number of MOSFET models exist in literature, the most popular among them is the BSIM (Berkeley Short-Channel IGFET Model). Currently, significant research is going on in the area of MOSFET modeling, in order to make these models more accurate in describing device behavior for ultra-short channel length devices. There are different levels of these models, e.g. LEVEL 1: Shichman-Hodges LEVEL 2: Geometric based analytical model LEVEL 3: Semi-empirical short channel model LEVEL 4: BSIM LEVEL 5: New BSIM (BSIM2) LEVEL 6: MOS6 (Sakurai and Newton) LEVEL 7: Universal extrinsic short channel model LEVEL 8: Unified long channel model (UCCM)

LEVEL 9: Short channel model LEVEL 10: Unified intrinsic short channel model LEVEL 11: Unified extrinsic a-Si TFT model LEVEL 12: Polysilicon TFT model The list given above is by no means complete, and there are plenty more new models, which describe short channel device behavior more accurately than their predecessors.

For SPICE simulation, the MOS element is defined in the following way: MX ND NG NS NB MNAME <L=VALUE> <W=VALUE> <AD=VALUE> <AS=VALUE> <PD=VALUE> <PS=VALUE> <NRD=VALUE> <NRS=VALUE> <NRG=VALUE> <NRB = VALUE> <OFF> <IC=VDS,VGS,VBS> <TEMP=T> where MX is the device number; ND, NG, NS, and NB are the node numbers for the drain, gate, source, and substrate respectively; L and W are the channel length and channel width respectively, AD and AS are the areas of the drain and source respectively, PD and PS are the perimeters of the drain and source respectively, NRD, NRS, NRG, and NRB are the relative resistivities of the drain, source, gate, and substrate respectively in number of squares, OFF indicates an optional initial value for the element in a DC analysis, the optional initial value IC=VDS,VGS,VBS is to be used together with UIC (use initial condition) in a Transient analysis, and the optional TEMP value is the temperature at which this device operates. Parameters for LEVELs 1, 2, 3, and 6:

VTO KP

zero-bias threshold voltage process transconductance parameter body effect coefficient

GAMMA PHI

surface potential channel length modulation parameter

LAMBDA RD RS RG RB

quasi-neutral drain resistance quasi-neutral source resistance gate resistance bulk ohmic resistance

RDS CBD CBS IS PB

drain-source shunt resistance zero bias drain-substrate junction capacitance zero bias source-substrate junction capacitance source/drain-substrate junction saturation current built-in voltage of the source/drain-substrate junction gate-source overlap capacitance per meter channel width gate-drain overlap capacitance per meter channel width gate-substrate overlap capacitance per meter channel

CGSO CGDO CGBO

length RSH CJ drain/source diffusion sheet resistance

zero bias bulk junction bottom capacitance per square meter of junction area bulk junction bottom grading coefficient

MJ

CJSW zero bias bulk junction sidewall capacitance per meter of junction perimeter MJSW JS TOX NSUB NSS NFS bulk junction sidewall grading coefficient

bulk junction saturation current per square meter of junction area gate oxide thickness (m) substrate doping surface state density fast surface state density

TPG type of gate material: +1 (opposite of substrate), 1 (same as substrate), 0 (Al gate) XJ LD metallurgical junction depth (m) lateral diffusion along length (m)

WD UO

lateral diffusion along width (m) surface mobility

10

COMPOUND SEMICONDUCTOR FIELD-EFFECT TRANSISTORS(MESFETs) Introduction

Currently, compound semiconductor FETs play important role in the electronics industry, e.g., GaAs FET amplifiers, oscillators, mixers, switches, attenuators, modulators, and current limiters are widely used, as well as high-speed ICs based on GaAs FETs and heterostructures FETs (HFETs) have been developed. Basically obtained by combining elements from columns III and V of the periodic table, e.g., GaAs, InP, InAs, InSb, AlAs, etc., having a wide range of band gaps (both direct and indirect), lattice constants, and other physical properties. Solid-state solutions are also possible, e.g., by varying the composition x (from 0 to 1) continuously in the ternary compound , one may obtain a continuous change of the different material properties, as the material changes from GaAs to AlAs. GaAs is the most studied and understood compound semiconductor material, and has proved indispensable for many device applications, e.g., ultra high speed transistors to lasers and solar cells. Room temperature lattice constant of GaAs (5.653 ) is very close to that

of AlAs (5.661 ) => the heterointerface between these two materials would have very small density of interface states => ideal candidate for heterostructures lasers. Technological innovations, e.g., Molecular Beam Epitaxy (MBE) and Metal Organic Chemical Vapor Deposition (MOCVD), allow growth of heterostructures with very sharp and clean heterointerfaces, and have very precise control over doping and composition profiles, typical resolution being of the order of the atomic distances. Other compound semiconductors having applications in ultra high speed submicron devices include , GaP, InP, AlN, etc. Advantages of GaAs Systems

The room temperature electron mobility in GaAs (8500 ) is much higher than that in Si (1250 ), due to the lower electron effective mass in GaAs (0.067 , where is the rest mass for electrons) as compared to Si (0.98 for longitudinal effective mass and 0.19 for transverse effective mass). Also, under high electric fields, the light electrons experience "ballistic transport" in GaAs for submicron devices, i.e., the electrons may move

over a small distance without suffering any collision (with either lattice vibration or lattice imperfections) at all, and, thus, their instantaneous velocity can be far higher than that in Si. Such ballistic transport is observed in devices having active device dimensions of 0.1 or less. For devices having active dimensions between 0.1 and 1.5 , electron velocity "overshoot" effects are important, which may also result in boosting the electron velocity to considerably higher levels than the stationary values. These effects are related to the finite time that it takes for an electron to relax its energy. As shown in Fig.6.1, electrons very close to the injecting contact are moving ballistically and the electron velocity is proportional to time.

Fig.6.1 Electron velocity versus distance for electrons injected into a region of constant electric field.

Further from the contact, the velocity reaches a peak value, the electron suffers a collision, and then the velocity decreases. Note: due to the overshoot effects, the peak value of the velocity is much higher than the stationary value reached as the distance increases further. In Si, ballistic and overshoot effects may also occur, however, they are much less pronounced due to the larger electron effective mass. Another important advantage of GaAs and InP devices is the availability of semi-insulating substrates, which eliminate parasitic capacitances related to junction isolation, and makes high-speed operation possible and allows fabrication of micro strip lines with small losses (especially important for applications in Microwave Monolithic Integrated Circuits (MMICs)). Also, GaAs being a direct band gap semiconductor, it is highly suitable for optoelectronic applications and makes possible a monolithic integration of ultra high speed submicron transistors together with laser or LEDs on the same chip for use in optical communication. These devices also have better radiation hardness since the direct band gap results in high electron-hole recombination rates. New technologies, e.g., MBE and MOCVD, and availability of excellent heterostructures systems, e.g., AlGaAs/GaAs, GaInAs/InP, InGaAs/AlGaAs, etc., have opened up a plethora of new quantum devices, such as

Heterostructure Field Effect Transistors (HFETs), Heterojunction Bipolar Transistors (HBTs), Hot Electron Transistors (HETs), Induced Base Transistors (IBTs), Permeable Base Transistors (PBTs), Vertical Ballistic Transistors (VBTs), Planar Doped Barrier Transistors (PDBTs), etc. Drawbacks of GaAs Systems

As compared to Si technology, GaAs technology is far more complex and risky (since As is potentially a lethal substance). Also, since As have very high vapor pressure, they tend to evaporate from the surface, making the crystal Ga rich => technological problem. Si has an excellent native oxide ( ), having reasonably high dielectric constant and excellent breakdown strength. On the other hand, the native oxide grown on GaAs (yielding both ) is nonstoichiometric, have very poor electronic properties, and creates a very high density of interface states => GaAs MOSFETs still remain a dream. Alternate choices: wide band gap AlGaAs and AlN may substitute as an insulator, however, the performance is not encouraging. Recently, on GaAs (oxidizing thin layers of Si deposited on GaAs by MBE) technology holds some promise for developing GaAs MOSFETs sometime in the near future. In any case, currently Schottky barrier MEtal Semiconductor Field Effect Transistors (MESFETs), Junction Field Effect Transistors (JFETs), and Heterostructure Field Effect Transistors (HFETs) are the most commonly used GaAs devices. Major Application Areas

Mostly used for microwave and ultra high speed applications, where their high speed properties are the most important, hence, scaling down the device sizes in order to exploit the ballistic and/or overshoot effects of the electron velocity are especially important. Use in the areas of optoelectronics (direct band gap) radiation-hard electronics (rapid EHP recombination due to direct band gap) high-temperature electronics (large band gaps of most compound semiconductors permit their use at high enough temperature, without leakage becoming excessive) power devices (high breakdown field and the ability to speed-up their turn on by light) Modeling Aspects

Since this technology is much less developed than its Si counterpart, reliable circuit and device modeling is especially important, and development of accurate device models is a prerequisite for the commercialization of compound semiconductor technology. Accurate device models have to be based on insight into the physics of the

devices, obtained from numerical simulations such as self-consistent twodimensional Monte Carlo modeling. Clearly, numerical device simulations are not directly applicable to circuit design involving hundreds to thousands of transistors interacting with each other and with other circuit elements, nor in device design where numerous dependencies of device characteristics on the design parameters have to be optimized, nor in device characterization where the device and process parameters must be extracted from experimental data. All these tasks require accurate analytical or semi-analytical device models, which must be based on physical device and material parameters, rather than using look-up tables and simple interpolations of the measured device characteristics, in order the provide the necessary feedback between the fabrication process and the device and circuit design. Basic MESFET Models

GaAs MESFETs are widely used in both analog as well as digital applications, with their microwave performance challenging that of HFETs, and their IC integration scale rapidly approaching 100,000 transistors per chip and beyond. With thin, highly doped channels and low parasitic resistances, GaAs MESFETs can obtain high currents and transconductances.

Fig. 6.2 Schematic representation of a MESFET.

The gate electrode is deposited directly on the semiconductor and forms a Schottky barrier contact with the conducting channel underneath, between the source and drain ohmic contacts. The gate bias modulates the depletion region under the gate and, thus, modulates the effective width of the neutral channel and thus the current flow between source and drain. Note: the carriers under motion in the channel do not come under close proximity of the interface due to the depletion region and, thus, the problems related to interface traps are largely avoided. Also, since the forward voltage that can be applied to the gate is limited by the built-in potential of the Schottky barrier, hence, it is a drawback when the device is operated in enhancement (normally off) logic, however, this limitation is less severe for low power circuits operating with a low power

supply voltage. Historically, MESFETs were discussed in early days in terms of the Shockley model, where carrier velocity saturation effect was neglected, and it was assumed that current saturation at high drain-source bias took place as a result of the channel getting pinched-off at the drain side of the channel. This model may be applicable for devices having very long channel lengths, however, gives a poor description of modern day devices having gate lengths of the order of 1 m or less. A deeper insight into MESFET device physics can be obtained from a detailed two-dimensional Monte Carlo simulation, however, simple analytical of semi-analytical models based on the device physics are still required for circuit simulators. The Shockley Model

Consider first the gate region of a MESFET (intrinsic device) with a uniform channel doping , a channel thickness d, and a built-in voltage for the gate contact. With a channel potential V(x) (relative to the intrinsic source) and an intrinsic gate-source voltage , the depletion width can be expressed (using the gradual channel approximation [GCA]) as

where is the dielectric permittivity of the semiconductor and built-in voltage of the source-channel junction.

is the

The threshold voltage corresponds to the gate-source voltage at which the depletion width at zero drain-source bias (V = 0) equals the channel width, or, in terms of Eq.(6.1)

where is referred to as the pinch-off voltage, and for a uniformly doped channel, is given by

EXAMPLE 6.1: A GaAs ( = 12.9) n-channel MESFET has a uniform channel doping of and an active layer thickness d of 1 m. Determine the pinch-off voltage and the threshold voltage , assuming that the -source doping is 5 x .

SOLUTION: From Eqn.(6.3), the pinch-off voltage

The source channel junction is a high-low ( voltage is given by

-n) junction, thus, the built-in

Therefore, from Eqn.(6.2), the threshold voltage is given by = = 0.16 - 0.7 = - 0.54 V.

For > , the channel is not fully depleted and a finite neutral region exists in the channel, which allows a significant drain current to pass, with magnitude increasing with an increase in . For < , the channel is fully depleted, and the drain current drops to a low value, characteristic of the subthreshold region of operation. Note: from Eqn.(6.1), it is obvious that the depletion width under the gate increases from source to drain when a positive drain-source bias is applied. The depletion width at the drain side of the gate , where L is the gate length, is obtained by replacing the channel potential by the intrinsic drainsource voltage in Eqn.(6.1). In the absence of velocity saturation of carriers, increases with increasing until the channel is pinched-off, which occurs when = d, corresponding to
1 2 3

COMPOUND SEMICONDUCTOR FIELD-EFFECT TRANSISTORS(MESFETs)

In the Shockley model, it is assumed that the electron drift velocity is proportional to the absolute value of the longitudinal electric field E = |dV(x)/dx|, i.e., = E, where is the low-field electron mobility. Under GCA, the potential drop dV across a small length dx along the channel can be written as

where Id is the drain current, dR is the channel resistance of the small section of length dx, and W is the gate width.

Equation (6.4) is valid below pinch-off, i.e., < d. Substituting the expression for dd(x) from Eqn.(6.1) into Eqn.(6.4), and integrating x from 0 to L, and V(x) from 0 to , the following drain current

characteristic is obtained

is the conductance of the undepleted channel. Equation (6.5) is referred to as the fundamental equation for FETs, and is valid only for . From Eqn.(6.5), it can be easily shown that the channel conductance becomes zero when = , hence, it can be argued that the drain current saturates at this value of , called the saturation voltage and, according to the Shockley model, = , and the corresponding drain saturation current becomes

EXAMPLE 6.2: Consider the n-channel GaAs MESFET of Example 6.1 with L =1 and W = 5 . Determine the saturation drain voltage, drain current, and the transconductance for = 0.3 V, and VDS = 0.1 V and 0.5 V. Assume n = 8500 . SOLUTION: The saturation drain voltage = = = 0.3 + 0.54 = 0.24 V.

The conductance of the undepleted channel

For the first case, (= 0.1 V) is less (= 0.24 V), hence, the device is under linear mode of operation, and the drain current is given by

Since is quite small, hence, from the approximate relation given by Eqn.(6.10), = 60 A/V, which is quite close to the answer obtained. Now, for the second case, (= 0.5 V) is greater than (= 0.24 V), therefore, the device is under saturation mode of operation, and the drain current is given by

Velocity Saturation Model

In the Shockley model, it was assumed that the carrier drift velocity increases linearly with the electric field, and from current continuity, it follows that the carrier drift velocity at the drain side of the gate approaches infinity as the pinch-off condition = d is reached, which is, of course, absurd. Rather, carrier velocity saturation would occur at sufficiently high electric fields, which gives an alternate mechanism for current saturation in the device.

A simple way of dealing with carrier velocity saturation is to assume a twopiece linear velocity-field relationship of the form

where is the carrier saturation velocity, and is the electric field required for carrier velocity saturation. For E(L) , the results from the Shockley model are still valid. Hence, the new saturation voltage, defined as the drain-source voltage at the onset of carrier velocity saturation, can be determined from Eqn.(6.4) in combination with Eqns.(6.1) and (6.5), resulting in the expression

From Eqn.(6.13), it can be seen that the saturation voltage corresponding to the Shockley model, i.e., = is recovered when >> 1. On the other hand, in the opposite limit, i.e., when << 1, which corresponds to near velocity saturation in the entire channel, it is found that , where it is assumed that << z(1 - z), where or intermediate cases, can be found either by solving Eqn.(6.13) as a third order equation in or by solving the equation numerically. However, a simple interpolation formula for the saturation voltage can be established by combining the results for the two limiting cases, i.e.,

Likewise, an interpolation formula, valid for devices with relatively low pinch-off voltages, can be found for the saturation current

Note: the square law given by Eqn.(6.16) is of the same form as that used in the SPICE modeling of he saturation current in JFETs, and it has also been

used to describe the saturation characteristics in SPICE simulation of GaAs MESFETs. Later, a more general version of Eqn.(6.16) was proposed, which covered devices with higher pinch-off voltages

Equation (6.17) can be used to determine the dependence of and the device transconductance on channel doping, gate length, electron mobility, and saturation velocity. The velocity saturation model now allows making a rough estimate of the intrinsic high speed performance of the MESFET. From Eqn.(6.16), one can calculate the transconductance at the saturation point

Furthermore, it may be argued that the gate-source capacitance at saturation will be of the order of sLW/d, hence, the cutoff frequency can be written approximately as

From Eqn.(6.20), it is obvious that a high can be obtained using a small L and a small , however, it is also desirable to have a device with a high current level, which requires a large doping sheet density ( d), thus, the best tradeoff is therefore to use a thin and highly doped channel.

EXAMPLE 6.3: Assuming = 2 105 m/sec, determine the saturation drain voltage, saturation drain current, and the transconductance in the saturation region for = 0.5 V for the n-channel GaAs MESFET considered in Examples 6.1 and 6.2, assuming velocity saturation of the carriers in the channel. Compare the results with those obtained in Example 6.2. Also, estimate the cutoff frequency of the device. Use the data given in Examples 6.1 and 6.2. SOLUTION: The electric field required for velocity saturation in the channel Es = vs/ = 2 107/8500 = 2.35 kV/cm. Thus, = L = 0.24 V. Since and (= 0.7 V) are of the order, therefore, the saturation drain voltage can approximately be given by

Effect of Source/Drain Series Resistance

Source and drain series resistance and may play important roles in determining the I-V characteristics of GaAs MESFETs. These resistances can be taken into account by using the following relationships between the extrinsic (lower case subscripts) and intrinsic (upper case subscripts) drain-source and gate-source bias voltages.

The saturation current in terms of the extrinsic gate voltage swing readily obtained by combining Eqns.(6.16) and (6.22):
1 2 3

is

COMPOUND SEMICONDUCTOR FIELD-EFFECT TRANSISTORS(MESFETs)

Device Modeling for CAD

For device modeling suitable for Computer Aided Design (CAD), one has to model the I-V characteristics for the entire range of drain-source voltages,

not only in the saturation regime. An empirical interpolation expression for the full, extrinsic MESFET I-V characteristics was proposed using a hyperbolic tangent function

where is an empirical constant that accounts for the finite output conductance in saturation, and is the extrinsic channel conductance of the linear region, given by

where is the intrinsic channel conductance at very low drain-source voltage, and for a uniformly doped channel, from Eqn.(6.9):

The finite output conductance in saturation, described in terms of the constant in Eqn.(6.24), may be related to the short channel effects and to parasitic currents in the substrate, such as space charge limited current. Hence, the output conductance may be greatly reduced by using a heterojunctions buffer to prevent carrier injection into the substrate. The models discussed above are suitable for CAD of GaAs MESFETs and GaAs MESFET circuits, however, some important second-order effects are not included in these models, e.g., o subthreshold current and drain voltage induced shift in the threshold voltage, o deviation from the gradual channel approximation (GCA), which may be especially important at the drain side of the channel, o possible formation of a high field region (i.e., a dipole layer) at the drain side of the channel, o inclusion of diffusion and incomplete depletion at the boundary between the depletion region and the conducting channel, o ballistic or overshoot effects, o effects of donor diffusion from the contact regions into the channel, o effects of the passivating silicon nitride layer, and o effects of traps. These factors may still be included indirectly by adjusting the model parameters such as mobility, saturation velocity, pinch-off voltage, etc., however, in a rigorous way, they can only be handled using numerical solutions, though for practical circuit simulators used in circuit design, analytical or very simple numerical models are still a necessity. Backgating and Sidegating Effects

These effects may strongly influence GaAs MESFET I-V characteristics. Backgating describes the effect of the substrate bias on the MESFET characteristics, and sidegating refers to the effect of a nearby device on the characteristics of a given MESFET. These effects are related to the finite depletion region, which exists at the boundary between the MESFET active layer and the substrate. The width of this layer depends on the density of traps and on the position of the Fermi level in the substrate and may be found using an equivalent pjunction" model, which predicts a certain dependence of the depletion width and of the threshold voltage on the substrate bias. However, in practical circuits, sidegating usually plays a more important role than backgating, and an accurate modeling of sidegating effects is quite difficult. An empirical equation (similar to the body bias equation in MOSFETs) is utilized in order to describe sidegating:

where is the threshold voltage unaffected by sidegating, is the source potential, is the potential causing the sidegating or backgating, and is a constant with a typical value of 0.1.

Fig.6.3 Experimental (symbols) and calculated (solid line) threshold voltage dependence on sidegating voltage.

For sidegating, is a function of the distance between the device and the sidegating contact, with the experimental data presented in the literature predicting that is inversely proportional to this distance, and, usually, sidegating becomes negligible only when this distance becomes quite large (at least 30 to 40 m). Gate Leakage Current

The gate leakage current may play an important role in compound semiconductor field effect transistors where the gate and the channel are separated by the depletion region of the Schottky contact in GaAs MESFETs.

For enhancement mode compound semiconductor FETs, the gate current can play a dominant role and may even affect the value of the "intrinsic" drain-source current . The gate current is modeled by two equivalent Schottky diodes connected from the gate to the source and from the gate to the drain. Using the well known diode equation, the total gate current can be found as

where Jss is the reverse saturation current density, calculated using either the thermionic or the thermionic-field emission theory, L and W are the gate length and gate width respectively, and are the intrinsic gatesource and gate-drain voltages respectively, and are the gatesource and gate-drain Schottky diode ideality factors respectively, and is the thermal voltage.

Fig.6.4 MESFET equivalent circuits: (a) conventional equivalent circuit, and (b) equivalent circuit that takes into account the effect of the gate current on the channel current.

To a first order approximation, this simple model may be adequate for a semi-quantitative description of the gate current in GaAs MESFETs. A more accurate description proposed introduced effective electron temperatures at the source side and the drain side of the channel. The electron temperature at the source side of the channel is taken to be close to the lattice temperature, i.e., T, whereas the drain side electron temperature is assumed to increase with the drain-source voltage to reflect the heating of the electrons in this part of the channel where the electric field is large.

This effect can easily be taken into account by modifying Eqn.(6.28) to read

where and are the reverse saturation current densities for the gatesource and the gate-drain diodes respectively, and In most GaAs MESFETs, the reverse gate saturation current is dependent on the reverse bias, and this dependence can be described by:

where are the reverse diode conductances, and g is the reverse bias conduction parameter. These expressions reproduce MESFET leakage characteristics in excellent agreement with the experimental data. Under forward bias, assuming thermionic emission mechanism,

The equivalent circuit of Fig.6.4(b) takes into account the effect of gate current on the channel current. Actually, the gate current is distributed along the channel, with the largest current density taking place near the source side of the channel, which leads to a redistribution of the electric field along the channel, with an increase in the field near the source side of the device, and an overall decrease in the drain current. This drop can even result in a negative differential resistance.

Practice Problems 6.1 Determine the pinch-off voltage and the threshold voltage for an n-channel GaAs MESFET with channel doping = and an active layer thickness d = 0.5 . Assume the -source doping to be equal to 5 x .

6.2 Assume the device of Problem 6.1 has L = 2 and W = 25 . Using Shockley model, determine the saturation drain voltage, drain current, and the transconductance for = 1 V, and = 0.5 V and 1 V. Assume = 8500 . 6.3 Assuming , determine the saturation drain voltage, saturation drain current, and the transconductance in the saturation region for = 1 V for the n-channel GaAs MESFET considered in Problems 6.1 and 6.2, assuming velocity saturation of the carriers in the channel. Compare the results with those obtained in Problem 6.2. Also, estimate the cutoff frequency of the device. Use the data given in Problems 6.1 and 6.2. 6.4 Consider a junction formed between an n-type GaAs MESFET channel doped at 2 x and a semi-insulating substrate. Model the substrate as a GaAs layer doped with deep acceptors with acceptor levels 0.7 eV above the top of the valence band. Sketch the band diagram and comment on the acceptor population versus distance, the depletion region width, and the total charge in the depletion layer. 6.5 Using the constant mobility model, calculate the MESFET and MOSFET transconductances in the saturation region for devices with a gate length of 5 and compare their dependencies on the gate voltage swing. The threshold voltage is = 1 V for both devices. Choose other device data of your choice. How should one modify the MESFET design to approach the shape of the MOSFET transconductance versus gate voltage dependence? 6.6 Use the saturation velocity model to calculate the MESFET and MOSFET transconductances in the saturation region for devices with a gate length of 1 and compare their dependencies on the gate voltage swing. The threshold voltage is = 1 V for both devices. Choose other device data of your choice. 6.7 Choosing device data of your choice, calculate and plot the device threshold voltage as a function of the substrate doping. Discuss the advantages and disadvantages of a high substrate doping. 6.8 How would you scale the MESFET channel doping and thickness with the gate length? Explain. 6.9 What are the possible advantages and disadvantages of a MESFET with a lowly doped region near the drain? 6.10 A constant MESFET transconductance is very important for microwave applications since it allows one to reduce intermodulation distortion. Discuss how a MESFET doping profile can be tailored to obtain a region of the transfer characteristic with a nearly constant transconductance. For simplicity, assume complete velocity saturation in the channel.