Professional Documents
Culture Documents
BY
PART-A
R.Y.M.E.C, BLY
Page 1
HDL Lab
Experiment No. 1
Aim: Write VHDL and verilog codes to realize all the logic gates.
VHDL Code library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity gates is port ( ain, bin : in std_logic; op_not, op_and, op_or : out std_logic; op_nand, op_nor : out std_logic; op_xor, op_xnor: out std_logic ); end gates; architecture logic_gates of gates is begin op_not<= not ain; op_and<= ain and bin; op_or<= ain or bin; op_nand<= ain nand bin; op_nor<= ain nor bin; op_xor<= ain xor bin; op_xnor<= ain xnor bin; end logic_gates;
R.Y.M.E.C, BLY
Page 2
HDL Lab
A B
2 1 3 AND2
A B
2 1 3 OR2
AND: Y= AB
OR: Y=A+B
A
INV
A B
2 1 3 NAND2
NOT: Y= A
NAND: Y= (AB)=A+B
A B
2 1 3 NOR2
A B
2 1 3 XOR2
A B
2 3 XNOR2
R.Y.M.E.C, BLY
Page 3
HDL Lab
0 1 1 1 0 1 1 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1 1 0 0 0 1
Verilog Code
module (ain, bin, op_or, op_and, op_not, op_xor, op-xnor, op_nand, op_nor); input ain, bin; output op_or, op_and, op_not, op_xor, op-xnor, op_nand, op_nor;
assign op_or = ain|bin; assign op_and = ain & bin; assign op_not = ~ ain assign op_xor = (ain ^ bin); assign op_xnor = ~ (ain ^ bin); assign op_nand = ~ (ain & bin); assign op_nor =~ (ain | bin); endmodule
R.Y.M.E.C, BLY
Page 4
HDL Lab
Experiment No. 2 Aim: Write VHDL and verilog codes for the following combinational designs.
entity DECODER is Port ( DIN : in std_logic_vector(1 downto 0); DOUT : out std_logic_vector(3 downto 0)); end DECODER; architecture Behavioral of DECODER is begin process(DIN) begin case DIN is when "00" => DOUT <= "0001"; when "01" => DOUT <= "0010"; when "10" => DOUT <= "0100"; when "11" => DOUT <= "1000"; when others => null; end case; end process; end Behavioral;
R.Y.M.E.C, BLY
Page 5
HDL Lab
2 TO 4 DECODER
EN
SEL(1)
INST1 INV
SEL(0)
INST2 INV
D0 D1 D2 D3
TRUTH TABLE
EN
Output D 0 D0 D1 D2
1 0 0 0
X 0 0 1
R.Y.M.E.C, BLY
Page 6
HDL Lab
0 1 1 D3
module decode_24(DIN,DOUT); input [1:0] DIN; output [3:0] DOUT; reg [3:0] DOUT; always @(DIN) begin case (DIN) 2'b00 : DOUT=4'b0001; 2'b01 : DOUT=4'b0010; 2'b10 : DOUT=4'b0100; default: DOUT=4'b1000; endcase end endmodule
R.Y.M.E.C, BLY
Page 7
HDL Lab
b.VHDL code for 8 to 3 encoder with priority. library IEEE; use IEEE.STD_LOGIC_1164.ALL;
entity enwp is port ( din : in std_logic_vector(7 downto 0); dout : out std_logic_vector(2 downto 0)); end enwp; architecture enwp_arch of enwp is begin process(din) begin case din is when "00000001" => dout<="000"; when "00000010" => dout<="001"; when "00000100" => dout<="010"; when "00001000" => dout<="011"; when "00010000" => dout<="100"; when "00100000" => dout<="101"; when "01000000" => dout<="110"; when "10000000" => dout<="111"; when others => dout<="zzz"; end case; end process; end enwp_arch;
R.Y.M.E.C, BLY
Page 8
HDL Lab
8 TO 3 ENCODER
X( 7
0)
0)
GS
E 1 0
X(7) X 1
X(6) X 1
X(5) X 1
X(4) X 1
X(3) X 1
X(2) X 1
X(1) X 1
X(0) X 1
GS 1 1
EO 1 0
Y(2) 1 1
Y(1) 1 1
Y(0) 1 1
R.Y.M.E.C, BLY
Page 9
HDL Lab
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 0 X 1 1 1 1 1 0 X X 1 1 1 1 0 X X X 1 1 1 0 X X X X 1 1 0 X X X X X 1 0 X X X X X X 0 X X X X X X X 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0
module ENCODE (DIN, DOUT); input [7:0] DIN; output [2:0] DOUT; reg [2:0] DOUT; always @ ( DIN ) begin casex ( DIN ) 8'b00000001 : DOUT 8'b0000001x : DOUT 8'b000001xx : DOUT 8'b00001xxx : DOUT 8'b0001xxxx : DOUT 8'b001xxxxx : DOUT 8'b01xxxxxx : DOUT 8'b1xxxxxxx : DOUT endcase end endmodule
= = = = = = = =
R.Y.M.E.C, BLY
Page 10
HDL Lab
HDL Lab elsif d_in=01000000 then d_out<= "110"; else d_out<=111; end if; end process; end architecture encwopri_arch;
E 1 0 0 0 0 0 0 0 0 0
X(7) X 1 1 1 1 1 1 1 1 0
X(6) X 1 1 1 1 1 1 1 0 1
X(5) X 1 1 1 1 1 1 0 1 1
X(4) X 1 1 1 1 1 0 1 1 1
X(3) X 1 1 1 1 0 1 1 1 1
X(2) X 1 1 1 0 1 1 1 1 1
X(1) X 1 1 0 1 1 1 1 1 1
X(0) X 1 0 1 1 1 1 1 1 1
GS 1 1 0 0 0 0 0 0 0 0
EO 1 0 1 1 1 1 1 1 1 1
Y(2) 1 1 1 1 1 1 0 0 0 0
Y(1) 1 1 1 1 0 0 1 1 0 0
Y(0) 1 1 1 0 1 0 1 0 1 0
R.Y.M.E.C, BLY
Page 12
HDL Lab
b.Verilog code for 8 to 3 encoder without priority. module ENCODE(DIN,DOUT); input [7:0] DIN; output [2:0] DOUT; reg [2:0] DOUT; always @(DIN) begin case (DIN) 8'b00000001 : DOUT = 3'b000; 8'b00000010 : DOUT = 3'b001; 8'b00000100 : DOUT = 3'b010; 8'b00001000 : DOUT = 3'b011; 8'b00010000 : DOUT = 3'b100; 8'b00100000 : DOUT = 3'b101; 8'b01000000 : DOUT = 3'b110; 8'b10000000 : DOUT = 3'b111; endcase end
endmodule
R.Y.M.E.C, BLY
Page 13
HDL Lab
entity mux_81 is Port ( inp : in std_logic_vector(7 downto 0); sel : in std_logic_vector(2 downto 0); outp: out std_logic); end mux_81; architecture mux_arch of mux_81 is
begin process (inp,sel) begin case sel is when "000" => outp <= inp(0); when "001" => outp <= inp(1); when "010" => outp <= inp(2); when "011" => outp <= inp(3); when "100" => outp <= inp(4); when "101" => outp <= inp(5); when "110" => outp <= inp(6); when others => outp <= inp(7); end case; end process;
R.Y.M.E.C, BLY Page 14
HDL Lab
end mux_arch;
8 TO 1 MUX
EN
SEL(2) SEL(1)
SEL(0)
INV3
INV2
INV1
D0
2 3 4 5 6 2 3 4 5 6 2 3 4 5 6 2 3 4 5 6 2 3 4 5 6 2 3 4 5 6 2 3 4 5 6 2 3 4 5 6
U1 1
AND5 U2 1
D1
AND5 U3 1
D2
D3
AND5 U5 1
D4
D5
AND5 U7 1
D6
AND5 U8 1
D7
AND5
logic diagram
Page 15
HDL Lab
EN
0 1 1 1 1 1 1 1
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
c. Verilog code for 8 to 1 Multiplexer. module mux_81(inp,sel,outp); input [7:0] inp; input [2:0] sel; output outp; reg outp; always @ (sel,inp) begin case(sel) 3'b000 : outp = inp[0]; 3'b001 : outp = inp[1]; 3'b010 : outp = inp[2]; 3'b011 : outp = inp[3]; 3'b100 : outp = inp[4]; 3'b101 : outp = inp[5]; 3'b110 : outp = inp[6]; default : outp = inp[7]; endcase end
endmodule
R.Y.M.E.C, BLY
Page 16
HDL Lab
d.VHDL code for 4-bit Binary to Gray code converter. library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity bin_to_gry is Port ( b3,b2,b1,b0 : in std_logic; g3,g2,g1,g0 : out std_logic); end bin_to_gry; architecture Behavioral of bin_to_gry is begin g3<=b3; g2<=b2 xor b3; g1<=b1 xor b2; g0<=b0 xor b1; end Behavioral;
R.Y.M.E.C, BLY Page 17
HDL Lab
BINARY TO GRAY
B3
U3 2
G3
1 3 XOR2 U2 2
B2 B1 B0
TRUTH TABLE
G2 G1 G0
1 3 XOR2 U1 2 1 3 XOR2
Decimal
0 1 2
Binary
B3B2B1B0
Gray
G3G2G1G0
R.Y.M.E.C, BLY
Page 18
HDL Lab
3 4 5 6 7 8 9 10 11 12 13 14 15 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0010 0110 0111 0101 0100 1100 1101 1111 1110 1010 1011 1001 1000
d.Verilog code for 4-bit Binary to Gray code converter. module bin_to_gry(b,g); input [3:0]b; output [3:0]g;
endmodule
R.Y.M.E.C, BLY
Page 19
HDL Lab
e. VHDL code for 1 to 8 Demultiplexer. library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following lines to use the declarations that are -- provided for instantiating Xilinx primitive components. --library UNISIM; --use UNISIM.VComponents.all; entity dmux_18 is Port ( din : in std_logic; sel : in std_logic_vector(2 downto 0); dout : out std_logic_vector(7 downto 0)); end dmux_18; architecture Behavioral of dmux_18 is begin process (din,sel) begin case sel is when "000" => dout(0)<=din; when "001" => dout(1)<=din;
R.Y.M.E.C, BLY Page 20
HDL Lab when "010" => dout(2)<=din; when "011" => dout(3)<=din; when "100" => dout(4)<=din; when "101" => dout(5)<=din; when "110" => dout(6)<=din; when others => dout(7)<=din; end case; end process; end Behavioral;
1 TO 8 DEMUX
EN
SEL(2)
SEL(1)
SEL(0)
INV3
INV2
INV1
2 3 4 5 6 2 3 4 5 6 2 3 4 5 6 2 3 4 5 6 2 3 4 5 6 2 3 4 5 6 2 3 4 5 6 2 3 4 5 6
U1 1
D0 D1 D2 D3 D4 D5 D6 D7
AND5 U2 1
AND5 U3 1
AND5 U4 1
AND5 U5 1
AND5 U6 1
AND5 U7 1
AND5 U8 1
AND5
Page 21
HDL Lab
LOGIC DIAGRAM EN CONTROL INPUTS SEL(3) 0 1 1 1 1 1 1 1 1 X 0 0 0 0 1 1 1 1 SEL(3) X 0 0 1 1 0 0 1 1 SEL(3) X 0 1 0 1 0 1 0 1 0 D0=Y D1=Y D2=Y D3=Y D4=Y D5=Y D6=Y D7=Y OUTPUTS
e. Verilog code for 1 to 8 Demultiplexer. module dmux_18(din,sel,dout); input din; input [2:0] sel; output [7:0] dout; reg [7:0] dout; always @(sel,din) begin case (sel) 3'b000 : dout[0]=din; 3'b001 : dout[1]=din; 3'b010 : dout[2]=din; 3'b011 : dout[3]=din; 3'b100 : dout[4]=din; 3'b101 : dout[5]=din; 3'b110 : dout[6]=din; default : dout[7]=din; endcase end endmodule
R.Y.M.E.C, BLY
Page 22
HDL Lab
4- BIT COMPARATOR
1- BIT COMPARATOR
A
INV1
U1 2 3 AND2
AB\
1 U3 2 1 3 NOR2
U2 2
B
INV2
1 3 AND2
A\B
Logic Diagram
TRUTH TABLE R.Y.M.E.C, BLY Page 24
HDL Lab
Comparing inputs
A 0 0 1 1 B 0 1 0 1 Y=(A>B) 0 0 1 0
Outputs
Y=(A<B) 0 1 0 0 Y=(A=B) 1 0 0 1
f. Verilog code for 1 bit comparator. module comp(a,b,gt,lt,eq); input a,b; output gt,lt,eq; reg gt,lt,eq; always @(a,b) begin eq = ~(a ^ b); lt = (~a) & b; gt = a & (~b); end endmodule
R.Y.M.E.C, BLY
Page 25
HDL Lab
g. VHDL code for 4 bit comparator. library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following lines to use the declarations that are -- provided for instantiating Xilinx primitive components. --library UNISIM; --use UNISIM.VComponents.all; entity comparator is Port ( a,b : in std_logic_vector(3 downto 0); x,y,z : out std_logic); end comparator; architecture Behavioral of comparator is begin process (a,b) begin x<='0'; y<='0'; z<='0'; if(a<b)then
R.Y.M.E.C, BLY Page 26
HDL Lab x<='1'; elsif (a=b)then y<='1'; elsif (a>b)then z<='1'; end if; end process;
end Behavioral;
R.Y.M.E.C, BLY
Page 27
HDL Lab
4-BIT COMPARATOR
g. Verilog code for 4 bit comparator. module comparator(a,b,x,y,z); input [3:0] a,b; output x,y,z; reg x,y,z; always @ (a,b) begin
R.Y.M.E.C, BLY Page 28
HDL Lab
x = 1'b0; y = 1'b0; z = 1'b0; if ( a<b) x = 1'b1; else if (a==b) y = 1'b1; else if (a>b) z = 1'b1; end
endmodule
Experiment No.3Aim: To write a VHDL and Verilog code to describe the functions of a Full adder using
three modeling styles. Data flow model Behavioral model Structural model
R.Y.M.E.C, BLY Page 29
HDL Lab
a.VHDL Code for Full adder using Data Flow model. library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity FA is Port ( A,B,CIN : in std_logic; COUT,SUM : out std_logic); end FA; architecture FA_DTFL of FA is begin SUM <= (A xor B xor CIN); COUT <= (A and B) or (B and CIN) or (A and CIN); end FA_DTFL;
a.Verilog Code for Full adder using Data Flow model. module FA_DF (A,B,CIN,COUT,SUM); input A,B,CIN; output COUT,SUM;
R.Y.M.E.C, BLY Page 30
HDL Lab assign SUM = (A ^ B ^ CIN); assign COUT = (A & B) | (B & CIN) | (A & CIN); endmodule
FULL ADDER
HALF ADDER
B Cin
U1 2 3 4 XOR3 U2 2 1 3 1
A(+)B(+)CSUM
A B
A(+)B
SUM
CARRY
AND2
A.B
Page 31
CARRY
HDL Lab
Logic Diagram
TRUTH TABLE
INPUTS
OUTPUTS
A 0 0 0 0 1 1 1 1
B 0 0 1 1 0 0 1 1
Cin 0 1 0 1 0 1 0 1
SUM 0 1 1 0 1 0 0 1
CARRY 0 0 0 1 0 1 1 1
b.VHDL code for full adder using Behavioral model. library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity FA is Port (A,B,CIN : in std_logic; COUT,SUM : out std_logic); end FA;
R.Y.M.E.C, BLY
Page 32
HDL Lab architecture FA_BEHAVE of FA is begin process(A,B,CIN) begin SUM <= (A xor B xor CIN); COUT <= (A and B) or (B and CIN) or (A and CIN); end process; end FA_BEHAVE;
module FA_BEHAVE (A,B,CIN,COUT,SUM); input A,B,CIN; output SUM, COUT; reg SUM,COUT;
R.Y.M.E.C, BLY
Page 33
HDL Lab always @(A,B,CIN) begin SUM = (A ^ B ^ CIN); COUT = (A & B) | (B & CIN) | (A & CIN); end;
endmodule
c.VHDL code for Full adder using structural model. library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity FULL_ADD is
R.Y.M.E.C, BLY Page 34
HDL Lab Port (A,B,CIN: in std_logic; SUM,COUT: out std_logic); end FULL_ADD; architecture STRUCT_ARCH of FULL_ADD is component HALF_ADD is port(A,B: in std_logic; S,C: out std_logic); end component; component OR21 is port(A,B: in std_logic; C: out std_logic); end component; signal S1,C1,C2 : std_logic; begin H1: HALF_ADD port map (A,B,S1,C1); H2: HALF_ADD port map (S1,CIN,SUM,C2); O1: OR21 port map (C1,C2,COUT); end STRUCT_ARCH; -- COMPONENT HALF_ADD library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity HALF_ADD is port (A,B: in std_logic; S,C: out std_logic); end HALF_ADD; architecture HALF_ADD_ARCH of HALF_ADD is begin S <= A xor B; C <= A and B; end HALF_ADD_ARCH;
R.Y.M.E.C, BLY
Page 35
HDL Lab -- COMPONENT OR21 library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity OR21 is port (A, B : in std_logic; C : out std_logic); end OR21; architecture OR21_ARCH of OR21 is begin C <= A or B; end OR21_ARCH;
c.Verilog code for Full adder using structural model. module FA_STR (A,B,CIN,SUM,COUT); input A, B, CIN; output SUM, COUT; wire S1,C1,C2;
R.Y.M.E.C, BLY Page 36
HDL Lab
// COMPONENT HA module HA(X,Y,S,C); input X; input Y; output S; output C; assign S= X ^ Y; assign C= X & Y; endmodule
//COMPONENT OR21 module OR21(I1,I2,I3); input I1; input I2; output I3; assign I3 = I1 | I2; endmodule
Experiment No 4 : Aim: To write a VHDL and Verilog code to ALU VHDL code for ALU library IEEE;
R.Y.M.E.C, BLY Page 37
HDL Lab use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following lines to use the declarations that are -- provided for instantiating Xilinx primitive components. --library UNISIM; --use UNISIM.VComponents.all; entity alu is Port (a : in std_logic_vector(3 downto 0); b : in std_logic_vector(3 downto 0); opcode : in std_logic_vector(3 downto 0); y : out std_logic_vector(3 downto 0)); end alu; architecture Behavioral of alu is begin process(a,b,opcode) begin case opcode is when "0000"=>y<=a; when "0001"=>y<=a+1; when "0010"=>y<=a-1; when "0011"=>y<=b; when "0100"=>y<=b+1; when "1000"=>y<=not a; when "1001"=>y<=not b; when "1010"=>y<=a and b; when "1011"=>y<=a or b; when "1100"=>y<=a nand b; when "1101"=>y<=a nor b; when "1110"=>y<=a xor b; when others=>y<=a xnor b; end case; end process; end Behavioral;
Experiment No. 5 Aim: Develop the HDL code for the following flip-flops SR, D, T, JK.
VHDL code for SR flip flop. library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;
R.Y.M.E.C, BLY Page 38
HDL Lab -- Uncomment the following lines to use the declarations that are -- provided for instantiating Xilinx primitive components. --library UNISIM; --use UNISIM.VComponents.all; entity srff is Port (sr : in std_logic_vector(1 downto 0); q : buffer std_logic; clk: in std_logic); end srff; architecture Behavioral of srff is begin process (clk) begin if (rising_edge (clk))then case sr is when "00"=>q<=q; when "01"=>q<='0'; when "10"=>q<='1'; when others=>q<='Z'; end case; end if; end process; end Behavioral;
SR FLIP FLOP
R.Y.M.E.C, BLY
Page 39
HDL Lab
Clk
Q\
TRUTH TABLE
S 0 0 1 1
R 0 1 0 1
Q+ Q 0 1 -
HDL Lab
module srff(sr, clk, q); input clk; output q; reg q; always @(clk) begin case(sr) 2b00: q=q; 2b01: q=0 2b10: q=1; 2b11: q=Z; endcase end endmodule
HDL Lab
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following lines to use the declarations that are -- provided for instantiating Xilinx primitive components. --library UNISIM; --use UNISIM.VComponents.all; entity d_fvhdl is Port ( d,clk : in std_logic; q : out std_logic); end d_fvhdl; architecture Behavioral of d_fvhdl is begin process(d,clk) begin if(rising_edge(clk))then q<=d; end if; end process; end Behavioral;
R.Y.M.E.C, BLY
Page 42
HDL Lab
D FLIP FLOP
Clk
Q\
TRUTH TABLE
CLK
D 0 1
Q+ 0 1
HDL Lab module d_fverilog(d,clk,q); input d,clk; output q; reg q; always@(clk) begin q<=d; end
endmodule
HDL Lab
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; library UNISIM; use UNISIM.VComponents.all; entity jk_ff is Port ( jk : in std_logic; Clk : in std_logic; q,qb : out std_logic ); end jkff; architecture jkff_arch of jkff is begin process(clk) variable temp1, temp2:std_logic; begin if(rising_edge(clk) case jk is when 00=>temp1:=temp1; when 01=>temp1:=0; when 10=>temp1:=1; when others=> null; end case; q<=temp1; temp2:=not temp1; qb<=temp2; endif; end process; end jkff_arch;
R.Y.M.E.C, BLY
Page 45
HDL Lab
JK FLIP FLOP
U5 2
J CLK
C1
1 3
U3 2 1 3 2 1 3 NAND2 NAND2 U1
AND2 INST1
Q\
TRUTH TABLE
J 0 0 1 1
K 0 1 0 1
Q+ Q 0 1 Q
R.Y.M.E.C, BLY
Page 46
HDL Lab
Verilog code for JK Flip flop. module jk_flipflopveri(jk,clk,q,qb); input [1:0] jk; input clk; output q,qb; reg q,qb; always@(posedge clk) begin case(jk) 2'b00:q=q; 2'b01:q=0; 2'b10:q=1; 2'b11:q=~q; endcase end
endmodule
R.Y.M.E.C, BLY
Page 47
HDL Lab
VHDL code for T flip flop. library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following lines to use the declarations that are -- provided for instantiating Xilinx primitive components. --library UNISIM; --use UNISIM.VComponents.all; entity t_ff is Port ( t,clk : in std_logic; q : out std_logic); end t_ff; architecture Behavioral of t_ff is begin process(clk,t) begin if(rising_edge(clk))then q<=not t; end if; end process; end Behavioral;
R.Y.M.E.C, BLY
Page 48
HDL Lab
T FLIPFLOP
Clk
Q\
TRUTH TABLE
CLK
T 0 1
Q+ 0
HDL Lab module t_ffverilog(clk,t,q); input clk,t; output q; reg q; always @(clk,t) begin q=~t; end
endmodule
Experiment No 6.
R.Y.M.E.C, BLY Page 50
HDL Lab
Aim: Design 4 bit binary, BCD counters(Synchronous reset and Asynchronous reset) and any sequence counters.
A. VHDL Code for BCD up-counter library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following lines to use the declarations that are -- provided for instantiating Xilinx primitive components. --library UNISIM; --use UNISIM.VComponents.all; entity bcd_async_up is Port ( clk,rn : in std_logic; q : out integer range 0 to 9); end bcd_async_up; architecture Behavioral of bcd_async_up is signal count:integer range 0 to 9:=0; begin process(clk,rn) begin if(rn='1')then count<=0; elsif(rising_edge(clk))then count<=count+1; end if; end process; q<=count; end Behavioral;
SYNCHRONOUS COUNTER
R.Y.M.E.C, BLY
Page 51
HDL Lab B.VHDL Code for BCD down-counter library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following lines to use the declarations that are -- provided for instantiating Xilinx primitive components. --library UNISIM; --use UNISIM.VComponents.all; entity bcd_async_dwn is Port ( clk,rn : in std_logic; q : out integer range 0 to 9); end bcd_async_dwn; architecture Behavioral of bcd_async_dwn is signal count:integer range 0 to 9:=0; begin process(clk,rn) begin if(rn='1')then count<=9; elsif(rising_edge(clk))then count<=count-1; end if; end process; q<=count; end Behavioral;
HDL Lab
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following lines to use the declarations that are -- provided for instantiating Xilinx primitive components. --library UNISIM; --use UNISIM.VComponents.all; entity binary_async_up is Port ( clk : in std_logic; rn : in std_logic; q : out std_logic_vector (3 downto 0)); end binary_async_up; architecture Behavioral of binary_async_up is signal count:std_logic_vector (3 downto 0):="0000"; begin process(clk,rn) begin if(rising_edge(clk)) then if(rn='1')then count<="0000"; else count<=count+1; end if; end if; end process; q<=count; end Behavioral;
R.Y.M.E.C, BLY
Page 53
HDL Lab D.VHDL Code for Binary Down counter library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following lines to use the declarations that are -- provided for instantiating Xilinx primitive components. --library UNISIM; --use UNISIM.VComponents.all; entity bin_async_dwn is port ( clk,rn : in std_logic; q : out std_logic_vector(3 downto 0)); end bin_async_dwn; architecture Behavioral of bin_async_dwn is signal count:std_logic_vector(3 downto 0):="1111"; begin process(clk,rn) begin if(rn='1')then count<="1111"; elsif(rising_edge(clk))then count<=count-1; end if; end process; q<=count; end Behavioral;
ASYNCHRONOUS COUNTER
HDL Lab library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following lines to use the declarations that are -- provided for instantiating Xilinx primitive components. --library UNISIM; --use UNISIM.VComponents.all; entity any_seq_cnt is Port ( clk : in std_logic; q : out std_logic_vector(3 downto 0)); end any_seq_cnt; architecture Behavioral of any_seq_cnt is begin process(clk) variable b: std_logic_vector(3 downto 0):="0000"; variable g: std_logic_vector(3 downto 0); begin if(rising_edge(clk))then g(3):=b(3); g(2):=b(3) xor b(2); g(1):=b(2) xor b(1); g(0):=b(1) xor b(0); q<=g; b:=b+"0001"; end if; end process; end Behavioral;
R.Y.M.E.C, BLY
Page 55
HDL Lab
Verilog code for Any Sequence counter module asc(clk, b, q); input clk; wire [3:0] b; output[3:0] q; assign b= 0000; always @(posedge(clk)) begin q[3]= b[3]; q[2]= b[3]^b[2]; q[1]= b[2]^b[1]; q[0]= b[1]^b[0]; b= b+0001; end endmodule
R.Y.M.E.C, BLY
Page 56
HDL Lab
PART-B
INTERFACING PROGRAMS
KEYMATRIX R.Y.M.E.C, BLY Page 57
HDL Lab
(a) LED segments (b) Four displays with common anode and (c) LED connection on CPLD or FPGA Board. a b 0 0 0 0 0 1 1 0 0 0 0 1 1 0 1 1 c 0 0 1 0 0 0 0 0 0 0 0 0 1 0 1 1 d 0 1 0 0 1 0 0 1 0 0 1 0 0 0 0 1 e 0 1 0 1 1 1 0 1 0 1 0 0 0 0 0 0 f 0 1 1 1 0 0 0 0 0 0 0 0 0 1 0 0 g 1 1 0 0 0 0 0 1 0 0 0 0 1 0 0 0
Binary
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0 1 0 0 1 0 0 0 0 0 0 1 0 1 0 0
HDL Lab use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; library UNISIM; use UNISIM.VComponents.all; --key0,1,2,3 keymatrix i/p --en1,2,3,4 are enable signals of 7 seg display --disp connects to 7 seg display lines --reset is swich i/p entity keymatrix is Port ( key0 : in std_logic; key1 : in std_logic; key2 : in std_logic; key3 : in std_logic; en1 : out std_logic; en2 : out std_logic; en3 : out std_logic; en4 : out std_logic; disp : out std_logic_vector(7 downto 0); row : out bit_vector(3 downto 0); clk : in std_logic; reset : in std_logic); end keymatrix; architecture Behavioral of keymatrix is --local signals signal temp : std_logic:='1'; signal bkey0: std_logic; signal bkey1: std_logic; signal bkey2: std_logic; signal bkey3: std_logic; signal bclk : std_logic; signal bclk1: std_logic; signal rowtemp: bit_vector(3 downto 0):="1110"; signal disptemp: std_logic_vector(3 downto 0); --sub component declaration of ibuf component ibuf port( i: in std_logic; o: out std_logic); end component; --sub component declaration of test count component testcnt port ( clk: in std_logic; one: out std_logic); end component; --component instantiation begin u1:ibuf port map( i => key0, o => bkey0); u2:ibuf port map( i => key1, o => bkey1); u3:ibuf port map( i => key2, o => bkey2); u4:ibuf port map( i => key3, o => bkey3);
R.Y.M.E.C, BLY
Page 59
HDL Lab u5:testcnt port map( clk => clk, one => bclk); u6:testcnt port map( clk => bclk, one => bclk1); en1 <= '0'; en2 <= '1'; en3 <= '1'; en4 <= '1'; pp1:process(bkey0,bkey1,bkey2,bkey3,reset,bclk1) begin --if reset ==1 display f on display if reset = '1' then disptemp <= "0000"; --else display the corrsponding pressed switch position else if bclk1'event and bclk1 = '1' then row <= rowtemp; if rowtemp = "1101" then if bkey0 = '0' then disptemp <= "0000"; elsif bkey1 = '0' then disptemp <= "0001"; elsif bkey2 = '0' then disptemp <= "0010"; elsif bkey3 = '0' then disptemp <= "0011"; end if; end if; if rowtemp = "1011" then if bkey0 = '0' then disptemp <= "0100"; elsif bkey1 = '0' then disptemp <= "0101"; elsif bkey2 = '0' then disptemp <= "0110"; elsif bkey3 = '0' then disptemp <= "0111"; end if; end if; if rowtemp = "0111" then if bkey0 = '0' then disptemp <= "1000"; elsif bkey1 = '0' then disptemp <= "1001";
R.Y.M.E.C, BLY
Page 60
HDL Lab elsif bkey2 = '0' then disptemp <= "1010"; elsif bkey3 = '0' then disptemp <= "1011"; end if; end if; if rowtemp = "1110" then if bkey0 = '0' then disptemp <= "1100"; elsif bkey1 = '0' then disptemp <= "1101"; elsif bkey2 = '0' then disptemp <= "1110"; elsif bkey3 = '0' then disptemp <= "1111"; end if; end if; rowtemp <= rowtemp rol 1; end if; end if; end process pp1; --to display on 7 seg pp2:process(disptemp) begin if disptemp = "0000" then disp <= "10001110"; elsif disptemp = "0001" then disp <= "10000011"; elsif disptemp = "0010" then disp <= "11111000"; elsif disptemp = "0011" then disp <= "10110000"; elsif disptemp = "0100" then disp <= "10000110"; elsif disptemp = "0101" then disp <= "10001000"; elsif disptemp = "0110" then disp <= "10000010"; elsif disptemp = "0111" then disp <= "10100100"; elsif disptemp = "1000" then disp <= "10100001"; elsif disptemp = "1001" then disp <= "10010000"; elsif disptemp = "1010" then disp <= "10010010"; elsif disptemp = "1011" then
R.Y.M.E.C, BLY
Page 61
HDL Lab disp <= "11111001"; elsif disptemp = "1100" then disp <= "11000110"; elsif disptemp = "1101" then disp <= "10000000"; elsif disptemp = "1110" then disp <= "10011001"; elsif disptemp = "1111" then disp <= "11000000"; end if; end process pp2; end Behavioral;
R.Y.M.E.C, BLY
Page 62
HDL Lab
2. STEPPER MOTOR
CPLD/FPGA
2. Aim: To write VHDL code to control speed, direction of DC and stepper motor a. STEPPER MOTOR:
R.Y.M.E.C, BLY Page 63
HDL Lab
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following lines to use the declarations that are -- provided for instantiating Xilinx primitive components. --library UNISIM; --use UNISIM.VComponents.all; entity stepper_motor_final is Port ( clock : in std_logic; cntrl : in std_logic; dout : out bit_vector(3 downto 0) ); end stepper_motor_final; architecture Behavioral of stepper_motor_final is --local signal declaration signal temp:bit_vector( 3 downto 0):= "0111"; signal bclk: std_logic; signal bclk1: std_logic; signal bclk2: std_logic; --sub component declaration of test count component testcnt is Port ( clk : in std_logic; one: out std_logic); end component; --component instantiation begin --port mapping of test cnt u1: testcnt port map( clk=> clock, one => bclk); u2: testcnt port map( clk=> bclk, one => bclk1); u3: testcnt port map( clk=> bclk1, one => bclk2); pp1:process( bclk2) begin if bclk2'event and bclk2 = '1' then if cntrl = '1' then temp <= temp rol 1 ; --anticlockwise rotation else temp <= temp ror 1; --clockwise rotation end if; end if; end process pp1; dout<=temp; end Behavioral; b. DC MOTOR: library IEEE; use IEEE.STD_LOGIC_1164.ALL;
R.Y.M.E.C, BLY Page 64
HDL Lab use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following lines to use the declarations that are -- provided for instantiating Xilinx primitive components. --library UNISIM; --use UNISIM.VComponents.all; entity dc_motor is Port ( psw : in std_logic_vector(2 downto 0); pdcm : out std_logic; clk : in std_logic); end dc_motor; architecture behavioral of dc_motor is signal sclkdiv : std_logic_vector(11 downto 0):= "000000000000"; signal p100k :std_logic; component testcnt is port(clk :in std_logic; one :out std_logic); end component; begin u1: testcnt port map(clk=>clk,one=>p100k); --10M/100=100k -- count upto 3000 process(p100k) begin if( rising_edge(clk)) then sclkdiv <= sclkdiv+1; end if; if(sclkdiv = "101110111000") then sclkdiv <= "000000000000"; end if; end process; process(psw,sclkdiv) variable vdcm : bit; begin if(sclkdiv = "000000000000") then vdcm := '1'; end if;
-- 1f4,320,44c,578,6a4,7d0,8fc,9c4, to vary the speeed of a dc motor if(psw = "000" and sclkdiv = "000111110100") then vdcm := '0'; elsif(psw = "001" and sclkdiv = "001100100000") then vdcm := '0'; elsif(psw = "010" and sclkdiv = "010001001100") then vdcm := '0'; elsif(psw = "011" and sclkdiv = "010101111000") then vdcm := '0'; elsif(psw = "100" and sclkdiv = "011010100100") then vdcm := '0'; elsif(psw = "101" and sclkdiv = "011111010000") then vdcm := '0';
R.Y.M.E.C, BLY Page 65
HDL Lab
Dept. of Instumentation Technology elsif(psw = "110" and sclkdiv = "100011111100") then vdcm := '0'; elsif(psw = "111" and sclkdiv = "100111000100") then vdcm := '0'; end if;
if(vdcm = '1') then pdcm <= '1'; else pdcm <= '0'; end if; end process; end behavioral;
R.Y.M.E.C, BLY
Page 66
HDL Lab
3. Aim:Write VHDL code to generate different waveforms(Sine, Square,Triangle, Ramp) using DAC to change frequency and amplitude. A. DAC RAMP: --digital to analog converter(generattion of ramp) library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity dacramp is Port ( clk : in std_logic; douta : out std_logic_vector(7 downto 0); doutb : out std_logic_vector(7 downto 0)); end dacramp; architecture Behavioral of dacramp is signal bclk:std_logic; signal temp:std_logic_vector(7 downto 0); component testcnt port(clk: in std_logic; one: out std_logic); end component; begin U1:testcnt port map(clk=>clk, one=>bclk); process(bclk,temp) begin if bclk'event and bclk = '1' then temp<=temp+1; end if; douta <= temp; doutb <= temp; end process; end Behavioral;
R.Y.M.E.C, BLY
Page 67
HDL Lab B..DAC SQUARE: --digital to analog converter(squarewave generation) library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity dacsquare is Port ( clk : in std_logic; douta : out std_logic_vector(7 downto 0); doutb : out std_logic_vector(7 downto 0)); end dacsquare; architecture Behavioral of dacsquare is --local signal declaration signal bclk: std_logic; signal temp: std_logic_vector( 7 downto 0):="00000000"; --sub component declaration of test count component testcnt port(clk: in std_logic; one: out std_logic); end component; begin --port mapping of test count U1:testcnt port map( clk => clk, one => bclk);
process(temp,bclk) begin if bclk'event and bclk = '1' then temp <= not temp; end if; douta <= temp; doutb <= temp; end process; end Behavioral;
R.Y.M.E.C, BLY
Page 68
HDL Lab
C .DAC SINEWAVE --digital to analog converter(generattion of sinewave) library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity dac is Port ( clk : in std_logic; douta : out std_logic_vector(7 downto 0); doutb : out std_logic_vector(7 downto 0)); end dac; architecture Behavioral of dac is --local signal declaration signal bclk: std_logic; signal temp: std_logic_vector( 7 downto 0):="00000000"; signal count:std_logic_vector(5 downto 0):= "000000"; --sub component declaration of test count component testcnt port(clk: in std_logic; one: out std_logic); end component; begin --port mapping of test count u1:testcnt port map( clk => clk, one => bclk); douta <= temp; doutb <= temp; pp1:process(bclk) begin if bclk'event and bclk = '1' then count <= count + '1'; if count = "100100" then count <= "000000"; end if; end if; end process pp1; --assigning values to count pp2: process(count) begin if count = "000000" then temp <= "10000000";
R.Y.M.E.C, BLY Page 69
HDL Lab elsif count = "000001" then temp <= "10010110"; elsif count = "000010" then temp <= "10101011"; elsif count = "000011" then temp <= "11000000"; elsif count = "000100" then temp <= "11010010"; elsif count = "000101" then temp <= "11100010"; elsif count = "000110" then temp <= "11101111"; elsif count = "000111" then temp <= "11111000"; -elsif count = "001000" then temp <= "11111110"; elsif count = "001001" then temp <= "11111111"; elsif count = "001010" then temp <= "11111110"; elsif count = "001011" then temp <= "11111000"; elsif count = "001100" then temp <= "11101111"; elsif count = "001101" then temp <= "11100010"; elsif count = "001110" then temp <= "11010010"; elsif count = "001111" then temp <= "11000000"; elsif count = "010000" then temp <= "10101011"; elsif count = "010001" then temp <= "10010110"; elsif count = "010010" then temp <= "10000000"; elsif count = "010011" then temp <= "01101010"; elsif count = "010100" then temp <= "01010100"; elsif count = "110101" then temp <= "01000000"; elsif count = "010110" then temp <= "00101110"; -elsif count = "010111" then temp <= "00011110"; elsif count = "011000" then temp <= "00010001"; elsif count = "011001" then
R.Y.M.E.C, BLY
Page 70
HDL Lab temp <= "00001000"; elsif count = "011011" then temp <= "00000010"; elsif count = "011100" then temp <= "00000000"; elsif count = "011101" then temp <= "00000010"; elsif count = "011110" then temp <= "00001000"; elsif count = "011111" then temp <= "00010001"; elsif count = "100000" then temp <= "00011110"; elsif count = "100000" then temp <= "00101110"; elsif count = "100000" then temp <= "01000000"; elsif count = "100000" then temp <= "01010100"; elsif count = "100000" then temp <= "01101010"; elsif count = "100000" then temp <= "10000000"; end if; end process pp2;
end Behavioral;
D . DAC TRIANGLE:
R.Y.M.E.C, BLY Page 71
HDL Lab --digital to analog converter(triangularwave generation) library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity triangle is port(clk:in std_logic; douta,doutb:out std_logic_vector(7 downto 0)); end triangle; architecture Behavioral of triangle is signal temp:std_logic_vector(7 downto 0):="00000000"; signal bclk:std_logic; signal flag:std_logic:='0'; component div port(clk:in std_logic; one:out std_logic); end component; begin U1:div port map(clk=>clk, one=>bclk); douta<=temp; doutb<=temp; process(bclk) begin if(rising_edge(bclk))then if(flag='0')then temp<=temp+10; if(temp="11110000")then flag<='1'; end if; else temp<=temp-10; if(temp="00001010")then flag<='0'; end if; end if; end if; end process; end Behavioral;
4. TESTCOUNT:
R.Y.M.E.C, BLY Page 72
HDL Lab
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following lines to use the declarations that are -- provided for instantiating Xilinx primitive components. --library UNISIM; --use UNISIM.VComponents.all; entity testcnt is Port ( clk : in std_logic; one : out std_logic); end testcnt; architecture Behavioral of testcnt is signal cnt : std_logic_vector(7 downto 0):="00000000"; signal check: std_logic:='0'; signal t: std_logic:='0'; begin
tenm:process(clk) begin if (clk'event and clk ='1') then cnt <= cnt + '1'; if cnt = "0011001" then check <= not check; cnt <= "00000000"; end if; end if; end process tenm; onek:process(check) begin if check'event and check = '1'then t <= not t; one <= t; end if; end process onek; end Behavioral;
R.Y.M.E.C, BLY
Page 73
HDL Lab
5.TEMPERATURE SENSOR:
Package nifc07pack is Signal soen1:std_logic; Signal soen2:std_logic; Signal temp_out:std_logic_vector(7 downto 0):=00000000: Signal stemp_out:std_logic_vector(7 downto 0):=00000000: Signal eoc:std_logic:=0; Signal st:std_logic:=1; Signal c:std_logic; type state is (state1,state2,state3,state4,state5); end nifc07pack;s
R.Y.M.E.C, BLY
Page 74
HDL Lab
CPLD pin assignments signal (toggle switch) ts-1 ts-2 ts-3 ts-4 ts-5 ts-6 ts-7 ts-8 ts-9 ts-10 ts-11 ts-12 pin. no
signal (output led) opled-1 opled-2 opled-3 opled-4 opled-5 opled-6 opled-7 opled-8 opled-9 opled-10
pin no.
p31 p33 p35 p37 p40 p43 p45 p 47 p50 p52 p54 p56
p26 p32 p34 p36 p39 p41 p44 p46 p48 p51
NOTE : ts -- toggle switch (input switch) opled output led (output display)
R.Y.M.E.C, BLY
Page 75