ANALOG INTEGRATED CIRCUITS ASSIGNMENT

DESIGN OF FULLY DIFFERENTIAL AMPLIFIER

The differential amplifier is a very important circuit in todays high performance analog and mixed signal circuits. In here, all the aspects of designing differential amplifier with predefined gain and other parameters will be discussed MOHAMAD MUDDASSIR GHOORUN 3/2/2012

ACKNOWLEDGEMENT:

Id like to thank Mr. Tan for his continuous support and help in the analog integrated circuit module. It was a pleasure to have been your student and I look forward to make use of the acquired knowledge in the industry.

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TABLE OF CONTENTS:

1. Introduction 2. Objectives 3. Theoretical aspect of fully differential amplifier 3.1Basic differential pair 3.2 Common source configuration 3.3 Common source stage with diode connected 3.4 Common drain configuration/ Buffer 4. Circuit design 5. Simulation results and analysis 6.Discussion and conclusion 7. References

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1. INTRODUCTION:

A differential signal is defined as one that is measured between two nodes that have equal and opposite signal excursions around a fixed potential. A very important reason of the use of differential operation over single ended signaling is higher immunity to environmental noise. The importance of amplifiers in todays world is very high and thus the study will help to come in terms with the associated field.

2. OBJECTIVES:

Design and simulate a fully differential CMOS amplifier. AC input signal of 5 mV is applied to the input for amplification. Thorough analysis on differential amplifier including DC, AC, transient analysis. The fully differential amplifier must achieve below specifications:

i. ii. iii. iv. v.

Power supply = 1.8V Minimum Gain = 30 dB Bandwidth = 100 MHz Current consumption < 1 mA The output is able to drive a capacitive load of 1pF. And 1 K ohm resistive load.

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3. THEORETICAL ASPECT OF FULLY DIFFERENTIAL AMPLIFIER:

Figure1: Reduction of coupling by differential operation As shown in the figure 1, the signal is distributed as two equal but opposite phases and a large clock waveform placed midway between the two. The transition disturbs the differential phases by equal amounts leaving the difference intact. Thus since the common mode level of the two phases is disturbed but the differential output is not corrupted, the arrangement is said to reject common mode noise.

3.1 BASIC DIFFERENTIAL PAIR:

Two single ended signal paths are incorporated to process the two phases as shown below:

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Figure 2: Basic Differential pair

Thus the basic differential pair consists of two single ended paths mainly a common source configuration for each one. The output is taken at the drain of the two NMOS as shown in figure 2. The common source configuration and related calculations is explained below:

3.2 COMMON SOURCE CONFIGURATION:

Figure 3: Common source with resistive load

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Due to the transconductance value gm, the transistor converts variations in the gate source voltage to a small current at the drain which then passes through Rd (resistor at output) to generate an output voltage. The output voltage at the drain is given by the following equation:

The above equation is only applicable when the transistor is working in saturation mode. For the transistor to work in saturation, the following parameter must be respected:

Vds Vgs-Vth
The small signal model for the common source configuration is shown below:

Figure 4: Small signal model for common source amplifier

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Iout = gm V1 + Vout / (r0|| Rd) 0 = gm Vin +Vout / Rd Av= Vout/ Vin = -gm Rd

Assuming Iout =0;

--------r0 is too big

Therefore,

3.3 COMMON SOURCE STAGE WITH DIODE CONNECTED LOAD:

Since it is difficult to manufacture resistors with tightly controlled values, resistor Rd in figure 3 is usually replaced by a MOS transistor as shown below:

Figure 4: MOS use instead of resistor

By analyzing this configuration, we can see that the transistor whether PMOS or NMOS, is always in saturation as the gate is shorted with the drain. Recall saturation formula:

Vds Vgs-Vth

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The impedance of the diode connected load is given by:

Rout = 1/ gm|| r0 = 1/gm

Thus for a common source with diode connected load, the higher the impedance, the higher is the gain. The negative sign shows that the gate is out of phase with the drain.

Av= -gm Rout

3.4 COMMON DRAIN CONFIGURATION/ BUFFER:

In order to drive a low impedance load, a buffer must be placed so as to drive the load with negligible loss of signal level. The concept of common drain (ac ground at drain) is shown below:

Figure 5: Common drain configuration

As we can see from Figure 5, the signal is input at the gate and output is taken from the source here. The gain is given as Av= gm Rs (Rs is much smaller than r01). Also to note that gain is not negative as the source is in phase with the gate. The small signal model of the above circuit is shown below:

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Figure 6: Common drain small signal model

4. CIRCUIT DESIGN:

Figure 7: Fully differential amplifier circuit

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The circuit design consists of a differential amplifier which is made up of two single ended common source configurations whose gain (Vout1-Vout2) is 33.21 dB. The transistors had to be made to operate within saturation region. The buffer, also known as source follower is of common drain configuration decreases the impedance of the circuit design and the final gain (Vout3-Vout4) of the design is 32.255 dB which is still above the required gain. Calculations and simulation results is made available on the next section. Moreover, also to note that the biasing of some of the transistors is made individually using a separate signal. However, we may also opt instead to use a current mirror to bias the transistors in saturation.

5. SIMULATION RESULTS AND ANALYSIS:

1. DC analysis:

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2. AC analysis:

Figure 8: Differential gain plot

We can either choose to use the small signal method to solve for the gain or we may use the direct method to calculate the gain of a common source amplifier. As shown above the gain of the differential amplifier is 33.2dB. The hand calculations done showed the exact estimated gain as shown below:

Av= Vout/Vin Gain of common source amplifier, Av = -gm4 Rout Given r0 = 1/gds, we first calculate the value of Rout; Rout = r03||r04

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r03 = [ 1 / (4.92*10^-5) ] = 20.325K r04 = [ 1 / (1.74*10^-5) ] = 57.471K Therefore, Rout = [ (20.325K)(57.471K) / (20.325K+57.471K) ] = 15.015K Therefore, Av = -gm4 Rout = - (1.52 * 10 ^-3) (15015) = 22.8228 Gain = 20 log (22.8223) = 27.167 dB. This gain is the single ended gain of the common source configuration. The calculated value correlate exactly with the simulation result as shown below:

Figure 9: Gain of common source in single ended configuration Differential amplifier gain = (Vout1- Vout 2) = 22.8228 +22.8228 = 45.6456 Taking log: 20 log (45.6456) = 33.19 dB [same as in simulation as shown in figure 8]

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3. Transient response:

Figure 10: Transient response graph at Vout1 As shown in figure 10, Peak voltage = 1.6677 1.554 = 0.1137 V Gain = Vout/ Vin = 22.8228 Vout = 22.8228 * Vin Vout = 22.8228 * (0.005) = 0.114V. As shown in figure 10, the simulation peak voltage and calculated peak voltage matches each other. Hence transient analysis is proved correct.

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4. Cut off frequency: fc= 1/ (2RC) = 1/ [2*1000* (cgd+cdb+cL) ] = 1/ [2*1000* ( (4e-14) + 0 + (10^-12) ) ]

fc = 153.03 Mhz. Internal capacitive values such as cgd and cdb were obtained from the .op i.e. the dc analysis from the error log file in LT spice software.

6. Discussion and conclusion:

As seen previously in the making of the differential amplifier, the differential gain is first obtained by saturating all the transistors and calculating the gain as shown in ac analysis. This gain is then fed to buffers which decrease the gain minimally as Av for common drain or buffer is closely equal to 1. In this assignment, both hand calculations and designing theories had to be learnt and therefore in the end, one may say that the assignment objectives have been achieved with a minimum of equipments as the proposed design was one among the easiest ones to understand.

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REFERENCES
Razavi, B., Design of analog CMOS integrated circuit,

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