E.C.Eng. Dept., J.C.U.N.Q.

Experiment E2302

COMMON EMITTER TRANSISTOR AMPLIFIER

Introduction
This introduction includes a brief review of the design of a single stage common emitter transistor amplifier. In order to complete this practical the student should have a basic understanding of the operation of an npn silicon transistor. Readers who are unfamiliar with this device are referred to the texts listed under the reference section below. Much of the design necessary for this practical can (and should) be completed before the lab session. There are two parts to transistor amplifier design. 1) dc biasing 2) ac amplifier design. To ensure linear amplification by a transistor amplifier, the amplifier is normally designed so that under quiescent (no input or dc) conditions it will be operating at the centre of a linear region, as normally determined from the transistor output characteristics (Ic vs Vce). The dc bias design part of the amplifier design will ensure that the amplifier operates about an appropriate quiescent point. Subsequent to this the ac amplifier design ensures that the amplifier provides the correct ac signal gain. D.C. BIAS DESIGN Figure 1 shows the arrangement most commonly used for biasing an npn bipolar transistor amplifier using a single power supply. The biasing technique consists of supplying the base of the transistor with a fraction of the supply voltage Vcc via the resistive divider network R1, R2. In addition RE is used to place the emitter at its correct voltage (determined by the value chosen for Ie) and Rc is chosen to place the collector at it's optimum operating point.

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Figure 1 : Bias Circuit for an npn bipolar transistor amplifier

The selection of R1 and R2 is simplified by replacing the voltage divider network R1, R2 by its Thevenin equivalent network. This is shown in Figure 2.

Figure 2 Thevenin equivalent voltage : Vbb = Vcc R2/(R1 + R2) Thevenin equivalent Resistance : Rbb = (R1.R2)/(R1 + R2) (1) (2)

The current, Ie, can be determined by writing Kirchhoff's loop equation for the base-emitter ground loop. Vbb = Ib Rbb + Vbe + Ie RE and using the equation Ib = Ie/( + 1) (3) (4)

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Ie=

V bb - V be Rbb RE + +1

(5)

To make Ie insensitive to temperature and variations, we design the circuit to satisfy the following constraint: RE >> Rbb/(+1) Ve = Ie RE 0.1 Vcc (6) (7)

Equation (6) shows that to make Ie insensitive to variations in we could choose to make Rbb small (i.e. lower values for R1 and R2). However this will result in a higher current drain from the power supply through R1 and R2 and a lowering of the amplifier input resistance. The amplifier ac input resistance being Rin = R1 || R2 || [(+1) (re+Re)] re = base-emitter resistance (usually small). A good compromise is to select R1 and R2 such that Rbb 5 RE. The design procedure to set Ie then is; 1. 2. 3. 4. 5. Find an appropriate value for Ve from equation (7). Choose RE using Ve and the desired value of Ie. Find an appropriate value for Rbb from equation (8). Use the approximate form of equation (5) to find Vbb. Given Vbb and Rbb, solve equations (1) and (2) simultaneously to find R1 and R2. (8)

Normally you would then select Rc such that the intersect of the ac load line with the dc load line gave the maximum symmetrical output voltage swing. The best solution may take a number of iterations to find. However, a rough first guess can be made by setting the collector voltage, Vc Vcc/2. Thus Rc = (Vcc - Vc)/IQ or Rc = Vcc/2IQ

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Figure 3 : AC and DC load lines The equations for the two load lines then become: DC Load line: VCE = VCC - IC RDC AC Load line: Vce = VAC - RAC Ic where, in this case, RDC = Rc + RE and RAC = Rc || RL + Re Note: RE & Re are the DC and AC emitter resistances respectively and RL is the load resistance. CLASSICAL SINGLE-STAGE COMMON EMITTER AMPLIFIER Figure 3 shows the complete circuit for a classical single-stage transistor amplifier employing the bias arrangement just described. A signal source Vs with output resistance Rs is coupled via Cin to the base of the transistor. Cin should be chosen large enough so that it appears as an ac short circuit over the frequency band of interest. The output from the collector is coupled to the load RL via the coupling capacitor Cout. Cout should also appear as a short circuit over the frequency band of interest. The detrimental effect of RE on the ac performance of the amplifier is eliminated by Ce. Ce acts as a short circuit to the frequencies of interest, effectively shorting RE as far as ac signals are concerned. Thus while the dc emitter current will continue to flow through RE, the ac signal current ie will flow through Ce, bypassing RE. For this reason Ce is called an "Emitter bypass capacitor" and the circuit is called a "Grounded emitter" or "Common-emitter amplifier". (10) (11)

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Figure 4 : Single Stage Common-Emitter Amplifier We shall analyse the circuit of Figure 5 to determine the amplifier gain and input resistance for ac signals in the frequency range of interest. Note in this circuit the emitter resistance has been split in two. One part, RE2, is shunted by an ac bypass capacitor Ce and will not play a role in the ac circuit analysis. The total resistance in the emitter RE1 + RE2, will need to be considered in the dc biasing design though.

Figure 5 : Small Signal Common Emitter Amplifier with emitter resistor partially bypassed Input Resistance To determine the fraction of the input signal Vs appearing at the base (vb) we first need to evaluate the input resistance Rin defined such that vb Rin = (9) vs Rin + R s

CE Transistor Amplifier Looking into the amplifier from VIN, an ac signal would see R1||R2||base resistance looking into the base. (N.B. a power supply appears as a signal ground). The base resistance Rb = vb/ib as vb = ie re + ie RE1 (10) (11)

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where re is the base-emitter resistance and is approximately equal to re = 26mV/IE at 25 C. also then therefore, ib = ie/(+1) (12) (13) (14)
o

Rb = ( + 1)(re + RE1) Rin = (R1||R2||[( + 1)(re + RE1)])

Voltage Gain Starting with the signal at the base, vb, we find vb = ie(re + RE1) Therefore the collector current will be ic = ie = vb / (re + RE1) To obtain the output voltage we multiply the total ac resistance between collector and ground (which will be Rc||RL) by ic. Thus vo = vc = - ie (Rc||RL) Where does the negative sign come from? - vb ( R c / / R L ) r e + RE 1 - ( RC / / R L ) re + R E1 (16) (15)

vo = as 1, vo = vb and the overall gain is

(17)

(18)

GAIN =

- vb vo vo = vs v s vb

CE Transistor Amplifier = R // RL - R in C R in + RS re + RE1 (19)

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Aim
To design a single stage transistor amplifier having an emitter bias stabilising network, and to compare measured and theoretical performances.

References
Micro-Electronic Circuits, Sedra A.S. and Smith K.C., Holt, Rinehart and Winston, 1982. Microelectronics, Millman J., McGraw Hill, 1979. Electronic Design: Ciruits & Systems, Savant, Roden, Carpenter, 2nd Ed., Benjamin/Cummings Pub. Co. 1991.

Procedure
1. Choose bias resistors (RE, R1, R2 and RC) with preferred values for an amplifier of the form shown in Figure 1. Design for a circuit with Vcc = 12 volts ICQ = 2.2 milliamps Assume = 300. Show that the maximum power dissipation, for all components, will not be exceeded. 2. Construct a circuit using the chosen components. Measure the quiescent operating conditions (currents and voltages) and compare with the calculated valves. Referring to the circuit of Figure 5, choose valves for RE1 and RE2 for your circuit of part 1 to give a signal gain for the amplifier of 10 (while maintaining the same quiescent conditions). Assume RL is infinite. (Hint; the amplifiers ac gain is approximately equal to RC/RE1.) Again show that the maximum power dissipation, for all components, will not be exceeded. Modify the circuit of part 2 by the addition of RE1 and RE2 (as calculated in part 3), Cin, Cout and CE. Apply a l0 kHz sinusoidal signal to the amplifier and adjust the signal level until no distortion occurs. Determine the voltage gain and phase shift of the amplifier and compare with theory. Increase the input signal level until the output just starts to distort (clip). Sketch the waveform obtained. Measure the ac output resistance of the amplifier at l 0kHz by placing a resistance box at RL

3.

4.

5.

6.

CE Transistor Amplifier and adjusting the resistance until the output level drops to 50% of the unloaded value. Be sure to check the output with the CRO to ensure clipping does not occur. If clipping is noticed reduce the input level and repeat.

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Report
1) Briefly explain how the bias design of Figure 1 tends to stabilise the device against an increase in collector current Ic? 2) How does the waveform recorded in part 5 provide information on the choice of quiescent operating point? 3) The hfe () for different BC548 transistors may vary from 110-800. Calculate the expected changes in the quiescent operating conditions that you may expect if you chose different BC548 transistors. 4) A rough guide for the design of common emitter transistor amplifiers is to assume the gain will be given by the ratio of the collector resistor Rc to the ac emitter resistance Re. Under what conditions does this rule of thumb give good results?

Equipment
CRO Signal Generator Transistor (npn) BC548 3 capacitors x 100 nF Various Resistors of student' s choice

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Appendix
Transistor Data
TYPE BC548 CASE SOT-30 POLARITY N-P-N VCE (max) 30v VCB (max) 30v Ic (max) lOOmA Vces 0.6 @ Ic = lOOmA hfe 110-800 @ Ic = 2mA Ptot(max) 500 mW

Figure 6 : Transistor Case SOT-30 Pin Out.