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ID 6 6 6 6 A A A A
TYPICAL RDS(on) = 1 EXTREMELY HIGH dv/dt CAPABILITY 100% AVALANCHE TESTED GATE CHARGE MINIMIZED VERY LOW INTRINSIC CAPACITANCES VERY GOOD MANUFACTURING REPEATIBILITY
3 1 2
TO-220
D PAK
TO-220FP
3 12
I2PAK
DESCRIPTION The SuperMESH series is obtained through an extreme optimization of STs well established stripbased PowerMESH layout. In addition to pushing on-resistance significantly down, special care is taken to ensure a very good dv/dt capability for the most demanding applications. Such series complements ST full range of high voltage MOSFETs including revolutionary MDmesh products.
APPLICATIONS HIGH CURRENT, HIGH SPEED SWITCHING s IDEAL FOR OFF-LINE POWER SUPPLIES, ADAPTORS AND PFC s LIGHTING
s
ORDERING INFORMATION
SALES TYPE STP6NK60Z STP6NK60ZFP STB6NK60ZT4 STB6NK60Z-1 MARKING P6NK60Z P6NK60ZFP B6NK60Z B6NK60Z PACKAGE TO-220 TO-220FP D2PAK I2PAK PACKAGING TUBE TUBE TAPE & REEL TUBE
April 2003
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Value
STP6NK60ZFP
Unit
VDS VDGR VGS ID ID IDM ( ) PTOT VESD(G-S) dv/dt (1) VISO Tj Tstg
Drain-source Voltage (VGS = 0) Drain-gate Voltage (RGS = 20 k) Gate- source Voltage Drain Current (continuous) at TC = 25C Drain Current (continuous) at TC = 100C Drain Current (pulsed) Total Dissipation at TC = 25C Derating Factor Gate source ESD(HBM-C=100pF, R=1.5K) Peak Diode Recovery voltage slope Insulation Withstand Voltage (DC) Operating Junction Temperature Storage Temperature 6 3.8 24 110 0.88
600 600 30 6 (*) 3.8 (*) 24 (*) 32 0.24 3500 4.5 2500 -55 to 150 -55 to 150
V V V A A A W W/C V V/ns V C C
( ) Pulse width limited by safe operating area (1) ISD 6A, di/dt 200A/s, VDD V(BR)DSS, Tj TJMAX. (*) Limited only by maximum temperature allowed
THERMAL DATA
TO-220 / D2PAK / I2PAK Rthj-case Rthj-amb Tl Thermal Resistance Junction-case Max Thermal Resistance Junction-ambient Max Maximum Lead Temperature For Soldering Purpose 1.14 62.5 300 TO-220FP 4.2 C/W C/W C
AVALANCHE CHARACTERISTICS
Symbol IAR EAS Parameter Avalanche Current, Repetitive or Not-Repetitive (pulse width limited by Tj max) Single Pulse Avalanche Energy (starting Tj = 25 C, ID = IAR, VDD = 50 V) Max Value 6 210 Unit A mJ
PROTECTION FEATURES OF GATE-TO-SOURCE ZENER DIODES The built-in back-to-back Zener diodes have specifically been designed to enhance not only the devices ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be applied from gate to souce. In this respect the Zener voltage is appropriate to achieve an efficient and costeffective intervention to protect the devices integrity. These integrated Zener diodes thus avoid the usage of external components.
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DYNAMIC
Symbol gfs (1) Ciss Coss Crss Coss eq. (3) Parameter Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Equivalent Output Capacitance Parameter Turn-on Delay Time Rise Time Total Gate Charge Gate-Source Charge Gate-Drain Charge Test Conditions VDS = 8 V, ID = 3 A VDS = 25V, f = 1 MHz, VGS = 0 Min. Typ. 5 905 115 25 56 Max. Unit S pF pF pF pF
SWITCHING ON
Symbol td(on) tr Qg Qgs Qgd Test Conditions VDD = 300 V, ID = 3 A RG = 4.7 VGS = 10 V (Resistive Load see, Figure 3) VDD = 480V, ID = 6 A, VGS = 10V Min. Typ. 14 14 33 6 17 46 Max. Unit ns ns nC nC nC
SWITCHING OFF
Symbol td(off) tf tr(Voff) tf tc Parameter Turn-off Delay Time Fall Time Off-voltage Rise Time Fall Time Cross-over Time Test Conditions VDD = 300 V, ID = 3 A RG = 4.7 VGS = 10 V (Resistive Load see, Figure 3) VDD = 480V, ID = 6 A, RG = 4.7, VGS = 10V (Inductive Load see, Figure 5) Min. Typ. 47 19 16 16 29 Max. Unit ns ns ns ns ns
Note: 1. Pulsed: Pulse duration = 300 s, duty cycle 1.5 %. 2. Pulse width limited by safe operating area. 3. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS.
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Output Characteristics
Transfer Characteristics
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Capacitance Variations
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Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times
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D1
L2
F1
G1
E
Dia. L5 L7 L6 L4
P011C
L9
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F2
H2
DIM. A B D E F F1 F2 G G1 H L2 L3 L4 L5 L6 L7
L3 L6 L7
F1 F
G1 H
F2
L2 L5
E
1 2 3
L4
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DIM.
C2
B2
L1 L2 D L
P011P5/E
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A1
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* on sales type
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics 2003 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. http://www.st.com
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