PrimeTime is a production from Synopsys for circuit timing analysis.

This is a simple description for how to use PrimeTime for VLSI class project. The class project requires all students to report the critical path with PrimeTime after designing their circuit. Here is the procedures students may want to follow for using PrimeTime. Please copy the primetime.tar.gz folder from the website to new folder

Once the folder has been downloaded type the following on the terminal window
tar -xvf primetime.tar.gz

The resulting folder should contain the following files 1) ndl_01.v and ndl_02.v these are the verilog files you will have the verilog files of your project. 2) Primetime.script 3) Variables1 1) After obtaining the library .lib file from ncx generation (there is already a script to run ncx tool and generate .lib files) students need to generate .db files based on the .lib file. You need to start lc_shell from the following path just type /home/cad/synopsys_2007.12/syn/bin/lc_shell Now read in and compile your .lib file by typing in: read_lib filename.lib write_lib lib_all format db output filename.db quit 2) Build a new directory and copy your verilog file, library .lib file and .db file (generated by step 1) to this directory 3) Copy the script for running PrimeTime to the same directory created by step 2; 4) To run Primetime you need revise the variable setting in the script copied in step 3. Change the directory location to a correct one. Do not forget to change your verilog name, .db file name and design name. Set up the desired clock period if you have flipflop in your design. 5) Run the Primetime by typing pt_shell f script_name Tips:

1) The verilog file imported into PrimeTime must be a flattened one. 2) If there is a clock signal in the design, it would be better to set an ideal transition for clock cycle, although normally we insert buffers for clock port when it drives many fanouts. To set ideal transition to clock input include set_ideal_transition max 50 clock_name in your PrimeTime script. max 50 means the maximum edge rate will be less than 50 ps. 3) If there is a reset signal for all flip-flops in the circuit we need block the timing analysis starting from that reset port since we are not interested in the timing analysis when the circuit is resetting. To block that port include set_false_path from reset_name in your PrimeTime script. If you have more questions you can check with the TA or look into the PrimeTime user guide.