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Abstract
An integrated CMOS voltage-mode buck dc-dc converter with on-chip pulse-width modulation (PWM) technique of switching control is presented in this paper. Also, a micro-power bandgap voltage reference generator is developed for the dc-dc converter. The PWM scheme employs a pseudo hyperbola curve current-compensation technique, by which the duty cycle of the oscillation signal is controllable, and the oscillation frequency can be remained constant approximately. The proposed dc-dc converter with a chip area of 0.915 mm2 is designed and fabricated with a 2P4M 0.35-m CMOS process. The experimental results show that the converter is well regulated over an output range from 1.0 V to 2.5 V, with an input voltage of 3.3 V. The maximum efficiency of the converter is 87 %, and its efficiency is kept above 81 % over an output power ranging from 60 mW to 410 mW.
1. Introduction
During the past few years, portable electronic devices are in great demand of consumer market. These devices require low-voltage, high efficiency dc converters to maximize the run time of the devices from a single battery source. In order to decrease the size and weight of these portable devices, miniaturization of the power modules is essential [1]-[3]. As a result, the trend is focused on implementation of converters with high efficiency and low-power consumption. To select an appropriate technology is an important issue for these applications. Pulse-width modulation (PWM) technique is the most frequently used technique in switching converters [1], [2]. The kernel circuit of PWM is voltagecontrolled duty-cycle (VCDC) circuit. Many
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For instance, the control techniques for converter are not appropriate for the portable applications because the PWM or VCDC circuits using in the converter can not be manufactured using CMOS technology without internal or/and external passive components. It is difficult to fabricate with digital CMOS processes and operates at low supply voltage. Consequently, we proposed an integrated voltage-mode dc-dc converter with on-chip PWM controlled circuit [12], [13] for the portable electronic systems. The proposed converter has been implemented with a standard 2P4M 0.35-m process in order to verify the performances of the converter.
Fig. 2. Illustrates the principles of duty ratio generation Fig. 2 illustrates the principles of duty ratio generation. In most applications, the amplitude of the carrier always keeps constant [3]. The control input to the modulator is only the modulation signal vc(t). The duty ratio D of the modulator satisfies the following equation: AC D = vc (t ) (3)
c(t ) = AC (
t ), TS
0 t TS
(1)
where AC is the carrier amplitude and TS is the switching period, which also is the carrier period. At the beginning of a switching cycle, the out pulse p(t) is set to high and reset to low when c(t)=vc(t). The duty ratio D in a switching cycle is defined as the ratio of the time interval when p(t)=1 to the switching period. In order to get a controllable duty ratio, the amplitude of the modulation signal, vc(t) must satisfy the following condition: 0 vc(t) AC (2)
can be remained approximately constant. The control driver provides non-overlap signals that are used to switch on/off the power switch transistors. The bandgap reference generator provides a stable reference voltage for the converter.
Fig. 3. Function block diagram of the proposed integrated buck DC-DC converter
if I c 2 >> I c1
if I c 2 << I c1
(4)
if I c1 I c 2
where VM is the transfer voltage of the delay cell and Cox is the gate oxide capacitance per unit area of both PMOS and NMOS transistors. The parameters p, (W/L)p, VTP, and VDD stand for effective channel mobility, aspect ratio, threshold voltage of a PMOS transistor and supply voltage, respectively; n, (W/L)n and VTN, stand for effective channel mobility, aspect ratio and threshold voltage of an NMOS transistor, respectively. The rise time tLH and fall time tHL of the delay cell can be derived as (5) and (6), respectively, t LH C PVM I c2 (5) Fig. 4. The delay cell
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t HL
C P (VDD VM ) I c1
(6)
where CP is the total input capacitance including MOS capacitor of the delay cell. Based on the delay cell, the PWM circuit can be constructed as shown in Fig. 5. This circuit is a current-controlled duty ring oscillator. The voltage of V1, V2, V3, V4, and Vop can be described as Fig. 6. To satisfy the oscillation condition, the stages of this oscillator must be odd, and the 5-stage oscillator was chosen to obtain the suitable frequency in this circuit. The oscillating period (T) and duty ratio (D) will be given by (8) and (9), respectively.
V V VM VM VDD VM T = 2C P M + DD + + I I p1 I p2 I p2 p1
(7) Or
1 1 T = 2CPVDD + I I p2 p1
(8) Fig. 6. The curve of V1, V2, V3, V4, and Vop bias current Ib for the compensation circuit. Fig. 7 is a pseudo hyperbola bias current (Ib) generator for the current compensation circuit. The transistors M27, M28, M29, and the current source In form the first compensation circuit, which is used to compensate the bias current in the case of duty-cycle control voltage Vc in the range from 0.5VDD to VDD. Using the approximate approach, the drain current of the transistor M28 (Ia) can be described approximately, as
if 0 < Vc < 0.5VDD 0 Ia In 2 + Gn (Vc Vr 1 ) if 0.5VDD < Vc < VDD
V VM VM 1 2C P DD + I I p2 I p2 p2 D= = 1 1 T + I p1 I p 2
(9)
(11) where Gn is the transconductance of the transistor M28. Similarly, the transistors M36, M37, M39, and the current source Im form the second compensation circuit, which is used to compensate the bias current in the case of duty-cycle control voltage Vc in the range from zero volts to 0.5VDD. Using the approximate approach, Ic, the drain current
(10)
As shown in (10), the sum of Ip1 and Ip2 must be a hyperbola function which is controlled by Vc. From (10), we can use the approximate linearity approach to find the
can
be
described
The transistors M38 and M39 construct a current mirror. Assume that the aspect ratios of M38 and M39 are equal; then, the drain currents of these two transistors are equal, i.e. IM38=IM39=Ic. Thus, the drain current of M29 is the sum of Ia and Ic. M29 and M30 also construct a current mirror. Let M29 and M30 have the same aspect ratio; then, M30 copies the drain current of M29, i.e. IM30=IM29=Ia+Ic. From (11) and (12) we get
Im G p (Vc Vr 2 ) if 0 < Vc < 0.5VDD Ib 2 I n + Gn (Vc Vr1 ) if 0.5VDD < Vc < VDD 2
Fig. 8. The current Ip1 and Ip2 generator In this work, we set bias current source Im and In be the same and equal to I. To satisfy the pseudo-curve current compensation, we can adjust the reference voltages Vr=0.5VDD, Vr1=0.75VDD, Vr2=0.25VDD, and tune the current source I to fulfill the pseudo compensation condition as described in (10).
(13) In order to use the circuit in Fig. 7 to achieve compensation, it is necessary to implement the charge current Ip1 and Ip2 to fulfill the condition as described in (10). Fig. 8 shows the architecture of the current Ip1 and Ip2 generator, which bias current is controlled by the pseudo hyperbola bias current generator as described in Fig. 7. Assume that the transistors M45 and M46 in Fig. 8 are matched; then Ip1 and Ip2 can be written as
I p1 = I p2 =
(14) (15)
where Gmn is the transconductance of M45. And assume that the transistors M41, M42, M44 and M48 are matched; then the current of M41 and M40 will equal to Ip1. Similarly, the current of M48 and M49 will equal to Ip2. Therefore, we can use current mirror to generate Ip1 and Ip2 for the ring oscillator as shown in Fig. 5, respectively.
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Fig. 10. Control driver circuit and waveform (a) circuit and (b) output waveform
Fig. 12. Chip micrograph of the converter the proposed buck dc-dc converter has been implemented with a standard 0.35-m CMOS process. The micrograph of the dc-dc converter is shown in Fig. 12, and the chip area is 0.915 mm2. The transient response of the dc-dc converter is shown in Fig. 13. The settling time is 150 s approximately with Vo=1 V and the load current to be 100 mA.
(17)
4. Experimental results
In order to verify the theoretical analysis,
Fig. 13. Transient response measurement results at: Vg=3.3 V, Vref=0.5 V, and RL=10 , (Vo=1.0 V).
(c) Fig. 14. Steady state experimental results of the proposed dc converter at: (a) Vg=3.3 V, Vo= 1.2 V, and duty=37%; (b) Vg=3.3 V, Vo= 1.5 V, and duty=51%; (c) Vg=3.3 V, Vo= 2 V, and duty=67%, approximately. Fig. 14 shows the experimental results of the output voltage (Vo), the inductor current (iL), and the switching clock of the buck converter at: (a) Vref=0.6 V, (b) Vref=0.75 V, and (c) Vref=1 V, respectively.
(a)
(b)
(a)
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(b) Fig. 15. Transient response of line regulation: (a) close-up of dynamics when Vg step-up, (b) close-up of the dynamics when Vg step-down.
(a)
(b) Fig. 16. Load regulation performance, (a) close up of the dynamics when load current step-down, (b) close-up of the dynamics when load current step-up.
4.4 Efficiency
In switching mode dc-dc converters, conducting loss and switching loss are two major power dissipations, which depend on the size of the switching transistors and the equivalent resistance of the filter elements. For PWM and synchronous rectification control, conduction loss is dominant at heavy load conditions, but switching loss is dominant at light load conditions. The efficiency of this work is shown in Fig. 17 with an input voltage of 3.3 V and an output voltage of 1.5 V. The maximum efficiency is
Fig. 17. Efficiency at Vg=3.3 V and Vo=1.5 V. 87% at loading current to be 80 mA, and its efficiency is kept above 81 % over an output power ranging from 60 mW to 410 mW. In
Fig. 17, the conduction loss is dominant when the loading current is larger than 80 mA, and the efficiency decreases with load current increasing. On the other hand, the switching loss is dominant when the loading current is less than 80 mA, and the efficiency decreases with load current decreasing.
5. Conclusions
An integrated buck dc-dc converter with on-chip PWM circuit has been designed, fabricated, and measured. The PWM scheme used in this converter only consists of CMOS transistors without internal or/and external passive components. The proposed dc-dc converter can operate at low supply voltage (1.5~3.3 V) and features low power consumption (0.41 W). The measurement results show that the converter regulates properly with duty ratio changing from 30 % to 80 %. This dc-dc converter will be useful in low voltage and low power portable system application.
Acknowledgment
The authors would like to thank the Chip Implementation Center (CIC), Taiwan, for the chip implementation, and Lunghwa University of Science and Technology for the funds and equipments support (2005).
Reference
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