Class 10

CpE358/CS381 Switching Theory and Logical Design Class 10
www.UandiStar
CpE358/CS381 Switching Theory and Logical Design Summer-1 2004
Copyright 2004 Stevens Institute of Technology All rights reserved
1-373
Today
Fundamental concepts of digital systems (Mano Chapter 1) Binary codes, number systems, and arithmetic (Ch 1) Boolean algebra (Ch 2) Simplification of switching equations (Ch 3) Digital device characteristics (e.g., TTL, CMOS)/design considerations (Ch 10) Combinatoric logical design including LSI implementation (Chapter 4) Flip-flops and state memory elements (Ch 5) Sequential logic analysis and design (Ch 5) Counters, shift register circuits (Ch 6) Hazards, Races, and time related issues in digital design (Ch 9) Synchronous vs. asynchronous design (Ch 9) Memory and Programmable logic (Ch 7) Minimization of sequential systems Introduction to Finite Automata
www.UandiStar
1-374
Course Roadmap
Logic Circuits with gates
www.UandiStar
1-375
Course Roadmap
Combinatorial Circuits
Logic Circuits with gates
www.UandiStar
1-376
Course Roadmap
Logic Circuits with gates Logic Circuits with memory
www.UandiStar
1-377
Course Roadmap
Logic Circuits with gates Logic Circuits with memory
Sequential Circuits
www.UandiStar
1-378
Course Roadmap
Logic Circuits with gates Logic Circuits with memory Specific Specific Specific Specific functions functions functions functions
Sequential Circuits
www.UandiStar
1-379
Course Roadmap
Sequential Circuits
Registers and Counters
www.UandiStar
1-380
Shift Register
Q0 Q1 Q2 Q3 Q4 Q5 Q6
SI
SO
Clk
Present State Q0 Q1 Q2 Q3 Q4 Q5 Q6
Input SI
Next State SIQ0Q1 Q2 Q3 Q4 Q5
Output S0=Q6
SI
N-bit S/R SO
SISO Register Serial-in, Serial-out
www.UandiStar
1-381
Shift Register Variants

Q0 Q1 Q2 Q3 Q4 Q5 Q6
SI
SO
Clk
Q0 Q1 Q2 SI
QN-1 SIPO Register Serial-in, Parallel-out
N-bit S/R SO
www.UandiStar
1-382

D0 Q0 D1 Q1 D2 Q2 D3 Q3 D4 Q4 D5 Q5 D6 Q6
Clk
D0 D1 D2 N-bit S/R Q0 Q1 Q2
DN-1 PIPO Register Parallel-in, Parallel-out QN-1

www.UandiStar
1-383

D0 Q0 QN-2 DN-1 QN-1
SI
SO
Clk P/S
D0 D1 D2
DN-1 Serial/Parallel Register Parallel-in/Serial-in, Parallel-out/Serial-out

www.UandiStar
P/S SI N-bit S/R SO Q0 Q1 Q2

QN-1
1-384
Tandem S/Rs
Serial registers
2N-bit S/R SI N-bit S/R SO SI N-bit S/R SO
Clock
www.UandiStar
1-385
Generic Moore Machine

State j n State Transition Controls 1 A/0 1 Outputs B/1 0 0 C/0
Inputs
All state-to-state transitions are potentially allowable.
www.UandiStar
1-386
S/R-based Moore Machine

S/R State 1 State Transition Controls n 1 A/0 1 j Outputs B/1 0 0 C/0
Inputs
Only specific state-to-state transitions are allowable.
www.UandiStar
1-387
Shift Register Sequences

State Transition Controls Output Mapping
S SI I N-bit S/R SO
www.UandiStar
1-388
Shift Register Sequences

Input
State Transition Controls
Output Mapping
S SI I N-bit S/R SO
SI=1 SI=1
11BCD 10BCD 01BCD 00BCD

www.UandiStar
1BCDE
SI=0 SI=1
ABCDE
SI=0
0BCDE
SI=0
1-389
S/R Data Scrambler/Encryptor

Fracasi scrambler:
S/R Sequential Function F(x)
S/R Sequential Function F(x)
Input Data
Descrambled Data
www.UandiStar
1-390
S/R Data Scrambler/Encryptor

Fraccassi scrambler:
N-bit S/R N-bit S/R N-bit S/R Input Data +
N-bit S/R N-bit S/R N-bit S/R + Descrambled Data
www.UandiStar
1-391
Course Roadmap
Sequential Circuits
Registers and Counters
www.UandiStar
1-392
Generic Moore Machine

State j n State Transition Controls 1 A/0 1 Outputs B/1 0 0 C/0
Inputs
All state-to-state transitions are potentially allowable.
www.UandiStar
1-393
Counter Moore Machine

Counter State m State Transition Controls n 1 A/0 1 j Outputs B/1 0 0 C/0
Inputs
State-to-state transitions follow a counting sequence Inputs (if any) may be used to set counting range, direction, starting point
www.UandiStar
1-394
Counters
Binary Ripple Counter
1 Clock 1
Clock A
www.UandiStar
1-395
Counters
1 Clock 1
Clock A B
www.UandiStar
1-396
Counters
1 Clock 1
Clock A B C
www.UandiStar
1-397
Counters
Binary Ripple Counter (idealized)
1 Clock 1
Clock A B C 000 111 011 101 001 110 010 100 000 111 011 101 001 110
www.UandiStar
1-398
Counters
Binary Ripple Counter (more realistic)
1 Clock 1
Clock A B C 000 111 011 101 001 110 010 100 000 111 011 101 001 110
100 110
{
111
{
101
{
100 110
110
111
101
www.UandiStar
1-399
Cascading Counters
1 Clock
T Q
Clock Q0
www.UandiStar
1-400
Cascading Counters
1 Clock
T Q
T Q
Clock Q0
www.UandiStar
1-401
Cascading Counters
1 Clock
T Q
T Q
T Q
Clock Q0 Q1
www.UandiStar
1-402
Cascading Counters
1 Clock
T Q
T Q
T Q
T Q
Clock Q0 Q1 QN
www.UandiStar
1-403
Cascading Counters
1 Clock
T Q
T Q
T Q
T Q
Clock Q0 Q1 QN
www.UandiStar
1-404
Ripple Counters vs. Synchronous Counters
FJAR(A,B,C) 1
FJBR(A,B,C) 1
FJBR(A,B,C) 1
Clock
FKAR(A,B,C) 1
FKBR(A,B,C) 1
FKBR(A,B,C) 1
FJAS(A,B,C) 1
FJBS(A,B,C) 1
FJBS(A,B,C) 1
FKAS(A,B,C) 1
FKBS(A,B,C) 1
FKBS(A,B,C) 1
Clock
www.UandiStar
CpE358/CS381 Switching Theory and Logical Design Summer-1 2004 Copyright 2004 Stevens Institute of Technology All rights reserved
1-405
Synchronous Counters
BCD Counter: State table
0001 0010 0011 0100
Present State 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001
Next State 0001 0010 0011 0100 0101 0110 0111 1000 1001 0000
0000
0101
1001 1000 0111
0110
www.UandiStar
1-406
BCD Counter: J-K inputs
DC 00 BA 00 01 11 10 DC 00 01 11 10 BA 00 01 11 10
0010 0001 0011 0100
X KA
0000
JA
01 11 10 00
0101
1001
0110 1000 0111
00 01 11 10
X KB
Present State Next State 0001 0010 0011 0100 0101 0110 0111 1000 1001 0000
1-407
JB
01 11 10 00
00 01 11 10
X KC
JC
01 11 10 00
J-K operation: 0 0 0 X
1 0 1 X
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001
00 01 11 10
X KD
1 0
X 1 X 1 1 0
JD
01 11 10
www.UandiStar
DC 00 BA 00 01 11 10 DC 00 01 BA 00 01 11 10
0010 0001 0011 0100
1 X X X X X X 0 X X X X X X 0 X X X X X X 0
X X X X X X X X KA
0000
JA
01 11 10 00
0101
11 10 00 01 11 10 00 01 11 10 00 01 11 10
1001 1000 0111
0110
JB
01 11 10 00
X X X X X X X X X X X X X X
KB
1-408
JC
01 11 10 00
KC
1 0 1 X
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001
1 0
X 1
JD
01
X X X X 10 X X CpE358/CS381
11
Switching Theory and Logical Design Summer-1 2004
X X X X X X Copyright 2004
Stevens Institute of Technology All rights reserved
KD
X 1 1 0
www.UandiStar
DC 00 BA 00 01 11 10 DC 00 01 11 10 00 01 11 10 00 01 11 10 00 01 11 10 BA 00 01 11 10
0010 0001 0011 0100
JA
01 11 10 00
1 1 X 1 0 0 X 0 0 X X 0
X X X X 1 1 X 0 0 X X 0
X X X X X X X X 1 X X X 0 1 X X
1 1 X X X X X X 0 X X X 0 0 X X
X X X X X X X X X 0 X X X X X 0
1 1 X 1 X X X X X 0 X X X X X 1
1 1 X X 1 1 X X X 1 X X X X X X
X X X X 0 0 X X X 0 X X
KA
0000
0101
1001 1000 0111
0110
JB
01 11 10 00
KB
1-409
JC
01 11 10 00
KC
1 0 1 X
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001
0 0 01 0 0 JD 11 X X 10 X X CpE358/CS381
X X KD X X Copyright 2004
1 0
X 1 X 1 1 0
www.UandiStar
DC 00 BA 00 01 11 10 DC 00 01 11 10 00 01 11 10 00 01 11 10 00 01 11 10 BA 00 01 11 10
0010 0001 0011 0100
JA
01 11 10 00
1 1 X 1 0 0 X 0 0 X X 0
X X X X 1 1 X 0 0 X X 0
1 1 X X X X X X 0 X X X 0 0 X X
1 1 X 1 X X X X X 0 X X X X X 1
1 1 X X 1 1 X X X 1 X X X X X X
X X X X 0 0 X X X 0 X X
KA
0000
0101
1001 1000 0111
0110
JB
01 11 10 00
KB
1-410
JC
01 11 10 00
KC
1 0 1 X
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001
0 0 01 0 0 JD 11 X X 10 X X CpE358/CS381
1 0
X 1 X 1 1 0
www.UandiStar
DC 00 BA 00 01 11 10 DC 00 01 11 10 00 01 11 10 00 01 11 10 00 01 11 10 BA 00 01 11 10
0010 0001 0011 0100
JA
01 11 10 00
1 1 X 1 0 0 X 0 0 X X 0
X X X X 1 1 X 0 0 X X 0
1 1 X X X X X X 0 X X X 0 0 X X
1 1 X 1 X X X X X 0 X X X X X 1
1 1 X X 1 1 X X X 1 X X X X X X
X X X X 0 0 X X X 0 X X
KA
0000
0101
1001 1000 0111
0110
JB
01 11 10 00
KB
JA = 1 KA = 1 JB = AD KB = A JC = AB KC = AB JD = ABC KD = A
Present State 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001
Next State 0001 0010 0011 0100 0101 0110 0111 1000 1001 0000
1-411
JC
01 11 10 00
KC
0 0 01 0 0 JD 11 X X 10 X X CpE358/CS381
www.UandiStar
BCD Counter
1 Clock
JA = 1 KA = 1
JDKD 00 01 00 01 00 01 00 11 JCKC 00 00 00 11 00 00 00 11 JBKB 00 11 00 11 00 11 00 11 JAKA 11 11 11 11 11 11 11 11
JB = AD KB = A
Next State 0001 0010 0011 0100 0101 0110 0111 1000
JC = AB KC = AB
Present State 1000 1001 1010 1011 1100 1101 1110 1111 JDKD 00 01 00 01 00 01 00 11 JCKC 00 00 00 11 00 00 00 11 JBKB 00 01 00 01 00 01 00 01 JAKA 11 11 11 11 11 11 11 11
JD = ABC KD = A
Next State 1001 0000 1011 0100 1101 0100 1111 0001
Present State 0000 0001 0010 0011 0100 0101 0110 0111
www.UandiStar
1-412
BCD Counter
Present State 0000 0001 0010 0011 0100 0101 0110 0111 JDKD 00 01 00 01 00 01 00 11 JCKC 00 00 00 11 00 00 00 11 JBKB 00 11 00 11 00 11 00 11 JAKA 11 11 11 11 11 11 11 11 Next State 0001 0010 0011 0100 0101 0110 0111 1000 Present State 1000 1001 1010 1011 1100 1101 1110 1111 JDKD 00 01 00 01 00 01 00 11 JCKC 00 00 00 11 00 00 00 11 JBKB 00 01 00 01 00 01 00 01 JAKA 11 11 11 11 11 11 11 11 Next State 1001 0000 1011 0100 1101 0100 1111 0001
0010 1110 1111 0001
0011 1101 0100 1011 1100 1010
0000
0101
1001 1000
0110 0111
www.UandiStar
1-413
Varieties of Counters
Counters with Parallel Load Normal counter operation D0 D1 D2 D3 1 CI CO LD Q0 Q1 Q2 Q3 0
State 0000 0001 0010 0011 0100 1000 1001 1010 1011 1100 1101 1110 1111 XXXX WXYZ
Load 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
CI 1 1 1 1 1 1 1 1 1 1 1 1 1 X 0
D3D2D1D0 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX ABCD XXXX
Next State 0001 0010 0011 0100 1000 1001 1010 1011 1100 1101 1110 1111 0000 ABCD WXYZ
CO 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 www.UandiStar
1-414
Counters with Parallel Load Normal counter operation D0 D1 D2 D3 1 CI CO LD Q0 Q1 Q2 Q3 0
State 0000 0001 0010 0011 0100 1000 1001 1010 1011 1100 1101 1110 1111 XXXX WXYZ
Load 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
CI 1 1 1 1 1 1 1 1 1 1 1 1 1 X 0
D3D2D1D0 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX ABCD XXXX
Next State 0001 0010 0011 0100 1000 1001 1010 1011 1100 1101 1110 1111 0000 ABCD WXYZ
CO 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 www.UandiStar
1-415
Counters with Parallel Load Loading next state in parallel D0 D1 D2 D3 = ABCD CI CO LD 1
State 0000 0001 0010 0011 0100 1000 1001 Load 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 CI 1 1 1 1 1 1 1 1 1 1 1 1 1 X 0 D3D2D1D0 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX ABCD XXXX Next State 0001 0010 0011 0100 1000 1001 1010 1011 1100 1101 1110 1111 0000 ABCD WXYZ CO 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 www.UandiStar
1-416
Q0 Q1 Q2 Q3 --> ABCD
1010 1011 1100 1101 1110 1111 XXXX WXYZ
Counters with Parallel Load
State 0000 Load 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 CI 1 1 1 1 1 1 1 1 1 1 1 1 1 X 0 D3D2D1D0 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX ABCD XXXX Next State 0001 0010 0011 0100 1000 1001 1010 1011 1100 1101 1110 1111 0000 ABCD WXYZ CO 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 www.UandiStar
1-417
D0 D1 D2 D3 0 CI CO LD Q0 Q1 Q2 Q3
0001 0010 0011 0100 1000 1001 1010 1011 1100 1101 1110 1111 XXXX WXYZ
Counters with Parallel Load
State 0000 Load 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 CI 1 1 1 1 1 1 1 1 1 1 1 1 1 X 0 D3D2D1D0 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX ABCD XXXX Next State 0001 0010 0011 0100 1000 1001 1010 1011 1100 1101 1110 1111 0000 ABCD WXYZ CO 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 www.UandiStar
1-418
D0 D1 D2 D3 CI CO LD Q0 Q1 Q2 Q3
0001 0010 0011 0100 1000 1001 1010 1011 1100 1101 1110 1111 XXXX WXYZ
Cascading Synchronous Counters

D0 D1 D2 D3 1 CI A LD Q0 Q1 Q2 Q3 Clock Clock Q0A Q1A Q2A Q3A COA Q0B
www.UandiStar
CpE358/CS381 Switching Theory and Logical Design Summer-1 2004 Copyright 2004 Stevens Institute of Technology All rights reserved 1-419
D0 D1 D2 D3 CI B 0 LD Q0 Q1 Q2 Q3 0 CO
D0 D1 D2 D3 CI C LD Q0 Q1 Q2 Q3 0 CO
CO
Programmable Synchronous Counters

LSB D0 D1 D2 D3 1 CI A LD Q0 Q1 Q2 Q3 Clock CO D0 D1 D2 D3 CI B LD Q0 Q1 Q2 Q3 CO MSB D0 D1 D2 D3 CI C LD Q0 Q1 Q2 Q3 CO
Assume D3CD0A = b11b10b9b8b7b6b5b4b3b2b1b0

State b11b10b9b8 b7b6b5b4 b3b2b1b0 ABCD EFGH 1111 ABCD 1111 1111 1111 1111 1111 Next State b11b10b9b8 b7b6b5b4 b3b2b1b0 + 1 ABCD EFGH+1 0000 ABCD+1 0000 0000 b11b10b9b8 b7b6b5b4 b3b2b1b0
COA 0 1 1 1
COB 0 0 1 1
COC 0 0 0 1 www.UandiStar
1-420
Applications of Programmable Counters

Programmable divide by N frequency divider: 2K-N
CI
CO LD
CI
CI LD
CO
CI LD
CO
CI LD
Clock/N
Clock
www.UandiStar
1-421
Reference Oscillator f R
Divide By K
Phase fR/K Comparator
Lowpass Filter
Voltage Controlled Oscillator
fS
Synthesized Frequency
Phase Locked Loop
fS/N
Divide By N
Channel Selection, N
fS =
N fR K
PLL frequency synthesizers used in TV, radio, cellular phones, PCs, modems, etc.
www.UandiStar
1-422
Master Clock
fm
Divide by A
fm/A
Divide by B
fm/B
Complex Digital System (e.g., PC)
Divide by C
fm/C
www.UandiStar
1-423
Timing Signal Generation
Master Clock
fm
Clock Phase A
Clock Phase B
Complex Digital System (e.g., PC)
Clock Phase C
www.UandiStar
1-424
Ring Counters
Only 1 FF is set at any given time
States 10000 01000
D Q D Q D Q D Q D Q
00100 00010 00001
Clock Clock QA QB QC QD QE
10000
www.UandiStar
1-425
Switch-tail Ring Counters (Johnson Counter)

States 00000 10000
D Q D Q D Q D Q D Q
E
Q
11000 11100 11110 11111 01111 00111 00011 00001 00000
Clock Clock QA QB QC QD QE
www.UandiStar
1-426
Summary
Fundamental concepts of digital systems (Mano Chapter 1) Binary codes, number systems, and arithmetic (Ch 1) Boolean algebra (Ch 2) Simplification of switching equations (Ch 3) Digital device characteristics (e.g., TTL, CMOS)/design considerations (Ch 10) Combinatoric logical design including LSI implementation (Chapter 4) Flip-flops and state memory elements (Ch 5) Sequential logic analysis and design (Ch 5) Counters, shift register circuits (Ch 6) Hazards, Races, and time related issues in digital design (Ch 9) Synchronous vs. asynchronous design (Ch 9) Memory and Programmable logic (Ch 7) Minimization of sequential systems Introduction to Finite Automata
www.UandiStar
1-427
Homework 10 due in Class 12

Show all work Problems 6-11, 6-23, 6-29
www.UandiStar
1-428

Class 10

Uploaded by

Document Information

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Class 10

Uploaded by

Copyright:

Available Formats

CpE358/CS381 Switching Theory and Logical Design Class 10

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

Logic Circuits with gates

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

Logic Circuits with gates

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

Logic Circuits with gates Logic Circuits with memory

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

Logic Circuits with gates Logic Circuits with memory

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

Registers and Counters

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

Next State SIQ0Q1 Q2 Q3 Q4 Q5

SISO Register Serial-in, Serial-out

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

Shift Register Variants

QN-1 SIPO Register Serial-in, Parallel-out

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

Shift Register Variants

DN-1 PIPO Register Parallel-in, Parallel-out QN-1

Copyright 2004 Stevens Institute of Technology All rights reserved

Shift Register Variants

DN-1 Serial/Parallel Register Parallel-in/Serial-in, Parallel-out/Serial-out

P/S SI N-bit S/R SO Q0 Q1 Q2

Copyright 2004 Stevens Institute of Technology All rights reserved

2N-bit S/R SI N-bit S/R SO SI N-bit S/R SO

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

Generic Moore Machine

All state-to-state transitions are potentially allowable.

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

S/R-based Moore Machine

Only specific state-to-state transitions are allowable.

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

Shift Register Sequences

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

Shift Register Sequences

11BCD 10BCD 01BCD 00BCD

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

S/R Data Scrambler/Encryptor

S/R Sequential Function F(x)

S/R Sequential Function F(x)

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

S/R Data Scrambler/Encryptor

N-bit S/R N-bit S/R N-bit S/R Input Data +

N-bit S/R N-bit S/R N-bit S/R + Descrambled Data

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004