School of Computer Science

CS 219

Computer Organization
TR 11:30 ~ 12:45 PM @ WRI C303 Fall 2006

Tuesday, Oct. 3, 2006

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Speed
Access time = Seek + Latency
Seek time
Moving head to correct track Under 10ms

(Rotational) latency
Disk rotates at constant speed Waiting for data to rotate under head At 15,000 RPM (=250 RPS), 4ms for one rotation, so 2ms average delay

Transfer time
Time required for data transfer
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Timing Comparison
Characteristics
Average seek time = 4ms RPM = 15,000 (average latency = 2ms) File = 5 tracks x 500 sectors/ track = 2500 sectors

1. If sequential

For reading a full track (500 sectors)

First track = seek + latency + full track = 4 + 2 + 4 ms = 10 ms Subsequent tracks = (little seek time) + latency + full track = 2 + 4 = 6 ms Total = 10 + 6 + 6 + 6 + 6 = 34 ms

2. If randomly distributed

For reading a sector (4 ms * 1/500)

Each sector = seek + latency + sector = 4 + 2 + 0.008 ms = 6.008 ms Total = 2500 * 6.008 = 15.02 sec
Need disk scheduling
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CD-ROM
Since 1983 Originally for audio
650Mbytes giving over 70 minutes audio

Data stored as pits Read by reflecting laser (780 nm)

VL = 400 ~ 700

Only one spiral track

Constant packing density Constant linear velocity
Disk spins at variable speed
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CD Operation
10~20 micron

Polycarbonate coated with highly reflective coat, usually aluminium

1.2mm

0.9~3.3 micron

Beginning or end of a pit = 1 No change = 0

0.12 micron deep (~1/6 of WL) 0.5 micron wide Pitch = 1.6 micron to next track

Interference by Phase difference

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Other Optical Storage

CD-Recordable (CD-R)
No pitting Dye layer changes reflectivity after high intensity laser Compatible with CD-ROM drives

CD-RW
Erasable (500,000 ~1,000,000 erase cycles) More reliable and longer life than magnetic disks Getting cheaper Mostly CD-ROM drive compatible Phase change of material by laser light
Material has two different reflectivities in different phase states, one poor reflection and the other good reflection

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DVD - Why greater capacity than CD?

1. More Compact (x7) Space between loops of spiral
Pitch = 1.6 micron in CD, 0.74 micron in DVD 0.834 micron in CD, 0.4 micron in DVD

Minimum distance between pits The combination = 7-fold increase Uses 650 nm laser 2. Second layer (~ x2) 8.5GB 3. Two-sides (x2) 17 GB
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4.7 GB

Input/Output Module
Communication between peripheral and the bus
Interface to CPU and Memory Interface to one or more peripherals

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I/O Module Function

Categories
1. 2. 3. 4. 5. Control & Timing CPU Communication Device Communication Data Buffering Error Detection

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Announcements
Midterm exam
Oct. 17 (Tue) Midterm review session on Oct. 12 (Thu) The exam will be mixture of multiple choice and short answers Range: Chapter 1 ~ 8
Final exam range: chapter 9 and beyond

Quiz on Thursday (Oct. 5)

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Chap 7. Continued
I/O techniques

Input Output Techniques

1.

Programmed
I/O occurs under the direct and continuous control of the requesting program

2.

Interrupt driven
Program issues I/O command and forgets until it gets interrupt for completion of the I/O

3.

Direct Memory Access (DMA)

Specialized I/O processor takes over control of I/O

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I/O Techniques I
Programmed I/O

Programmed I/O - Steps

1. 2. 3. 4. 5. 6. 7.

CPU requests I/O operation I/O module performs operation I/O module sets status bits CPU checks status bits periodically I/O module does not inform CPU directly I/O module does not interrupt CPU CPU may wait or come back later

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Programmed I/O
CPU has direct control over I/O
Sensing status Read/write commands Transferring data

CPU waits for I/O module to complete operation Wastes CPU time

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I/O Commands
CPU issues address
Identifies module (& device if >1 per module)

CPU issues command (4 types)

1. Control - telling module what to do
e.g. spin up disk e.g. power? Error? Module transfers data via buffer from/to device

2. Test - check status 3. & 4. Read / Write

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Addressing I/O Devices

Under programmed I/O, data transfer is very like memory access (CPU viewpoint)
There are many I/O devices Each I/O device given unique identifier CPU commands contain identifier (address)

I/O Address

Two types

1. Memory mapped I/O 2. Isolated I/O (or Port mapped I/O)

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I/O Mapping (1)

Memory mapped I/O
I/O devices and memory share an address space
Status and data registers appear at memory locations I/O address can be anywhere within the address space Address bus is shared

I/O looks just like memory read/write

Advantages
No special commands for I/O wide range of memory commands available programming CPU logic is simpler and cheaper more efficient

Disadvantages
memory address is used up by I/O (not that big a deal nowadays with 64 bit address)
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I/O Mapping (2)

Isolated I/O
Separate address spaces from memory
Each has full range of address space isolated from each other Useful for CPU with small addressing capability (e.g. 16-bit)

Memory Read/write lines + I/O command lines Special commands for I/O Limited set, e.g., IN, OUT Easy to identify from assembly program

Generally found on Intel processors Both Memory-mapped and Isolated I/O are in common use
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Memory Mapped vs. Isolated I/O

0 - 511: Memory address 512 - 1023: I/O address How to move 1 byte from kbd to accumulator? 0 0

memory

I/O

1023

1023

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I/O Techniques II
Interrupt-Driven I/O

Interrupt Driven I/O

Overcomes CPU waiting No repeated CPU checking of device I/O module interrupts when ready

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Comparison of Three Techniques

Reading a Block of Data

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Interrupt Driven I/O - I/O Viewpoint

1. CPU issues READ command 2. I/O module gets data (into data register) from

peripheral whilst CPU does other work 3. I/O module interrupts CPU (then wait) 4. CPU requests data 5. I/O module transfers data (by data bus)

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Interrupt Driven I/O

- CPU Viewpoint 1. Issue READ command 2. Do other work 3. Check for interrupt at end of each instruction

cycle 4. If interrupted:Save context (registers) Process interrupt

Fetch data & store

However, Interrupt-driven I/O still consumes a lot of CPU time Every data word must pass through the processor
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Interrupt Driven I/O - Design Issues

How do you identify the module issuing the interrupt?
There are multiple devices! 4 solutions available

How do you deal with multiple interrupts?

i.e. an interrupt handler being interrupted We saw that there are two ways (sequential and priority-based)
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Identifying Interrupting Module (1)

1. Different interrupt line for each module Limits number of devices Plus, each I/O module may have multiple devices Impractical for large number of devices Moreover, each line may be connected to multiple modules 2. Software poll CPU detects interrupt, and start polling (CPU asks each module in turn)
1. TESTI/O command on address line 2. Reading status register from each I/O module

Slow
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Identifying Interrupting Module (2)

3. Daisy Chain or Hardware poll Interrupt Acknowledge sent down a chain Module responsible places vector on bus CPU uses vector to identify handler routine (vectored Interrupt), instead of starting general ISR first
Common Interrupt Request Line

Interrupt ACK

BPRN = Bus Priority In

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Identifying Interrupting Module (3)

4. Bus Arbitration

Uses vectored interrupt, too Module must claim the bus before it can raise interrupt
Only one module can raise the interrupt request line

After CPU ACKs, it places its vector on data line e.g. PCI & SCSI

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Multiple Interrupts
All the above 4 techniques can be also used for prioritizing multiple interrupts
Multiple lines: Each interrupt line has a priority. Processor picks one with highest priority. Software polling: by the polling order Daisy chain: order of chaining Bus arbitration: discussed in 3.4
Centralized vs. Distributed

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Example of I/O

Example - PC
Intel 80x86 has one interrupt line
Single Interrupt Request (INTR) Single Interrupt ACK (INTA)

For handling multiple devices, 80x86 based systems use a 8259A interrupt controller
Introduced in 1980, now part of Southbridge chipset 8259A has 8 interrupt lines For more than 8 modules: cascade of 8 chips for up to 64 modules

C in 82C59A stands for CMOS version

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8259A Interrupt Controller

1. 2. 3. 4. 5. 6.

For more than 8 modules: cascade of 8 chips for up to 64 modules

8259A accepts interrupts 8259A determines priority 8259A signals 80x86 (raises INTR line) CPU Acknowledges 8259A puts correct vector on data bus CPU processes interrupt
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8259A Interrupt Controller

Programmable
Called PIC (Programmable Interrupt Controller) 80386 processor determines the priority by setting a control word in 8259A
Master 8259
IRQ0 Intel 8253 or Intel 8254 Programmable Interval Timer, aka the System Timer IRQ1 Keyboard IRQ2 Not Assigned in PC/XT; Cascaded to Slave 8259 INT line in PC/AT IRQ3 Serial Port COM2 and COM4 IRQ4 Serial Port COM1 and COM3 IRQ5 IDE controller in PC/XT; LPT2 in PC/AT IRQ6 Floppy disk controller IRQ7 LPT1

Modes
Fully nested: fixed priority from 0 to 7 Rotating: same priority. Serve them in rotation Special mask: inhibit interrupt from certain devices
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Slave 8259 (PC/AT and later only)

IRQ8 Real-time clock (RTC) IRQ9 Receives IRQ2's device interrupt IRQ10 Not Assigned IRQ11 Not Assigned IRQ12 PS/2 mouse IRQ13 Math coprocessor IRQ14 Primary IDE controller IRQ15 Secondary IDE controller

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FYI - Beyond 8259A

8259A is not included as a separate chip in an x86 PC. Rather, its functionality is included as part of the motherboard's Southbridge chipset. 8259A is slow and cannot be used with multiple processors
Being phased out for exclusive use of the Intel APIC (Advanced Programmable Interrupt Controller) Architecture. APIC containing a magnitude more outputs and much more complex priority schemes.

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Example of I/O module

Which chip is used for programmed I/O and Interrupt Driven I/O? 82C55A Programmable Peripheral Interface
Single-chip, general-purpose I/O module Can be used for a variety of devices Designed for Intel 80386

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I/O Techniques III

Pro???? Int???

DMA

Direct Memory Access (DMA)

Interrupt driven is better than programmed I/O, but still requires active CPU intervention
Transfer rate is limited CPU is tied up

DMA is the answer

DMA moves data between system memory and a peripheral without bothering CPU Especially good for large data transfer

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DMA Operation
1. CPU tells DMA controller: 1. Read or Write? 2. I/O Device address 3. Starting address of memory block for data 4. Amount of data to be transferred 2. CPU carries on with other work 3. DMA controller deals with transfer 4. DMA controller sends interrupt when

finished

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Comparison of Three Techniques

Reading a Block of Data

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DMA Function
Additional Module (hardware) on bus
Mimicking CPU Memory wouldnt notice the difference

DMA controller takes over from CPU for I/O

Transferring data to/from memory over the system bus Only when the processor does not need it Or suspend CPU called cycle stealing
Typical DMA block diagram
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DMA Transfer - Cycle Stealing (1)

CPU and DMA compete for the bus, but DMA wins if it is ready CPU suspended just before DMA accesses bus
i.e. before an operand or data fetch or a data write

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DMA Transfer - Cycle Stealing (2)

DMA transfers one word, then returns control to CPU DMA is Not an interrupt
CPU does not switch context CPU just loses one memory cycles (gets suspended) Slows down CPU, but still far more efficient than interrupt-driven I/O

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DMA modes
Previous = Single-cycle mode
Bus REQ / ACK overhead for each word, resulting in performance drop.

Burst Mode DMA

The entire source block is copied to the destination. The DMA controller gains exclusive access to the bus for the duration of the transfer, during which time the program is effectively shut down.

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Intel 8237A DMA Controller

Interfaces to 80x86 family and DRAM
1. When DMA module needs buses it sends HRQ (hold request) signal to processor 2. CPU responds HLDA (hold acknowledge) 3. DMA module can use buses
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Next class
More on I/O Chap 8. Operating System Support

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