i hc Bch Khoa Nng Khoa in T - Vin Thng

Bo co tiu lun MSP430

Thnh vin: V Th Mn L B Tun Bi Hu Tri Nguyn Hu Anh Khoa GVHD: Phm Xun Trung

Chng 1 : L thuyt
1.1 Tng quan v MSP430 (Mixed Signal Controller).

1.1.1 Chip MSP430G2x31. - Ngun cung cp: 1.8V 3.6V - Cng sut tiu tn cc thp. - 5 ch tit kim nng lng. - Wake-up nhanh t ch Standby <1us - Kin trc RISC 16 bits - C nhiu ngun xung Clock la chn. - Timer_A 16 bit vi 2 thanh ghi Compare/Capture. - USI h tr I2C, SPI - 10 bit 200kbps ADC vi ngun tham chiu ni, Sample v Hold, Autoscan.

1.1.2

S chn.

1.2 H thng Reset, Ngt v cc ch hot ng. 1.2.1 H thng Reset v khi ng: C 2 h thng POR (Power on Reset) v PUC (Power UP Clear). - POR ch c sinh 3 s kin sau: o Cp ngun cho thit b. o Tn hiu chn ~RST/NMI xung mc thp o SVS mc thp khi PORON = 1 - PUC c sinh ra khi POR c sinh, nhng khng xy ra ngc li. Cc s kin sau s sinh ra PUC: o POR c sinh ra. o o WDT ht hiu lc Cht an ton ca WDT v Flash memory b vi phm.

1.2.2

H thng ngt

C 3 loi ngt trong msp430 l: Reset h thng, Non-maskable NMI, maskable.

1.3 B nh v t chc b nh 1.3.1 Khng gian a ch. B nh MSP430 theo kin trc von-Neumann khng gian nh bao gm cc thanh ghi c chc nng c bit SFRs, ngoi vi, RAM, Flash/ROM nh hnh bn. Flash/ROM: ln ty thuc vo tng dng chip. B nh Flash c th s dng cho c data v code. Word hoc byte tables c th c lu tr v s dng ngay trn Flash m khng cn sao chp vo RAM. Interrupt vector c nh 16bytes t 0FFE0h 0FFFFh RAM: bt u t 200h, ln ca RAM ph thuc vo dng chip v lng RAM ang s dng.

Peripheral Module: 16 bit c nh a ch t 100h 1FFh, c truy cp bng word, nu truy cp bng byte th byte cao lun lun bng 0. Ngoi vi 8bit t 10h n FFh ch c truy cp bng byte. SFRs: 16 byte t 0h n 16h.

1.3.2 T chc b nh B nh c t chc theo cc byte. Cc byte c nh a ch chn v l. B nh MSP430 cn c th thao tc vi word 16bit. Mt word gm 2 byte k nhau (High byte & Low byte), a ch ca word l a ch ca byte thp, v vy lun l a ch chn

1.4 CPU Bao gm ALU , 16 thanh ghi 16 bit v cc mch logic gii m lnh v thc hin chng trnh. 4 thanh ghi u: PC - l b m chng trnh cha a ch ca lnh k tip , SP, SR - cha tp hp cc c nh C,N,Z,V hoc GIE hoc CPUOFF OSC, Constant Generator - cha cc hng s nh 1 2 4. . V 12 thanh ghi mc ch chung. C word v byte c th c ghi vo trong thanh ghi ca CPU. Khi d liu ghi vo l byte thi byte cao s b xa byte thp cha gi tr ca byte a vo.

1.5 Clock Generator S phn cng v cc ngun xung clock

ng b cc hot ng ca Vi iu khin MSP430 c nhiu ngun xung clock la chn nhm ti u ha hiu sut v cng sut hot ng. Clock c th c cu hnh hot ng m khng cn thnh phn bn ngoi no,hoc vi 1 in tr, hoc vi 1 , 2 thch anh ngoi. o Low frequency Crystal Clock LFXT1CLK: Ngun Clock ny ly t thch anh ngoi gn vo chn XIN, XOUT. Intended frequency l 32Khz l ngun ca ACLK. C th hot ng tn s cao hn. o Crystal to Clock XT2CLK : dng thch anh ngoi gn vo 2 chn XT2IN XT2OUT, mc ch l dng vi thch anh tn sos cao 400KHz 6Mhz o Digitalally Controlled Oscillator Clock (DCOCLK): clock ni, mc nh khi khng cu hnh th dng cho tn hiu MCLK 900Khz o Very Low Frequency (VLOCLK) l ngn ni c cng sut thp, tn s thp 12Khz. Cc tn hiu Clock: o Master Clock: dng cho CPU. ngun c chn bi SELMx (Basic Clock System Control Register BCSCTL 2) c th l VLOCLK XT2CLK LFXT1CLK DCOCLK, chia tn s c la chon bi DIVMx o Submaster Clock: dng cho cc ngoi vi, ngun ca n l VLOCLK XT2CLK LFXT1CLK DCOCLK c iu khin bi cc bit SELS SCG (BCSCTL2), chia tn s DIVSx o Auxillary Clock: dng cho cc module ngoi vi. Ngun cha n LFXT1CLK hoc VLOCLK, c th chia tn s 1 2 4 8 ln.

1.6

Ng ra/ vo 1.6.1 Cu trc xut nhp: o Gm 8 port xut nhp t P0 -> P7. o Mi port gm 8 chn o Mi chn c th lm u vo hay u ra,c th c c hay c ghi ring l. o Port P1 v P2 c kh nng ngt

o o o o o o o

Mi ngt c cu hnh theo cnh ln,cnh xung ca sn xung hoc theo tn hiu vo tng ng vi cc vector ngt 1.6.2 c tnh xut nhp: o chc nng ca chn khng ph thuc vo vic lp trnh o c th lm input hay output o P1 v P2 c cu hnh ring cho ngt o khng ph thuc vo thanh ghi input hay output o cu hnh c in tr ko 1.6.3 Hot ng xut nhp: o c lp trnh bng phn mm 1.6.4 Thanh ghi input o Bit=0:u vo mc thp o Bit =1:u vo mc cao 1.6.5 Thanh ghi output: o Khi khng s dng in tr ko,gi tr cc thanh ghi tng ng: o Bit=0:u vo mc thp o Bit =1:u vo mc cao o Khi khng s dng in tr ko,gi tr tng ng: o Bit=0: in tr ko xung o Bit =1: in tr ko ln 1.6.6 Thanh ghi nh hng PxDIR: Cc chn lm u vo hay u ra c nh hng bi cc bit ca thanh ghi PxDIR Bit=0:chn c nh hng lm u vo(ch d nhm ln vi PIC) Bit =1:chn c nh hng lm u ra 1.6.7 Thanh ghi cho php in tr ko PxREN: Mi bit ca thanh ghi PxREN cho php hay khng cho php in tr ko Bit=0: in tr ko xung Bit =1: in tr ko ln 1.6.8 Thanh ghi la chn chc nng PxSEL PxSEL2: Cc bit ca thanh ghi PxSEL v PxSEL2 c s dng la chn chc nng l Port xut nhp hay cc chc nng c bit khc o PxSEL 0 1 0 1 Chc nng ca chn Chc nng xut nhp Module u tin c la chn ng k trc Module ngoi vi th 2 c la chn

PxSEL2 0 0 1 1

Lu : khi PxSEL=1,cc ngt ca P1 v P2 b cm. 1.6.9 Cc ngt P1 v P2: o Mi chn ca P1 v P2 u c kh nng ngt. o Ngt c cu hnh bi thanh ghi PxIFG, PxIE v PxIES. o S dng thanh ghi PxIFG xc nh nguyn nhn ngt ca P1 v P2 a) Thanh ghi c ngt P1IFG v P2IFG o Mi bit ca thanh ghi PxIFGx l 1 c ngt tng ng vi chn xut nhp v khi c cnh xung tn hiu ti cc chn.tt c cc c ngt ca thanh ghi PxIFGx i hi 1 ngt tng ng vi cc bit PxIE v GIE c set. o Mi c ngt c reset bng phn mm. o Phn mm c th set c ngt o Bit=0: khng c c ngt no o Bit =1: c 1 ngt ang ch

o o o o

1.6.10 Thanh ghi la chn ngt bng sn xung P1IES v P2IES. Bit=0: c ngt c set ln khi c cnh ln ca xung Bit =1: c ngt c set ln khi c cnh xung ca xung 1.6.11 Thanh ghi cho php ngt P1IE v P2IE Bit=0: cm ngt Bit =1: cho php ngt

1.7 Timer_A 1.7.1 Gii thiu v Timer_A:

Timer_A c: o 16bit timer/counter vi 4 ch hot ng: Stop, Up, Continuous, Up/Down. o Ngun xung clock c th la chn v cu hnh t nhiu ngun khc nhau o 3 thanh ghi Capture/Compare (TACCRx) o PWM

2 vector ngt : TACCR0 v TAIV 1.7.2 S phn cng Timer_A 1.7.3 Cc thanh ghi s dng trong Timer_A:

1.7.4 o

La chn ngun xung clock cho Timer_A:

Ngun xung clock cho timerA c th c la chn t ngun xung clock : ACLK, SMCLK hay t ngun bn ngoi TACLK, INCLK thng qua vic la chn cc bit TASSELx(TACTL). C th: TASSELx Ngun la chn 00 TACLK 01 ACLK 10 SMCLK 11 INCLK o Cc ngun xung clock c la chn ny c th c s dng trc tip cho hot ng ca Timer_A hay c th c chia bi 2, 4, 8 bng cch s dng cc bit IDx(TACTL). C th: IDx Ngun clock c chia 00 /1 01 /2 10 /4 11 /8 1.7.5 Cc ch hot ng ca Timer_A:

TimerA c 4 ch hot ng : Stop, Up, Continuous, Up/Down c la chn bi cc bit MCx(TACTL).C th: MCx Mode Description

00 01 10 11

Stop Up Continuous Up/Down

TimerA khng hot ng Timer_A m lp li t 0 n gi tr thanh ghi TACCR0 Timer_A m lp li t 0 n gi tr FFFFh Timer_A m lp li t 0TACCR00

Timer_A hot ng ngay khi gi tr cc bit MCx khc 00 v ngun xung clock c chn cho Timer_A hot ng. Khi TimerA hot ng ch Up hoc Up/Down, timer s dng hot ng khi ghi gi tr 0 vo thanh ghi TACCR0 1.7.5.1 Up Mode:

Thay i gi tr thanh ghi TACCR0 khi timer ang hot ng: + Nu gi tr mi bng hay ln hn gi tr c hay ln hn gi tr hin ti, Timer s m n gi tr mi. + Nu gi tr mi b hn gi tr hin ti, timer s m li t gi tr 0. o Cu hnh Timer_A hot ng ch Up: Cho php ngt TACCR0 CCIFG: CCIE =1 trong thanh ghi TACCTL0 Np gi tr vo thanh ghi TACCR0: TACCR0 = xxxx La chn ngun xung clock dng cho Timer_A thit lp gi tr cc bits TASSELx trong thanh ghi TACTL Thit lp gi tr chia cho xung clock: thit lp bits IDx trong thanh ghi TACTL (mc nh IDx = 00 -/1) La chn timer_A hot ng ch Up: thit lp MCx = 01 trong TACTL Code cho chng trnh ngt

1.7.5.2 Continuous Mode: Cu hnh Timer_A hot ng ch Continuous: Tng t nh trn 1.7.5.3 Up/Down Mode:

Thay i gi tr thanh ghi TACCR0 khi timer ang hot ng: Nu timer ang trong chiu m xung, timer s tip tc m xung n 0. Nu timer ang trong chiu m ln v gi tr mi ln hn hay bng gi tr c hay ln hn gi tr hin ti, timer s m n gi tr mi trc khi m xung. Nu timer ang trong chiu m ln v gi tr mi b hn gi tr gi tr hin ti, timer s bt u m xung o Cu hnh Timer_A hot ng ch Up: Tng t nh trn 1.7.6 Compare Mode: Compare mode c la chn khi bit CAP()=0(mc nh). Compare mode dng to ra khong thi gian hay iu ch rng xung PWM Compare mode hot ng da trn nguyn tc so snh gi tr ca thanh ghi timer_A(TAR) vi gi tr thanh ghi TACCRx Khi gi tr ca TAR bng gi tr ca TACCRx th s xut hin cc s kin: C ngt CCIFG =1 EQUx = 1 EQUx nh hng n li ra PWM Tn hiu CCI lt sang SCCI 1.7.7 Output Unit: Mi khi capture/compare cha mt b OUTPUT UNIT dng iu ch rng xung PWM. Mi OUTPUT UNIT c 8 ch hot ng to ra tn hiu da trn tn hiu EQU0 v EQUx. OUTPUT UNIT c la chn hot ng da trn gi tr ca cc bit OUTMODx. C th: o
OUTMODx 000 001 010 011 100 101 110 111 Mode Output Set Toggle/Reset Set/Reset Toggle Reset Toggle/Set Reset/Set Description Tn hiu ra OUTx c xc nh bi bit OUTx Li ra c set khi TAR = TACCRx.N s gi nguyn nh vy cho n khi timer c reset hay khi 1 output mode khc c la chn v nh hng n li ra. Li ra o trng thi khi TAR = TACCRx v reset khi TAR = TACCR0 Li ra set khi TAR = TACCRx v reset khi TAR = TACCR0 Li ra o trng thi khi TAR = TACCRx. Chu k tn hin ra gp 2 ln chu k timer Li ra reset khi TAR = TACCRx. N s gi nguyn nh th cho n khi 1 output mode khc c la chn v nh hng n li ra Li ra o trng thi khi TAR= TACCRx v set khi TAR = TACCR0 Li ra reset khi TAR = TACCRx v set khi TAR = TACCR0

Cu hnh PWM: Cu hnh chc nng I/O nhn chc nng ra OUTx ca PWM: V cc chn P1.1 P1.2 v P1.3 l nhng chn ra ca PWM nn cn cu hnh cc bits tng ng trong thanh ghi P1DIR v P1SEL. V d: P1DIR = 0x0C, P1SEL= 0x0C chn chn P1.2 v P1.3 l chn ra PWM ca CCR1 v CCR2

Np gi tr cho TACCR0, TACCRx La chn thanh ghi capture/compare to PWM : Thit lp cc bit OUTMODx trong thanh ghi TACCTLx tng ng.

La chn ngun xung clock, h s chia v ch hot ng cho Timer_A : Thit lp cc bit TASSELx, IDx v MCx trong thanh ghi TACTL 1.7.8 Ngt Timer_A: Timer_A c 2 vector ngt: Vector ngt TACCR0 cho TACCR0 CCIFG Vector ngt TAIV cho TAIFG v CCIFGs ca CCR1 v CCR2 C th : C ngt TACCR0 CCIFG c u tin cao nht trong ngt Timer_A v t ng reset khi chng trnh ngt c thc thi C ngt TACCR1 CCIFG ,TACCR2 CCIFG v TAIFG c cng vector ngt TAIV v c phn chia theo mc u tin nh sau:

Ngt c mc u tin cao hn s c thc hin trc bng cch np 1 gi tr vo thanh ghi TAIV. Gi tr ny s c tnh ton hay cng vo thanh ghi PC nhy ti chng trnh con phc v ngt. C ngt CCIFG ca TACCR1 v TACCR2 cng c t ng reset khi thot khi chng trnh ngt. Nu c 1 ngt khc xy ra khi ang thc hin ngt, ngt khc s c thc hin ngay lp tc sau khi ngt trc c thc thi xong. 1.8 ADC10: C th la chn ngun clock cho ADC: ADC10OSC (5Mhz), ACLK, MCLK, SMCLK. Vref ni v ngoi.

10 bit ADC, 8 knh ADC. Tc 200kpbs.

Autoscan C th ly nhiu knh cng lc.

iu khin chuyn i d liu v t ng lu tr mu ly. C ngt

1.8.1 -

Phn cng v hot ng:

ADC10 c cu hnh bi 2 thanh ghi ADC10CTL0 v ADC10CTL1 v 2 thanh ghi ny ch c thay i khi ENC = 0; khi bt u ly mu th phai a ENC = 1; Nadc = 1023 La chn knh ADC: ADC10AEx bits Voltage Reference Generator: Ngun ni 1.5V 2.5V hoc Vcc c la chn da vo bit REFON REF2_5 REFOUT Sample and Conversion Timing: SHTx la chn chu k ly mu 4 8 16 64xADC10CLK,

Conversion Mode:

CNEQx 00 01 10 11

MODE Single chanel Single Conversion Sequence of channels Repeat single channels Repeat Sequence of channels

1.8.2 Mode Single Chanel Single Conversion. Sau khi bt chuyn i ADC10 (ADC10ON) v thit lp knh ly ADC (INCHx).

i ENC v ADC10SC c kch hot th bt u chuyn i Lu mu d liu vo khi tn hiu SAMPCON mc cao vi tc l 4/8/16/64x ADC10CLK. Qu trnh chuyn i d liu sau s mt thm 12xADC10CLK. Lu kt qu vo ADC10MEM v set c ADC10IFG mt thm 1 ADC10CLK Trong qu trnh thc hin tng bc trn nu c thay i tn hiu SHS, ENC -

ADC10SC th qu trnh s nhy v trng thi i 1 hoc tt c cc tn hiu trn c set tr li.

1.8.3

Mode Single of Sequence

c phn tch ging mode trn nhng khc ch l qu trnh t kt thc khi cc knh la chn c ly mu ht iu ny c bo bng tn hiu EOS.x nu tn hiu ny bng 1 qu trnh chuyn i cc knh xong.

1.8.4

Cc bit hay dng trong ADC Trong thanh ADCCTL1 ghi

o o

INCHx (4bits) : la chn knh ly ADC. ADC10DIVx (2bits) : ADC10 Clock Divider. ADC10SSELx (2bits): Clock source select. Trong thanh ghi ADCCTL0

SREFx (3bits): Chn ngun p tham chiu. ADC10SHTx (2bits): chn thi gian sample v hold. ADC10SR (1bits) : tc ly mu 0 (200kbps) 1(150kbps). REFOUT (1bit): C chn ngun tham chiu ngoi hay khng. REFON (1bit): bt ngun tham chiu ni ->REF2_5V (1bit) ngun ni l 1.5V hay 2V ADC10ON: Bt ADC10. ADC10IE: cho php ngt ADC10 Trong thanh ghi ADC10AE0

o o

o o

ADC10AE0x (Bit 7-0) cho php chn ng vo l ng vo Analog Cch cu hnh n gin cho ADC hot ng.

1.8.5 ADC10 DATA TRANFER CONTROLLER c kch hot nu gi tr thanh ghi ADC10DTC1 khc khng. Khi ADC10 chuyn i xong gi tr c y vao ADC10MEM, b chuyn d liu c kch hot.Mi DTC tranfer cn 1 chu k MCLK. C 2 ch : One block v two block tranfer 1.8.6 ADC10 Interupt Mt ngt v mt vector ngt i km vi b ADC10. Khi DTC khng c dng th ADC10IFG c set khi qu trnh chuyn i ADC xong v d liu c load vo ADC10MEM. Khi dng DTC th ADC10IFG c set khi khi vic chuyn vo b nh 1 block hon thnh.Nu bit GIE v ADC10IE c set th khi ADC10IFG c set th s to ra ngt.

1.9 UART 1.9.1 Gii thiu : o L b truyn nhn d liu ni tip bt ng b o Khi kt hp vi mi thit b chuyn i in p khc nhau n to ra 1 chun giao tip khc nhau ( vd: chun RS232 thng qua MAX232,) o D liu c ng gi thnh cc khung truyn trc khi truyn i, mt khung truyn bao gm : o Start bit (=0): bo cho thit b nhn chun b c d liu truyn n o Data : l phn d liu gi i ngay sau start bit o Parity bit : l bit c thm vo kim tra d liu sau khi truyn o Stop bit : thng l 1 bit hoc 2 bit dng bo kt thc mt khung truyn o Tc baud ( s bit truyn trong 1s) c 2 thit b truyn v nhn phi ging nhau 1.9.2 Hot ng: o USCI_UART c reset bi PUC hoc set bit UCSWRST o USCI_UART hot ng khi clear bit UCSWRST o Hot ng nhn d liu ca UART o Sau khi clear bit UCSWRST, b nhn d liu v b tc baud sn sng v trng thi ch o Khi pht hin start bit th qu trnh nhn d liu bt u v ngc li khi khng pht hin start bit th quay v trng thi ch o Hot ng truyn d liu ca UART o Sau khi clear bit UCSWRST, b nhn truyn d liu v b tc baud sn sng v trng thi ch o Khi c d liu ghi vo thanh ghi UCAxTXBUF th qu trnh truyn d liu bt u o D liu c truyn vo Transmit shift register khi thanh ghi ny rng v tip tc c truyn sang thit b nhn o C UCAxTXIFG c set khi m UCAxTXBUF sn sng cho d liu tip theo o Nu d liu khng c ghi vo UCAxTXBUF th b UART li tip tc vo trng thi ch 1.9.3 Thit lp tc baud : C 2 ch thit lp, c la chn bng bit UCOS16

BITCLK = tc baud Tc baud ny c tnh t xung BRCLK qua h s chia N = (fBRCLK / Baud rate), do h s N thng khng phi l s nguyn.V vy tng chnh xc, ngoi b chia divider cn c b iu bin modulator o thit lp tc baud vi cc chnh xc khc nhau, ta s dng bng o Commonly used Baud Rates ca msp430 thit lp cc gi tr cho UCBRx, UCBRFx, UCBRSx. 1.9.4 Ngt UART : +Transmit interrupt o C ngt UCAxTXIFG c set khi thanh ghi UCAxTXBUF sn sng nhn d liu mi cn truyn o o

o xy ra ngt th c UCAxTXIE v GIE cn c set o C ngt UCAxTXIFG t ng reset khi d liu c ghi vo UCAxTXBUF + Receive interrupt o C ngt UCAxRXIFG c set d liu c nhn v cha trong thanh ghi UCAxTXBUF o xy ra ngt th c UCAxTXIE v GIE cn c set o C ngt UCAxRXIFG t ng reset khi d liu c c ra khi UCAxRXBUF Thanh ghi : UCAxCTL0 : thanh ghi iu khin 0 UCAxCTL1 : thanh ghi iu khin 1 IE2 : thanh ghi iu khin ngt UCAxBRO : thanh ghi to h s chia tn UCAxBR1 : thanh ghi to h s chia tn UCA0MCTL : iu khin modulation 1.9.5 Kch hot UART : o Vic thay i gi tr trn cc thanh ghi k trn s kch hot UART vi nhiu mode khc nhau, chng hn mun UART cu hnh : Baud rate = 9600 , nhn d liu ni tip truyn t my vi tnh o Chn ngun cung cp clock v thit lp tc baud theo bng trong datasheet o o o o o o

BCSCTL1 = CALBC1_1MHZ; // Set DCO DCOCTL = CALDCO_1MHZ; UCA0CTL1 |= UCSSEL_2; // SMCLK UCA0BR0 = 104; // 1MHz/104 ~ 9600 , UCBRx = 104 UCA0BR1 = 0; UCA0MCTL = UCBRS0; // UCBRSx = 1 o Bt u kch hot UART UCA0CTL1 &= ~UCSWRST; // Turn on UART o Kch hot ngt ca b nhn IE2 |= UCA0RXIE; // Enable USCI_A0 RX interrupt 1.10 SPI 1.10.1 Gii thiu : o Cung cp mt giao thc ni tip ng b kp gia MCU v thit b ngoi vi o Giao tip SPI c thc hin thng qua bus 4 dy MISO, MOSI, SCK, SS MISO: Master Input Slave Output MOSI: Master Output Slave Input. SCK : Serial Clock SS : Slave Select. 1.10.2 Hot ng: o Tn hiu SCK c cung cp bi Master nhm to xung ng b cho php d liu c truyn o o o i hoc khi c d liu nhn c. Tc ca d liu truyn i s thay i theo s thay i ca SCK ( s thay i tc truyn khng nh hng n d liu ). Master v Slave u c thanh ghi dch ni tip bn trong. Master bt u vic trao i d liu bng cch truyn i mt byte vo thanh ghi dch ca n, sau byte d liu s c a sang Slave theo ng tn hiu MOSI

Slave s truyn d liu nm trong thanh ghi dch ca chnh n ngc tr v Master thng qua

ng tn hiu MISO. + Nh vy d liu ca hai thanh ghi s c trao i vi nhau. Vic c v ghi d liu vo Slave din ra cng mt lc nn tc trao i d liu din ra rt nhanh. Do , giao thc SPI l mt giao thc rt c hiu qu. + Ch c thit b Master mi c th cp xung SCK, d liu s khng c truyn i nu nh Master khng cung cp xung SCK. + Tt c cc thit b Slave u c iu khin bi xung nhp pht ra t Master (Slave khng c kh nng pht xung). + Thng th tn hiu SS dng chn Slave s tc ng mc thp ch ra Slave no c truy cp. Tn hiu ny phi c s dng khi c nhiu hn 1 Slave trong cng h thng v thng khng s dng n khi trong mch ch c 1 Slave. 1.10.3 Thanh ghi nh hng SPI + USICKCTL : USI clock control register + USICNT : USI bit counter register + USICTL0 : USI control register 0 + USICTL1 : USI control register 1 1.10.4 Kch hot SPI + Vic thay i gi tr trn cc thanh ghi k trn s kch hot SPI vi nhiu mode khc nhau, chng hn mun SPI cu hnh : SPI Master + xung clock ACLK / 4 + USICTL0 |= USIPE6 + USIPE5 + USIMST + USIOE;

+ USICTL1 |= USICKPH + USIIE;

+ USICKCTL = USIDIV_2 + USISSEL_1; + USICTL0 &= ~USISWRST;

// chia 2, ACLK

+ USICNT = 8; 1.10.5 Ngt SPI : + USIIFG c set khi bit USICNTx = 0 (t ng gim v 0 khi truyn ht d liu hoc t np gi tr 0) + USIIFG b xa khi bit USICNTx > 0 v USIIFGCC = 0 ,hoc xa trc tip bng code.

Chng 2: Thc hnh

2.1

PORT1 :

//****************************************************************************** // MSP430G2xx1 Demo - Software Poll P1.4, Set P1.0 if P1.4 = 1 // // Description: Poll P1.4 in a loop, if hi P1.0 is set, if low, P1.0 reset. // ACLK = n/a, MCLK = SMCLK = default DCO // // MSP430F2x32 // ----------------// /|\| XIN|// || | // --|RST XOUT|// /|\ | | // --o--|P1.4 P1.0|-->LED // \|/ // //****************************************************************************** #include <msp430F2232.h> void main(void) { WDTCTL = WDTPW + WDTHOLD; // Stop watchdog timer P1DIR |= 0x01; // Set P1.0 to output direction while (1) // Test P1.4 { if ((0x10 & P1IN)) P1OUT |= 0x01; // if P1.4 set, set P1.0 else P1OUT &= ~0x01; // else reset } }

2.2

PORT1 & INTERRUPT:

//****************************************************************************** // MSP430G2xx1 Demo - Software Port Interrupt Service on P1.4 from LPM4 // // Description: A hi/low transition on P1.4 will trigger P1_ISR which, // toggles P1.0. Normal mode is LPM4 ~ 0.1uA. LPM4 current can be measured // with the LED removed, all unused P1.x/P2.x configured as output or inputs // pulled high or low, and ensure the P1.4 interrupt input does not float. // ACLK = n/a, MCLK = SMCLK = default DCO // // MSP430G2x32 // ----------------// /|\| XIN|// || | // --|RST XOUT|// /|\ | | // --o--|P1.4 P1.0|-->LED // \|/ //****************************************************************************** #include <msp430g2232.h> void main(void) { WDTCTL = WDTPW + WDTHOLD; // Stop watchdog timer P1DIR |= 0x01; // Set P1.0 to output direction P1IE |= 0x10; // P1.4 interrupt enabled P1IES |= 0x10; // P1.4 Hi/lo edge P1IFG &= ~0x10; // P1.4 IFG cleared _BIS_SR(LPM4_bits + GIE); } // Port 1 interrupt service routine #pragma vector=PORT1_VECTOR __interrupt void Port_1(void) { P1OUT ^= 0x01; // P1.0 = toggle P1IFG &= ~0x10; // P1.4 IFG cleared // Enter LPM4 w/interrupt

2.3

V d hot ng ca Timer_A :

#include <msp430g2231.h>

void void void void void

FaultRoutine(void); ConfigWDT(void); ConfigClocks(void); ConfigLEDs(void); ConfigTimerA2(void);

__interrupt void Timer_A (void) { P1OUT ^= 0x01; CCR0 += 62500; }

// Toggle P1.0 // Add Offset to CCR0

void main(void) { ConfigWDT(); ConfigClocks(); ConfigPINs(); ConfigTimerA2(); _BIS_SR(LPM0_bits + GIE); // Enter LPM0 w/ interrupt } void ConfigWDT(void) { WDTCTL = WDTPW + WDTHOLD; // Stop watchdog timer } //Configure Clock void ConfigClocks(void) { if (CALBC1_1MHZ ==0xFF || CALDCO_1MHZ == 0xFF) FaultRoutine(); // If calibration data is erased // run FaultRoutine() BCSCTL1 = CALBC1_1MHZ; // Set range DCOCTL = CALDCO_1MHZ; // Set DCO step + modulation BCSCTL3 |= LFXT1S_2; // LFXT1 = VLO IFG1 &= ~OFIFG; // Clear OSCFault flag BCSCTL2 |= SELM_0 + DIVM_3 + DIVS_3; // MCLK = DCO/8, SMCLK = DCO/8 } void FaultRoutine(void) { P1OUT = BIT0; // P1.0 on (red LED) while(1); // TRAP } void ConfigPINs(void) { P1DIR = BIT6 + BIT0; outputs P1OUT = 0; }

S nguyn l:

// P1.6 and P1.0 // LEDs off

void ConfigTimerA2(void) { CCTL0 = CCIE; // CCR0 interrupt enabled CCR0 = 62500; TACTL = TASSEL_2 + MC_2; // SMCLK, contmode } // Timer A0 interrupt service routine #pragma vector=TIMERA0_VECTOR

Trong v d trn, Timer_A hot ng ch continuous, s xy ra ngt khi gi tr thanh ghi TAR m n gi tr thanh ghi TACCR0, chng trnh con phc v ngt s lt trng thi chn P1.0 lm n led sng tt theo. Vi cc ch hot ng khc ca Timer_A, ta ch cn thay i cu hnh trong chng trnh con ConfigTimerA2

2.4

PWM:
ConfigWDT(); ConfigClocks(); ConfigPINs(); ConfigTimerA2(); _BIS_SR(LPM0_bits); interrupt }

#include <msp430g2231.h> void void void void void FaultRoutine(void); ConfigWDT(void); ConfigClocks(void); ConfigPINs(void); ConfigTimerA2(void);

// Enter LPM0 w/

void main(void) {

void ConfigWDT(void) { WDTCTL = WDTPW + WDTHOLD; watchdog timer

// Stop

} //Configure Clock void ConfigClocks(void) { if (CALBC1_1MHZ ==0xFF || CALDCO_1MHZ == 0xFF) FaultRoutine(); // If calibration data is erased // run FaultRoutine() BCSCTL1 = CALBC1_1MHZ; // Set range DCOCTL = CALDCO_1MHZ; // Set DCO step + modulation BCSCTL3 |= LFXT1S_2; // LFXT1 = VLO IFG1 &= ~OFIFG; // Clear OSCFault flag BCSCTL2 |= SELM_0 + DIVM_3 + DIVS_3; // MCLK = DCO/8, SMCLK = DCO/8 } void FaultRoutine(void) { P1OUT = BIT0; while(1); } void ConfigPINs(void) { P1DIR = BIT2 + BIT1; P1SEL = BIT2 + BIT1; P1.1 <--> OUT0 }

S nguyn l:

// P1.0 on (red LED) // TRAP

// P1.2 and P1.1 outputs // P1.2 <--> OUT1 and

void ConfigTimerA2(void) { CCR0 = 1001; CCTL1 = OUTMOD_7; CCTL0 = OUTMOD_4; CCR1 = 501; cycle 50% TACTL = TASSEL_2 + MC_1; mode, No divide

// PWM Period // CCR1 reset/set // CCR0 toggle // CCR1 PWM duty // SMCLK, Up

Trong v d trn, ta s to ra 2 xung PWM trn 2 chn P1.1 v P1.2 Xung PWM chn P1.1 s l li ra OUT0 (thanh ghi TACCR0) hot ng mode 4(toggle). Xung PWM chn P1.2 s l li ra OUT1 (thanh ghi TACCR1) hot ng mode 7 (reset/set), rng

2.5 ADC10 & Interupt //****************************************************************************** // MSP430G2x31 Demo - ADC10, Sample A1, AVcc Ref, Set P1.0 if > 0.5*AVcc //

// Description: A single sample is made on A1 with reference to AVcc. // Software sets ADC10SC to start sample and conversion - ADC10SC // automatically cleared at EOC. ADC10 internal oscillator times sample (16x) // and conversion. In Mainloop MSP430 waits in LPM0 to save power until ADC10 // conversion complete, ADC10_ISR will force exit from LPM0 in Mainloop on // reti. If A1 > 0.5*AVcc, P1.0 set, else reset. // // MSP430F2x32 // ----------------// /|\| XIN |// || | // --|RST XOUT|// | | // >---|P2.1/A1 P1.1|-->LED // //****************************************************************************** #include "msp430F2132.h" void main(void) { WDTCTL = WDTPW + WDTHOLD; // Stop WDT ADC10CTL0 = ADC10SHT_2 + ADC10ON + ADC10IE; // ADC10ON, interrupt enabled ADC10CTL1 = INCH_1; // input A1 ADC10AE0 |= 0x02; // PA.1 ADC option select P1DIR |= BIT1 + BIT2; // Set P1.1, 1.2 to output direction for (;;) { P1OUT |= 0x04; __delay_cycles(1000); P1OUT &= ~0x04; __delay_cycles(1000); ADC10CTL0 |= ENC + ADC10SC; // Sampling and conversion start __bis_SR_register(CPUOFF + GIE); // LPM0, ADC10_ISR will force exit if (ADC10MEM < 0x1FF) P1OUT &= ~0x02; // Clear P1.1 LED off M S P 4 3 0 G 2 2 3 C h o t else P 1 . C 0 l k P 1 . 5 a t a D P1OUT |= 0x02; // Set P1.1 LED on P 1 . 6 } V C C } // ADC10 interrupt service routine #pragma vector=ADC10_VECTOR __interrupt void ADC10_ISR(void) { 8 __bic_SR_register_on_exit(CPUOFF); // Clear CPUOFF bit from 0(SR) G N D V C
13 10 11 12 14 SR C LK R C LK G C LR 7 4 H C 5 9

V U 1 6 1

2.6

Phn thc hnh giao tip SPI :

7 6 5 4 3 2 1 15

// Giao tip msp430g2232 vi 74hc595 qua chun giao tip SPI // D liu t msp430 s truyn qua 595 to hiu ng sng led trn led 7 on // Phn cng s thc hin trn kit launch pad theo s nh hnh bn #include <msp430g2231.h> int i=0;
V C C 1 6 2 8 7 9 10 3 4 5 U 4

V V

c c

c 1 c 2 S

p g f e d c b a 7 e g m

9 e n t

SD O m

Q Q Q Q Q Q Q Q

H G F E D C B A

SD I

5 C

. 8

in i

int b[10]={0xFE,0xFD,0xFB,0xF7,0xEF,0xDF}; void main(void) { WDTCTL = WDTPW + WDTHOLD; // Stop WDT P1DIR |= 0x01; // P1.0 is output USICTL0 |= USIPE6 + USIPE5 + USIMST + USIOE; // Port, SPI Master USICTL1 |= USICKPH + USIIE; // Counter interrupt, flag remains set USICKCTL = USIDIV_2 + USISSEL_1; // /4 ACLK USICTL0 &= ~USISWRST; // USI released for operation USISRL = b[i]; USICNT = 8; // init-load counter 8 bits _BIS_SR(LPM3_bits + GIE); // Enter LPM3 + interrupt } #pragma vector=USI_VECTOR // USI interrupt service routine __interrupt void USI_ISR(void) { // create positive edge clock on p1.0 P1OUT &= ~0x01; __delay_cycles(100000); P1OUT |= 0x01; USISRL = b[i] ; if(i==5) { i=0; } else{ i++; } USICNT = 8; // re-load counter }

2.7

Phn thc hnh giao tip UART

// Giao tip msp430g2553 vi my vi tnh qua chun giao tip UART // D liu c truyn t my vi tnh xung msp430 bng phn mm Advanced Serial Port Terminal // Nu d liu truyn l s, th msp430 s x l v bt tt cc led trn kit launch pad // Nu d liu l ch th msp430 s truyn ngc li cho my vi tnh hin th ln mn hnh ca Advanced Serial Port Terminal // Phn cng s thc hin trn kit launch pad rev 1.4 , ch ghp ni cc jump thc hin UART trn kit

#include "msp430g2553.h" #define UART_TXD 0x02 #define UART_RXD 0x04 unsigned int t1; void main(void) { WDTCTL = WDTPW + WDTHOLD; // Stop WDT BCSCTL1 = CALBC1_1MHZ; // Set DCO DCOCTL = CALDCO_1MHZ; P1SEL = BIT1 + BIT2 ; // P1.1 = RXD, P1.2=TXD P1SEL2 = BIT1 + BIT2; UCA0CTL1 |= UCSSEL_2; // SMCLK UCA0BR0 = 104; // 1MHz / 104 ~ 9600 UCA0BR1 = 0; UCA0MCTL = UCBRS0; // Modulation = 1 UCA0CTL1 &= ~UCSWRST; // Turn on UART (USCI)

IE2 |= UCA0RXIE; // Enable USCI_A0 RX interrupt P1DIR = 0xFF & ~UART_RXD; // Set all pins but RXD to output P1OUT = 0x00 ; __bis_SR_register(LPM0_bits+GIE); //Enable ngat ngoai vi t1=0; } #pragma vector=USCIAB0RX_VECTOR __interrupt void USCI0RX_ISR(void) { if(UCA0RXBUF > '/' && UCA0RXBUF < ':') t1 = t1*10 + (UCA0RXBUF-'0') ; else { if(UCA0RXBUF == ':') { switch(t1) { case 11: P1OUT |= BIT0; break; // bat led do p1.0 case 12: P1OUT |= BIT6; break; // bat led xanh p1.6 case 91: P1OUT &=~ BIT0; break; // tat led do p1.0 case 92: P1OUT &=~ BIT6; break; // tat led xanh p1.6 default: break; } t1 = 0 ; } else while (!(IFG2 & UCA0TXIFG)); // USCI_A0 TX buffer ready? if(UCA0RXBUF != ':') UCA0TXBUF = UCA0RXBUF; } }

2.8

WDT

//******************************************************************************

// MSP430G2xx1 Demo - WDT, Toggle P1.0, Interval Overflow ISR, DCO SMCLK // // Description: Toggle P1.0 using software timed by the WDT ISR. Toggle rate // is approximately 30ms based on default DCO/SMCLK clock source // used in this example for the WDT. // ACLK = n/a, MCLK = SMCLK = default // // MSP430G2xx2 // ----------------// /|\| XIN|// || | // --|RST XOUT|// | | // | P1.0|-->LED // //****************************************************************************** #include <msp430g2232.h> void main(void) { WDTCTL = WDT_MDLY_32; IE1 |= WDTIE; P1DIR |= 0x01; _BIS_SR(LPM0_bits + GIE); } // Watchdog Timer interrupt service routine #pragma vector=WDT_VECTOR __interrupt void watchdog_timer(void) { P1OUT ^= 0x01; // Toggle P1.0 using exclusive-OR }

// Set Watchdog Timer interval to ~30ms // Enable WDT interrupt // Set P1.0 to output direction // Enter LPM0 w/ interrupt